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comparison gcc/config/spu/spu-builtins.md @ 47:3bfb6c00c1e0

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update it from 4.4.2 to 4.4.3.
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Sun, 07 Feb 2010 17:44:34 +0900
parents a06113de4d67
children 77e2b8dfacca
comparison
equal deleted inserted replaced
46:b85a337e5837 47:3bfb6c00c1e0
525 "" 525 ""
526 "bislede\t$lr,%0" 526 "bislede\t$lr,%0"
527 [(set_attr "type" "br")]) 527 [(set_attr "type" "br")])
528 528
529 ;; float convert 529 ;; float convert
530 (define_insn "spu_csflt" 530 (define_expand "spu_csflt"
531 [(set (match_operand:V4SF 0 "spu_reg_operand")
532 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
533 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
534 ""
535 {
536 if (GET_CODE (operands[2]) == CONST_INT
537 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
538 {
539 error ("spu_convtf expects an integer literal in the range [0, 127].");
540 operands[2] = force_reg (SImode, operands[2]);
541 }
542 if (GET_CODE (operands[2]) != CONST_INT)
543 {
544 rtx exp2;
545 rtx cnv = gen_reg_rtx (V4SFmode);
546 rtx scale = gen_reg_rtx (SImode);
547 rtx op2 = force_reg (SImode, operands[2]);
548 rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
549 emit_insn (gen_subsi3 (scale, const1_rtx, op2));
550 exp2 = spu_gen_exp2 (V4SFmode, scale);
551 emit_insn (gen_floatv4siv4sf2_mul (cnv, operands[1], m1));
552 emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
553 }
554 else
555 {
556 rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
557 emit_insn (gen_floatv4siv4sf2_div (operands[0], operands[1], exp2));
558 }
559 DONE;
560 })
561
562 (define_expand "spu_cflts"
563 [(set (match_operand:V4SI 0 "spu_reg_operand")
564 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
565 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
566 ""
567 {
568 rtx exp2;
569 if (GET_CODE (operands[2]) == CONST_INT
570 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
571 {
572 error ("spu_convts expects an integer literal in the range [0, 127].");
573 operands[2] = force_reg (SImode, operands[2]);
574 }
575 exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
576 if (GET_CODE (operands[2]) != CONST_INT)
577 {
578 rtx mul = gen_reg_rtx (V4SFmode);
579 emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
580 emit_insn (gen_fix_truncv4sfv4si2 (operands[0], mul));
581 }
582 else
583 emit_insn (gen_fix_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
584 DONE;
585 })
586
587 (define_expand "spu_cuflt"
531 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 588 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
532 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r") 589 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
533 (match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CSFLT ))] 590 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
534 "" 591 ""
535 "csflt\t%0,%1,%2" 592 {
536 [(set_attr "type" "fp7")]) 593 if (GET_CODE (operands[2]) == CONST_INT
537 594 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
538 (define_insn "spu_cflts" 595 {
539 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 596 error ("spu_convtf expects an integer literal in the range [0, 127].");
540 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r") 597 operands[2] = force_reg (SImode, operands[2]);
541 (match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTS ))] 598 }
542 "" 599 if (GET_CODE (operands[2]) != CONST_INT)
543 "cflts\t%0,%1,%2" 600 {
544 [(set_attr "type" "fp7")]) 601 rtx exp2;
545 602 rtx cnv = gen_reg_rtx (V4SFmode);
546 (define_insn "spu_cuflt" 603 rtx scale = gen_reg_rtx (SImode);
547 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 604 rtx op2 = force_reg (SImode, operands[2]);
548 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r") 605 rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
549 (match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CUFLT ))] 606 emit_insn (gen_subsi3 (scale, const1_rtx, op2));
550 "" 607 exp2 = spu_gen_exp2 (V4SFmode, scale);
551 "cuflt\t%0,%1,%2" 608 emit_insn (gen_floatunsv4siv4sf2_mul (cnv, operands[1], m1));
552 [(set_attr "type" "fp7")]) 609 emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
553 610 }
554 (define_insn "spu_cfltu" 611 else
555 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 612 {
556 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r") 613 rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
557 (match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTU ))] 614 emit_insn (gen_floatunsv4siv4sf2_div (operands[0], operands[1], exp2));
558 "" 615 }
559 "cfltu\t%0,%1,%2" 616 DONE;
560 [(set_attr "type" "fp7")]) 617 })
618
619 (define_expand "spu_cfltu"
620 [(set (match_operand:V4SI 0 "spu_reg_operand")
621 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
622 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
623 ""
624 {
625 rtx exp2;
626 if (GET_CODE (operands[2]) == CONST_INT
627 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
628 {
629 error ("spu_convtu expects an integer literal in the range [0, 127].");
630 operands[2] = force_reg (SImode, operands[2]);
631 }
632 exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
633 if (GET_CODE (operands[2]) != CONST_INT)
634 {
635 rtx mul = gen_reg_rtx (V4SFmode);
636 emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
637 emit_insn (gen_fixuns_truncv4sfv4si2 (operands[0], mul));
638 }
639 else
640 emit_insn (gen_fixuns_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
641 DONE;
642 })
561 643
562 (define_expand "spu_frds" 644 (define_expand "spu_frds"
563 [(set (match_operand:V4SF 0 "spu_reg_operand" "") 645 [(set (match_operand:V4SF 0 "spu_reg_operand" "")
564 (vec_select:V4SF 646 (vec_select:V4SF
565 (vec_concat:V4SF 647 (vec_concat:V4SF