Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/spu/spu.md @ 47:3bfb6c00c1e0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.2 to 4.4.3.
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Sun, 07 Feb 2010 17:44:34 +0900
parents a06113de4d67
children 77e2b8dfacca
comparison
equal deleted inserted replaced
46:b85a337e5837 47:3bfb6c00c1e0
134 (UNSPEC_ABSDB 29) 134 (UNSPEC_ABSDB 29)
135 (UNSPEC_ORX 30) 135 (UNSPEC_ORX 30)
136 (UNSPEC_HEQ 31) 136 (UNSPEC_HEQ 31)
137 (UNSPEC_HGT 32) 137 (UNSPEC_HGT 32)
138 (UNSPEC_HLGT 33) 138 (UNSPEC_HLGT 33)
139 (UNSPEC_CSFLT 34)
140 (UNSPEC_CFLTS 35)
141 (UNSPEC_CUFLT 36)
142 (UNSPEC_CFLTU 37)
143 (UNSPEC_STOP 38) 139 (UNSPEC_STOP 38)
144 (UNSPEC_STOPD 39) 140 (UNSPEC_STOPD 39)
145 (UNSPEC_SET_INTR 40) 141 (UNSPEC_SET_INTR 40)
146 (UNSPEC_FSCRRD 42) 142 (UNSPEC_FSCRRD 42)
147 (UNSPEC_FSCRWR 43) 143 (UNSPEC_FSCRWR 43)
180 SI V4SI 176 SI V4SI
181 V2DI 177 V2DI
182 SF V4SF 178 SF V4SF
183 DF V2DF]) 179 DF V2DF])
184 180
181 (define_mode_iterator QHSI [QI HI SI])
182 (define_mode_iterator QHSDI [QI HI SI DI])
185 (define_mode_iterator DTI [DI TI]) 183 (define_mode_iterator DTI [DI TI])
186 184
187 (define_mode_iterator VINT [QI V16QI 185 (define_mode_iterator VINT [QI V16QI
188 HI V8HI 186 HI V8HI
189 SI V4SI 187 SI V4SI
229 227
230 (define_mode_attr f2i [(SF "si") (V4SF "v4si") 228 (define_mode_attr f2i [(SF "si") (V4SF "v4si")
231 (DF "di") (V2DF "v2di")]) 229 (DF "di") (V2DF "v2di")])
232 (define_mode_attr F2I [(SF "SI") (V4SF "V4SI") 230 (define_mode_attr F2I [(SF "SI") (V4SF "V4SI")
233 (DF "DI") (V2DF "V2DI")]) 231 (DF "DI") (V2DF "V2DI")])
232 (define_mode_attr i2f [(SI "sf") (V4SI "v4sf")
233 (DI "df") (V2DI "v2df")])
234 (define_mode_attr I2F [(SI "SF") (V4SI "V4SF")
235 (DI "DF") (V2DI "V2DF")])
234 236
235 (define_mode_attr DF2I [(DF "SI") (V2DF "V2DI")]) 237 (define_mode_attr DF2I [(DF "SI") (V2DF "V2DI")])
236 238
237 (define_mode_attr umask [(HI "f") (V8HI "f") 239 (define_mode_attr umask [(HI "f") (V8HI "f")
238 (SI "g") (V4SI "g")]) 240 (SI "g") (V4SI "g")])
314 316
315 317
316 ;; move internal 318 ;; move internal
317 319
318 (define_insn "_mov<mode>" 320 (define_insn "_mov<mode>"
319 [(set (match_operand:MOV 0 "spu_nonimm_operand" "=r,r,r,r,r,m") 321 [(set (match_operand:MOV 0 "spu_dest_operand" "=r,r,r,r,r,m")
320 (match_operand:MOV 1 "spu_mov_operand" "r,A,f,j,m,r"))] 322 (match_operand:MOV 1 "spu_mov_operand" "r,A,f,j,m,r"))]
321 "spu_valid_move (operands)" 323 "register_operand(operands[0], <MODE>mode)
324 || register_operand(operands[1], <MODE>mode)"
322 "@ 325 "@
323 ori\t%0,%1,0 326 ori\t%0,%1,0
324 il%s1\t%0,%S1 327 il%s1\t%0,%S1
325 fsmbi\t%0,%S1 328 fsmbi\t%0,%S1
326 c%s1d\t%0,%S1($sp) 329 c%s1d\t%0,%S1($sp)
334 (match_operand:VSI 2 "immediate_operand" "i")))] 337 (match_operand:VSI 2 "immediate_operand" "i")))]
335 "" 338 ""
336 "iohl\t%0,%2@l") 339 "iohl\t%0,%2@l")
337 340
338 (define_insn "_movdi" 341 (define_insn "_movdi"
339 [(set (match_operand:DI 0 "spu_nonimm_operand" "=r,r,r,r,r,m") 342 [(set (match_operand:DI 0 "spu_dest_operand" "=r,r,r,r,r,m")
340 (match_operand:DI 1 "spu_mov_operand" "r,a,f,k,m,r"))] 343 (match_operand:DI 1 "spu_mov_operand" "r,a,f,k,m,r"))]
341 "spu_valid_move (operands)" 344 "register_operand(operands[0], DImode)
345 || register_operand(operands[1], DImode)"
342 "@ 346 "@
343 ori\t%0,%1,0 347 ori\t%0,%1,0
344 il%d1\t%0,%D1 348 il%d1\t%0,%D1
345 fsmbi\t%0,%D1 349 fsmbi\t%0,%D1
346 c%d1d\t%0,%D1($sp) 350 c%d1d\t%0,%D1($sp)
347 lq%p1\t%0,%1 351 lq%p1\t%0,%1
348 stq%p0\t%1,%0" 352 stq%p0\t%1,%0"
349 [(set_attr "type" "fx2,fx2,shuf,shuf,load,store")]) 353 [(set_attr "type" "fx2,fx2,shuf,shuf,load,store")])
350 354
351 (define_insn "_movti" 355 (define_insn "_movti"
352 [(set (match_operand:TI 0 "spu_nonimm_operand" "=r,r,r,r,r,m") 356 [(set (match_operand:TI 0 "spu_dest_operand" "=r,r,r,r,r,m")
353 (match_operand:TI 1 "spu_mov_operand" "r,U,f,l,m,r"))] 357 (match_operand:TI 1 "spu_mov_operand" "r,U,f,l,m,r"))]
354 "spu_valid_move (operands)" 358 "register_operand(operands[0], TImode)
359 || register_operand(operands[1], TImode)"
355 "@ 360 "@
356 ori\t%0,%1,0 361 ori\t%0,%1,0
357 il%t1\t%0,%T1 362 il%t1\t%0,%T1
358 fsmbi\t%0,%T1 363 fsmbi\t%0,%T1
359 c%t1d\t%0,%T1($sp) 364 c%t1d\t%0,%T1($sp)
360 lq%p1\t%0,%1 365 lq%p1\t%0,%1
361 stq%p0\t%1,%0" 366 stq%p0\t%1,%0"
362 [(set_attr "type" "fx2,fx2,shuf,shuf,load,store")]) 367 [(set_attr "type" "fx2,fx2,shuf,shuf,load,store")])
363 368
364 (define_insn_and_split "load" 369 (define_split
365 [(set (match_operand 0 "spu_reg_operand" "=r") 370 [(set (match_operand 0 "spu_reg_operand")
366 (match_operand 1 "memory_operand" "m")) 371 (match_operand 1 "memory_operand"))]
367 (clobber (match_operand:TI 2 "spu_reg_operand" "=&r")) 372 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16
368 (clobber (match_operand:SI 3 "spu_reg_operand" "=&r"))] 373 && GET_MODE(operands[0]) == GET_MODE(operands[1])
369 "GET_MODE(operands[0]) == GET_MODE(operands[1])" 374 && !reload_in_progress && !reload_completed"
370 "#"
371 ""
372 [(set (match_dup 0) 375 [(set (match_dup 0)
373 (match_dup 1))] 376 (match_dup 1))]
374 { spu_split_load(operands); DONE; }) 377 { if (spu_split_load(operands))
375 378 DONE;
376 (define_insn_and_split "store" 379 })
377 [(set (match_operand 0 "memory_operand" "=m") 380
378 (match_operand 1 "spu_reg_operand" "r")) 381 (define_split
379 (clobber (match_operand:TI 2 "spu_reg_operand" "=&r")) 382 [(set (match_operand 0 "memory_operand")
380 (clobber (match_operand:TI 3 "spu_reg_operand" "=&r"))] 383 (match_operand 1 "spu_reg_operand"))]
381 "GET_MODE(operands[0]) == GET_MODE(operands[1])" 384 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16
382 "#" 385 && GET_MODE(operands[0]) == GET_MODE(operands[1])
383 "" 386 && !reload_in_progress && !reload_completed"
384 [(set (match_dup 0) 387 [(set (match_dup 0)
385 (match_dup 1))] 388 (match_dup 1))]
386 { spu_split_store(operands); DONE; }) 389 { if (spu_split_store(operands))
387 390 DONE;
391 })
388 ;; Operand 3 is the number of bytes. 1:b 2:h 4:w 8:d 392 ;; Operand 3 is the number of bytes. 1:b 2:h 4:w 8:d
389 393
390 (define_expand "cpat" 394 (define_expand "cpat"
391 [(set (match_operand:TI 0 "spu_reg_operand" "=r,r") 395 [(set (match_operand:TI 0 "spu_reg_operand" "=r,r")
392 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "r,r") 396 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "r,r")
460 (match_operand:V2SI 1 "spu_reg_operand" "r") 464 (match_operand:V2SI 1 "spu_reg_operand" "r")
461 (parallel [(const_int 1) ]))))] 465 (parallel [(const_int 1) ]))))]
462 "" 466 ""
463 "xswd\t%0,%1"); 467 "xswd\t%0,%1");
464 468
465 (define_expand "extendqiti2" 469 ;; By splitting this late we don't allow much opportunity for sharing of
470 ;; constants. That's ok because this should really be optimized away.
471 (define_insn_and_split "extend<mode>ti2"
466 [(set (match_operand:TI 0 "register_operand" "") 472 [(set (match_operand:TI 0 "register_operand" "")
467 (sign_extend:TI (match_operand:QI 1 "register_operand" "")))] 473 (sign_extend:TI (match_operand:QHSDI 1 "register_operand" "")))]
468 "" 474 ""
469 "spu_expand_sign_extend(operands); 475 "#"
470 DONE;") 476 ""
471 477 [(set (match_dup:TI 0)
472 (define_expand "extendhiti2" 478 (sign_extend:TI (match_dup:QHSDI 1)))]
473 [(set (match_operand:TI 0 "register_operand" "") 479 {
474 (sign_extend:TI (match_operand:HI 1 "register_operand" "")))] 480 spu_expand_sign_extend(operands);
475 "" 481 DONE;
476 "spu_expand_sign_extend(operands); 482 })
477 DONE;")
478
479 (define_expand "extendsiti2"
480 [(set (match_operand:TI 0 "register_operand" "")
481 (sign_extend:TI (match_operand:SI 1 "register_operand" "")))]
482 ""
483 "spu_expand_sign_extend(operands);
484 DONE;")
485
486 (define_expand "extendditi2"
487 [(set (match_operand:TI 0 "register_operand" "")
488 (sign_extend:TI (match_operand:DI 1 "register_operand" "")))]
489 ""
490 "spu_expand_sign_extend(operands);
491 DONE;")
492 483
493 484
494 ;; zero_extend 485 ;; zero_extend
495 486
496 (define_insn "zero_extendqihi2" 487 (define_insn "zero_extendqihi2"
523 (zero_extend:DI (match_operand:SI 1 "spu_reg_operand" "r")))] 514 (zero_extend:DI (match_operand:SI 1 "spu_reg_operand" "r")))]
524 "" 515 ""
525 "rotqmbyi\t%0,%1,-4" 516 "rotqmbyi\t%0,%1,-4"
526 [(set_attr "type" "shuf")]) 517 [(set_attr "type" "shuf")])
527 518
519 (define_insn "zero_extendqiti2"
520 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
521 (zero_extend:TI (match_operand:QI 1 "spu_reg_operand" "r")))]
522 ""
523 "andi\t%0,%1,0x00ff\;rotqmbyi\t%0,%0,-12"
524 [(set_attr "type" "multi0")
525 (set_attr "length" "8")])
526
527 (define_insn "zero_extendhiti2"
528 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
529 (zero_extend:TI (match_operand:HI 1 "spu_reg_operand" "r")))]
530 ""
531 "shli\t%0,%1,16\;rotqmbyi\t%0,%0,-14"
532 [(set_attr "type" "multi1")
533 (set_attr "length" "8")])
534
528 (define_insn "zero_extendsiti2" 535 (define_insn "zero_extendsiti2"
529 [(set (match_operand:TI 0 "spu_reg_operand" "=r") 536 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
530 (zero_extend:TI (match_operand:SI 1 "spu_reg_operand" "r")))] 537 (zero_extend:TI (match_operand:SI 1 "spu_reg_operand" "r")))]
531 "" 538 ""
532 "rotqmbyi\t%0,%1,-12" 539 "rotqmbyi\t%0,%1,-12"
592 [(set_attr "type" "shuf")]) 599 [(set_attr "type" "shuf")])
593 600
594 601
595 ;; float conversions 602 ;; float conversions
596 603
597 (define_insn "floatsisf2" 604 (define_insn "float<mode><i2f>2"
598 [(set (match_operand:SF 0 "spu_reg_operand" "=r") 605 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
599 (float:SF (match_operand:SI 1 "spu_reg_operand" "r")))] 606 (float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r")))]
600 "" 607 ""
601 "csflt\t%0,%1,0" 608 "csflt\t%0,%1,0"
602 [(set_attr "type" "fp7")]) 609 [(set_attr "type" "fp7")])
603 610
604 (define_insn "floatv4siv4sf2" 611 (define_insn "fix_trunc<mode><f2i>2"
605 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 612 [(set (match_operand:<F2I> 0 "spu_reg_operand" "=r")
606 (float:V4SF (match_operand:V4SI 1 "spu_reg_operand" "r")))] 613 (fix:<F2I> (match_operand:VSF 1 "spu_reg_operand" "r")))]
607 ""
608 "csflt\t%0,%1,0"
609 [(set_attr "type" "fp7")])
610
611 (define_insn "fix_truncsfsi2"
612 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
613 (fix:SI (match_operand:SF 1 "spu_reg_operand" "r")))]
614 "" 614 ""
615 "cflts\t%0,%1,0" 615 "cflts\t%0,%1,0"
616 [(set_attr "type" "fp7")]) 616 [(set_attr "type" "fp7")])
617 617
618 (define_insn "fix_truncv4sfv4si2" 618 (define_insn "floatuns<mode><i2f>2"
619 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 619 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
620 (fix:V4SI (match_operand:V4SF 1 "spu_reg_operand" "r")))] 620 (unsigned_float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r")))]
621 ""
622 "cflts\t%0,%1,0"
623 [(set_attr "type" "fp7")])
624
625 (define_insn "floatunssisf2"
626 [(set (match_operand:SF 0 "spu_reg_operand" "=r")
627 (unsigned_float:SF (match_operand:SI 1 "spu_reg_operand" "r")))]
628 "" 621 ""
629 "cuflt\t%0,%1,0" 622 "cuflt\t%0,%1,0"
630 [(set_attr "type" "fp7")]) 623 [(set_attr "type" "fp7")])
631 624
632 (define_insn "floatunsv4siv4sf2" 625 (define_insn "fixuns_trunc<mode><f2i>2"
633 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") 626 [(set (match_operand:<F2I> 0 "spu_reg_operand" "=r")
634 (unsigned_float:V4SF (match_operand:V4SI 1 "spu_reg_operand" "r")))] 627 (unsigned_fix:<F2I> (match_operand:VSF 1 "spu_reg_operand" "r")))]
635 ""
636 "cuflt\t%0,%1,0"
637 [(set_attr "type" "fp7")])
638
639 (define_insn "fixuns_truncsfsi2"
640 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
641 (unsigned_fix:SI (match_operand:SF 1 "spu_reg_operand" "r")))]
642 "" 628 ""
643 "cfltu\t%0,%1,0" 629 "cfltu\t%0,%1,0"
644 [(set_attr "type" "fp7")]) 630 [(set_attr "type" "fp7")])
645 631
646 (define_insn "fixuns_truncv4sfv4si2" 632 (define_insn "float<mode><i2f>2_mul"
647 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") 633 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
648 (unsigned_fix:V4SI (match_operand:V4SF 1 "spu_reg_operand" "r")))] 634 (mult:<I2F> (float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r"))
649 "" 635 (match_operand:<I2F> 2 "spu_inv_exp2_operand" "w")))]
650 "cfltu\t%0,%1,0" 636 ""
637 "csflt\t%0,%1,%w2"
638 [(set_attr "type" "fp7")])
639
640 (define_insn "float<mode><i2f>2_div"
641 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
642 (div:<I2F> (float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r"))
643 (match_operand:<I2F> 2 "spu_exp2_operand" "v")))]
644 ""
645 "csflt\t%0,%1,%v2"
646 [(set_attr "type" "fp7")])
647
648
649 (define_insn "fix_trunc<mode><f2i>2_mul"
650 [(set (match_operand:<F2I> 0 "spu_reg_operand" "=r")
651 (fix:<F2I> (mult:VSF (match_operand:VSF 1 "spu_reg_operand" "r")
652 (match_operand:VSF 2 "spu_exp2_operand" "v"))))]
653 ""
654 "cflts\t%0,%1,%v2"
655 [(set_attr "type" "fp7")])
656
657 (define_insn "floatuns<mode><i2f>2_mul"
658 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
659 (mult:<I2F> (unsigned_float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r"))
660 (match_operand:<I2F> 2 "spu_inv_exp2_operand" "w")))]
661 ""
662 "cuflt\t%0,%1,%w2"
663 [(set_attr "type" "fp7")])
664
665 (define_insn "floatuns<mode><i2f>2_div"
666 [(set (match_operand:<I2F> 0 "spu_reg_operand" "=r")
667 (div:<I2F> (unsigned_float:<I2F> (match_operand:VSI 1 "spu_reg_operand" "r"))
668 (match_operand:<I2F> 2 "spu_exp2_operand" "v")))]
669 ""
670 "cuflt\t%0,%1,%v2"
671 [(set_attr "type" "fp7")])
672
673 (define_insn "fixuns_trunc<mode><f2i>2_mul"
674 [(set (match_operand:<F2I> 0 "spu_reg_operand" "=r")
675 (unsigned_fix:<F2I> (mult:VSF (match_operand:VSF 1 "spu_reg_operand" "r")
676 (match_operand:VSF 2 "spu_exp2_operand" "v"))))]
677 ""
678 "cfltu\t%0,%1,%v2"
651 [(set_attr "type" "fp7")]) 679 [(set_attr "type" "fp7")])
652 680
653 (define_insn "extendsfdf2" 681 (define_insn "extendsfdf2"
654 [(set (match_operand:DF 0 "spu_reg_operand" "=r") 682 [(set (match_operand:DF 0 "spu_reg_operand" "=r")
655 (unspec:DF [(match_operand:SF 1 "spu_reg_operand" "r")] 683 (unspec:DF [(match_operand:SF 1 "spu_reg_operand" "r")]
2325 (lshiftrt:VHSI (match_dup:VHSI 1) 2353 (lshiftrt:VHSI (match_dup:VHSI 1)
2326 (neg:VHSI (match_dup:VHSI 3))))] 2354 (neg:VHSI (match_dup:VHSI 3))))]
2327 "" 2355 ""
2328 [(set_attr "type" "*,fx3")]) 2356 [(set_attr "type" "*,fx3")])
2329 2357
2358 (define_insn "<v>lshr<mode>3_imm"
2359 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r")
2360 (lshiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r")
2361 (match_operand:VHSI 2 "immediate_operand" "W")))]
2362 ""
2363 "rot<bh>mi\t%0,%1,-%<umask>2"
2364 [(set_attr "type" "fx3")])
2330 2365
2331 (define_insn "rotm_<mode>" 2366 (define_insn "rotm_<mode>"
2332 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r") 2367 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
2333 (lshiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r") 2368 (lshiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
2334 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))] 2369 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))]
2336 "@ 2371 "@
2337 rot<bh>m\t%0,%1,%2 2372 rot<bh>m\t%0,%1,%2
2338 rot<bh>mi\t%0,%1,-%<nmask>2" 2373 rot<bh>mi\t%0,%1,-%<nmask>2"
2339 [(set_attr "type" "fx3")]) 2374 [(set_attr "type" "fx3")])
2340 2375
2341 (define_expand "lshr<mode>3" 2376 (define_insn_and_split "lshr<mode>3"
2342 [(parallel [(set (match_operand:DTI 0 "spu_reg_operand" "") 2377 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r,r")
2343 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "") 2378 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r,r")
2344 (match_operand:SI 2 "spu_nonmem_operand" ""))) 2379 (match_operand:SI 2 "spu_nonmem_operand" "r,O,P")))]
2345 (clobber (match_dup:DTI 3))
2346 (clobber (match_dup:SI 4))
2347 (clobber (match_dup:SI 5))])]
2348 ""
2349 "if (GET_CODE (operands[2]) == CONST_INT)
2350 {
2351 emit_insn (gen_lshr<mode>3_imm(operands[0], operands[1], operands[2]));
2352 DONE;
2353 }
2354 operands[3] = gen_reg_rtx (<MODE>mode);
2355 operands[4] = gen_reg_rtx (SImode);
2356 operands[5] = gen_reg_rtx (SImode);")
2357
2358 (define_insn_and_split "lshr<mode>3_imm"
2359 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
2360 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
2361 (match_operand:SI 2 "immediate_operand" "O,P")))]
2362 "" 2380 ""
2363 "@ 2381 "@
2382 #
2364 rotqmbyi\t%0,%1,-%h2 2383 rotqmbyi\t%0,%1,-%h2
2365 rotqmbii\t%0,%1,-%e2" 2384 rotqmbii\t%0,%1,-%e2"
2366 "!satisfies_constraint_O (operands[2]) && !satisfies_constraint_P (operands[2])" 2385 "REG_P (operands[2]) || (!satisfies_constraint_O (operands[2]) && !satisfies_constraint_P (operands[2]))"
2367 [(set (match_dup:DTI 0) 2386 [(set (match_dup:DTI 3)
2368 (lshiftrt:DTI (match_dup:DTI 1) 2387 (lshiftrt:DTI (match_dup:DTI 1)
2369 (match_dup:SI 4))) 2388 (match_dup:SI 4)))
2370 (set (match_dup:DTI 0) 2389 (set (match_dup:DTI 0)
2371 (lshiftrt:DTI (match_dup:DTI 0) 2390 (lshiftrt:DTI (match_dup:DTI 3)
2372 (match_dup:SI 5)))] 2391 (match_dup:SI 5)))]
2373 { 2392 {
2374 HOST_WIDE_INT val = INTVAL(operands[2]); 2393 operands[3] = gen_reg_rtx (<MODE>mode);
2375 operands[4] = GEN_INT (val&7); 2394 if (GET_CODE (operands[2]) == CONST_INT)
2376 operands[5] = GEN_INT (val&-8); 2395 {
2396 HOST_WIDE_INT val = INTVAL(operands[2]);
2397 operands[4] = GEN_INT (val & 7);
2398 operands[5] = GEN_INT (val & -8);
2399 }
2400 else
2401 {
2402 rtx t0 = gen_reg_rtx (SImode);
2403 rtx t1 = gen_reg_rtx (SImode);
2404 emit_insn (gen_subsi3(t0, GEN_INT(0), operands[2]));
2405 emit_insn (gen_subsi3(t1, GEN_INT(7), operands[2]));
2406 operands[4] = gen_rtx_AND (SImode, gen_rtx_NEG (SImode, t0), GEN_INT (7));
2407 operands[5] = gen_rtx_AND (SImode, gen_rtx_NEG (SImode, gen_rtx_AND (SImode, t1, GEN_INT (-8))), GEN_INT (-8));
2408 }
2377 } 2409 }
2378 [(set_attr "type" "shuf,shuf")]) 2410 [(set_attr "type" "*,shuf,shuf")])
2379 2411
2380 (define_insn_and_split "lshr<mode>3_reg" 2412 (define_expand "shrqbybi_<mode>"
2381 [(set (match_operand:DTI 0 "spu_reg_operand" "=r")
2382 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r")
2383 (match_operand:SI 2 "spu_reg_operand" "r")))
2384 (clobber (match_operand:DTI 3 "spu_reg_operand" "=&r"))
2385 (clobber (match_operand:SI 4 "spu_reg_operand" "=&r"))
2386 (clobber (match_operand:SI 5 "spu_reg_operand" "=&r"))]
2387 ""
2388 "#"
2389 ""
2390 [(set (match_dup:DTI 3)
2391 (lshiftrt:DTI (match_dup:DTI 1)
2392 (and:SI (neg:SI (match_dup:SI 4))
2393 (const_int 7))))
2394 (set (match_dup:DTI 0)
2395 (lshiftrt:DTI (match_dup:DTI 3)
2396 (and:SI (neg:SI (and:SI (match_dup:SI 5)
2397 (const_int -8)))
2398 (const_int -8))))]
2399 {
2400 emit_insn (gen_subsi3(operands[4], GEN_INT(0), operands[2]));
2401 emit_insn (gen_subsi3(operands[5], GEN_INT(7), operands[2]));
2402 })
2403
2404 (define_insn_and_split "shrqbybi_<mode>"
2405 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") 2413 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
2406 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") 2414 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
2407 (and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I") 2415 (and:SI (neg:SI (and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")
2408 (const_int -8)))) 2416 (const_int -8)))
2409 (clobber (match_scratch:SI 3 "=&r,X"))]
2410 ""
2411 "#"
2412 "reload_completed"
2413 [(set (match_dup:DTI 0)
2414 (lshiftrt:DTI (match_dup:DTI 1)
2415 (and:SI (neg:SI (and:SI (match_dup:SI 3) (const_int -8)))
2416 (const_int -8))))] 2417 (const_int -8))))]
2418 ""
2417 { 2419 {
2418 if (GET_CODE (operands[2]) == CONST_INT) 2420 if (GET_CODE (operands[2]) == CONST_INT)
2419 operands[3] = GEN_INT (7 - INTVAL (operands[2])); 2421 operands[2] = GEN_INT (7 - INTVAL (operands[2]));
2420 else 2422 else
2421 emit_insn (gen_subsi3 (operands[3], GEN_INT (7), operands[2])); 2423 {
2422 } 2424 rtx t0 = gen_reg_rtx (SImode);
2423 [(set_attr "type" "shuf")]) 2425 emit_insn (gen_subsi3 (t0, GEN_INT (7), operands[2]));
2426 operands[2] = t0;
2427 }
2428 })
2424 2429
2425 (define_insn "rotqmbybi_<mode>" 2430 (define_insn "rotqmbybi_<mode>"
2426 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") 2431 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
2427 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") 2432 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
2428 (and:SI (neg:SI (and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I") 2433 (and:SI (neg:SI (and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")
2463 "@ 2468 "@
2464 rotqmbi\t%0,%1,%2 2469 rotqmbi\t%0,%1,%2
2465 rotqmbii\t%0,%1,-%E2" 2470 rotqmbii\t%0,%1,-%E2"
2466 [(set_attr "type" "shuf")]) 2471 [(set_attr "type" "shuf")])
2467 2472
2468 (define_insn_and_split "shrqby_<mode>" 2473 (define_expand "shrqby_<mode>"
2469 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") 2474 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
2470 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") 2475 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
2471 (mult:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I") 2476 (mult:SI (neg:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I"))
2472 (const_int 8)))) 2477 (const_int 8))))]
2473 (clobber (match_scratch:SI 3 "=&r,X"))] 2478 ""
2474 ""
2475 "#"
2476 "reload_completed"
2477 [(set (match_dup:DTI 0)
2478 (lshiftrt:DTI (match_dup:DTI 1)
2479 (mult:SI (neg:SI (match_dup:SI 3)) (const_int 8))))]
2480 { 2479 {
2481 if (GET_CODE (operands[2]) == CONST_INT) 2480 if (GET_CODE (operands[2]) == CONST_INT)
2482 operands[3] = GEN_INT (-INTVAL (operands[2])); 2481 operands[2] = GEN_INT (-INTVAL (operands[2]));
2483 else 2482 else
2484 emit_insn (gen_subsi3 (operands[3], GEN_INT (0), operands[2])); 2483 {
2485 } 2484 rtx t0 = gen_reg_rtx (SImode);
2486 [(set_attr "type" "shuf")]) 2485 emit_insn (gen_subsi3 (t0, GEN_INT (0), operands[2]));
2486 operands[2] = t0;
2487 }
2488 })
2487 2489
2488 (define_insn "rotqmby_<mode>" 2490 (define_insn "rotqmby_<mode>"
2489 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") 2491 [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
2490 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") 2492 (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
2491 (mult:SI (neg:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")) 2493 (mult:SI (neg:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I"))
2515 (ashiftrt:VHSI (match_dup:VHSI 1) 2517 (ashiftrt:VHSI (match_dup:VHSI 1)
2516 (neg:VHSI (match_dup:VHSI 3))))] 2518 (neg:VHSI (match_dup:VHSI 3))))]
2517 "" 2519 ""
2518 [(set_attr "type" "*,fx3")]) 2520 [(set_attr "type" "*,fx3")])
2519 2521
2522 (define_insn "<v>ashr<mode>3_imm"
2523 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r")
2524 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r")
2525 (match_operand:VHSI 2 "immediate_operand" "W")))]
2526 ""
2527 "rotma<bh>i\t%0,%1,-%<umask>2"
2528 [(set_attr "type" "fx3")])
2529
2520 2530
2521 (define_insn "rotma_<mode>" 2531 (define_insn "rotma_<mode>"
2522 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r") 2532 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
2523 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r") 2533 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
2524 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))] 2534 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))]
2599 } 2609 }
2600 DONE; 2610 DONE;
2601 }) 2611 })
2602 2612
2603 2613
2604 (define_expand "ashrti3" 2614 (define_insn_and_split "ashrti3"
2605 [(set (match_operand:TI 0 "spu_reg_operand" "") 2615 [(set (match_operand:TI 0 "spu_reg_operand" "=r,r")
2606 (ashiftrt:TI (match_operand:TI 1 "spu_reg_operand" "") 2616 (ashiftrt:TI (match_operand:TI 1 "spu_reg_operand" "r,r")
2607 (match_operand:SI 2 "spu_nonmem_operand" "")))] 2617 (match_operand:SI 2 "spu_nonmem_operand" "r,i")))]
2608 "" 2618 ""
2619 "#"
2620 ""
2621 [(set (match_dup:TI 0)
2622 (ashiftrt:TI (match_dup:TI 1)
2623 (match_dup:SI 2)))]
2609 { 2624 {
2610 rtx sign_shift = gen_reg_rtx (SImode); 2625 rtx sign_shift = gen_reg_rtx (SImode);
2611 rtx sign_mask = gen_reg_rtx (TImode); 2626 rtx sign_mask = gen_reg_rtx (TImode);
2612 rtx sign_mask_v4si = gen_rtx_SUBREG (V4SImode, sign_mask, 0); 2627 rtx sign_mask_v4si = gen_rtx_SUBREG (V4SImode, sign_mask, 0);
2613 rtx op1_v4si = spu_gen_subreg (V4SImode, operands[1]); 2628 rtx op1_v4si = spu_gen_subreg (V4SImode, operands[1]);
2688 rotqbii\t%0,%1,%e2" 2703 rotqbii\t%0,%1,%e2"
2689 [(set_attr "type" "shuf,shuf")]) 2704 [(set_attr "type" "shuf,shuf")])
2690 2705
2691 2706
2692 ;; struct extract/insert 2707 ;; struct extract/insert
2693 ;; We have to handle mem's because GCC will generate invalid SUBREG's 2708 ;; We handle mem's because GCC will generate invalid SUBREG's
2694 ;; if it handles them. We generate better code anyway. 2709 ;; and inefficient code.
2695 2710
2696 (define_expand "extv" 2711 (define_expand "extv"
2697 [(set (match_operand 0 "register_operand" "") 2712 [(set (match_operand:TI 0 "register_operand" "")
2698 (sign_extract (match_operand 1 "register_operand" "") 2713 (sign_extract:TI (match_operand 1 "nonimmediate_operand" "")
2699 (match_operand:SI 2 "const_int_operand" "")
2700 (match_operand:SI 3 "const_int_operand" "")))]
2701 ""
2702 { spu_expand_extv(operands, 0); DONE; })
2703
2704 (define_expand "extzv"
2705 [(set (match_operand 0 "register_operand" "")
2706 (zero_extract (match_operand 1 "register_operand" "")
2707 (match_operand:SI 2 "const_int_operand" "") 2714 (match_operand:SI 2 "const_int_operand" "")
2708 (match_operand:SI 3 "const_int_operand" "")))] 2715 (match_operand:SI 3 "const_int_operand" "")))]
2709 "" 2716 ""
2710 { spu_expand_extv(operands, 1); DONE; }) 2717 {
2718 spu_expand_extv (operands, 0);
2719 DONE;
2720 })
2721
2722 (define_expand "extzv"
2723 [(set (match_operand:TI 0 "register_operand" "")
2724 (zero_extract:TI (match_operand 1 "nonimmediate_operand" "")
2725 (match_operand:SI 2 "const_int_operand" "")
2726 (match_operand:SI 3 "const_int_operand" "")))]
2727 ""
2728 {
2729 spu_expand_extv (operands, 1);
2730 DONE;
2731 })
2711 2732
2712 (define_expand "insv" 2733 (define_expand "insv"
2713 [(set (zero_extract (match_operand 0 "register_operand" "") 2734 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2714 (match_operand:SI 1 "const_int_operand" "") 2735 (match_operand:SI 1 "const_int_operand" "")
2715 (match_operand:SI 2 "const_int_operand" "")) 2736 (match_operand:SI 2 "const_int_operand" ""))
2716 (match_operand 3 "nonmemory_operand" ""))] 2737 (match_operand 3 "nonmemory_operand" ""))]
2717 "" 2738 ""
2718 { spu_expand_insv(operands); DONE; }) 2739 { spu_expand_insv(operands); DONE; })
2740
2741 ;; Simplify a number of patterns that get generated by extv, extzv,
2742 ;; insv, and loads.
2743 (define_insn_and_split "trunc_shr_ti<mode>"
2744 [(set (match_operand:QHSI 0 "spu_reg_operand" "=r")
2745 (truncate:QHSI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "0")
2746 (const_int 96)])))]
2747 ""
2748 "#"
2749 "reload_completed"
2750 [(const_int 0)]
2751 {
2752 spu_split_convert (operands);
2753 DONE;
2754 }
2755 [(set_attr "type" "convert")
2756 (set_attr "length" "0")])
2757
2758 (define_insn_and_split "trunc_shr_tidi"
2759 [(set (match_operand:DI 0 "spu_reg_operand" "=r")
2760 (truncate:DI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "0")
2761 (const_int 64)])))]
2762 ""
2763 "#"
2764 "reload_completed"
2765 [(const_int 0)]
2766 {
2767 spu_split_convert (operands);
2768 DONE;
2769 }
2770 [(set_attr "type" "convert")
2771 (set_attr "length" "0")])
2772
2773 (define_insn_and_split "shl_ext_<mode>ti"
2774 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
2775 (ashift:TI (match_operator:TI 2 "extend_operator" [(match_operand:QHSI 1 "spu_reg_operand" "0")])
2776 (const_int 96)))]
2777 ""
2778 "#"
2779 "reload_completed"
2780 [(const_int 0)]
2781 {
2782 spu_split_convert (operands);
2783 DONE;
2784 }
2785 [(set_attr "type" "convert")
2786 (set_attr "length" "0")])
2787
2788 (define_insn_and_split "shl_ext_diti"
2789 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
2790 (ashift:TI (match_operator:TI 2 "extend_operator" [(match_operand:DI 1 "spu_reg_operand" "0")])
2791 (const_int 64)))]
2792 ""
2793 "#"
2794 "reload_completed"
2795 [(const_int 0)]
2796 {
2797 spu_split_convert (operands);
2798 DONE;
2799 }
2800 [(set_attr "type" "convert")
2801 (set_attr "length" "0")])
2802
2803 (define_insn "sext_trunc_lshr_tiqisi"
2804 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
2805 (sign_extend:SI (truncate:QI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "r")
2806 (const_int 120)]))))]
2807 ""
2808 "rotmai\t%0,%1,-24"
2809 [(set_attr "type" "fx3")])
2810
2811 (define_insn "zext_trunc_lshr_tiqisi"
2812 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
2813 (zero_extend:SI (truncate:QI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "r")
2814 (const_int 120)]))))]
2815 ""
2816 "rotmi\t%0,%1,-24"
2817 [(set_attr "type" "fx3")])
2818
2819 (define_insn "sext_trunc_lshr_tihisi"
2820 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
2821 (sign_extend:SI (truncate:HI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "r")
2822 (const_int 112)]))))]
2823 ""
2824 "rotmai\t%0,%1,-16"
2825 [(set_attr "type" "fx3")])
2826
2827 (define_insn "zext_trunc_lshr_tihisi"
2828 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
2829 (zero_extend:SI (truncate:HI (match_operator:TI 2 "shiftrt_operator" [(match_operand:TI 1 "spu_reg_operand" "r")
2830 (const_int 112)]))))]
2831 ""
2832 "rotmi\t%0,%1,-16"
2833 [(set_attr "type" "fx3")])
2719 2834
2720 2835
2721 ;; String/block move insn. 2836 ;; String/block move insn.
2722 ;; Argument 0 is the destination 2837 ;; Argument 0 is the destination
2723 ;; Argument 1 is the source 2838 ;; Argument 1 is the source
4367 PUT_MODE (SET_SRC (c), GET_MODE (operands[0])); 4482 PUT_MODE (SET_SRC (c), GET_MODE (operands[0]));
4368 emit_insn (c); 4483 emit_insn (c);
4369 DONE; 4484 DONE;
4370 }) 4485 })
4371 4486
4372 (define_insn "_spu_convert" 4487 (define_insn_and_split "_spu_convert"
4373 [(set (match_operand 0 "spu_reg_operand" "=r") 4488 [(set (match_operand 0 "spu_reg_operand" "=r")
4374 (unspec [(match_operand 1 "spu_reg_operand" "0")] UNSPEC_CONVERT))] 4489 (unspec [(match_operand 1 "spu_reg_operand" "0")] UNSPEC_CONVERT))]
4375 "operands" 4490 ""
4376 "" 4491 "#"
4492 "reload_completed"
4493 [(const_int 0)]
4494 {
4495 spu_split_convert (operands);
4496 DONE;
4497 }
4377 [(set_attr "type" "convert") 4498 [(set_attr "type" "convert")
4378 (set_attr "length" "0")]) 4499 (set_attr "length" "0")])
4379
4380 (define_peephole2
4381 [(set (match_operand 0 "spu_reg_operand")
4382 (unspec [(match_operand 1 "spu_reg_operand")] UNSPEC_CONVERT))]
4383 ""
4384 [(use (const_int 0))]
4385 "")
4386 4500
4387 4501
4388 ;; 4502 ;;
4389 (include "spu-builtins.md") 4503 (include "spu-builtins.md")
4390 4504
5250 5364
5251 DONE; 5365 DONE;
5252 }") 5366 }")
5253 5367
5254 (define_insn "stack_protect_set" 5368 (define_insn "stack_protect_set"
5255 [(set (match_operand:SI 0 "spu_mem_operand" "=m") 5369 [(set (match_operand:SI 0 "memory_operand" "=m")
5256 (unspec:SI [(match_operand:SI 1 "spu_mem_operand" "m")] UNSPEC_SP_SET)) 5370 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
5257 (set (match_scratch:SI 2 "=&r") (const_int 0))] 5371 (set (match_scratch:SI 2 "=&r") (const_int 0))]
5258 "" 5372 ""
5259 "lq%p1\t%2,%1\;stq%p0\t%2,%0\;xor\t%2,%2,%2" 5373 "lq%p1\t%2,%1\;stq%p0\t%2,%0\;xor\t%2,%2,%2"
5260 [(set_attr "length" "12") 5374 [(set_attr "length" "12")
5261 (set_attr "type" "multi1")] 5375 (set_attr "type" "multi1")]
5262 ) 5376 )
5263 5377
5264 (define_expand "stack_protect_test" 5378 (define_expand "stack_protect_test"
5265 [(match_operand 0 "spu_mem_operand" "") 5379 [(match_operand 0 "memory_operand" "")
5266 (match_operand 1 "spu_mem_operand" "") 5380 (match_operand 1 "memory_operand" "")
5267 (match_operand 2 "" "")] 5381 (match_operand 2 "" "")]
5268 "" 5382 ""
5269 { 5383 {
5270 rtx compare_result; 5384 rtx compare_result;
5271 rtx bcomp, loc_ref; 5385 rtx bcomp, loc_ref;
5287 DONE; 5401 DONE;
5288 }) 5402 })
5289 5403
5290 (define_insn "stack_protect_test_si" 5404 (define_insn "stack_protect_test_si"
5291 [(set (match_operand:SI 0 "spu_reg_operand" "=&r") 5405 [(set (match_operand:SI 0 "spu_reg_operand" "=&r")
5292 (unspec:SI [(match_operand:SI 1 "spu_mem_operand" "m") 5406 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
5293 (match_operand:SI 2 "spu_mem_operand" "m")] 5407 (match_operand:SI 2 "memory_operand" "m")]
5294 UNSPEC_SP_TEST)) 5408 UNSPEC_SP_TEST))
5295 (set (match_scratch:SI 3 "=&r") (const_int 0))] 5409 (set (match_scratch:SI 3 "=&r") (const_int 0))]
5296 "" 5410 ""
5297 "lq%p1\t%0,%1\;lq%p2\t%3,%2\;ceq\t%0,%0,%3\;xor\t%3,%3,%3" 5411 "lq%p1\t%0,%1\;lq%p2\t%3,%2\;ceq\t%0,%0,%3\;xor\t%3,%3,%3"
5298 [(set_attr "length" "16") 5412 [(set_attr "length" "16")