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comparison gcc/config/arm/fa526.md @ 68:561a7518be6b

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update gcc-4.6
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 21 Aug 2011 07:07:55 +0900
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children 04ced10e8804
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67:f6334be47118 68:561a7518be6b
1 ;; Faraday FA526 Pipeline Description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
4
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
10 ;; version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 ;; for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
20
21 ;; These descriptions are based on the information contained in the
22 ;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
23 ;;
24 ;; Modeled pipeline characteristics:
25 ;; LD -> any use: latency = 3 (2 cycle penalty).
26 ;; ALU -> any use: latency = 2 (1 cycle penalty).
27
28 ;; This automaton provides a pipeline description for the Faraday
29 ;; FA526 core.
30 ;;
31 ;; The model given here assumes that the condition for all conditional
32 ;; instructions is "true", i.e., that all of the instructions are
33 ;; actually executed.
34
35 (define_automaton "fa526")
36
37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38 ;; Pipelines
39 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
40
41 ;; There is a single pipeline
42 ;;
43 ;; The ALU pipeline has fetch, decode, execute, memory, and
44 ;; write stages. We only need to model the execute, memory and write
45 ;; stages.
46
47 ;; S E M W
48
49 (define_cpu_unit "fa526_core" "fa526")
50
51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
52 ;; ALU Instructions
53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54
55 ;; ALU instructions require two cycles to execute, and use the ALU
56 ;; pipeline in each of the three stages. The results are available
57 ;; after the execute stage stage has finished.
58 ;;
59 ;; If the destination register is the PC, the pipelines are stalled
60 ;; for several cycles. That case is not modeled here.
61
62 ;; ALU operations
63 (define_insn_reservation "526_alu_op" 1
64 (and (eq_attr "tune" "fa526")
65 (eq_attr "type" "alu"))
66 "fa526_core")
67
68 (define_insn_reservation "526_alu_shift_op" 2
69 (and (eq_attr "tune" "fa526")
70 (eq_attr "type" "alu_shift,alu_shift_reg"))
71 "fa526_core")
72
73 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
74 ;; Multiplication Instructions
75 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
76
77 (define_insn_reservation "526_mult1" 2
78 (and (eq_attr "tune" "fa526")
79 (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy"))
80 "fa526_core")
81
82 (define_insn_reservation "526_mult2" 5
83 (and (eq_attr "tune" "fa526")
84 (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
85 umlals,smulls,smlals,smlawx"))
86 "fa526_core*4")
87
88 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
89 ;; Load/Store Instructions
90 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
91
92 ;; The models for load/store instructions do not accurately describe
93 ;; the difference between operations with a base register writeback
94 ;; (such as "ldm!"). These models assume that all memory references
95 ;; hit in dcache.
96
97 (define_insn_reservation "526_load1_op" 3
98 (and (eq_attr "tune" "fa526")
99 (eq_attr "type" "load1,load_byte"))
100 "fa526_core")
101
102 (define_insn_reservation "526_load2_op" 4
103 (and (eq_attr "tune" "fa526")
104 (eq_attr "type" "load2"))
105 "fa526_core*2")
106
107 (define_insn_reservation "526_load3_op" 5
108 (and (eq_attr "tune" "fa526")
109 (eq_attr "type" "load3"))
110 "fa526_core*3")
111
112 (define_insn_reservation "526_load4_op" 6
113 (and (eq_attr "tune" "fa526")
114 (eq_attr "type" "load4"))
115 "fa526_core*4")
116
117 (define_insn_reservation "526_store1_op" 0
118 (and (eq_attr "tune" "fa526")
119 (eq_attr "type" "store1"))
120 "fa526_core")
121
122 (define_insn_reservation "526_store2_op" 1
123 (and (eq_attr "tune" "fa526")
124 (eq_attr "type" "store2"))
125 "fa526_core*2")
126
127 (define_insn_reservation "526_store3_op" 2
128 (and (eq_attr "tune" "fa526")
129 (eq_attr "type" "store3"))
130 "fa526_core*3")
131
132 (define_insn_reservation "526_store4_op" 3
133 (and (eq_attr "tune" "fa526")
134 (eq_attr "type" "store4"))
135 "fa526_core*4")
136
137 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
138 ;; Branch and Call Instructions
139 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
140
141 ;; Branch instructions are difficult to model accurately. The FA526
142 ;; core can predict most branches. If the branch is predicted
143 ;; correctly, and predicted early enough, the branch can be completely
144 ;; eliminated from the instruction stream. Some branches can
145 ;; therefore appear to require zero cycle to execute. We assume that
146 ;; all branches are predicted correctly, and that the latency is
147 ;; therefore the minimum value.
148
149 (define_insn_reservation "526_branch_op" 0
150 (and (eq_attr "tune" "fa526")
151 (eq_attr "type" "branch"))
152 "fa526_core")
153
154 ;; The latency for a call is actually the latency when the result is available.
155 ;; i.e. R0 ready for int return value. For most cases, the return value is set
156 ;; by a mov instruction, which has 1 cycle latency.
157 (define_insn_reservation "526_call_op" 1
158 (and (eq_attr "tune" "fa526")
159 (eq_attr "type" "call"))
160 "fa526_core")
161