Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/arm/iterators.md @ 68:561a7518be6b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update gcc-4.6
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 21 Aug 2011 07:07:55 +0900
parents
children 04ced10e8804
comparison
equal deleted inserted replaced
67:f6334be47118 68:561a7518be6b
1 ;; Code and mode itertator and attribute definitions for the ARM backend
2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21
22 ;;----------------------------------------------------------------------------
23 ;; Mode iterators
24 ;;----------------------------------------------------------------------------
25
26 ;; A list of modes that are exactly 64 bits in size. This is used to expand
27 ;; some splits that are the same for all modes when operating on ARM
28 ;; registers.
29 (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
30
31 (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
32
33 ;; A list of integer modes that are up to one word long
34 (define_mode_iterator QHSI [QI HI SI])
35
36 ;; Integer element sizes implemented by IWMMXT.
37 (define_mode_iterator VMMX [V2SI V4HI V8QI])
38
39 ;; Integer element sizes for shifts.
40 (define_mode_iterator VSHFT [V4HI V2SI DI])
41
42 ;; Integer and float modes supported by Neon and IWMMXT.
43 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
44
45 ;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
46 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
47
48 ;; Integer modes supported by Neon and IWMMXT
49 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
50
51 ;; Integer modes supported by Neon and IWMMXT, except V2DI
52 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
53
54 ;; Double-width vector modes.
55 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
56
57 ;; Double-width vector modes plus 64-bit elements.
58 (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
59
60 ;; Double-width vector modes without floating-point elements.
61 (define_mode_iterator VDI [V8QI V4HI V2SI])
62
63 ;; Quad-width vector modes.
64 (define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
65
66 ;; Quad-width vector modes plus 64-bit elements.
67 (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
68
69 ;; Quad-width vector modes without floating-point elements.
70 (define_mode_iterator VQI [V16QI V8HI V4SI])
71
72 ;; Quad-width vector modes, with TImode added, for moves.
73 (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
74
75 ;; Opaque structure types wider than TImode.
76 (define_mode_iterator VSTRUCT [EI OI CI XI])
77
78 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
79 (define_mode_iterator VTAB [TI EI OI])
80
81 ;; Widenable modes.
82 (define_mode_iterator VW [V8QI V4HI V2SI])
83
84 ;; Narrowable modes.
85 (define_mode_iterator VN [V8HI V4SI V2DI])
86
87 ;; All supported vector modes (except singleton DImode).
88 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
89
90 ;; All supported vector modes (except those with 64-bit integer elements).
91 (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
92
93 ;; Supported integer vector modes (not 64 bit elements).
94 (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
95
96 ;; Supported integer vector modes (not singleton DI)
97 (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
98
99 ;; Vector modes, including 64-bit integer elements.
100 (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
101
102 ;; Vector modes including 64-bit integer elements, but no floats.
103 (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
104
105 ;; Vector modes for float->int conversions.
106 (define_mode_iterator VCVTF [V2SF V4SF])
107
108 ;; Vector modes form int->float conversions.
109 (define_mode_iterator VCVTI [V2SI V4SI])
110
111 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
112 (define_mode_iterator VMD [V4HI V2SI V2SF])
113
114 ;; Vector modes for quadword multiply-accumulate, etc. insns.
115 (define_mode_iterator VMQ [V8HI V4SI V4SF])
116
117 ;; Above modes combined.
118 (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
119
120 ;; As VMD, but integer modes only.
121 (define_mode_iterator VMDI [V4HI V2SI])
122
123 ;; As VMQ, but integer modes only.
124 (define_mode_iterator VMQI [V8HI V4SI])
125
126 ;; Above modes combined.
127 (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
128
129 ;; Modes with 8-bit and 16-bit elements.
130 (define_mode_iterator VX [V8QI V4HI V16QI V8HI])
131
132 ;; Modes with 8-bit elements.
133 (define_mode_iterator VE [V8QI V16QI])
134
135 ;; Modes with 64-bit elements only.
136 (define_mode_iterator V64 [DI V2DI])
137
138 ;; Modes with 32-bit elements only.
139 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
140
141 ;; Modes with 8-bit, 16-bit and 32-bit elements.
142 (define_mode_iterator VU [V16QI V8HI V4SI])
143
144 ;;----------------------------------------------------------------------------
145 ;; Code iterators
146 ;;----------------------------------------------------------------------------
147
148 ;; A list of condition codes used in compare instructions where
149 ;; the carry flag from the addition is used instead of doing the
150 ;; compare a second time.
151 (define_code_iterator LTUGEU [ltu geu])
152
153 ;; A list of ...
154 (define_code_iterator ior_xor [ior xor])
155
156 ;; Operations on two halves of a quadword vector.
157 (define_code_iterator vqh_ops [plus smin smax umin umax])
158
159 ;; Operations on two halves of a quadword vector,
160 ;; without unsigned variants (for use with *SFmode pattern).
161 (define_code_iterator vqhs_ops [plus smin smax])
162
163 ;; A list of widening operators
164 (define_code_iterator SE [sign_extend zero_extend])
165
166 ;;----------------------------------------------------------------------------
167 ;; Mode attributes
168 ;;----------------------------------------------------------------------------
169
170 ;; Determine element size suffix from vector mode.
171 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
172
173 ;; vtbl<n> suffix for NEON vector modes.
174 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
175
176 ;; (Opposite) mode to convert to/from for NEON mode conversions.
177 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
178 (V4SI "V4SF") (V4SF "V4SI")])
179
180 ;; Define element mode for each vector mode.
181 (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
182 (V4HI "HI") (V8HI "HI")
183 (V2SI "SI") (V4SI "SI")
184 (V2SF "SF") (V4SF "SF")
185 (DI "DI") (V2DI "DI")])
186
187 ;; Element modes for vector extraction, padded up to register size.
188
189 (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
190 (V4HI "SI") (V8HI "SI")
191 (V2SI "SI") (V4SI "SI")
192 (V2SF "SF") (V4SF "SF")
193 (DI "DI") (V2DI "DI")])
194
195 ;; Mode of pair of elements for each vector mode, to define transfer
196 ;; size for structure lane/dup loads and stores.
197 (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
198 (V4HI "SI") (V8HI "SI")
199 (V2SI "V2SI") (V4SI "V2SI")
200 (V2SF "V2SF") (V4SF "V2SF")
201 (DI "V2DI") (V2DI "V2DI")])
202
203 ;; Similar, for three elements.
204 ;; ??? Should we define extra modes so that sizes of all three-element
205 ;; accesses can be accurately represented?
206 (define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
207 (V4HI "V4HI") (V8HI "V4HI")
208 (V2SI "V4SI") (V4SI "V4SI")
209 (V2SF "V4SF") (V4SF "V4SF")
210 (DI "EI") (V2DI "EI")])
211
212 ;; Similar, for four elements.
213 (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
214 (V4HI "V4HI") (V8HI "V4HI")
215 (V2SI "V4SI") (V4SI "V4SI")
216 (V2SF "V4SF") (V4SF "V4SF")
217 (DI "OI") (V2DI "OI")])
218
219 ;; Register width from element mode
220 (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
221 (V4HI "P") (V8HI "q")
222 (V2SI "P") (V4SI "q")
223 (V2SF "P") (V4SF "q")
224 (DI "P") (V2DI "q")])
225
226 ;; Wider modes with the same number of elements.
227 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
228
229 ;; Narrower modes with the same number of elements.
230 (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
231
232 ;; Narrower modes with double the number of elements.
233 (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
234 (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
235
236 ;; Modes with half the number of equal-sized elements.
237 (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
238 (V4SI "V2SI") (V4SF "V2SF") (V2DF "DF")
239 (V2DI "DI")])
240
241 ;; Same, but lower-case.
242 (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
243 (V4SI "v2si") (V4SF "v2sf")
244 (V2DI "di")])
245
246 ;; Modes with twice the number of equal-sized elements.
247 (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
248 (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
249 (DI "V2DI")])
250
251 ;; Same, but lower-case.
252 (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
253 (V2SI "v4si") (V2SF "v4sf")
254 (DI "v2di")])
255
256 ;; Modes with double-width elements.
257 (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
258 (V4HI "V2SI") (V8HI "V4SI")
259 (V2SI "DI") (V4SI "V2DI")])
260
261 ;; Double-sized modes with the same element size.
262 ;; Used for neon_vdup_lane, where the second operand is double-sized
263 ;; even when the first one is quad.
264 (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
265 (V4SI "V2SI") (V4SF "V2SF")
266 (V8QI "V8QI") (V4HI "V4HI")
267 (V2SI "V2SI") (V2SF "V2SF")])
268
269 ;; Mode of result of comparison operations (and bit-select operand 1).
270 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
271 (V4HI "V4HI") (V8HI "V8HI")
272 (V2SI "V2SI") (V4SI "V4SI")
273 (V2SF "V2SI") (V4SF "V4SI")
274 (DI "DI") (V2DI "V2DI")])
275
276 ;; Get element type from double-width mode, for operations where we
277 ;; don't care about signedness.
278 (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
279 (V4HI "i16") (V8HI "i16")
280 (V2SI "i32") (V4SI "i32")
281 (DI "i64") (V2DI "i64")
282 (V2SF "f32") (V4SF "f32")])
283
284 ;; Same, but for operations which work on signed values.
285 (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
286 (V4HI "s16") (V8HI "s16")
287 (V2SI "s32") (V4SI "s32")
288 (DI "s64") (V2DI "s64")
289 (V2SF "f32") (V4SF "f32")])
290
291 ;; Same, but for operations which work on unsigned values.
292 (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
293 (V4HI "u16") (V8HI "u16")
294 (V2SI "u32") (V4SI "u32")
295 (DI "u64") (V2DI "u64")
296 (V2SF "f32") (V4SF "f32")])
297
298 ;; Element types for extraction of unsigned scalars.
299 (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
300 (V4HI "u16") (V8HI "u16")
301 (V2SI "32") (V4SI "32")
302 (V2SF "32") (V4SF "32")])
303
304 (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
305 (V4HI "16") (V8HI "16")
306 (V2SI "32") (V4SI "32")
307 (DI "64") (V2DI "64")
308 (V2SF "32") (V4SF "32")])
309
310 ;; Element sizes for duplicating ARM registers to all elements of a vector.
311 (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
312
313 ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
314 (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
315 (V4HI "TI") (V8HI "OI")
316 (V2SI "TI") (V4SI "OI")
317 (V2SF "TI") (V4SF "OI")
318 (DI "TI") (V2DI "OI")])
319
320 ;; Same, but lower-case.
321 (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
322 (V4HI "ti") (V8HI "oi")
323 (V2SI "ti") (V4SI "oi")
324 (V2SF "ti") (V4SF "oi")
325 (DI "ti") (V2DI "oi")])
326
327 ;; Extra suffix on some 64-bit insn names (to avoid collision with standard
328 ;; names which we don't want to define).
329 (define_mode_attr V_suf64 [(V8QI "") (V16QI "")
330 (V4HI "") (V8HI "")
331 (V2SI "") (V4SI "")
332 (V2SF "") (V4SF "")
333 (DI "_neon") (V2DI "")])
334
335
336 ;; Scalars to be presented to scalar multiplication instructions
337 ;; must satisfy the following constraints.
338 ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
339 ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
340
341 ;; This mode attribute is used to obtain the correct register constraints.
342
343 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
344 (V8HI "x") (V4SI "t") (V4SF "t")])
345
346 ;; Predicates used for setting neon_type
347
348 (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
349 (V4HI "false") (V8HI "false")
350 (V2SI "false") (V4SI "false")
351 (V2SF "true") (V4SF "true")
352 (DI "false") (V2DI "false")])
353
354 (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
355 (V4HI "true") (V8HI "true")
356 (V2SI "false") (V4SI "false")
357 (V2SF "false") (V4SF "false")
358 (DI "false") (V2DI "false")])
359
360
361 (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
362 (V4HI "true") (V8HI "false")
363 (V2SI "true") (V4SI "false")
364 (V2SF "true") (V4SF "false")
365 (DI "true") (V2DI "false")])
366
367 (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
368 (V4HI "4") (V8HI "8")
369 (V2SI "2") (V4SI "4")
370 (V2SF "2") (V4SF "4")
371 (DI "1") (V2DI "2")
372 (DF "1") (V2DF "2")])
373
374 ;; Same as V_widen, but lower-case.
375 (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
376
377 ;; Widen. Result is half the number of elements, but widened to double-width.
378 (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
379
380 ;; Conditions to be used in extend<mode>di patterns.
381 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
382 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
383 (QI "&& arm_arch6")])
384 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
385 (HI "nonimmediate_operand")
386 (QI "nonimmediate_operand")])
387 (define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
388
389 ;;----------------------------------------------------------------------------
390 ;; Code attributes
391 ;;----------------------------------------------------------------------------
392
393 ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
394 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
395 (umin "vmin") (umax "vmax")])
396
397 ;; Signs of above, where relevant.
398 (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
399 (umax "u")])
400
401 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
402 (define_code_attr optab [(ltu "ltu") (geu "geu")])
403
404 ;; Assembler mnemonics for signedness of widening operations.
405 (define_code_attr US [(sign_extend "s") (zero_extend "u")])