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comparison gcc/config/microblaze/microblaze.h @ 68:561a7518be6b

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update gcc-4.6
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 21 Aug 2011 07:07:55 +0900
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children 04ced10e8804
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67:f6334be47118 68:561a7518be6b
1 /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
2 Copyright 2009, 2010, 2011 Free Software Foundation, Inc.
3
4 Contributed by Michael Eager <eager@eagercon.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* Standard GCC variables that we reference. */
23
24 /* MicroBlaze external variables defined in microblaze.c. */
25
26 /* Which pipeline to schedule for. */
27 enum pipeline_type
28 {
29 MICROBLAZE_PIPE_3 = 0,
30 MICROBLAZE_PIPE_5 = 1
31 };
32
33 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
34
35 /* print_operand punctuation chars */
36 extern char microblaze_print_operand_punct[];
37
38 /* # bytes of data/sdata cutoff */
39 extern int microblaze_section_threshold;
40
41 /* Map register # to debug register # */
42 extern int microblaze_dbx_regno[];
43
44 extern int microblaze_no_unsafe_delay;
45 extern enum pipeline_type microblaze_pipe;
46
47 #define OBJECT_FORMAT_ELF
48
49 /* Default target_flags if no switches are specified */
50 #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT)
51
52 /* What is the default setting for -mcpu= . We set it to v4.00.a even though
53 we are actually ahead. This is safest version that has generate code
54 compatible for the original ISA */
55 #define MICROBLAZE_DEFAULT_CPU "v4.00.a"
56
57 /* Macros to decide whether certain features are available or not,
58 depending on the instruction set architecture level. */
59
60 #define DRIVER_SELF_SPECS \
61 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \
62 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
63 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
64 "%{mxl-soft-div:%<mno-xl-soft-div}", \
65 "%{msoft-float:%<mhard-float}"
66
67 /* Tell collect what flags to pass to nm. */
68 #ifndef NM_FLAGS
69 #define NM_FLAGS "-Bn"
70 #endif
71
72 /* Names to predefine in the preprocessor for this target machine. */
73 #define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
74
75 /* Assembler specs. */
76
77 #define TARGET_ASM_SPEC ""
78
79 #define ASM_SPEC "\
80 %(target_asm_spec)"
81
82 /* Extra switches sometimes passed to the linker. */
83 /* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
84
85 #define LINK_SPEC "%{shared:-shared} -N -relax \
86 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
87 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
88 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
89 %{!T*: -dT xilinx.ld%s}"
90
91 /* Specs for the compiler proper */
92
93 #ifndef CC1_SPEC
94 #define CC1_SPEC " \
95 %{G*} \
96 %(subtarget_cc1_spec) \
97 %{mxl-multiply-high:-mcpu=v6.00.a} \
98 "
99 #endif
100
101 #define EXTRA_SPECS \
102 { "target_asm_spec", TARGET_ASM_SPEC }, \
103 SUBTARGET_EXTRA_SPECS
104
105 /* Print subsidiary information on the compiler version in use. */
106 #define MICROBLAZE_VERSION MICROBLAZE_DEFAULT_CPU
107
108 #ifndef MACHINE_TYPE
109 #define MACHINE_TYPE "MicroBlaze/ELF"
110 #endif
111
112 #ifndef TARGET_VERSION_INTERNAL
113 #define TARGET_VERSION_INTERNAL(STREAM) \
114 fprintf (STREAM, " %s %s", MACHINE_TYPE, MICROBLAZE_VERSION)
115 #endif
116
117 #ifndef TARGET_VERSION
118 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
119 #endif
120
121 /* Local compiler-generated symbols must have a prefix that the assembler
122 understands. */
123
124 #ifndef LOCAL_LABEL_PREFIX
125 #define LOCAL_LABEL_PREFIX "$"
126 #endif
127
128 /* fixed registers. */
129 #define MB_ABI_BASE_REGNUM 0
130 #define MB_ABI_STACK_POINTER_REGNUM 1
131 #define MB_ABI_GPRO_REGNUM 2
132 #define MB_ABI_GPRW_REGNUM 13
133 #define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
134 #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
135 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
136 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
137 #define MB_ABI_ASM_TEMP_REGNUM 18
138 /* This is our temp register. */
139 #define MB_ABI_FRAME_POINTER_REGNUM 19
140 #define MB_ABI_PIC_ADDR_REGNUM 20
141 #define MB_ABI_PIC_FUNC_REGNUM 21
142 /* Volatile registers. */
143 #define MB_ABI_INT_RETURN_VAL_REGNUM 3
144 #define MB_ABI_INT_RETURN_VAL2_REGNUM 4
145 #define MB_ABI_FIRST_ARG_REGNUM 5
146 #define MB_ABI_LAST_ARG_REGNUM 10
147 #define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
148 - MB_ABI_FIRST_ARG_REGNUM + 1)
149 #define MB_ABI_STATIC_CHAIN_REGNUM 3
150 #define MB_ABI_TEMP1_REGNUM 11
151 #define MB_ABI_TEMP2_REGNUM 12
152 #define MB_ABI_MSR_SAVE_REG 11
153 /* Volatile register used to save MSR in interrupt handlers. */
154
155
156 /* Debug stuff. */
157
158 /* How to renumber registers for dbx and gdb. */
159 #define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)]
160
161 /* Generate DWARF exception handling info. */
162 #define DWARF2_UNWIND_INFO 1
163
164 /* Don't generate .loc operations. */
165 #define DWARF2_ASM_LINE_DEBUG_INFO 0
166
167 /* The DWARF 2 CFA column which tracks the return address. */
168 #define DWARF_FRAME_RETURN_COLUMN \
169 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
170
171 /* Initial state of return address on entry to func = R15.
172 Actually, the RA is at R15+8, but gcc doesn't know how
173 to generate this.
174 NOTE: GDB has a workaround and expects this incorrect value.
175 If this is fixed, a corresponding fix to GDB is needed. */
176 #define INCOMING_RETURN_ADDR_RTX \
177 gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
178
179 /* Use DWARF 2 debugging information by default. */
180 #define DWARF2_DEBUGGING_INFO
181 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
182
183 /* Target machine storage layout */
184
185 #define BITS_BIG_ENDIAN 0
186 #define BYTES_BIG_ENDIAN 1
187 #define WORDS_BIG_ENDIAN 1
188 #define BITS_PER_UNIT 8
189 #define BITS_PER_WORD 32
190 #define UNITS_PER_WORD 4
191 #define MIN_UNITS_PER_WORD 4
192 #define INT_TYPE_SIZE 32
193 #define SHORT_TYPE_SIZE 16
194 #define LONG_TYPE_SIZE 32
195 #define LONG_LONG_TYPE_SIZE 64
196 #define FLOAT_TYPE_SIZE 32
197 #define DOUBLE_TYPE_SIZE 64
198 #define LONG_DOUBLE_TYPE_SIZE 64
199 #define POINTER_SIZE 32
200 #define PARM_BOUNDARY 32
201 #define FUNCTION_BOUNDARY 32
202 #define EMPTY_FIELD_BOUNDARY 32
203 #define STRUCTURE_SIZE_BOUNDARY 8
204 #define BIGGEST_ALIGNMENT 32
205 #define STRICT_ALIGNMENT 1
206 #define PCC_BITFIELD_TYPE_MATTERS 1
207
208 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
209 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
210 && (ALIGN) < BITS_PER_WORD \
211 ? BITS_PER_WORD \
212 : (ALIGN))
213
214 #define DATA_ALIGNMENT(TYPE, ALIGN) \
215 ((((ALIGN) < BITS_PER_WORD) \
216 && (TREE_CODE (TYPE) == ARRAY_TYPE \
217 || TREE_CODE (TYPE) == UNION_TYPE \
218 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
219
220 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
221 (((TREE_CODE (TYPE) == ARRAY_TYPE \
222 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
223 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
224
225 #define WORD_REGISTER_OPERATIONS
226
227 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
228
229 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
230 if (GET_MODE_CLASS (MODE) == MODE_INT \
231 && GET_MODE_SIZE (MODE) < 4) \
232 (MODE) = SImode;
233
234 /* Standard register usage. */
235
236 /* On the MicroBlaze, we have 32 integer registers */
237
238 #define FIRST_PSEUDO_REGISTER 36
239
240 #define FIXED_REGISTERS \
241 { \
242 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
243 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
244 1, 1, 1, 1 \
245 }
246
247 #define CALL_USED_REGISTERS \
248 { \
249 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
250 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
251 1, 1, 1, 1 \
252 }
253
254 #define GP_REG_FIRST 0
255 #define GP_REG_LAST 31
256 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
257 #define GP_DBX_FIRST 0
258
259 #define ST_REG 32
260 #define AP_REG_NUM 33
261 #define RAP_REG_NUM 34
262 #define FRP_REG_NUM 35
263
264 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
265 #define ST_REG_P(REGNO) ((REGNO) == ST_REG)
266
267 #define HARD_REGNO_NREGS(REGNO, MODE) \
268 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
269
270 /* Value is 1 if hard register REGNO can hold a value of machine-mode
271 MODE. In 32 bit mode, require that DImode and DFmode be in even
272 registers. For DImode, this makes some of the insns easier to
273 write, since you don't have to worry about a DImode value in
274 registers 3 & 4, producing a result in 4 & 5.
275
276 To make the code simpler HARD_REGNO_MODE_OK now just references an
277 array built in override_options. Because machmodes.h is not yet
278 included before this file is processed, the MODE bound can't be
279 expressed here. */
280 extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
281 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
282 microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
283
284 #define MODES_TIEABLE_P(MODE1, MODE2) \
285 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
286 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
287 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
288 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
289
290 #define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
291
292 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
293
294 /* Base register for access to local variables of the function. We
295 pretend that the frame pointer is
296 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
297 to HARD_FRAME_POINTER_REGNUM. We can get away with this because
298 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
299 register(return address for interrupt), and will not be used for
300 anything else. */
301
302 #define FRAME_POINTER_REGNUM FRP_REG_NUM
303 #define HARD_FRAME_POINTER_REGNUM \
304 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
305 #define ARG_POINTER_REGNUM AP_REG_NUM
306 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
307 #define STATIC_CHAIN_REGNUM \
308 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
309
310 /* registers used in prologue/epilogue code when the stack frame
311 is larger than 32K bytes. These registers must come from the
312 scratch register set, and not used for passing and returning
313 arguments and any other information used in the calling sequence
314 (such as pic). */
315
316 #define MICROBLAZE_TEMP1_REGNUM \
317 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
318
319 #define MICROBLAZE_TEMP2_REGNUM \
320 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
321
322 #define NO_FUNCTION_CSE 1
323
324 #define PIC_OFFSET_TABLE_REGNUM \
325 (flag_pic ? (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM) : \
326 INVALID_REGNUM)
327
328 enum reg_class
329 {
330 NO_REGS, /* no registers in set. */
331 GR_REGS, /* integer registers. */
332 ST_REGS, /* status register. */
333 ALL_REGS, /* all registers. */
334 LIM_REG_CLASSES /* max value + 1. */
335 };
336
337 #define N_REG_CLASSES (int) LIM_REG_CLASSES
338
339 #define GENERAL_REGS GR_REGS
340
341 #define REG_CLASS_NAMES \
342 { \
343 "NO_REGS", \
344 "GR_REGS", \
345 "ST_REGS", \
346 "ALL_REGS" \
347 }
348
349 #define REG_CLASS_CONTENTS \
350 { \
351 { 0x00000000, 0x00000000 }, /* no registers. */ \
352 { 0xffffffff, 0x00000000 }, /* integer registers. */ \
353 { 0x00000000, 0x00000001 }, /* status registers. */ \
354 { 0xffffffff, 0x0000000f } /* all registers. */ \
355 }
356
357 extern enum reg_class microblaze_regno_to_class[];
358
359 #define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
360
361 #define BASE_REG_CLASS GR_REGS
362
363 #define INDEX_REG_CLASS GR_REGS
364
365 #define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
366
367 /* REGISTER AND CONSTANT CLASSES */
368
369 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
370 #define LARGE_INT(X) \
371 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff)
372 #define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
373 /* Test for a valid operand for a call instruction.
374 Don't allow the arg pointer register or virtual regs
375 since they may change into reg + const, which the patterns
376 can't handle yet. */
377 #define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
378 || (GET_CODE (X) == REG && X != arg_pointer_rtx\
379 && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
380 && REGNO (X) <= LAST_VIRTUAL_REGISTER)))
381
382 /* True if VALUE is a signed 16-bit number. */
383 #define SMALL_OPERAND(VALUE) \
384 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
385
386 /* Constant which cannot be loaded in one instruction. */
387 #define LARGE_OPERAND(VALUE) \
388 ((((VALUE) & ~0x0000ffff) != 0) \
389 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
390 && (((VALUE) & 0x0000ffff) != 0 \
391 || (((VALUE) & ~2147483647) != 0 \
392 && ((VALUE) & ~2147483647) != ~2147483647)))
393
394 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
395 ((CLASS) != ALL_REGS \
396 ? (CLASS) \
397 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
398 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
399 ? (GR_REGS) \
400 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
401 || GET_MODE (X) == VOIDmode) \
402 ? (GR_REGS) : (CLASS))))
403
404 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
405 (GET_MODE_CLASS (MODE) == MODE_INT)
406
407 #define CLASS_MAX_NREGS(CLASS, MODE) \
408 ((GET_MODE_SIZE (MODE) + (UNITS_PER_WORD) - 1) / (UNITS_PER_WORD))
409
410 /* Stack layout; function entry, exit and calling. */
411
412 #define STACK_GROWS_DOWNWARD
413
414 /* Changed the starting frame offset to including the new link stuff */
415 #define STARTING_FRAME_OFFSET \
416 (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL))
417
418 /* The return address for the current frame is in r31 if this is a leaf
419 function. Otherwise, it is on the stack. It is at a variable offset
420 from sp/fp/ap, so we define a fake hard register rap which is a
421 poiner to the return address on the stack. This always gets eliminated
422 during reload to be either the frame pointer or the stack pointer plus
423 an offset. */
424
425 #define RETURN_ADDR_RTX(count, frame) \
426 microblaze_return_addr(count,frame)
427
428 extern struct microblaze_frame_info current_frame_info;
429
430 #define ELIMINABLE_REGS \
431 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
432 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
433 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
434 { RETURN_ADDRESS_POINTER_REGNUM, \
435 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
436 { RETURN_ADDRESS_POINTER_REGNUM, \
437 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
438 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
439 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
440
441 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
442 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
443
444 #define ACCUMULATE_OUTGOING_ARGS 1
445
446 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
447
448 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
449
450 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
451
452 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
453
454 #define STACK_BOUNDARY 32
455
456 #define NUM_OF_ARGS 6
457
458 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
459
460 #define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
461 #define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
462
463 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
464
465 #define LIBCALL_VALUE(MODE) \
466 gen_rtx_REG ( \
467 ((GET_MODE_CLASS (MODE) != MODE_INT \
468 || GET_MODE_SIZE (MODE) >= 4) \
469 ? (MODE) \
470 : SImode), GP_RETURN)
471
472 /* 1 if N is a possible register number for a function value.
473 On the MicroBlaze, R2 R3 are the only register thus used.
474 Currently, R2 are only implemented here (C has no complex type) */
475
476 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
477
478 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
479
480 typedef struct microblaze_args
481 {
482 int gp_reg_found; /* whether a gp register was found yet */
483 int arg_number; /* argument number */
484 int arg_words; /* # total words the arguments take */
485 int fp_arg_words; /* # words for FP args */
486 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
487 int fp_code; /* Mode of FP arguments */
488 int num_adjusts; /* number of adjustments made */
489 /* Adjustments made to args pass in regs. */
490 /* ??? The size is doubled to work around a bug in the code that sets the
491 adjustments in function_arg. */
492 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS * 2];
493 } CUMULATIVE_ARGS;
494
495 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
496 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
497
498 #define NO_PROFILE_COUNTERS 1
499
500 #define FUNCTION_PROFILER(FILE, LABELNO) { \
501 { \
502 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
503 } \
504 }
505
506 #define EXIT_IGNORE_STACK 1
507
508 #define TRAMPOLINE_SIZE (32 + 8)
509
510 #define TRAMPOLINE_ALIGNMENT 32
511
512 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
513
514 #define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
515
516 #ifndef REG_OK_STRICT
517 #define REG_STRICT_FLAG 0
518 #else
519 #define REG_STRICT_FLAG 1
520 #endif
521
522 #define REG_OK_FOR_BASE_P(X) \
523 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
524
525 #define REG_OK_FOR_INDEX_P(X) \
526 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
527
528 #define MAX_REGS_PER_ADDRESS 2
529
530
531 /* Identify valid constant addresses. Exclude if PIC addr which
532 needs scratch register. */
533 #define CONSTANT_ADDRESS_P(X) \
534 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
535 || GET_CODE (X) == CONST_INT \
536 || (GET_CODE (X) == CONST \
537 && ! (flag_pic && pic_address_needs_scratch (X))))
538
539 /* Define this, so that when PIC, reload won't try to reload invalid
540 addresses which require two reload registers. */
541 #define LEGITIMATE_PIC_OPERAND_P(X) (!pic_address_needs_scratch (X))
542
543 /* At present, GAS doesn't understand li.[sd], so don't allow it
544 to be generated at present. */
545 #define LEGITIMATE_CONSTANT_P(X) \
546 (GET_CODE (X) != CONST_DOUBLE \
547 || microblaze_const_double_ok (X, GET_MODE (X)))
548
549 #define CASE_VECTOR_MODE (SImode)
550
551 #ifndef DEFAULT_SIGNED_CHAR
552 #define DEFAULT_SIGNED_CHAR 1
553 #endif
554
555 #define MOVE_MAX 4
556 #define MAX_MOVE_MAX 8
557
558 #define SLOW_BYTE_ACCESS 1
559
560 /* sCOND operations return 1. */
561 #define STORE_FLAG_VALUE 1
562
563 #define SHIFT_COUNT_TRUNCATED 1
564
565 /* This results in inefficient code for 64 bit to 32 conversions.
566 Something needs to be done about this. Perhaps not use any 32 bit
567 instructions? Perhaps use PROMOTE_MODE? */
568 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
569
570 #define Pmode SImode
571
572 #define FUNCTION_MODE SImode
573
574 /* Mode should alwasy be SImode */
575 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
576 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
577 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
578 : 12)
579
580 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
581 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
582
583 #define BRANCH_COST(speed_p, predictable_p) 2
584
585 /* Control the assembler format that we output. */
586 #define ASM_APP_ON " #APP\n"
587 #define ASM_APP_OFF " #NO_APP\n"
588
589 #define REGISTER_NAMES { \
590 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
591 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
592 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
593 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
594 "rmsr", "$ap", "$rap", "$frp" }
595
596 #define ADDITIONAL_REGISTER_NAMES \
597 { \
598 { "r0", 0 + GP_REG_FIRST }, \
599 { "r1", 1 + GP_REG_FIRST }, \
600 { "r2", 2 + GP_REG_FIRST }, \
601 { "r3", 3 + GP_REG_FIRST }, \
602 { "r4", 4 + GP_REG_FIRST }, \
603 { "r5", 5 + GP_REG_FIRST }, \
604 { "r6", 6 + GP_REG_FIRST }, \
605 { "r7", 7 + GP_REG_FIRST }, \
606 { "r8", 8 + GP_REG_FIRST }, \
607 { "r9", 9 + GP_REG_FIRST }, \
608 { "r10", 10 + GP_REG_FIRST }, \
609 { "r11", 11 + GP_REG_FIRST }, \
610 { "r12", 12 + GP_REG_FIRST }, \
611 { "r13", 13 + GP_REG_FIRST }, \
612 { "r14", 14 + GP_REG_FIRST }, \
613 { "r15", 15 + GP_REG_FIRST }, \
614 { "r16", 16 + GP_REG_FIRST }, \
615 { "r17", 17 + GP_REG_FIRST }, \
616 { "r18", 18 + GP_REG_FIRST }, \
617 { "r19", 19 + GP_REG_FIRST }, \
618 { "r20", 20 + GP_REG_FIRST }, \
619 { "r21", 21 + GP_REG_FIRST }, \
620 { "r22", 22 + GP_REG_FIRST }, \
621 { "r23", 23 + GP_REG_FIRST }, \
622 { "r24", 24 + GP_REG_FIRST }, \
623 { "r25", 25 + GP_REG_FIRST }, \
624 { "r26", 26 + GP_REG_FIRST }, \
625 { "r27", 27 + GP_REG_FIRST }, \
626 { "r28", 28 + GP_REG_FIRST }, \
627 { "r29", 29 + GP_REG_FIRST }, \
628 { "r30", 30 + GP_REG_FIRST }, \
629 { "r31", 31 + GP_REG_FIRST }, \
630 { "rmsr", ST_REG} \
631 }
632
633 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
634
635 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
636
637 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
638
639 /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
640
641 Unfortunately, we still need to set the section explicitly. Somehow,
642 our binutils assign .comm and .lcomm variables to the "current" section
643 in the assembly file, rather than where they implicitly belong. We need to
644 remove this explicit setting in GCC when binutils can understand sections
645 better. */
646 #undef ASM_OUTPUT_ALIGNED_COMMON
647 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
648 do { \
649 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
650 && (int) (SIZE) <= microblaze_section_threshold \
651 && TARGET_XLGPOPT) \
652 { \
653 switch_to_section (sbss_section); \
654 } \
655 else \
656 { \
657 switch_to_section (bss_section); \
658 } \
659 fprintf (FILE, "%s", COMMON_ASM_OP); \
660 assemble_name ((FILE), (NAME)); \
661 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
662 (SIZE), (ALIGN) / BITS_PER_UNIT); \
663 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
664 } while (0)
665
666 #undef ASM_OUTPUT_ALIGNED_LOCAL
667 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
668 do { \
669 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
670 && (int) (SIZE) <= microblaze_section_threshold \
671 && TARGET_XLGPOPT) \
672 { \
673 switch_to_section (sbss_section); \
674 } \
675 else \
676 { \
677 switch_to_section (bss_section); \
678 } \
679 fprintf (FILE, "%s", LCOMMON_ASM_OP); \
680 assemble_name ((FILE), (NAME)); \
681 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
682 (SIZE), (ALIGN) / BITS_PER_UNIT); \
683 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
684 } while (0)
685
686 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
687 do { \
688 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
689 } while (0)
690
691 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
692 { \
693 }
694
695 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
696 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
697
698 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
699 fprintf (STREAM, "\t%s\t%sL%d\n", \
700 ".gpword", \
701 LOCAL_LABEL_PREFIX, VALUE)
702
703 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
704 do { \
705 if (flag_pic == 2) \
706 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
707 ".gpword", \
708 LOCAL_LABEL_PREFIX, VALUE); \
709 else \
710 fprintf (STREAM, "\t%s\t%sL%d\n", \
711 ".gpword", \
712 LOCAL_LABEL_PREFIX, VALUE); \
713 } while (0)
714
715 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
716 fprintf (STREAM, "\t.align\t%d\n", (LOG))
717
718 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
719 fprintf (STREAM, "\t.space\t%lu\n", (SIZE))
720
721 #define ASCII_DATA_ASM_OP "\t.ascii\t"
722 #define STRING_ASM_OP "\t.asciz\t"
723
724 #define ASM_OUTPUT_IDENT(FILE, STRING) \
725 microblaze_asm_output_ident (FILE, STRING)
726
727 /* Default to -G 8 */
728 #ifndef MICROBLAZE_DEFAULT_GVALUE
729 #define MICROBLAZE_DEFAULT_GVALUE 8
730 #endif
731
732 /* Given a decl node or constant node, choose the section to output it in
733 and select that section. */
734
735 /* Store in OUTPUT a string (made with alloca) containing
736 an assembler-name for a local static variable named NAME.
737 LABELNO is an integer which is different for each call. */
738 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
739 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
740 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO)))
741
742 /* How to start an assembler comment.
743 The leading space is important (the microblaze assembler requires it). */
744 #ifndef ASM_COMMENT_START
745 #define ASM_COMMENT_START " #"
746 #endif
747
748 #define BSS_VAR 1
749 #define SBSS_VAR 2
750 #define DATA_VAR 4
751 #define SDATA_VAR 5
752 #define RODATA_VAR 6
753 #define SDATA2_VAR 7
754
755 /* These definitions are used in with the shift_type flag in the rtl. */
756 #define SHIFT_CONST 1
757 #define SHIFT_REG 2
758 #define USE_ADDK 3
759
760 /* Handle interrupt attribute. */
761 extern int interrupt_handler;
762 extern int save_volatiles;
763
764 #define INTERRUPT_HANDLER_NAME "_interrupt_handler"
765
766 /* These #define added for C++. */
767 #define UNALIGNED_SHORT_ASM_OP ".data16"
768 #define UNALIGNED_INT_ASM_OP ".data32"
769 #define UNALIGNED_DOUBLE_INT_ASM_OP ".data8"
770
771 #define ASM_BYTE_OP ".data8"
772
773 /* The following #defines are used in the headers files. Always retain these. */
774
775 /* Added for declaring size at the end of the function. */
776 #undef ASM_DECLARE_FUNCTION_SIZE
777 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
778 do { \
779 if (!flag_inhibit_size_directive) \
780 { \
781 char label[256]; \
782 static int labelno; \
783 labelno++; \
784 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
785 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
786 fprintf (FILE, "%s", SIZE_ASM_OP); \
787 assemble_name (FILE, (FNAME)); \
788 fprintf (FILE, ","); \
789 assemble_name (FILE, label); \
790 fprintf (FILE, "-"); \
791 assemble_name (FILE, (FNAME)); \
792 putc ('\n', FILE); \
793 } \
794 } while (0)
795
796 #define GLOBAL_ASM_OP "\t.globl\t"
797 #define TYPE_ASM_OP "\t.type\t"
798 #define SIZE_ASM_OP "\t.size\t"
799 #define COMMON_ASM_OP "\t.comm\t"
800 #define LCOMMON_ASM_OP "\t.lcomm\t"
801
802 #define MAX_OFILE_ALIGNMENT (32768*8)
803
804 #define TYPE_OPERAND_FMT "@%s"
805
806 /* Write the extra assembler code needed to declare an object properly. */
807 #undef ASM_DECLARE_OBJECT_NAME
808 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
809 do { \
810 fprintf (FILE, "%s", TYPE_ASM_OP); \
811 assemble_name (FILE, NAME); \
812 putc (',', FILE); \
813 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
814 putc ('\n', FILE); \
815 size_directive_output = 0; \
816 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
817 { \
818 size_directive_output = 1; \
819 fprintf (FILE, "%s", SIZE_ASM_OP); \
820 assemble_name (FILE, NAME); \
821 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
822 int_size_in_bytes (TREE_TYPE (DECL))); \
823 } \
824 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
825 } while (0)
826
827 #undef ASM_FINISH_DECLARE_OBJECT
828 #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
829 do { \
830 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
831 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
832 && ! AT_END && TOP_LEVEL \
833 && DECL_INITIAL (DECL) == error_mark_node \
834 && !size_directive_output) \
835 { \
836 size_directive_output = 1; \
837 fprintf (FILE, "%s", SIZE_ASM_OP); \
838 assemble_name (FILE, name); \
839 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
840 int_size_in_bytes (TREE_TYPE (DECL))); \
841 } \
842 } while (0)
843
844 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
845 do { fputc ( '\t', FILE); \
846 assemble_name (FILE, LABEL1); \
847 fputs ( " = ", FILE); \
848 assemble_name (FILE, LABEL2); \
849 fputc ( '\n', FILE); \
850 } while (0)
851
852 #define ASM_WEAKEN_LABEL(FILE,NAME) \
853 do { fputs ("\t.weakext\t", FILE); \
854 assemble_name (FILE, NAME); \
855 fputc ('\n', FILE); \
856 } while (0)
857
858 #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
859 #undef UNIQUE_SECTION_P
860 #define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
861
862 #undef TARGET_ASM_NAMED_SECTION
863 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
864
865 /* Define the strings to put out for each section in the object file.
866
867 Note: For ctors/dtors, we want to give these sections the SHF_WRITE
868 attribute to allow shared libraries to patch/resolve addresses into
869 these locations. On Microblaze, there is no concept of shared libraries
870 yet, so this is for future use. */
871 #define TEXT_SECTION_ASM_OP "\t.text"
872 #define DATA_SECTION_ASM_OP "\t.data"
873 #define READONLY_DATA_SECTION_ASM_OP \
874 "\t.rodata"
875 #define BSS_SECTION_ASM_OP "\t.bss"
876 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
877 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
878 #define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
879 #define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
880
881 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
882 #define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
883 #define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
884 #define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
885
886 /* We do this to save a few 10s of code space that would be taken up
887 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
888 definition in crtstuff.c. */
889 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
890 asm ( SECTION_OP "\n" \
891 "\tbrlid r15, " #FUNC "\n\t nop\n" \
892 TEXT_SECTION_ASM_OP);
893
894 /* We need to group -lm as well, since some Newlib math functions
895 reference __errno! */
896 #undef LIB_SPEC
897 #define LIB_SPEC \
898 "%{!nostdlib: \
899 %{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
900 %{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
901
902 #undef ENDFILE_SPEC
903 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
904
905 #define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
906 #define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
907 #define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
908 #define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
909 #define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
910 %{mno-clearbss: sim-crtinit.o%s}} \
911 %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
912
913 #define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
914
915 #undef SUBTARGET_EXTRA_SPECS
916 #define SUBTARGET_EXTRA_SPECS \
917 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
918 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
919 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
920 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
921 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
922 { "startfile_default", STARTFILE_DEFAULT_SPEC },
923
924 #undef STARTFILE_SPEC
925 #define STARTFILE_SPEC "\
926 %{Zxl-mode-executable : %(startfile_executable) ; \
927 mxl-mode-executable : %(startfile_executable) ; \
928 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
929 mxl-mode-xmdstub : %(startfile_xmdstub) ; \
930 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
931 mxl-mode-bootstrap : %(startfile_bootstrap) ; \
932 Zxl-mode-novectors : %(startfile_novectors) ; \
933 mxl-mode-novectors : %(startfile_novectors) ; \
934 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
935 mxl-mode-xilkernel : %(startfile_xilkernel) ; \
936 : %(startfile_default) \
937 } \
938 %(startfile_crtinit)"