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comparison gcc/config/i386/i386.h @ 19:58ad6c70ea60

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update gcc from 4.4.0 to 4.4.1.
author kent@firefly.cr.ie.u-ryukyu.ac.jp
date Thu, 24 Sep 2009 13:21:57 +0900
parents a06113de4d67
children 77e2b8dfacca
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equal deleted inserted replaced
18:33936f7f2835 19:58ad6c70ea60
806 data to make it all fit in fewer cache lines. */ 806 data to make it all fit in fewer cache lines. */
807 807
808 #define LOCAL_DECL_ALIGNMENT(DECL) \ 808 #define LOCAL_DECL_ALIGNMENT(DECL) \
809 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 809 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
810 810
811 /* If defined, a C expression to compute the minimum required alignment
812 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
813 MODE, assuming normal alignment ALIGN.
814
815 If this macro is not defined, then (ALIGN) will be used. */
816
817 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
818 ix86_minimum_alignment (EXP, MODE, ALIGN)
819
811 820
812 /* If defined, a C expression that gives the alignment boundary, in 821 /* If defined, a C expression that gives the alignment boundary, in
813 bits, of an argument with the specified mode and type. If it is 822 bits, of an argument with the specified mode and type. If it is
814 not defined, `PARM_BOUNDARY' is used for all arguments. */ 823 not defined, `PARM_BOUNDARY' is used for all arguments. */
815 824
935 944
936 945
937 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 946 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
938 947
939 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 948 /* Macro to conditionally modify fixed_regs/call_used_regs. */
940 #define CONDITIONAL_REGISTER_USAGE \ 949 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage ()
941 do { \
942 int i; \
943 unsigned int j; \
944 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
945 { \
946 if (fixed_regs[i] > 1) \
947 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
948 if (call_used_regs[i] > 1) \
949 call_used_regs[i] = (call_used_regs[i] \
950 == (TARGET_64BIT ? 3 : 2)); \
951 } \
952 j = PIC_OFFSET_TABLE_REGNUM; \
953 if (j != INVALID_REGNUM) \
954 fixed_regs[j] = call_used_regs[j] = 1; \
955 if (TARGET_64BIT \
956 && ((cfun && cfun->machine->call_abi == MS_ABI) \
957 || (!cfun && DEFAULT_ABI == MS_ABI))) \
958 { \
959 call_used_regs[SI_REG] = 0; \
960 call_used_regs[DI_REG] = 0; \
961 call_used_regs[XMM6_REG] = 0; \
962 call_used_regs[XMM7_REG] = 0; \
963 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
964 call_used_regs[i] = 0; \
965 } \
966 if (! TARGET_MMX) \
967 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
968 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
969 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
970 if (! TARGET_SSE) \
971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
972 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
973 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
974 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387)) \
975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
976 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i)) \
977 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
978 if (! TARGET_64BIT) \
979 { \
980 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
981 reg_names[i] = ""; \
982 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
983 reg_names[i] = ""; \
984 } \
985 } while (0)
986 950
987 /* Return number of consecutive hard regs needed starting at reg REGNO 951 /* Return number of consecutive hard regs needed starting at reg REGNO
988 to hold something of mode MODE. 952 to hold something of mode MODE.
989 This is ordinarily the length in words of a value of mode MODE 953 This is ordinarily the length in words of a value of mode MODE
990 but can be less for certain modes in special long registers. 954 but can be less for certain modes in special long registers.
1206 enum reg_class 1170 enum reg_class
1207 { 1171 {
1208 NO_REGS, 1172 NO_REGS,
1209 AREG, DREG, CREG, BREG, SIREG, DIREG, 1173 AREG, DREG, CREG, BREG, SIREG, DIREG,
1210 AD_REGS, /* %eax/%edx for DImode */ 1174 AD_REGS, /* %eax/%edx for DImode */
1175 CLOBBERED_REGS, /* call-clobbered integers */
1211 Q_REGS, /* %eax %ebx %ecx %edx */ 1176 Q_REGS, /* %eax %ebx %ecx %edx */
1212 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1177 NON_Q_REGS, /* %esi %edi %ebp %esp */
1213 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1178 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1214 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1179 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1215 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1180 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1254 #define REG_CLASS_NAMES \ 1219 #define REG_CLASS_NAMES \
1255 { "NO_REGS", \ 1220 { "NO_REGS", \
1256 "AREG", "DREG", "CREG", "BREG", \ 1221 "AREG", "DREG", "CREG", "BREG", \
1257 "SIREG", "DIREG", \ 1222 "SIREG", "DIREG", \
1258 "AD_REGS", \ 1223 "AD_REGS", \
1224 "CLOBBERED_REGS", \
1259 "Q_REGS", "NON_Q_REGS", \ 1225 "Q_REGS", "NON_Q_REGS", \
1260 "INDEX_REGS", \ 1226 "INDEX_REGS", \
1261 "LEGACY_REGS", \ 1227 "LEGACY_REGS", \
1262 "GENERAL_REGS", \ 1228 "GENERAL_REGS", \
1263 "FP_TOP_REG", "FP_SECOND_REG", \ 1229 "FP_TOP_REG", "FP_SECOND_REG", \
1271 "FLOAT_INT_REGS", \ 1237 "FLOAT_INT_REGS", \
1272 "INT_SSE_REGS", \ 1238 "INT_SSE_REGS", \
1273 "FLOAT_INT_SSE_REGS", \ 1239 "FLOAT_INT_SSE_REGS", \
1274 "ALL_REGS" } 1240 "ALL_REGS" }
1275 1241
1276 /* Define which registers fit in which classes. 1242 /* Define which registers fit in which classes. This is an initializer
1277 This is an initializer for a vector of HARD_REG_SET 1243 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1278 of length N_REG_CLASSES. */ 1244
1245 Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1246 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */
1279 1247
1280 #define REG_CLASS_CONTENTS \ 1248 #define REG_CLASS_CONTENTS \
1281 { { 0x00, 0x0 }, \ 1249 { { 0x00, 0x0 }, \
1282 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1250 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1283 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1251 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1284 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1252 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1285 { 0x03, 0x0 }, /* AD_REGS */ \ 1253 { 0x03, 0x0 }, /* AD_REGS */ \
1254 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \
1286 { 0x0f, 0x0 }, /* Q_REGS */ \ 1255 { 0x0f, 0x0 }, /* Q_REGS */ \
1287 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1256 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1288 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1257 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1289 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1258 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1290 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1259 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1473 || ((CLASS) == CREG) \ 1442 || ((CLASS) == CREG) \
1474 || ((CLASS) == BREG) \ 1443 || ((CLASS) == BREG) \
1475 || ((CLASS) == AD_REGS) \ 1444 || ((CLASS) == AD_REGS) \
1476 || ((CLASS) == SIREG) \ 1445 || ((CLASS) == SIREG) \
1477 || ((CLASS) == DIREG) \ 1446 || ((CLASS) == DIREG) \
1447 || ((CLASS) == SSE_FIRST_REG) \
1478 || ((CLASS) == FP_TOP_REG) \ 1448 || ((CLASS) == FP_TOP_REG) \
1479 || ((CLASS) == FP_SECOND_REG)) 1449 || ((CLASS) == FP_SECOND_REG))
1480 1450
1481 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1451 /* Return a class of registers that cannot change FROM mode to TO mode. */
1482 1452