CbC/CbC_gcc: gcc/combine.c comparison

comparison gcc/combine.c @ 55:77e2b8dfacca gcc-4.4.5

update it from 4.4.3 to 4.5.0

author	ryoma <e075725@ie.u-ryukyu.ac.jp>
date	Fri, 12 Feb 2010 23:39:51 +0900
parents	3bfb6c00c1e0
children	b7f97abdc517

comparison

equal deleted inserted replaced

-:c156f1bd5cd9
+:77e2b8dfacca
 /* Incremented for each basic block.  */
 static int label_tick;
-/* Reset to label_tick for each label.  */
+/* Reset to label_tick for each extended basic block in scanning order.  */
 static int label_tick_ebb_start;
 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 /* Record one modification to rtl structure
 to be undone by storing old_contents into *where.  */
+enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
 struct undo
 {
 struct undo *next;
-enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
+enum undo_kind kind;
 union { rtx r; int i; enum machine_mode m; } old_contents;
 union { rtx *r; int *i; } where;
 };
 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 and last insn referencing DEST.  */
 static rtx *
 find_single_use (rtx dest, rtx insn, rtx *ploc)
 {
+basic_block bb;
 rtx next;
 rtx *result;
 rtx link;
 #ifdef HAVE_cc0
 #endif
 if (!REG_P (dest))
 return 0;
-for (next = next_nonnote_insn (insn);
+bb = BLOCK_FOR_INSN (insn);
-next != 0 && !LABEL_P (next);
+for (next = NEXT_INSN (insn);
-next = next_nonnote_insn (next))
+next && BLOCK_FOR_INSN (next) == bb;
+next = NEXT_INSN (next))
 if (INSN_P (next) && dead_or_set_p (next, dest))
 {
 	for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
 	  if (XEXP (link, 0) == insn)
 	    break;
 possible.  Unfortunately, there are way too many mode changes
 that are perfectly valid, so we'd waste too much effort for
 little gain doing the checks here.  Focus on catching invalid
 transformations involving integer constants.  */
 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
-&& GET_CODE (newval) == CONST_INT)
+&& CONST_INT_P (newval))
 {
 /* Sanity check that we're replacing oldval with a CONST_INT
 	 that is a valid sign-extension for the original mode.  */
 gcc_assert (INTVAL (newval)
 		  == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 	 original mode would be gone.  Unfortunately, we can't tell
 	 when do_SUBST is called to replace the operand thereof, so we
 	 perform this test on oldval instead, checking whether an
 	 invalid replacement took place before we got here.  */
 gcc_assert (!(GET_CODE (oldval) == SUBREG
-		    && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
+		    && CONST_INT_P (SUBREG_REG (oldval))));
 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
-		    && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
+		    && CONST_INT_P (XEXP (oldval, 0))));
 }
 if (undobuf.frees)
 buf = undobuf.frees, undobuf.frees = buf->next;
 else
 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 /* Subroutine of try_combine.  Determine whether the combine replacement
 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
 undobuf.other_insn.  Note that I1 and/or NEWI2PAT may be NULL_RTX.
 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX.  This
 function returns false, if the costs of all instructions can be
 estimated, and the replacements are more expensive than the original
 sequence.  */
 /* Pass through each block from the end, recording the uses of each
 register and establishing log links when def is encountered.
 Note that we do not clear next_use array in order to save time,
 so we have to test whether the use is in the same basic block as def.
 There are a few cases below when we do not consider the definition or
 usage -- these are taken from original flow.c did. Don't ask me why it is
 done this way; I don't know and if it works, I don't want to know.  */
 FOR_EACH_BB (bb)
 {
 FOR_BB_INSNS_REVERSE (bb, insn)
 {
-if (!INSN_P (insn))
+if (!NONDEBUG_INSN_P (insn))
 continue;
 	  /* Log links are created only once.  */
 	  gcc_assert (!LOG_LINKS (insn));
 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
 if (INSN_P (insn))
 free_INSN_LIST_list (&LOG_LINKS (insn));
 }
 /* Main entry point for combiner.  F is the first insn of the function.
 NREGS is the first unused pseudo-reg number.
 Return nonzero if the combiner has turned an indirect jump
 #ifdef HAVE_cc0
 rtx prev;
 #endif
 rtx links, nextlinks;
 rtx first;
+basic_block last_bb;
 int new_direct_jump_p = 0;
 for (first = f; first && !INSN_P (first); )
 first = NEXT_INSN (first);
 /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 problems when, for example, we have j <<= 1 in a loop.  */
 nonzero_sign_valid = 0;
+label_tick = label_tick_ebb_start = 1;
 /* Scan all SETs and see if we can deduce anything about what
 bits are known to be zero for some registers and how many copies
 of the sign bit are known to exist for those registers.
 Also set any known values so that we can use it while searching
 for what bits are known to be set.  */
-label_tick = label_tick_ebb_start = 1;
 setup_incoming_promotions (first);
+/* Allow the entry block and the first block to fall into the same EBB.
+Conceptually the incoming promotions are assigned to the entry block.  */
+last_bb = ENTRY_BLOCK_PTR;
 create_log_links ();
 FOR_EACH_BB (this_basic_block)
 {
 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
 last_call_luid = 0;
 mem_last_set = -1;
 label_tick++;
+if (!single_pred_p (this_basic_block)
+	  || single_pred (this_basic_block) != last_bb)
+	label_tick_ebb_start = label_tick;
+last_bb = this_basic_block;
 FOR_BB_INSNS (this_basic_block, insn)
 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
 	  {
 subst_low_luid = DF_INSN_LUID (insn);
 subst_insn = insn;
 	      					optimize_this_for_speed_p);
 	    if (dump_file)
 	      fprintf(dump_file, "insn_cost %d: %d\n",
 		    INSN_UID (insn), INSN_COST (insn));
 	  }
-	else if (LABEL_P (insn))
-	  label_tick_ebb_start = label_tick;
 }
 nonzero_sign_valid = 1;
 /* Now scan all the insns in forward order.  */
 label_tick = label_tick_ebb_start = 1;
 init_reg_last ();
 setup_incoming_promotions (first);
+last_bb = ENTRY_BLOCK_PTR;
 FOR_EACH_BB (this_basic_block)
 {
 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
 last_call_luid = 0;
 mem_last_set = -1;
 label_tick++;
+if (!single_pred_p (this_basic_block)
+	  || single_pred (this_basic_block) != last_bb)
+	label_tick_ebb_start = label_tick;
+last_bb = this_basic_block;
 rtl_profile_for_bb (this_basic_block);
 for (insn = BB_HEAD (this_basic_block);
 	   insn != NEXT_INSN (BB_END (this_basic_block));
 	   insn = next ? next : NEXT_INSN (insn))
 	{
 	  next = 0;
-	  if (INSN_P (insn))
+	  if (NONDEBUG_INSN_P (insn))
 	    {
 	      /* See if we know about function return values before this
 		 insn based upon SUBREG flags.  */
 	      check_promoted_subreg (insn, PATTERN (insn));
 		record_dead_and_set_regs (insn);
 	    retry:
 	      ;
 	    }
-	  else if (LABEL_P (insn))
-	    label_tick_ebb_start = label_tick;
 	}
 }
 default_rtl_profile ();
 clear_log_links ();
 setup_incoming_promotions (rtx first)
 {
 tree arg;
 bool strictly_local = false;
-if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
-return;
 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
 arg = TREE_CHAIN (arg))
 {
-rtx reg = DECL_INCOMING_RTL (arg);
+rtx x, reg = DECL_INCOMING_RTL (arg);
 int uns1, uns3;
 enum machine_mode mode1, mode2, mode3, mode4;
 /* Only continue if the incoming argument is in a register.  */
 if (!REG_P (reg))
 /* The mode and signedness of the argument after any source language and
 TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
 /* The mode and signedness of the argument as it is actually passed,
 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
-mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
+mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
+				     TREE_TYPE (cfun->decl), 0);
 /* The mode of the register in which the argument is being passed.  */
 mode4 = GET_MODE (reg);
-/* Eliminate sign extensions in the callee when possible.  Only
+/* Eliminate sign extensions in the callee when:
-do this when:
+	 (a) A mode promotion has occurred;  */
-	 (a) a mode promotion has occurred;
+if (mode1 == mode3)
-	 (b) the mode of the register is the same as the mode of
+	continue;
-	     the argument as it is passed; and
+/* (b) The mode of the register is the same as the mode of
-	 (c) the signedness does not change across any of the promotions; and
+	     the argument as it is passed; */
-	 (d) when no language-level promotions (which we cannot guarantee
+if (mode3 != mode4)
-	     will have been done by an external caller) are necessary,
+	continue;
-	     unless we know that this function is only ever called from
+/* (c) There's no language level extension;  */
-	     the current compilation unit -- all of whose call sites will
+if (mode1 == mode2)
-	     do the mode1 --> mode2 promotion.  */
+	;
-if (mode1 != mode3
+/* (c.1) All callers are from the current compilation unit.  If that's
-&& mode3 == mode4
+	 the case we don't have to rely on an ABI, we only have to know
-&& uns1 == uns3
+	 what we're generating right now, and we know that we will do the
-	  && (mode1 == mode2 || strictly_local))
+	 mode1 to mode2 promotion with the given sign.  */
-{
+else if (!strictly_local)
-	  /* Record that the value was promoted from mode1 to mode3,
+	continue;
-	     so that any sign extension at the head of the current
+/* (c.2) The combination of the two promotions is useful.  This is
-	     function may be eliminated.  */
+	 true when the signs match, or if the first promotion is unsigned.
-	  rtx x;
+	 In the later case, (sign_extend (zero_extend x)) is the same as
-	  x = gen_rtx_CLOBBER (mode1, const0_rtx);
+	 (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
-	  x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
+else if (uns1)
-	  record_value_for_reg (reg, first, x);
+	uns3 = true;
-	}
+else if (uns3)
+	continue;
+/* Record that the value was promoted from mode1 to mode3,
+	 so that any sign extension at the head of the current
+	 function may be eliminated.  */
+x = gen_rtx_CLOBBER (mode1, const0_rtx);
+x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
+record_value_for_reg (reg, first, x);
 }
 }
 /* Called via note_stores.  If X is a pseudo that is narrower than
 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 	     ??? For 2.5, try to tighten up the MD files in this regard
 	     instead of this kludge.  */
 	  if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
-	      && GET_CODE (src) == CONST_INT
+	      && CONST_INT_P (src)
 	      && INTVAL (src) > 0
 	      && 0 != (INTVAL (src)
 		       & ((HOST_WIDE_INT) 1
 			  << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 	    src = GEN_INT (INTVAL (src)
 	   && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 {
 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 	{
 	  rtx elt = XVECEXP (PATTERN (insn), 0, i);
-	  rtx note;
 	  switch (GET_CODE (elt))
 	    {
 	    /* This is important to combine floating point insns
 	       for the SH4 port.  */
 	    case SET:
 	      /* Ignore SETs whose result isn't used but not those that
 		 have side-effects.  */
 	      if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
-		  && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
+		  && insn_nothrow_p (insn)
-		      || INTVAL (XEXP (note, 0)) <= 0)
+		  && !side_effects_p (elt))
-		  && ! side_effects_p (elt))
 		break;
 	      /* If we have already found a SET, this is a second one and
 		 so we cannot combine with this insn.  */
 	      if (set)
 {
 case MOD:  case DIV:  case UMOD:  case UDIV:
 return 1;
 case MULT:
-return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
+return ! (CONST_INT_P (XEXP (x, 1))
 		&& exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
 default:
 if (BINARY_P (x))
 	return contains_muldiv (XEXP (x, 0))
 	    || contains_muldiv (XEXP (x, 1));
 x = XEXP (x, 0);
 return GET_CODE (x) == SUBREG
 	 && SUBREG_REG (x) == reg
 	 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
+}
+#ifdef AUTO_INC_DEC
+/* Replace auto-increment addressing modes with explicit operations to
+access the same addresses without modifying the corresponding
+registers.  If AFTER holds, SRC is meant to be reused after the
+side effect, otherwise it is to be reused before that.  */
+static rtx
+cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
+{
+rtx x = src;
+const RTX_CODE code = GET_CODE (x);
+int i;
+const char *fmt;
+switch (code)
+{
+case REG:
+case CONST_INT:
+case CONST_DOUBLE:
+case CONST_FIXED:
+case CONST_VECTOR:
+case SYMBOL_REF:
+case CODE_LABEL:
+case PC:
+case CC0:
+case SCRATCH:
+/* SCRATCH must be shared because they represent distinct values.  */
+return x;
+case CLOBBER:
+if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
+	return x;
+break;
+case CONST:
+if (shared_const_p (x))
+	return x;
+break;
+case MEM:
+mem_mode = GET_MODE (x);
+break;
+case PRE_INC:
+case PRE_DEC:
+case POST_INC:
+case POST_DEC:
+gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
+if (after == (code == PRE_INC || code == PRE_DEC))
+	x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
+else
+	x = gen_rtx_PLUS (GET_MODE (x),
+			  cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
+			  GEN_INT ((code == PRE_INC || code == POST_INC)
+				   ? GET_MODE_SIZE (mem_mode)
+				   : -GET_MODE_SIZE (mem_mode)));
+return x;
+case PRE_MODIFY:
+case POST_MODIFY:
+if (after == (code == PRE_MODIFY))
+	x = XEXP (x, 0);
+else
+	x = XEXP (x, 1);
+return cleanup_auto_inc_dec (x, after, mem_mode);
+default:
+break;
+}
+/* Copy the various flags, fields, and other information.  We assume
+that all fields need copying, and then clear the fields that should
+not be copied.  That is the sensible default behavior, and forces
+us to explicitly document why we are *not* copying a flag.  */
+x = shallow_copy_rtx (x);
+/* We do not copy the USED flag, which is used as a mark bit during
+walks over the RTL.  */
+RTX_FLAG (x, used) = 0;
+/* We do not copy FRAME_RELATED for INSNs.  */
+if (INSN_P (x))
+RTX_FLAG (x, frame_related) = 0;
+fmt = GET_RTX_FORMAT (code);
+for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+if (fmt[i] == 'e')
+XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
+else if (fmt[i] == 'E' || fmt[i] == 'V')
+{
+	int j;
+	XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
+	for (j = 0; j < XVECLEN (x, i); j++)
+	  XVECEXP (x, i, j)
+	    = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
+}
+return x;
+}
+/* Auxiliary data structure for propagate_for_debug_stmt.  */
+struct rtx_subst_pair
+{
+rtx to;
+bool adjusted;
+bool after;
+};
+/* DATA points to an rtx_subst_pair.  Return the value that should be
+substituted.  */
+static rtx
+propagate_for_debug_subst (rtx from ATTRIBUTE_UNUSED, void *data)
+{
+struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
+if (!pair->adjusted)
+{
+pair->adjusted = true;
+pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
+return pair->to;
+}
+return copy_rtx (pair->to);
+}
+#endif
+/* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
+and LAST.  If MOVE holds, debug insns must also be moved past
+LAST.  */
+static void
+propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
+{
+rtx next, move_pos = move ? last : NULL_RTX, loc;
+#ifdef AUTO_INC_DEC
+struct rtx_subst_pair p;
+p.to = src;
+p.adjusted = false;
+p.after = move;
+#endif
+next = NEXT_INSN (insn);
+while (next != last)
+{
+insn = next;
+next = NEXT_INSN (insn);
+if (DEBUG_INSN_P (insn))
+	{
+#ifdef AUTO_INC_DEC
+	  loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
+					 dest, propagate_for_debug_subst, &p);
+#else
+	  loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
+#endif
+	  if (loc == INSN_VAR_LOCATION_LOC (insn))
+	    continue;
+	  INSN_VAR_LOCATION_LOC (insn) = loc;
+	  if (move_pos)
+	    {
+	      remove_insn (insn);
+	      PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
+	      move_pos = emit_debug_insn_after (insn, move_pos);
+	    }
+	  else
+	    df_insn_rescan (insn);
+	}
+}
+}
+/* Delete the unconditional jump INSN and adjust the CFG correspondingly.
+Note that the INSN should be deleted *after* removing dead edges, so
+that the kept edge is the fallthrough edge for a (set (pc) (pc))
+but not for a (set (pc) (label_ref FOO)).  */
+static void
+update_cfg_for_uncondjump (rtx insn)
+{
+basic_block bb = BLOCK_FOR_INSN (insn);
+bool at_end = (BB_END (bb) == insn);
+if (at_end)
+purge_dead_edges (bb);
+delete_insn (insn);
+if (at_end && EDGE_COUNT (bb->succs) == 1)
+single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
 }
 /* Try to combine the insns I1 and I2 into I3.
 Here I1 and I2 appear earlier than I3.
 /* Contains I3 if the destination of I3 is used in its source, which means
 that the old life of I3 is being killed.  If that usage is placed into
 I2 and not in I3, a REG_DEAD note must be made.  */
 rtx i3dest_killed = 0;
 /* SET_DEST and SET_SRC of I2 and I1.  */
-rtx i2dest, i2src, i1dest = 0, i1src = 0;
+rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
+/* Set if I2DEST was reused as a scratch register.  */
+bool i2scratch = false;
 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
 rtx i1pat = 0, i2pat = 0;
 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
 int i2dest_killed = 0, i1dest_killed = 0;
 undobuf.other_insn = 0;
 /* Reset the hard register usage information.  */
 CLEAR_HARD_REG_SET (newpat_used_regs);
+if (dump_file && (dump_flags & TDF_DETAILS))
+{
+if (i1)
+	fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
+		 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
+else
+	fprintf (dump_file, "\nTrying %d -> %d:\n",
+		 INSN_UID (i2), INSN_UID (i3));
+}
 /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
 code below, set I1 to be the earlier of the two insns.  */
 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
 temp = i1, i1 = i2, i2 = temp;
 	 the resulting insn isn't likely to be recognized anyway.  */
 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
 				    SET_DEST (PATTERN (i3)))
-&& next_real_insn (i2) == i3)
+&& next_active_insn (i2) == i3)
 {
 rtx p2 = PATTERN (i2);
 /* Make sure that the destination of I3,
 	 which we are going to substitute into one output of I2,
 	      subst_insn = i3;
 	      subst_low_luid = DF_INSN_LUID (i2);
 	      added_sets_2 = added_sets_1 = 0;
+	      i2src = SET_DEST (PATTERN (i3));
 	      i2dest = SET_SRC (PATTERN (i3));
 	      i2dest_killed = dead_or_set_p (i2, i2dest);
 	      /* Replace the dest in I2 with our dest and make the resulting
 		 insn the new pattern for I3.  Then skip to where we
 /* If I2 is setting a pseudo to a constant and I3 is setting some
 sub-part of it to another constant, merge them by making a new
 constant.  */
 if (i1 == 0
 && (temp = single_set (i2)) != 0
-&& (GET_CODE (SET_SRC (temp)) == CONST_INT
+&& (CONST_INT_P (SET_SRC (temp))
 	  || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
 && GET_CODE (PATTERN (i3)) == SET
-&& (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
+&& (CONST_INT_P (SET_SRC (PATTERN (i3)))
 	  || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
 {
 rtx dest = SET_DEST (PATTERN (i3));
 int offset = -1;
 int width = 0;
 if (GET_CODE (dest) == ZERO_EXTRACT)
 	{
-	  if (GET_CODE (XEXP (dest, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (dest, 1))
-	      && GET_CODE (XEXP (dest, 2)) == CONST_INT)
+	      && CONST_INT_P (XEXP (dest, 2)))
 	    {
 	      width = INTVAL (XEXP (dest, 1));
 	      offset = INTVAL (XEXP (dest, 2));
 	      dest = XEXP (dest, 0);
 	      if (BITS_BIG_ENDIAN)
 	  HOST_WIDE_INT mhi, ohi, ihi;
 	  HOST_WIDE_INT mlo, olo, ilo;
 	  rtx inner = SET_SRC (PATTERN (i3));
 	  rtx outer = SET_SRC (temp);
-	  if (GET_CODE (outer) == CONST_INT)
+	  if (CONST_INT_P (outer))
 	    {
 	      olo = INTVAL (outer);
 	      ohi = olo < 0 ? -1 : 0;
 	    }
 	  else
 	    {
 	      olo = CONST_DOUBLE_LOW (outer);
 	      ohi = CONST_DOUBLE_HIGH (outer);
 	    }
-	  if (GET_CODE (inner) == CONST_INT)
+	  if (CONST_INT_P (inner))
 	    {
 	      ilo = INTVAL (inner);
 	      ihi = ilo < 0 ? -1 : 0;
 	    }
 	  else
 	  subst_low_luid = DF_INSN_LUID (i2);
 	  added_sets_2 = added_sets_1 = 0;
 	  i2dest = SET_DEST (temp);
 	  i2dest_killed = dead_or_set_p (i2, i2dest);
-/* Replace the source in I2 with the new constant and make the
-resulting insn the new pattern for I3.  Then skip to
-where we validate the pattern.  Everything was set up above.  */
 	  SUBST (SET_SRC (temp),
 		 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
 	  newpat = PATTERN (i2);
-/* The dest of I3 has been replaced with the dest of I2.  */
-changed_i3_dest = 1;
 	  goto validate_replacement;
 	}
 }
 #ifndef HAVE_cc0
 	    XVECEXP (newpat, 0, --total_sets)
 	      = subst (i2pat, i1dest, i1src, 0, 0);
 	}
 }
+/* We come here when we are replacing a destination in I2 with the
+destination of I3.  */
 validate_replacement:
 /* Note which hard regs this insn has as inputs.  */
 mark_used_regs_combine (newpat);
 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
 && asm_noperands (newpat) < 0)
 {
 rtx set0 = XVECEXP (newpat, 0, 0);
 rtx set1 = XVECEXP (newpat, 0, 1);
-rtx note;
 if (((REG_P (SET_DEST (set1))
 	    && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
 	   || (GET_CODE (SET_DEST (set1)) == SUBREG
 	       && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
-	  && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
+	  && insn_nothrow_p (i3)
-	      || INTVAL (XEXP (note, 0)) <= 0)
+	  && !side_effects_p (SET_SRC (set1)))
-	  && ! side_effects_p (SET_SRC (set1)))
 	{
 	  newpat = set0;
 	  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
 	}
 else if (((REG_P (SET_DEST (set0))
 		 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
 		|| (GET_CODE (SET_DEST (set0)) == SUBREG
 		    && find_reg_note (i3, REG_UNUSED,
 				      SUBREG_REG (SET_DEST (set0)))))
-	       && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
+	       && insn_nothrow_p (i3)
-		   || INTVAL (XEXP (note, 0)) <= 0)
+	       && !side_effects_p (SET_SRC (set0)))
-	       && ! side_effects_p (SET_SRC (set0)))
 	{
 	  newpat = set1;
 	  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
 	  if (insn_code_number >= 0)
 		  undobuf.undos = buf->next;
 		  buf->next = undobuf.frees;
 		  undobuf.frees = buf;
 		}
 	    }
+	  i2scratch = m_split != 0;
 	}
 /* If recog_for_combine has discarded clobbers, try to use them
 	 again for the split.  */
 if (m_split == 0 && newpat_vec_with_clobbers)
 	  enum rtx_code split_code = GET_CODE (*split);
 	  enum machine_mode split_mode = GET_MODE (*split);
 	  bool subst_done = false;
 	  newi2pat = NULL_RTX;
+	  i2scratch = true;
 	  /* Get NEWDEST as a register in the proper mode.  We have already
 	     validated that we can do this.  */
 	  if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
 	    {
 	      if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
 	  /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
 	     an ASHIFT.  This can occur if it was inside a PLUS and hence
 	     appeared to be a memory address.  This is a kludge.  */
 	  if (split_code == MULT
-	      && GET_CODE (XEXP (*split, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (*split, 1))
 	      && INTVAL (XEXP (*split, 1)) > 0
 	      && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
 	    {
 	      SUBST (*split, gen_rtx_ASHIFT (split_mode,
 					     XEXP (*split, 0), GEN_INT (i)));
 {
 undo_all ();
 return 0;
 }
+if (MAY_HAVE_DEBUG_INSNS)
+{
+struct undo *undo;
+for (undo = undobuf.undos; undo; undo = undo->next)
+	if (undo->kind == UNDO_MODE)
+	  {
+	    rtx reg = *undo->where.r;
+	    enum machine_mode new_mode = GET_MODE (reg);
+	    enum machine_mode old_mode = undo->old_contents.m;
+	    /* Temporarily revert mode back.  */
+	    adjust_reg_mode (reg, old_mode);
+	    if (reg == i2dest && i2scratch)
+	      {
+		/* If we used i2dest as a scratch register with a
+		   different mode, substitute it for the original
+		   i2src while its original mode is temporarily
+		   restored, and then clear i2scratch so that we don't
+		   do it again later.  */
+		propagate_for_debug (i2, i3, reg, i2src, false);
+		i2scratch = false;
+		/* Put back the new mode.  */
+		adjust_reg_mode (reg, new_mode);
+	      }
+	    else
+	      {
+		rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
+		rtx first, last;
+		if (reg == i2dest)
+		  {
+		    first = i2;
+		    last = i3;
+		  }
+		else
+		  {
+		    first = i3;
+		    last = undobuf.other_insn;
+		    gcc_assert (last);
+		  }
+		/* We're dealing with a reg that changed mode but not
+		   meaning, so we want to turn it into a subreg for
+		   the new mode.  However, because of REG sharing and
+		   because its mode had already changed, we have to do
+		   it in two steps.  First, replace any debug uses of
+		   reg, with its original mode temporarily restored,
+		   with this copy we have created; then, replace the
+		   copy with the SUBREG of the original shared reg,
+		   once again changed to the new mode.  */
+		propagate_for_debug (first, last, reg, tempreg, false);
+		adjust_reg_mode (reg, new_mode);
+		propagate_for_debug (first, last, tempreg,
+				     lowpart_subreg (old_mode, reg, new_mode),
+				     false);
+	      }
+	  }
+}
 /* If we will be able to accept this, we have made a
 change to the destination of I3.  This requires us to
 do a few adjustments.  */
 if (changed_i3_dest)
 LOG_LINKS (i2) = 0;
 REG_NOTES (i2) = 0;
 if (newi2pat)
 {
+	if (MAY_HAVE_DEBUG_INSNS && i2scratch)
+	  propagate_for_debug (i2, i3, i2dest, i2src, false);
 	INSN_CODE (i2) = i2_code_number;
 	PATTERN (i2) = newi2pat;
 }
 else
-SET_INSN_DELETED (i2);
+{
+	if (MAY_HAVE_DEBUG_INSNS && i2src)
+	  propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
+	SET_INSN_DELETED (i2);
+}
 if (i1)
 {
 	LOG_LINKS (i1) = 0;
 	REG_NOTES (i1) = 0;
+	if (MAY_HAVE_DEBUG_INSNS)
+	  propagate_for_debug (i1, i3, i1dest, i1src, false);
 	SET_INSN_DELETED (i1);
 }
 /* Get death notes for everything that is now used in either I3 or
 I2 and used to die in a previous insn.  If we built two new
 know these are REG_UNUSED and want them to go to the desired insn,
 so we always pass it as i3.  */
 if (newi2pat && new_i2_notes)
 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
 if (new_i3_notes)
 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
 /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
 put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
 we discard it in distribute_notes, we will decrement it again.  */
 if (i3dest_killed)
 {
 	if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
+	  distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
-					       NULL_RTX),
+					    NULL_RTX),
 			    NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
 	else
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
+	  distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
-					       NULL_RTX),
+					    NULL_RTX),
 			    NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
 			    elim_i2, elim_i1);
 }
 if (i2dest_in_i2src)
 {
 	if (newi2pat && reg_set_p (i2dest, newi2pat))
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
+	  distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
 			    NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
 	else
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
+	  distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
 			    NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
 			    NULL_RTX, NULL_RTX);
 }
 if (i1dest_in_i1src)
 {
 	if (newi2pat && reg_set_p (i1dest, newi2pat))
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
+	  distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
 			    NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
 	else
-	  distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
+	  distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
 			    NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
 			    NULL_RTX, NULL_RTX);
 }
 distribute_links (i3links);
 set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
 can affect nonzero_bits of newpat */
 if (newi2pat)
 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
-/* Set new_direct_jump_p if a new return or simple jump instruction
-has been created.
-If I3 is now an unconditional jump, ensure that it has a
-BARRIER following it since it may have initially been a
-conditional jump.  It may also be the last nonnote insn.  */
-if (returnjump_p (i3) || any_uncondjump_p (i3))
-{
-	*new_direct_jump_p = 1;
-	mark_jump_label (PATTERN (i3), i3, 0);
-	if ((temp = next_nonnote_insn (i3)) == NULL_RTX
-	    || !BARRIER_P (temp))
-	  emit_barrier_after (i3);
-}
-if (undobuf.other_insn != NULL_RTX
-	&& (returnjump_p (undobuf.other_insn)
-	    || any_uncondjump_p (undobuf.other_insn)))
-{
-	*new_direct_jump_p = 1;
-	if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
-	    || !BARRIER_P (temp))
-	  emit_barrier_after (undobuf.other_insn);
-}
-/* An NOOP jump does not need barrier, but it does need cleaning up
-of CFG.  */
-if (GET_CODE (newpat) == SET
-	&& SET_SRC (newpat) == pc_rtx
-	&& SET_DEST (newpat) == pc_rtx)
-*new_direct_jump_p = 1;
 }
 if (undobuf.other_insn != NULL_RTX)
 {
 if (dump_file)
 	{
 	  fprintf (dump_file, "modifying other_insn ");
 	  fprintf (dump_file, "modifying insn i3 ");
 	  dump_insn_slim (dump_file, i3);
 	}
 df_insn_rescan (i3);
 }
+/* Set new_direct_jump_p if a new return or simple jump instruction
+has been created.  Adjust the CFG accordingly.  */
+if (returnjump_p (i3) || any_uncondjump_p (i3))
+{
+*new_direct_jump_p = 1;
+mark_jump_label (PATTERN (i3), i3, 0);
+update_cfg_for_uncondjump (i3);
+}
+if (undobuf.other_insn != NULL_RTX
+&& (returnjump_p (undobuf.other_insn)
+	  || any_uncondjump_p (undobuf.other_insn)))
+{
+*new_direct_jump_p = 1;
+update_cfg_for_uncondjump (undobuf.other_insn);
+}
+/* A noop might also need cleaning up of CFG, if it comes from the
+simplification of a jump.  */
+if (GET_CODE (newpat) == SET
+&& SET_SRC (newpat) == pc_rtx
+&& SET_DEST (newpat) == pc_rtx)
+{
+*new_direct_jump_p = 1;
+update_cfg_for_uncondjump (i3);
+}
 combine_successes++;
 undo_commit ();
 if (added_links_insn
 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
 	 using LO_SUM and HIGH.  */
 if (GET_CODE (XEXP (x, 0)) == CONST
 	  || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
 	{
+	  enum machine_mode address_mode
+	    = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
 	  SUBST (XEXP (x, 0),
-		 gen_rtx_LO_SUM (Pmode,
+		 gen_rtx_LO_SUM (address_mode,
-				 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
+				 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
 				 XEXP (x, 0)));
 	  return &XEXP (XEXP (x, 0), 0);
 	}
 #endif
 	 address is not valid, perhaps will can split it up using
 	 the machine-specific way to split large constants.  We use
 	 the first pseudo-reg (one of the virtual regs) as a placeholder;
 	 it will not remain in the result.  */
 if (GET_CODE (XEXP (x, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
-	  && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
+	  && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
+					    MEM_ADDR_SPACE (x)))
 	{
 	  rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
 	  rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
 						      XEXP (x, 0)),
 					 subst_insn);
 	      && ! reg_mentioned_p (reg,
 				    SET_SRC (PATTERN (seq)))
 	      && NONJUMP_INSN_P (NEXT_INSN (seq))
 	      && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
 	      && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
-	      && memory_address_p (GET_MODE (x),
+	      && memory_address_addr_space_p
-				   SET_SRC (PATTERN (NEXT_INSN (seq)))))
+		   (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
+		    MEM_ADDR_SPACE (x)))
 	    {
 	      rtx src1 = SET_SRC (PATTERN (seq));
 	      rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
 	      /* Replace the placeholder in SRC2 with SRC1.  If we can
 	}
 /* If we have a PLUS whose first operand is complex, try computing it
 separately by making a split there.  */
 if (GET_CODE (XEXP (x, 0)) == PLUS
-&& ! memory_address_p (GET_MODE (x), XEXP (x, 0))
+&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
+					    MEM_ADDR_SPACE (x))
 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
 return &XEXP (XEXP (x, 0), 0);
 break;
 /* See if this is a bitfield assignment with everything constant.  If
 	 so, this is an IOR of an AND, so split it into that.  */
 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
 	  && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
 	      <= HOST_BITS_PER_WIDE_INT)
-	  && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (SET_DEST (x), 1))
-	  && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
+	  && CONST_INT_P (XEXP (SET_DEST (x), 2))
-	  && GET_CODE (SET_SRC (x)) == CONST_INT
+	  && CONST_INT_P (SET_SRC (x))
 	  && ((INTVAL (XEXP (SET_DEST (x), 1))
 	       + INTVAL (XEXP (SET_DEST (x), 2)))
 	      <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
 	  && ! side_effects_p (XEXP (SET_DEST (x), 0)))
 	{
 	     have taken more than one insn to make.  If the constant were
 	     not a valid argument to the AND but took only one insn to make,
 	     this is no worse, but if it took more than one insn, it will
 	     be better.  */
-	  if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (SET_SRC (x), 1))
 	      && REG_P (XEXP (SET_SRC (x), 0))
 	      && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
 	      && REG_P (SET_DEST (x))
 	      && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
 	      && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
 	  unsignedp = 0;
 	  break;
 	case SIGN_EXTRACT:
 	case ZERO_EXTRACT:
-	  if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (SET_SRC (x), 1))
-	      && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
+	      && CONST_INT_P (XEXP (SET_SRC (x), 2)))
 	    {
 	      inner = XEXP (SET_SRC (x), 0);
 	      len = INTVAL (XEXP (SET_SRC (x), 1));
 	      pos = INTVAL (XEXP (SET_SRC (x), 2));
 	      if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
 		return new_rtx;
 	      if (GET_CODE (x) == SUBREG
-		  && (GET_CODE (new_rtx) == CONST_INT
+		  && (CONST_INT_P (new_rtx)
 		      || GET_CODE (new_rtx) == CONST_DOUBLE))
 		{
 		  enum machine_mode mode = GET_MODE (x);
 		  x = simplify_subreg (GET_MODE (x), new_rtx,
 				       GET_MODE (SUBREG_REG (x)),
 				       SUBREG_BYTE (x));
 		  if (! x)
 		    x = gen_rtx_CLOBBER (mode, const0_rtx);
 		}
-	      else if (GET_CODE (new_rtx) == CONST_INT
+	      else if (CONST_INT_P (new_rtx)
 		       && GET_CODE (x) == ZERO_EXTEND)
 		{
 		  x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
 						new_rtx, GET_MODE (XEXP (x, 0)));
 		  gcc_assert (x);
 		x = simplify_gen_relational (reversed, mode, VOIDmode,
 					     cond, cop1);
 	      /* Likewise, we can make the negate of a comparison operation
 		 if the result values are - STORE_FLAG_VALUE and zero.  */
-	      else if (GET_CODE (true_rtx) == CONST_INT
+	      else if (CONST_INT_P (true_rtx)
 		       && INTVAL (true_rtx) == - STORE_FLAG_VALUE
 		       && false_rtx == const0_rtx)
 		x = simplify_gen_unary (NEG, mode,
 					simplify_gen_relational (cond_code,
 								 mode, VOIDmode,
 								 cond, cop1),
 					mode);
-	      else if (GET_CODE (false_rtx) == CONST_INT
+	      else if (CONST_INT_P (false_rtx)
 		       && INTVAL (false_rtx) == - STORE_FLAG_VALUE
 		       && true_rtx == const0_rtx
 		       && ((reversed = reversed_comparison_code_parts
 					(cond_code, cond, cop1, NULL))
 			   != UNKNOWN))
 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
 	 replaced by (lshiftrt X C).  This will convert
 	 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
 if (GET_CODE (temp) == ASHIFTRT
-	  && GET_CODE (XEXP (temp, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (temp, 1))
 	  && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
 	return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
 				     INTVAL (XEXP (temp, 1)));
 /* If X has only a single bit that might be nonzero, say, bit I, convert
 	 because we don't know the real bitsize of the partial
 	 integer mode.  */
 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
 	break;
-if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
+if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
-	  && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
-				    GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
 	SUBST (XEXP (x, 0),
 	       force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
 			      GET_MODE_MASK (mode), 0));
+/* We can truncate a constant value and return it.  */
+if (CONST_INT_P (XEXP (x, 0)))
+	return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
 	 whose value is a comparison can be replaced with a subreg if
 	 STORE_FLAG_VALUE permits.  */
 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 	  && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
 	  && (temp = get_last_value (XEXP (x, 0)))
 	  && COMPARISON_P (temp))
 	return gen_lowpart (mode, XEXP (x, 0));
 break;
-#ifdef HAVE_cc0
-case COMPARE:
-/* Convert (compare FOO (const_int 0)) to FOO unless we aren't
-	 using cc0, in which case we want to leave it as a COMPARE
-	 so we can distinguish it from a register-register-copy.  */
-if (XEXP (x, 1) == const0_rtx)
-	return XEXP (x, 0);
-/* x - 0 is the same as x unless x's mode has signed zeros and
-	 allows rounding towards -infinity.  Under those conditions,
-	 0 - 0 is -0.  */
-if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
-	    && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
-	  && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
-	return XEXP (x, 0);
-break;
-#endif
 case CONST:
 /* (const (const X)) can become (const X).  Do it this way rather than
 	 returning the inner CONST since CONST can be shared with a
 	 REG_EQUAL note.  */
 	 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
 	 bit-field and can be replaced by either a sign_extend or a
 	 sign_extract.  The `and' may be a zero_extend and the two
 	 <c>, -<c> constants may be reversed.  */
 if (GET_CODE (XEXP (x, 0)) == XOR
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
 	  && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
 	      || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
 	  && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 	  && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
-	       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
+	       && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
 	       && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
 		   == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
 	      || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
 		  && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
 		      == (unsigned int) i + 1))))
 case MINUS:
 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
 	 (and <foo> (const_int pow2-1))  */
 if (GET_CODE (XEXP (x, 1)) == AND
-	  && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 1), 1))
 	  && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
 	  && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
 	return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
 				       -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
 break;
 	  if (result)
 	    return result;
 	}
 /* Try simplify a*(b/c) as (a*b)/c.  */
 if (FLOAT_MODE_P (mode) && flag_associative_math
 	  && GET_CODE (XEXP (x, 0)) == DIV)
 	{
 	  rtx tem = simplify_binary_operation (MULT, mode,
 					       XEXP (XEXP (x, 0), 0),
 					       XEXP (x, 1));
 break;
 case UDIV:
 /* If this is a divide by a power of two, treat it as a shift if
 	 its first operand is a shift.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
 	  && (GET_CODE (XEXP (x, 0)) == ASHIFT
 	      || GET_CODE (XEXP (x, 0)) == LSHIFTRT
 	      || GET_CODE (XEXP (x, 0)) == ASHIFTRT
 	      || GET_CODE (XEXP (x, 0)) == ROTATE
 case LSHIFTRT:
 case ASHIFTRT:
 case ROTATE:
 case ROTATERT:
 /* If this is a shift by a constant amount, simplify it.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+if (CONST_INT_P (XEXP (x, 1)))
 	return simplify_shift_const (x, code, mode, XEXP (x, 0),
 				     INTVAL (XEXP (x, 1)));
 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
 	SUBST (XEXP (x, 1),
 if (comparison_p
 && reversed_comparison_code (cond, NULL) != UNKNOWN
 && (true_rtx == pc_rtx
 	  || (CONSTANT_P (true_rtx)
-	      && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
+	      && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
 	  || true_rtx == const0_rtx
 	  || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
 	  || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
 	      && !OBJECT_P (false_rtx))
 	  || reg_mentioned_p (true_rtx, false_rtx)
 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
 negation of a single bit, we can convert this operation to a shift.  We
 can actually do this more generally, but it doesn't seem worth it.  */
 if (true_code == NE && XEXP (cond, 1) == const0_rtx
-&& false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
+&& false_rtx == const0_rtx && CONST_INT_P (true_rtx)
 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
 	   && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
 	  || ((num_sign_bit_copies (XEXP (cond, 0), mode)
 	       == GET_MODE_BITSIZE (mode))
 	      && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
 simplify_shift_const (NULL_RTX, ASHIFT, mode,
 			    gen_lowpart (mode, XEXP (cond, 0)), i);
 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
 if (true_code == NE && XEXP (cond, 1) == const0_rtx
-&& false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
+&& false_rtx == const0_rtx && CONST_INT_P (true_rtx)
 && GET_MODE (XEXP (cond, 0)) == mode
 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
 	  == nonzero_bits (XEXP (cond, 0), mode)
 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
 return XEXP (cond, 0);
 	    }
 	}
 if (other_changed)
 	undobuf.other_insn = other_insn;
-#ifdef HAVE_cc0
-/* If we are now comparing against zero, change our source if
-	 needed.  If we do not use cc0, we always have a COMPARE.  */
-if (op1 == const0_rtx && dest == cc0_rtx)
-	{
-	  SUBST (SET_SRC (x), op0);
-	  src = op0;
-	}
-else
-#endif
 /* Otherwise, if we didn't previously have a COMPARE in the
 	 correct mode, we need one.  */
 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
 	{
 {
 case AND:
 /* We can call simplify_and_const_int only if we don't lose
 	 any (sign) bits when converting INTVAL (op1) to
 	 "unsigned HOST_WIDE_INT".  */
-if (GET_CODE (op1) == CONST_INT
+if (CONST_INT_P (op1)
 	  && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 	      || INTVAL (op1) > 0))
 	{
 	  x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
 	  if (GET_CODE (x) != AND)
 	 we can't tell whether the implicit way is right.
 	 Even for a mode that is no wider than a const_int,
 	 we can't win, because we need to sign extend one of its bits through
 	 the rest of it, and we don't know which bit.  */
-if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+if (CONST_INT_P (XEXP (x, 0)))
 	return x;
 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
 	 (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
 	 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
 case SIGN_EXTRACT:
 /* If the operand is a CLOBBER, just return it.  */
 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
 	return XEXP (x, 0);
-if (GET_CODE (XEXP (x, 1)) != CONST_INT
+if (!CONST_INT_P (XEXP (x, 1))
-	  || GET_CODE (XEXP (x, 2)) != CONST_INT
+	  || !CONST_INT_P (XEXP (x, 2))
 	  || GET_MODE (XEXP (x, 0)) == VOIDmode)
 	return x;
 /* Reject MODEs that aren't scalar integers because turning vector
 	 or complex modes into shifts causes problems.  */
 	  inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
 	  len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
 	  pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
 	}
 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
-	       && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (SET_DEST (x), 1)))
 	{
 	  inner = XEXP (SET_DEST (x), 0);
 	  len = INTVAL (XEXP (SET_DEST (x), 1));
 	  pos = XEXP (SET_DEST (x), 2);
 	  /* A constant position should stay within the width of INNER.  */
-	  if (GET_CODE (pos) == CONST_INT
+	  if (CONST_INT_P (pos)
 	      && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
 	    break;
 	  if (BITS_BIG_ENDIAN)
 	    {
-	      if (GET_CODE (pos) == CONST_INT)
+	      if (CONST_INT_P (pos))
 		pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
 			       - INTVAL (pos));
 	      else if (GET_CODE (pos) == MINUS
-		       && GET_CODE (XEXP (pos, 1)) == CONST_INT
+		       && CONST_INT_P (XEXP (pos, 1))
 		       && (INTVAL (XEXP (pos, 1))
 			   == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
 		/* If position is ADJUST - X, new position is X.  */
 		pos = XEXP (pos, 0);
 	      else
 if (MEM_P (SUBREG_REG (inner)))
 	is_mode = GET_MODE (SUBREG_REG (inner));
 inner = SUBREG_REG (inner);
 }
 else if (GET_CODE (inner) == ASHIFT
-	   && GET_CODE (XEXP (inner, 1)) == CONST_INT
+	   && CONST_INT_P (XEXP (inner, 1))
 	   && pos_rtx == 0 && pos == 0
 	   && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
 {
 /* We're extracting the least significant bits of an rtx
 	 (ashift X (const_int C)), where LEN > C.  Extract the
 	return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
 }
 inner_mode = GET_MODE (inner);
-if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
+if (pos_rtx && CONST_INT_P (pos_rtx))
 pos = INTVAL (pos_rtx), pos_rtx = 0;
 /* See if this can be done without an extraction.  We never can if the
 width of the field is not the same as that of some integer mode. For
 registers, we can only avoid the extraction if the position is at the
 		   : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
 if (mode == tmode)
 	return new_rtx;
-if (GET_CODE (new_rtx) == CONST_INT)
+if (CONST_INT_P (new_rtx))
 	return gen_int_mode (INTVAL (new_rtx), mode);
 /* If we know that no extraneous bits are set, and that the high
 	 bit is not set, convert the extraction to the cheaper of
 	 sign and zero extension, that are equivalent in these cases.  */
 		  - GET_MODE_SIZE (wanted_inner_mode) - offset);
 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
 }
-/* If INNER is not memory, we can always get it into the proper mode.  If we
+/* If INNER is not memory, get it into the proper mode.  If we are changing
-are changing its mode, POS must be a constant and smaller than the size
+its mode, POS must be a constant and smaller than the size of the new
-of the new mode.  */
+mode.  */
 else if (!MEM_P (inner))
 {
+/* On the LHS, don't create paradoxical subregs implicitely truncating
+	 the register unless TRULY_NOOP_TRUNCATION.  */
+if (in_dest
+	  && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
+				     GET_MODE_BITSIZE (wanted_inner_mode)))
+	return NULL_RTX;
 if (GET_MODE (inner) != wanted_inner_mode
 	  && (pos_rtx != 0
 	      || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
-	return 0;
+	return NULL_RTX;
 if (orig_pos < 0)
-	return 0;
+	return NULL_RTX;
 inner = force_to_mode (inner, wanted_inner_mode,
 			     pos_rtx
 			     || len + orig_pos >= HOST_BITS_PER_WIDE_INT
 			     ? ~(unsigned HOST_WIDE_INT) 0
 {
 case ASHIFT:
 /* This is the shift itself.  If it is wide enough, we will return
 	 either the value being shifted if the shift count is equal to
 	 COUNT or a shift for the difference.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) >= count)
 	return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
 				     INTVAL (XEXP (x, 1)) - count);
 break;
 break;
 case PLUS:  case IOR:  case XOR:  case AND:
 /* If we can safely shift this constant and we find the inner shift,
 	 make a new operation.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
 	  && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
 	return simplify_gen_binary (code, mode, tem,
 				    GEN_INT (INTVAL (XEXP (x, 1)) >> count));
 switch (code)
 {
 case ASHIFT:
 /* Convert shifts by constants into multiplications if inside
 	 an address.  */
-if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
+if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
 	  && INTVAL (XEXP (x, 1)) >= 0)
 	{
 	  new_rtx = make_compound_operation (XEXP (x, 0), next_code);
 	  new_rtx = gen_rtx_MULT (mode, new_rtx,
 break;
 case AND:
 /* If the second operand is not a constant, we can't do anything
 	 with it.  */
-if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+if (!CONST_INT_P (XEXP (x, 1)))
 	break;
 /* If the constant is a power of two minus one and the first operand
 	 is a logical right shift, make an extraction.  */
 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
 /* If we are have (and (rotate X C) M) and C is larger than the number
 	 of bits in M, this is an extraction.  */
 else if (GET_CODE (XEXP (x, 0)) == ROTATE
-	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	       && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	       && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
 	       && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
 	{
 	  new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
 	  new_rtx = make_extraction (mode, new_rtx,
 	 a logical shift and our mask turns off all the propagated sign
 	 bits, we can replace the logical shift with an arithmetic shift.  */
 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
 	       && !have_insn_for (LSHIFTRT, mode)
 	       && have_insn_for (ASHIFTRT, mode)
-	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	       && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	       && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
 	       && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
 	       && mode_width <= HOST_BITS_PER_WIDE_INT)
 	{
 	  unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
 lhs = XEXP (x, 0);
 rhs = XEXP (x, 1);
 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
 	 this is a SIGN_EXTRACT.  */
-if (GET_CODE (rhs) == CONST_INT
+if (CONST_INT_P (rhs)
 	  && GET_CODE (lhs) == ASHIFT
-	  && GET_CODE (XEXP (lhs, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (lhs, 1))
 	  && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
 	  && INTVAL (rhs) < mode_width)
 	{
 	  new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
 	  new_rtx = make_extraction (mode, new_rtx,
 	 seem worth the effort; the case checked for occurs on Alpha.  */
 if (!OBJECT_P (lhs)
 	  && ! (GET_CODE (lhs) == SUBREG
 		&& (OBJECT_P (SUBREG_REG (lhs))))
-	  && GET_CODE (rhs) == CONST_INT
+	  && CONST_INT_P (rhs)
 	  && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
 	  && INTVAL (rhs) < mode_width
 	  && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
 	new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
 			       0, NULL_RTX, mode_width - INTVAL (rhs),
 	    /* If we have something other than a SUBREG, we might have
 	       done an expansion, so rerun ourselves.  */
 	    if (GET_CODE (newer) != SUBREG)
 	      newer = make_compound_operation (newer, in_code);
+	    /* force_to_mode can expand compounds.  If it just re-expanded the
+	       compound use gen_lowpart instead to convert to the desired
+	       mode.  */
+	    if (rtx_equal_p (newer, x))
+	      return gen_lowpart (GET_MODE (x), tem);
 	    return newer;
 	  }
 	if (simplified)
 would need an explicit truncation.  */
 static rtx
 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
 {
-if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
+if (!CONST_INT_P (x)
-|| TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
+&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
-				GET_MODE_BITSIZE (GET_MODE (x)))
+&& !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
-|| (REG_P (x) && reg_truncated_to_mode (mode, x)))
+				 GET_MODE_BITSIZE (GET_MODE (x)))
-return gen_lowpart (mode, x);
+&& !(REG_P (x) && reg_truncated_to_mode (mode, x)))
-else
+{
-return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
+/* Bit-cast X into an integer mode.  */
+if (!SCALAR_INT_MODE_P (GET_MODE (x)))
+	x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
+x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
+			      x, GET_MODE (x));
+}
+return gen_lowpart (mode, x);
 }
 /* See if X can be simplified knowing that we will only refer to it in
 MODE and will only refer to those bits that are nonzero in MASK.
 If other bits are being computed or if masking operations are done
 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
 x = const0_rtx;
 /* If X is a CONST_INT, return a new one.  Do this here since the
 test below will fail.  */
-if (GET_CODE (x) == CONST_INT)
+if (CONST_INT_P (x))
 {
 if (SCALAR_INT_MODE_P (mode))
 	return gen_int_mode (INTVAL (x) & mask, mode);
 else
 	{
 get X in the proper mode.  */
 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
 return gen_lowpart (mode, x);
-/* The arithmetic simplifications here do the wrong thing on vector modes.  */
+/* We can ignore the effect of a SUBREG if it narrows the mode or
-if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
+if the constant masks to zero all the bits the mode doesn't have.  */
-return gen_lowpart (mode, x);
+if (GET_CODE (x) == SUBREG
+&& subreg_lowpart_p (x)
+&& ((GET_MODE_SIZE (GET_MODE (x))
+	   < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
+	  || (0 == (mask
+		    & GET_MODE_MASK (GET_MODE (x))
+		    & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
+return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
+/* The arithmetic simplifications here only work for scalar integer modes.  */
+if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
+return gen_lowpart_or_truncate (mode, x);
 switch (code)
 {
 case CLOBBER:
 /* If X is a (clobber (const_int)), return it since we know we are
 x = expand_compound_operation (x);
 if (GET_CODE (x) != code)
 	return force_to_mode (x, mode, mask, next_select);
 break;
-case SUBREG:
+case TRUNCATE:
-if (subreg_lowpart_p (x)
+/* Similarly for a truncate.  */
-	  /* We can ignore the effect of this SUBREG if it narrows the mode or
+return force_to_mode (XEXP (x, 0), mode, mask, next_select);
-	     if the constant masks to zero all the bits the mode doesn't
-	     have.  */
-	  && ((GET_MODE_SIZE (GET_MODE (x))
-	       < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
-	      || (0 == (mask
-			& GET_MODE_MASK (GET_MODE (x))
-			& ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
-	return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
-break;
 case AND:
 /* If this is an AND with a constant, convert it into an AND
 	 whose constant is the AND of that constant with MASK.  If it
 	 remains an AND of MASK, delete it since it is redundant.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+if (CONST_INT_P (XEXP (x, 1)))
 	{
 	  x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
 				      mask & INTVAL (XEXP (x, 1)));
 	  /* If X is still an AND, see if it is an AND with a mask that
 	     is just some low-order bits.  If so, and it is MASK, we don't
 	     need it.  */
-	  if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
 	      && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
 		  == mask))
 	    x = XEXP (x, 0);
 	  /* If it remains an AND, try making another AND with the bits
 	     in the mode mask that aren't in MASK turned on.  If the
 	     constant in the AND is wide enough, this might make a
 	     cheaper constant.  */
-	  if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
 	      && GET_MODE_MASK (GET_MODE (x)) != mask
 	      && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 	    {
 	      HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
 				    | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
 	if (width < HOST_BITS_PER_WIDE_INT
 	    && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
 	  smask |= (HOST_WIDE_INT) -1 << width;
-	if (GET_CODE (XEXP (x, 1)) == CONST_INT
+	if (CONST_INT_P (XEXP (x, 1))
 	    && exact_log2 (- smask) >= 0
 	    && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
 	    && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
 	  return force_to_mode (plus_constant (XEXP (x, 0),
 					       (INTVAL (XEXP (x, 1)) & smask)),
 goto binop;
 case MINUS:
 /* If X is (minus C Y) where C's least set bit is larger than any bit
 	 in the mask, then we may replace with (neg Y).  */
-if (GET_CODE (XEXP (x, 0)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 0))
 	  && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
 					& -INTVAL (XEXP (x, 0))))
 	      > mask))
 	{
 	  x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
 	  return force_to_mode (x, mode, mask, next_select);
 	}
 /* Similarly, if C contains every bit in the fuller_mask, then we may
 	 replace with (not Y).  */
-if (GET_CODE (XEXP (x, 0)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 0))
 	  && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
 	      == INTVAL (XEXP (x, 0))))
 	{
 	  x = simplify_gen_unary (NOT, GET_MODE (x),
 				  XEXP (x, 1), GET_MODE (x));
 	 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
 	 operation which may be a bitfield extraction.  Ensure that the
 	 constant we form is not wider than the mode of X.  */
 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
 	  && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  && ((INTVAL (XEXP (XEXP (x, 0), 1))
 	       + floor_log2 (INTVAL (XEXP (x, 1))))
 	      < GET_MODE_BITSIZE (GET_MODE (x)))
 	  && (INTVAL (XEXP (x, 1))
 	      & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
 binop:
 /* For most binary operations, just propagate into the operation and
 	 change the mode if we have an operation of that mode.  */
-op0 = gen_lowpart_or_truncate (op_mode,
+op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
-				     force_to_mode (XEXP (x, 0), mode, mask,
+op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
-						    next_select));
-op1 = gen_lowpart_or_truncate (op_mode,
+/* If we ended up truncating both operands, truncate the result of the
-				     force_to_mode (XEXP (x, 1), mode, mask,
+	 operation instead.  */
-					next_select));
+if (GET_CODE (op0) == TRUNCATE
+	  && GET_CODE (op1) == TRUNCATE)
+	{
+	  op0 = XEXP (op0, 0);
+	  op1 = XEXP (op1, 0);
+	}
+op0 = gen_lowpart_or_truncate (op_mode, op0);
+op1 = gen_lowpart_or_truncate (op_mode, op1);
 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
 	x = simplify_gen_binary (code, op_mode, op0, op1);
 break;
 	 However, we cannot do anything with shifts where we cannot
 	 guarantee that the counts are smaller than the size of the mode
 	 because such a count will have a different meaning in a
 	 wider mode.  */
-if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (! (CONST_INT_P (XEXP (x, 1))
 	     && INTVAL (XEXP (x, 1)) >= 0
 	     && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
 	  && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
 		&& (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
 		    < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
 	break;
 /* If the shift count is a constant and we can do arithmetic in
 	 the mode of the shift, refine which bits we need.  Otherwise, use the
 	 conservative form of the mask.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) >= 0
 	  && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
 	  && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
 	mask >>= INTVAL (XEXP (x, 1));
 else
 case LSHIFTRT:
 /* Here we can only do something if the shift count is a constant,
 	 this shift constant is valid for the host, and we can do arithmetic
 	 in OP_MODE.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
 	  && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
 	{
 	  rtx inner = XEXP (x, 0);
 	  unsigned HOST_WIDE_INT inner_mask;
 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
 	 shift and AND produces only copies of the sign bit (C2 is one less
 	 than a power of two), we can do this with just a shift.  */
 if (GET_CODE (x) == LSHIFTRT
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  /* The shift puts one of the sign bit copies in the least significant
 	     bit.  */
 	  && ((INTVAL (XEXP (x, 1))
 	       + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
 	      >= GET_MODE_BITSIZE (GET_MODE (x)))
 	 MASK only includes those bits, this can be a logical shift, which may
 	 allow simplifications.  If MASK is a single-bit field not within
 	 those bits, we are requesting a copy of the sign bit and hence can
 	 shift the sign bit to the appropriate location.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
+if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
 	  && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
 	{
 	  int i;
 	  /* If the considered data is wider than HOST_WIDE_INT, we can't
 /* If this is a zero- or sign-extension operation that just affects bits
 	 we don't care about, remove it.  Be sure the call above returned
 	 something that is still a shift.  */
 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) >= 0
 	  && (INTVAL (XEXP (x, 1))
 	      <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
 	  && GET_CODE (XEXP (x, 0)) == ASHIFT
 	  && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
 case ROTATERT:
 /* If the shift count is constant and we can do computations
 	 in the mode of X, compute where the bits we care about are.
 	 Otherwise, we can't do anything.  Don't change the mode of
 	 the shift or propagate MODE into the shift, though.  */
-if (GET_CODE (XEXP (x, 1)) == CONST_INT
+if (CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) >= 0)
 	{
 	  temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
 					    GET_MODE (x), GEN_INT (mask),
 					    XEXP (x, 1));
-	  if (temp && GET_CODE (temp) == CONST_INT)
+	  if (temp && CONST_INT_P (temp))
 	    SUBST (XEXP (x, 0),
 		   force_to_mode (XEXP (x, 0), GET_MODE (x),
 				  INTVAL (temp), next_select));
 	}
 break;
 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
 	 same as the XOR case above.  Ensure that the constant we form is not
 	 wider than the mode of X.  */
 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
 	  && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
 	      < GET_MODE_BITSIZE (GET_MODE (x)))
 	  && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
 	{
 a clear of a one-bit field.  We will have changed it to
 (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
 for a SUBREG.  */
 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
-&& GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
+&& CONST_INT_P (XEXP (XEXP (src, 0), 0))
 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
 {
 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
 				1, 1, 1, 0);
 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
 && subreg_lowpart_p (XEXP (src, 0))
 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
 	  < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
-&& GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
+&& CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
 {
 assign = make_extraction (VOIDmode, dest, 0,
 				XEXP (SUBREG_REG (XEXP (src, 0)), 1),
 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
 SRC is an AND with all bits of that field set, then we can discard
 the AND.  */
 if (GET_CODE (dest) == ZERO_EXTRACT
-&& GET_CODE (XEXP (dest, 1)) == CONST_INT
+&& CONST_INT_P (XEXP (dest, 1))
 && GET_CODE (src) == AND
-&& GET_CODE (XEXP (src, 1)) == CONST_INT)
+&& CONST_INT_P (XEXP (src, 1)))
 {
 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
 unsigned HOST_WIDE_INT ze_mask;
 rhs = expand_compound_operation (XEXP (src, 0));
 lhs = expand_compound_operation (XEXP (src, 1));
 if (GET_CODE (rhs) == AND
-&& GET_CODE (XEXP (rhs, 1)) == CONST_INT
+&& CONST_INT_P (XEXP (rhs, 1))
 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
 else if (GET_CODE (lhs) == AND
-	   && GET_CODE (XEXP (lhs, 1)) == CONST_INT
+	   && CONST_INT_P (XEXP (lhs, 1))
 	   && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
 else
 return x;
 		       0);
 /* If SRC is masked by an AND that does not make a difference in
 the value being stored, strip it.  */
 if (GET_CODE (assign) == ZERO_EXTRACT
-&& GET_CODE (XEXP (assign, 1)) == CONST_INT
+&& CONST_INT_P (XEXP (assign, 1))
 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
 && GET_CODE (src) == AND
-&& GET_CODE (XEXP (src, 1)) == CONST_INT
+&& CONST_INT_P (XEXP (src, 1))
 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
 	  == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
 src = XEXP (src, 0);
 return gen_rtx_SET (VOIDmode, assign, src);
 if (GET_CODE (varop) == CLOBBER)
 return varop;
 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
 to VAROP and return the new constant.  */
-if (GET_CODE (varop) == CONST_INT)
+if (CONST_INT_P (varop))
 return gen_int_mode (INTVAL (varop) & constop, mode);
 /* See what bits may be nonzero in VAROP.  Unlike the general case of
 a call to nonzero_bits, here we don't care about bits outside
 MODE.  */
 	 ??? For 2.5, try to tighten up the MD files in this regard
 	 instead of this kludge.  */
 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
-	  && GET_CODE (tem) == CONST_INT
+	  && CONST_INT_P (tem)
 	  && INTVAL (tem) > 0
 	  && 0 != (INTVAL (tem)
 		   & ((HOST_WIDE_INT) 1
 		      << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 	tem = GEN_INT (INTVAL (tem)
 *pconst0 = trunc_int_for_mode (const0, mode);
 return 1;
 }
+/* A helper to simplify_shift_const_1 to determine the mode we can perform
+the shift in.  The original shift operation CODE is performed on OP in
+ORIG_MODE.  Return the wider mode MODE if we can perform the operation
+in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
+result of the shift is subject to operation OUTER_CODE with operand
+OUTER_CONST.  */
+static enum machine_mode
+try_widen_shift_mode (enum rtx_code code, rtx op, int count,
+		      enum machine_mode orig_mode, enum machine_mode mode,
+		      enum rtx_code outer_code, HOST_WIDE_INT outer_const)
+{
+if (orig_mode == mode)
+return mode;
+gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
+/* In general we can't perform in wider mode for right shift and rotate.  */
+switch (code)
+{
+case ASHIFTRT:
+/* We can still widen if the bits brought in from the left are identical
+	 to the sign bit of ORIG_MODE.  */
+if (num_sign_bit_copies (op, mode)
+	  > (unsigned) (GET_MODE_BITSIZE (mode)
+			- GET_MODE_BITSIZE (orig_mode)))
+	return mode;
+return orig_mode;
+case LSHIFTRT:
+/* Similarly here but with zero bits.  */
+if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
+	  && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
+	return mode;
+/* We can also widen if the bits brought in will be masked off.  This
+	 operation is performed in ORIG_MODE.  */
+if (outer_code == AND)
+	{
+	  int care_bits = low_bitmask_len (orig_mode, outer_const);
+	  if (care_bits >= 0
+	      && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
+	    return mode;
+	}
+/* fall through */
+case ROTATE:
+return orig_mode;
+case ROTATERT:
+gcc_unreachable ();
+default:
+return mode;
+}
+}
 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
 The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
 simplify it.  Otherwise, return a simplified value.
 The shift is normally computed in the widest mode we find in VAROP, as
 	    count = bitsize / GET_MODE_NUNITS (result_mode) - count;
 	  else
 	    count = bitsize - count;
 	}
-/* We need to determine what mode we will do the shift in.  If the
+shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
-	 shift is a right shift or a ROTATE, we must always do it in the mode
+					 mode, outer_op, outer_const);
-	 it was originally done in.  Otherwise, we can do it in MODE, the
-	 widest mode encountered.  */
-shift_mode
-	= (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
-	   ? result_mode : mode);
 /* Handle cases where the count is greater than the size of the mode
 	 minus 1.  For ASHIFT, use the size minus one as the count (this can
 	 occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
 	 take the count modulo the size.  For other shifts, the result is
 	case MULT:
 	  /* Some machines use MULT instead of ASHIFT because MULT
 	     is cheaper.  But it is still better on those machines to
 	     merge two shifts into one.  */
-	  if (GET_CODE (XEXP (varop, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (varop, 1))
 	      && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
 	    {
 	      varop
 		= simplify_gen_binary (ASHIFT, GET_MODE (varop),
 				       XEXP (varop, 0),
 	    }
 	  break;
 	case UDIV:
 	  /* Similar, for when divides are cheaper.  */
-	  if (GET_CODE (XEXP (varop, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (varop, 1))
 	      && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
 	    {
 	      varop
 		= simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
 				       XEXP (varop, 0),
 	case LSHIFTRT:
 	case ASHIFT:
 	case ROTATE:
 	  /* Here we have two nested shifts.  The result is usually the
 	     AND of a new shift with a mask.  We compute the result below.  */
-	  if (GET_CODE (XEXP (varop, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (varop, 1))
 	      && INTVAL (XEXP (varop, 1)) >= 0
 	      && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
 	      && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
 	      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 	      && !VECTOR_MODE_P (result_mode))
 		= simplify_const_binary_operation (code, result_mode, mask_rtx,
 						   GEN_INT (count));
 	      /* Give up if we can't compute an outer operation to use.  */
 	      if (mask_rtx == 0
-		  || GET_CODE (mask_rtx) != CONST_INT
+		  || !CONST_INT_P (mask_rtx)
 		  || ! merge_outer_ops (&outer_op, &outer_const, AND,
 					INTVAL (mask_rtx),
 					result_mode, &complement_p))
 		break;
 	  /* If we have (A << B << C) for any shift, we can convert this to
 	     (A << C << B).  This wins if A is a constant.  Only try this if
 	     B is not a constant.  */
 	  else if (GET_CODE (varop) == code
-		   && GET_CODE (XEXP (varop, 0)) == CONST_INT
+		   && CONST_INT_P (XEXP (varop, 0))
-		   && GET_CODE (XEXP (varop, 1)) != CONST_INT)
+		   && !CONST_INT_P (XEXP (varop, 1)))
 	    {
 	      rtx new_rtx = simplify_const_binary_operation (code, mode,
 							 XEXP (varop, 0),
 							 GEN_INT (count));
 	      varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
 	     to allow it to possibly combine with another logical and the
 	     shift to combine with another shift.  This also canonicalizes to
 	     what a ZERO_EXTRACT looks like.  Also, some machines have
 	     (and (shift)) insns.  */
-	  if (GET_CODE (XEXP (varop, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (varop, 1))
 	      /* We can't do this if we have (ashiftrt (xor))  and the
 		 constant has its sign bit set in shift_mode.  */
 	      && !(code == ASHIFTRT && GET_CODE (varop) == XOR
 		   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
 					      shift_mode))
 	      && (new_rtx = simplify_const_binary_operation (code, result_mode,
 							 XEXP (varop, 1),
 							 GEN_INT (count))) != 0
-	      && GET_CODE (new_rtx) == CONST_INT
+	      && CONST_INT_P (new_rtx)
 	      && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
 				  INTVAL (new_rtx), result_mode, &complement_p))
 	    {
 	      varop = XEXP (varop, 0);
 	      continue;
 	  /* If we can't do that, try to simplify the shift in each arm of the
 	     logical expression, make a new logical expression, and apply
 	     the inverse distributive law.  This also can't be done
 	     for some (ashiftrt (xor)).  */
-	  if (GET_CODE (XEXP (varop, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (varop, 1))
 	     && !(code == ASHIFTRT && GET_CODE (varop) == XOR
 		  && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
 					     shift_mode)))
 	    {
 	      rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
 	      continue;
 	    }
 	  /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
 	  if (code == ASHIFT
-	      && GET_CODE (XEXP (varop, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (varop, 1))
 	      && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
 							 XEXP (varop, 1),
 							 GEN_INT (count))) != 0
-	      && GET_CODE (new_rtx) == CONST_INT
+	      && CONST_INT_P (new_rtx)
 	      && merge_outer_ops (&outer_op, &outer_const, PLUS,
 				  INTVAL (new_rtx), result_mode, &complement_p))
 	    {
 	      varop = XEXP (varop, 0);
 	      continue;
 	     signbit', and attempt to change the PLUS to an XOR and move it to
 	     the outer operation as is done above in the AND/IOR/XOR case
 	     leg for shift(logical). See details in logical handling above
 	     for reasoning in doing so.  */
 	  if (code == LSHIFTRT
-	      && GET_CODE (XEXP (varop, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (varop, 1))
 	      && mode_signbit_p (result_mode, XEXP (varop, 1))
 	      && (new_rtx = simplify_const_binary_operation (code, result_mode,
 							 XEXP (varop, 1),
 							 GEN_INT (count))) != 0
-	      && GET_CODE (new_rtx) == CONST_INT
+	      && CONST_INT_P (new_rtx)
 	      && merge_outer_ops (&outer_op, &outer_const, XOR,
 				  INTVAL (new_rtx), result_mode, &complement_p))
 	    {
 	      varop = XEXP (varop, 0);
 	      continue;
 	  if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
 	      && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
 	      && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
 	      && (code == LSHIFTRT || code == ASHIFTRT)
-	      && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
 	      && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
 	      && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
 	    {
 	      count = 0;
 	      varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
 	case TRUNCATE:
 	  /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
 	     if the truncate does not affect the value.  */
 	  if (code == LSHIFTRT
 	      && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
-	      && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
 	      && (INTVAL (XEXP (XEXP (varop, 0), 1))
 		  >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
 		      - GET_MODE_BITSIZE (GET_MODE (varop)))))
 	    {
 	      rtx varop_inner = XEXP (varop, 0);
 	}
 break;
 }
-/* We need to determine what mode to do the shift in.  If the shift is
+shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
-a right shift or ROTATE, we must always do it in the mode it was
+				     outer_op, outer_const);
-originally done in.  Otherwise, we can do it in MODE, the widest mode
-encountered.  The code we care about is that of the shift that will
-actually be done, not the shift that was originally requested.  */
-shift_mode
-= (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
-? result_mode : mode);
 /* We have now finished analyzing the shift.  The result should be
 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
 to the result of the shift.  OUTER_CONST is the relevant constant,
 	   i < XVECLEN (newpat, 0); i++)
 	{
 	  if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
 	      && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
 	    return -1;
 	  if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
 	    {
 	      gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
-	      notes = gen_rtx_EXPR_LIST (REG_UNUSED,
+	      notes = alloc_reg_note (REG_UNUSED,
-					 XEXP (XVECEXP (newpat, 0, i), 0), notes);
+				      XEXP (XVECEXP (newpat, 0, i), 0), notes);
 	    }
 	}
 pat = newpat;
 }
 /* We can only support MODE being wider than a word if X is a
 constant integer or has a mode the same size.  */
 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
 && ! ((imode == VOIDmode
-	     && (GET_CODE (x) == CONST_INT
+	     && (CONST_INT_P (x)
 		 || GET_CODE (x) == CONST_DOUBLE))
 	    || isize == osize))
 goto fail;
 /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
 	  && GET_CODE (XEXP (op1, 0)) == ASHIFT
 	  && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
 	  && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
 	  && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
 	      == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
-	  && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (op0, 1))
 	  && XEXP (op0, 1) == XEXP (op1, 1)
 	  && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
 	  && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
 	  && (INTVAL (XEXP (op0, 1))
 	      == (GET_MODE_BITSIZE (GET_MODE (op0))
 	      || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
 		  && (code != GT && code != LT && code != GE && code != LE))
 	      || (GET_CODE (op0) == ASHIFTRT
 		  && (code != GTU && code != LTU
 		      && code != GEU && code != LEU)))
-	  && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (op0, 1))
 	  && INTVAL (XEXP (op0, 1)) >= 0
 	  && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
 	  && XEXP (op0, 1) == XEXP (op1, 1))
 	{
 	  enum machine_mode mode = GET_MODE (op0);
 	 Similarly, check for a case where the AND's are ZERO_EXTEND
 	 operations from some narrower mode even though a SUBREG is not
 	 present.  */
 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
-	       && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	       && CONST_INT_P (XEXP (op0, 1))
-	       && GET_CODE (XEXP (op1, 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (op1, 1)))
 	{
 	  rtx inner_op0 = XEXP (op0, 0);
 	  rtx inner_op1 = XEXP (op1, 0);
 	  HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
 	  HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
 /* We now enter a loop during which we will try to simplify the comparison.
 For the most part, we only are concerned with comparisons with zero,
 but some things may really be comparisons with zero but not start
 out looking that way.  */
-while (GET_CODE (op1) == CONST_INT)
+while (CONST_INT_P (op1))
 {
 enum machine_mode mode = GET_MODE (op0);
 unsigned int mode_width = GET_MODE_BITSIZE (mode);
 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
 int equality_comparison_p;
 	     with zero, we can convert this into an equality comparison
 	     between the position and the location of the single bit.  */
 	  /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
 	     have already reduced the shift count modulo the word size.  */
 	  if (!SHIFT_COUNT_TRUNCATED
-	      && GET_CODE (XEXP (op0, 0)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 0))
 	      && XEXP (op0, 1) == const1_rtx
 	      && equality_comparison_p && const_op == 0
 	      && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
 	    {
 	      if (BITS_BIG_ENDIAN)
 	  break;
 	case ROTATE:
 	  /* If we are testing equality and our count is a constant, we
 	     can perform the inverse operation on our RHS.  */
-	  if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
 	      && (tem = simplify_binary_operation (ROTATERT, mode,
 						   op1, XEXP (op0, 1))) != 0)
 	    {
 	      op0 = XEXP (op0, 0);
 	      op1 = tem;
 	  /* If we are doing a < 0 or >= 0 comparison, it means we are testing
 	     a particular bit.  Convert it to an AND of a constant of that
 	     bit.  This will be converted into a ZERO_EXTRACT.  */
 	  if (const_op == 0 && sign_bit_comparison_p
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && mode_width <= HOST_BITS_PER_WIDE_INT)
 	    {
 	      op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
 					    ((HOST_WIDE_INT) 1
 					     << (mode_width - 1
 	      && ! unsigned_comparison_p
 	      && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
 	      && ((unsigned HOST_WIDE_INT) const_op
 		  < (((unsigned HOST_WIDE_INT) 1
 		      << (GET_MODE_BITSIZE (mode) - 1))))
-	      && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
+	      && have_insn_for (COMPARE, mode))
 	    {
 	      op0 = XEXP (op0, 0);
 	      continue;
 	    }
 	  break;
 	  if (mode_width <= HOST_BITS_PER_WIDE_INT
 	      && subreg_lowpart_p (op0)
 	      && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
 	      && GET_CODE (SUBREG_REG (op0)) == PLUS
-	      && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
+	      && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
 	    {
 	      enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
 	      rtx a = XEXP (SUBREG_REG (op0), 0);
 	      HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
 	  mode = GET_MODE (XEXP (op0, 0));
 	  if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
 	      && (unsigned_comparison_p || equality_comparison_p)
 	      && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
 	      && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
-	      && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
+	      && have_insn_for (COMPARE, mode))
 	    {
 	      op0 = XEXP (op0, 0);
 	      continue;
 	    }
 	  break;
 	    }
 	  /* The sign bit of (minus (ashiftrt X C) X), where C is the number
 	     of bits in X minus 1, is one iff X > 0.  */
 	  if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
-	      && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
 	      && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
 		 == mode_width - 1
 	      && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
 	    {
 	      op0 = XEXP (op0, 1);
 	  /* If we are comparing (and (lshiftrt X C1) C2) for equality with
 	     zero and X is a comparison and C1 and C2 describe only bits set
 	     in STORE_FLAG_VALUE, we can compare with X.  */
 	  if (const_op == 0 && equality_comparison_p
 	      && mode_width <= HOST_BITS_PER_WIDE_INT
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
-	      && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
 	      && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
 	      && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
 	    {
 	      mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
 		      << INTVAL (XEXP (XEXP (op0, 0), 1)));
 	  /* If we are doing an equality comparison of an AND of a bit equal
 	     to the sign bit, replace this with a LT or GE comparison of
 	     the underlying value.  */
 	  if (equality_comparison_p
 	      && const_op == 0
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && mode_width <= HOST_BITS_PER_WIDE_INT
 	      && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
 		  == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
 	    {
 	      op0 = XEXP (op0, 0);
 	     unless TRULY_NOOP_TRUNCATION allows it or the register is
 	     known to hold a value of the required mode the
 	     transformation is invalid.  */
 	  if ((equality_comparison_p || unsigned_comparison_p)
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
 				   & GET_MODE_MASK (mode))
 				  + 1)) >= 0
 	      && const_op >> i == 0
 	      && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
 		      || (mode_width > GET_MODE_BITSIZE (tmode)
 			  && mode_width <= BITS_PER_WORD)
 #endif
 		      || (mode_width <= GET_MODE_BITSIZE (tmode)
 			  && subreg_lowpart_p (XEXP (op0, 0))))
-		  && GET_CODE (XEXP (op0, 1)) == CONST_INT
+		  && CONST_INT_P (XEXP (op0, 1))
 		  && mode_width <= HOST_BITS_PER_WIDE_INT
 		  && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
 		  && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
 		  && (c1 & ~GET_MODE_MASK (tmode)) == 0
 		  && c1 != mask
 	      rtx shift_op = XEXP (XEXP (op0, 0), 0);
 	      rtx shift_count = XEXP (XEXP (op0, 0), 1);
 	      if (GET_CODE (shift_op) == NOT
 		  || (GET_CODE (shift_op) == XOR
-		      && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
+		      && CONST_INT_P (XEXP (shift_op, 1))
-		      && GET_CODE (shift_count) == CONST_INT
+		      && CONST_INT_P (shift_count)
 		      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 		      && (INTVAL (XEXP (shift_op, 1))
 			  == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
 		{
 		  op0 = simplify_and_const_int
 	  /* If we have (compare (ashift FOO N) (const_int C)) and
 	     the high order N bits of FOO (N+1 if an inequality comparison)
 	     are known to be zero, we can do this by comparing FOO with C
 	     shifted right N bits so long as the low-order N bits of C are
 	     zero.  */
-	  if (GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (op0, 1))
 	      && INTVAL (XEXP (op0, 1)) >= 0
 	      && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
 		  < HOST_BITS_PER_WIDE_INT)
 	      && ((const_op
 		   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
 	      continue;
 	    }
 	  /* If we are doing a sign bit comparison, it means we are testing
 	     a particular bit.  Convert it to the appropriate AND.  */
-	  if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
 	      && mode_width <= HOST_BITS_PER_WIDE_INT)
 	    {
 	      op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
 					    ((HOST_WIDE_INT) 1
 					     << (mode_width - 1
 	  /* If this an equality comparison with zero and we are shifting
 	     the low bit to the sign bit, we can convert this to an AND of the
 	     low-order bit.  */
 	  if (const_op == 0 && equality_comparison_p
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
 		 == mode_width - 1)
 	    {
 	      op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
 					    (HOST_WIDE_INT) 1);
 	case ASHIFTRT:
 	  /* If this is an equality comparison with zero, we can do this
 	     as a logical shift, which might be much simpler.  */
 	  if (equality_comparison_p && const_op == 0
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT)
+	      && CONST_INT_P (XEXP (op0, 1)))
 	    {
 	      op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
 					  XEXP (op0, 0),
 					  INTVAL (XEXP (op0, 1)));
 	      continue;
 	    }
 	  /* If OP0 is a sign extension and CODE is not an unsigned comparison,
 	     do the comparison in a narrower mode.  */
 	  if (! unsigned_comparison_p
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && GET_CODE (XEXP (op0, 0)) == ASHIFT
 	      && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
 	      && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
 					 MODE_INT, 1)) != BLKmode
 	      && (((unsigned HOST_WIDE_INT) const_op
 	  /* Likewise if OP0 is a PLUS of a sign extension with a
 	     constant, which is usually represented with the PLUS
 	     between the shifts.  */
 	  if (! unsigned_comparison_p
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && GET_CODE (XEXP (op0, 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
 	      && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
 	      && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
 	      && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
 					 MODE_INT, 1)) != BLKmode
 	      && (((unsigned HOST_WIDE_INT) const_op
 	case LSHIFTRT:
 	  /* If we have (compare (xshiftrt FOO N) (const_int C)) and
 	     the low order N bits of FOO are known to be zero, we can do this
 	     by comparing FOO with C shifted left N bits so long as no
 	     overflow occurs.  */
-	  if (GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  if (CONST_INT_P (XEXP (op0, 1))
 	      && INTVAL (XEXP (op0, 1)) >= 0
 	      && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
 	      && mode_width <= HOST_BITS_PER_WIDE_INT
 	      && (nonzero_bits (XEXP (op0, 0), mode)
 		  & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
 	  /* If we are using this shift to extract just the sign bit, we
 	     can replace this with an LT or GE comparison.  */
 	  if (const_op == 0
 	      && (equality_comparison_p || sign_bit_comparison_p)
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (op0, 1))
 	      && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
 		 == mode_width - 1)
 	    {
 	      op0 = XEXP (op0, 0);
 	      code = (code == NE || code == GT ? LT : GE);
 	 tmode = GET_MODE_WIDER_MODE (tmode))
 if (have_insn_for (COMPARE, tmode))
 	{
 	  int zero_extended;
+	  /* If this is a test for negative, we can make an explicit
+	     test of the sign bit.  Test this first so we can use
+	     a paradoxical subreg to extend OP0.  */
+	  if (op1 == const0_rtx && (code == LT || code == GE)
+	      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
+	    {
+	      op0 = simplify_gen_binary (AND, tmode,
+					 gen_lowpart (tmode, op0),
+					 GEN_INT ((HOST_WIDE_INT) 1
+						  << (GET_MODE_BITSIZE (mode)
+						      - 1)));
+	      code = (code == LT) ? NE : EQ;
+	      break;
+	    }
 	  /* If the only nonzero bits in OP0 and OP1 are those in the
 	     narrower mode and this is an equality or unsigned comparison,
 	     we can use the wider mode.  Similarly for sign-extended
 	     values, in which case it is true for all comparisons.  */
 	  zero_extended = ((code == EQ || code == NE
 			    || code == GEU || code == GTU
 			    || code == LEU || code == LTU)
 			   && (nonzero_bits (op0, tmode)
 			       & ~GET_MODE_MASK (mode)) == 0
-			   && ((GET_CODE (op1) == CONST_INT
+			   && ((CONST_INT_P (op1)
 				|| (nonzero_bits (op1, tmode)
 				    & ~GET_MODE_MASK (mode)) == 0)));
 	  if (zero_extended
 	      || ((num_sign_bit_copies (op0, tmode)
 		op0 = simplify_gen_binary (AND, tmode,
 					   gen_lowpart (tmode,
 							XEXP (op0, 0)),
 					   gen_lowpart (tmode,
 							XEXP (op0, 1)));
+	      else
-	      op0 = gen_lowpart (tmode, op0);
+		{
-	      if (zero_extended && GET_CODE (op1) == CONST_INT)
+		  if (zero_extended)
-		op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
+		    {
-	      op1 = gen_lowpart (tmode, op1);
+		      op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
-	      break;
+		      op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
-	    }
+		    }
+		  else
-	  /* If this is a test for negative, we can make an explicit
+		    {
-	     test of the sign bit.  */
+		      op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
+		      op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
-	  if (op1 == const0_rtx && (code == LT || code == GE)
+		    }
-	      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
+		  break;
-	    {
+		}
-	      op0 = simplify_gen_binary (AND, tmode,
-					 gen_lowpart (tmode, op0),
-					 GEN_INT ((HOST_WIDE_INT) 1
-						  << (GET_MODE_BITSIZE (mode)
-						      - 1)));
-	      code = (code == LT) ? NE : EQ;
-	      break;
 	    }
 	}
 #ifdef CANONICALIZE_COMPARISON
 /* If this machine only supports a subset of valid comparisons, see if we
 if (insn)
 	rsp->last_set = insn;
 rsp->last_set_value = 0;
-rsp->last_set_mode = 0;
+rsp->last_set_mode = VOIDmode;
 rsp->last_set_nonzero_bits = 0;
 rsp->last_set_sign_bit_copies = 0;
 rsp->last_death = 0;
-rsp->truncated_to_mode = 0;
+rsp->truncated_to_mode = VOIDmode;
 }
 /* Mark registers that are being referenced in this value.  */
 if (value)
 update_table_tick (value);
 /* The value being assigned might refer to X (like in "x++;").  In that
 case, we must replace it with (clobber (const_int 0)) to prevent
 infinite loops.  */
 rsp = VEC_index (reg_stat_type, reg_stat, regno);
-if (value && ! get_last_value_validate (&value, insn,
+if (value && !get_last_value_validate (&value, insn, label_tick, 0))
-					  rsp->last_set_label, 0))
 {
 value = copy_rtx (value);
-if (! get_last_value_validate (&value, insn,
+if (!get_last_value_validate (&value, insn, label_tick, 1))
-				     rsp->last_set_label, 1))
 	value = 0;
 }
 /* For the main register being modified, update the value, the mode, the
 nonzero bits, and the number of sign bit copies.  */
 	    rsp = VEC_index (reg_stat_type, reg_stat, i);
 	    rsp->last_set_invalid = 1;
 	    rsp->last_set = insn;
 	    rsp->last_set_value = 0;
-	    rsp->last_set_mode = 0;
+	    rsp->last_set_mode = VOIDmode;
 	    rsp->last_set_nonzero_bits = 0;
 	    rsp->last_set_sign_bit_copies = 0;
 	    rsp->last_death = 0;
-	    rsp->truncated_to_mode = 0;
+	    rsp->truncated_to_mode = VOIDmode;
 	  }
 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
 /* We can't combine into a call pattern.  Remember, though, that
 	    break;
 	  }
 }
 }
-/* Utility routine for the following function.  Verify that all the registers
+/* Verify that all the registers and memory references mentioned in *LOC are
-mentioned in *LOC are valid when *LOC was part of a value set when
+still valid.  *LOC was part of a value set in INSN when label_tick was
-label_tick == TICK.  Return 0 if some are not.
+equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
+the invalid references with (clobber (const_int 0)) and return 1.  This
-If REPLACE is nonzero, replace the invalid reference with
+replacement is useful because we often can get useful information about
-(clobber (const_int 0)) and return 1.  This replacement is useful because
+the form of a value (e.g., if it was produced by a shift that always
-we often can get useful information about the form of a value (e.g., if
+produces -1 or 0) even though we don't know exactly what registers it
-it was produced by a shift that always produces -1 or 0) even though
+was produced from.  */
-we don't know exactly what registers it was produced from.  */
 static int
 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
 {
 rtx x = *loc;
 	  }
 	}
 return 1;
 }
-/* If this is a memory reference, make sure that there were
+/* If this is a memory reference, make sure that there were no stores after
-no stores after it that might have clobbered the value.  We don't
+it that might have clobbered the value.  We don't have alias info, so we
-have alias info, so we assume any store invalidates it.  */
+assume any store invalidates it.  Moreover, we only have local UIDs, so
+we also assume that there were stores in the intervening basic blocks.  */
 else if (MEM_P (x) && !MEM_READONLY_P (x)
-	   && DF_INSN_LUID (insn) <= mem_last_set)
+	   && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
 {
 if (replace)
 	*loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
 return replace;
 }
 if (rsp->last_set_label == label_tick
 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
 return 0;
 /* If the value has all its registers valid, return it.  */
-if (get_last_value_validate (&value, rsp->last_set,
+if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
-			       rsp->last_set_label, 0))
 return value;
 /* Otherwise, make a copy and replace any invalid register with
 (clobber (const_int 0)).  If that fails for some reason, return 0.  */
 value = copy_rtx (value);
-if (get_last_value_validate (&value, rsp->last_set,
+if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
-			       rsp->last_set_label, 1))
 return value;
 return 0;
 }
 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
 	if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
 	  return 0;
 }
-/* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
+/* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
-beginning of function.  */
+beginning of basic block.  */
-for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
+block = BLOCK_FOR_INSN (insn);
-insn = prev_nonnote_insn (insn))
+for (;;)
 {
-note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
+if (INSN_P (insn))
-if (reg_dead_flag)
+{
-	return reg_dead_flag == 1 ? 1 : 0;
+	  note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
+	  if (reg_dead_flag)
-if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
+	    return reg_dead_flag == 1 ? 1 : 0;
-	return 1;
-}
+	  if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
+	    return 1;
-/* Get the basic block that we were in.  */
+}
-if (insn == 0)
-block = ENTRY_BLOCK_PTR->next_bb;
+if (insn == BB_HEAD (block))
-else
+	break;
-{
-FOR_EACH_BB (block)
+insn = PREV_INSN (insn);
-	if (insn == BB_HEAD (block))
+}
-	  break;
+/* Look at live-in sets for the basic block that we were in.  */
-if (block == EXIT_BLOCK_PTR)
-	return 0;
-}
 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
 if (REGNO_REG_SET_P (df_get_live_in (block), i))
 return 0;
 return 1;
 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
 	  && ! reg_referenced_p (x, maybe_kill_insn))
 	return;
 if (where_dead
+	  && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
 	  && DF_INSN_LUID (where_dead) >= from_luid
 	  && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
 	{
 	  rtx note = remove_death (regno, where_dead);
 	    {
 	      XEXP (note, 1) = *pnotes;
 	      *pnotes = note;
 	    }
 	  else
-	    *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
+	    *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
 	}
 return;
 }
 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
 	return 1;
 return 0;
 }
+/* Return the next insn after INSN that is neither a NOTE nor a
+DEBUG_INSN.  This routine does not look inside SEQUENCEs.  */
+static rtx
+next_nonnote_nondebug_insn (rtx insn)
+{
+while (insn)
+{
+insn = NEXT_INSN (insn);
+if (insn == 0)
+	break;
+if (NOTE_P (insn))
+	continue;
+if (DEBUG_INSN_P (insn))
+	continue;
+break;
+}
+return insn;
+}
 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
 as appropriate.  I3 and I2 are the insns resulting from the combination
 insns including FROM (I2 may be zero).
 		  && CALL_P (from_insn)
 		  && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
 		place = from_insn;
 	      else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
 		place = i3;
-	      else if (i2 != 0 && next_nonnote_insn (i2) == i3
+	      else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
 		       && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
 		place = i2;
 	      else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
 			&& !(i2mod
 			     && reg_overlap_mentioned_p (XEXP (note, 0),
 	    {
 	      basic_block bb = this_basic_block;
 	      for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
 		{
-		  if (! INSN_P (tem))
+		  if (!NONDEBUG_INSN_P (tem))
 		    {
 		      if (tem == BB_HEAD (bb))
 			break;
 		      continue;
 		    }
 			  if (! dead_or_set_p (place, piece)
 			      && ! reg_bitfield_target_p (piece,
 							  PATTERN (place)))
 			    {
-			      rtx new_note
+			      rtx new_note = alloc_reg_note (REG_DEAD, piece,
-				= gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
+							     NULL_RTX);
 			      distribute_notes (new_note, place, place,
 						NULL_RTX, NULL_RTX, NULL_RTX);
 			    }
 			  else if (! refers_to_regno_p (i, i + 1,
 							PATTERN (place), 0)
 				   && ! find_regno_fusage (place, USE, i))
 			    for (tem = PREV_INSN (place); ;
 				 tem = PREV_INSN (tem))
 			      {
-				if (! INSN_P (tem))
+				if (!NONDEBUG_INSN_P (tem))
 				  {
 				    if (tem == BB_HEAD (bb))
 			 	      break;
 				    continue;
 				  }
 	  XEXP (note, 1) = REG_NOTES (place);
 	  REG_NOTES (place) = note;
 	}
 if (place2)
-	REG_NOTES (place2)
+	add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
-	  = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
-			    XEXP (note, 0), REG_NOTES (place2));
 }
 }
 /* Similarly to above, distribute the LOG_LINKS that used to be present on
 I3, I2, and I1 to new locations.  This is also called to add a link
 for (insn = NEXT_INSN (XEXP (link, 0));
 	   (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
 		     || BB_HEAD (this_basic_block->next_bb) != insn));
 	   insn = NEXT_INSN (insn))
-	if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
+	if (DEBUG_INSN_P (insn))
+	  continue;
+	else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
 	  {
 	    if (reg_referenced_p (reg, PATTERN (insn)))
 	      place = insn;
 	    break;
 	  }
 rest_of_handle_combine,               /* execute */
 NULL,                                 /* sub */
 NULL,                                 /* next */
 0,                                    /* static_pass_number */
 TV_COMBINE,                           /* tv_id */
-0,                                    /* properties_required */
+PROP_cfglayout,                       /* properties_required */
 0,                                    /* properties_provided */
 0,                                    /* properties_destroyed */
 0,                                    /* todo_flags_start */
 TODO_dump_func |
 TODO_df_finish | TODO_verify_rtl_sharing |

Mercurial > hg > CbC > CbC_gcc

comparison gcc/combine.c @ 55:77e2b8dfacca gcc-4.4.5