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comparison gcc/config/arc/arc.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
583 (match_operand:SI 3 "register_operand" "")))] 583 (match_operand:SI 3 "register_operand" "")))]
584 "" 584 ""
585 " 585 "
586 { 586 {
587 enum rtx_code code = GET_CODE (operands[1]); 587 enum rtx_code code = GET_CODE (operands[1]);
588 rtx ccreg 588 rtx cc_reg = gen_compare_reg (code, XEXP (operands[1], 0),
589 = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1), 589 XEXP (operands[1], 1));
590 61); 590 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx);
591
592 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
593 }") 591 }")
594
595 ;(define_expand "movdicc"
596 ; [(set (match_operand:DI 0 "register_operand" "")
597 ; (if_then_else:DI (match_operand 1 "comparison_operator" "")
598 ; (match_operand:DI 2 "nonmemory_operand" "")
599 ; (match_operand:DI 3 "register_operand" "")))]
600 ; "0 /* ??? this would work better if we had cmpdi */"
601 ; "
602 ;{
603 ; enum rtx_code code = GET_CODE (operands[1]);
604 ; rtx ccreg
605 ; = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
606 ; 61);
607 ;
608 ; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
609 ;}")
610 592
611 (define_expand "movsfcc" 593 (define_expand "movsfcc"
612 [(set (match_operand:SF 0 "register_operand" "") 594 [(set (match_operand:SF 0 "register_operand" "")
613 (if_then_else:SF (match_operand 1 "comparison_operator" "") 595 (if_then_else:SF (match_operand 1 "comparison_operator" "")
614 (match_operand:SF 2 "nonmemory_operand" "") 596 (match_operand:SF 2 "nonmemory_operand" "")
615 (match_operand:SF 3 "register_operand" "")))] 597 (match_operand:SF 3 "register_operand" "")))]
616 "" 598 ""
617 " 599 "
618 { 600 {
619 enum rtx_code code = GET_CODE (operands[1]); 601 enum rtx_code code = GET_CODE (operands[1]);
620 rtx ccreg 602 rtx cc_reg = gen_compare_reg (code, XEXP (operands[1], 0),
621 = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1), 603 XEXP (operands[1], 1));
622 61); 604 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx);
623
624 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
625 }") 605 }")
626
627 ;(define_expand "movdfcc"
628 ; [(set (match_operand:DF 0 "register_operand" "")
629 ; (if_then_else:DF (match_operand 1 "comparison_operator" "")
630 ; (match_operand:DF 2 "nonmemory_operand" "")
631 ; (match_operand:DF 3 "register_operand" "")))]
632 ; "0 /* ??? can generate less efficient code if constants involved */"
633 ; "
634 ;{
635 ; enum rtx_code code = GET_CODE (operands[1]);
636 ; rtx ccreg
637 ; = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
638 ; 61);
639 ;
640 ; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
641 ;}")
642 606
643 (define_insn "*movsicc_insn" 607 (define_insn "*movsicc_insn"
644 [(set (match_operand:SI 0 "register_operand" "=r") 608 [(set (match_operand:SI 0 "register_operand" "=r")
645 (if_then_else:SI (match_operand 1 "comparison_operator" "") 609 (if_then_else:SI (match_operand 1 "comparison_operator" "")
646 (match_operand:SI 2 "nonmemory_operand" "rJi") 610 (match_operand:SI 2 "nonmemory_operand" "rJi")
647 (match_operand:SI 3 "register_operand" "0")))] 611 (match_operand:SI 3 "register_operand" "0")))]
648 "" 612 ""
649 "mov.%d1 %0,%S2" 613 "mov.%d1 %0,%S2"
650 [(set_attr "type" "cmove")]) 614 [(set_attr "type" "cmove")])
651 615
652 ; ??? This doesn't properly handle constants.
653 ;(define_insn "*movdicc_insn"
654 ; [(set (match_operand:DI 0 "register_operand" "=r,r")
655 ; (if_then_else:DI (match_operand 1 "comparison_operator" "")
656 ; (match_operand:DI 2 "nonmemory_operand" "r,Ji")
657 ; (match_operand:DI 3 "register_operand" "0,0")))]
658 ; "0"
659 ; "*
660 ;{
661 ; switch (which_alternative)
662 ; {
663 ; case 0 :
664 ; /* We normally copy the low-numbered register first. However, if
665 ; the first register operand 0 is the same as the second register of
666 ; operand 1, we must copy in the opposite order. */
667 ; if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
668 ; return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
669 ; else
670 ; return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
671 ; case 1 :
672 ; return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
673 ; }
674 ;}"
675 ; [(set_attr "type" "cmove,cmove")
676 ; (set_attr "length" "2,4")])
677
678 (define_insn "*movsfcc_insn" 616 (define_insn "*movsfcc_insn"
679 [(set (match_operand:SF 0 "register_operand" "=r,r") 617 [(set (match_operand:SF 0 "register_operand" "=r,r")
680 (if_then_else:SF (match_operand 1 "comparison_operator" "") 618 (if_then_else:SF (match_operand 1 "comparison_operator" "")
681 (match_operand:SF 2 "nonmemory_operand" "r,E") 619 (match_operand:SF 2 "nonmemory_operand" "r,E")
682 (match_operand:SF 3 "register_operand" "0,0")))] 620 (match_operand:SF 3 "register_operand" "0,0")))]
684 "@ 622 "@
685 mov.%d1 %0,%2 623 mov.%d1 %0,%2
686 mov.%d1 %0,%2 ; %A2" 624 mov.%d1 %0,%2 ; %A2"
687 [(set_attr "type" "cmove,cmove")]) 625 [(set_attr "type" "cmove,cmove")])
688 626
689 ;(define_insn "*movdfcc_insn"
690 ; [(set (match_operand:DF 0 "register_operand" "=r,r")
691 ; (if_then_else:DF (match_operand 1 "comparison_operator" "")
692 ; (match_operand:DF 2 "nonmemory_operand" "r,E")
693 ; (match_operand:DF 3 "register_operand" "0,0")))]
694 ; "0"
695 ; "*
696 ;{
697 ; switch (which_alternative)
698 ; {
699 ; case 0 :
700 ; /* We normally copy the low-numbered register first. However, if
701 ; the first register operand 0 is the same as the second register of
702 ; operand 1, we must copy in the opposite order. */
703 ; if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
704 ; return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
705 ; else
706 ; return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
707 ; case 1 :
708 ; return \"mov.%d1 %0,%L2\;mov.%d1 %R0,%H2 ; %A2\";
709 ; }
710 ;}"
711 ; [(set_attr "type" "cmove,cmove")
712 ; (set_attr "length" "2,4")])
713 627
714 ;; Zero extension instructions. 628 ;; Zero extension instructions.
715 ;; ??? We don't support volatile memrefs here, but I'm not sure why. 629 ;; ??? We don't support volatile memrefs here, but I'm not sure why.
716 630
717 (define_insn "zero_extendqihi2" 631 (define_insn "zero_extendqihi2"
1154 (set_attr "length" "8")]) 1068 (set_attr "length" "8")])
1155 1069
1156 ;; Compare instructions. 1070 ;; Compare instructions.
1157 ;; This controls RTL generation and register allocation. 1071 ;; This controls RTL generation and register allocation.
1158 1072
1159 ;; We generate RTL for comparisons and branches by having the cmpxx
1160 ;; patterns store away the operands. Then, the scc and bcc patterns
1161 ;; emit RTL for both the compare and the branch.
1162
1163 (define_expand "cmpsi"
1164 [(set (reg:CC 61)
1165 (compare:CC (match_operand:SI 0 "register_operand" "")
1166 (match_operand:SI 1 "nonmemory_operand" "")))]
1167 ""
1168 "
1169 {
1170 arc_compare_op0 = operands[0];
1171 arc_compare_op1 = operands[1];
1172 DONE;
1173 }")
1174
1175 ;; ??? We may be able to relax this a bit by adding a new constant 'K' for 0. 1073 ;; ??? We may be able to relax this a bit by adding a new constant 'K' for 0.
1176 ;; This assumes sub.f 0,symbol,0 is a valid insn. 1074 ;; This assumes sub.f 0,symbol,0 is a valid insn.
1177 ;; Note that "sub.f 0,r0,1" is an 8 byte insn. To avoid unnecessarily 1075 ;; Note that "sub.f 0,r0,1" is an 8 byte insn. To avoid unnecessarily
1178 ;; creating 8 byte insns we duplicate %1 in the destination reg of the insn 1076 ;; creating 8 byte insns we duplicate %1 in the destination reg of the insn
1179 ;; if it's a small constant. 1077 ;; if it's a small constant.
1209 sub.f 0,%0,%1 1107 sub.f 0,%0,%1
1210 sub.f %1,%0,%1 1108 sub.f %1,%0,%1
1211 sub.f 0,%0,%1" 1109 sub.f 0,%0,%1"
1212 [(set_attr "type" "compare,compare,compare")]) 1110 [(set_attr "type" "compare,compare,compare")])
1213 1111
1214 ;; Next come the scc insns. 1112 ;; Next come the scc insn and its expander.
1215 1113
1216 (define_expand "seq" 1114 (define_expand "cstoresi4"
1217 [(set (match_operand:SI 0 "register_operand" "=r") 1115 [(set (match_dup 4)
1218 (eq:SI (match_dup 1) (const_int 0)))] 1116 (match_op_dup 5
1117 [(match_operand:SI 2 "register_operand" "")
1118 (match_operand:SI 3 "nonmemory_operand" "")]))
1119 (set (match_operand:SI 0 "register_operand")
1120 (match_operator:SI 1 "ordered_comparison_operator"
1121 [(match_dup 4)
1122 (const_int 0)]))]
1219 "" 1123 ""
1220 " 1124 "
1221 { 1125 {
1222 operands[1] = gen_compare_reg (EQ, arc_compare_op0, arc_compare_op1); 1126 operands[4] = gen_compare_reg (GET_CODE (operands[1]),
1223 }") 1127 operands[2], operands[3]);
1224 1128 operands[5] = gen_rtx_fmt_ee (COMPARE,
1225 (define_expand "sne" 1129 GET_MODE (operands[4]),
1226 [(set (match_operand:SI 0 "register_operand" "=r") 1130 operands[2], operands[3]);
1227 (ne:SI (match_dup 1) (const_int 0)))]
1228 ""
1229 "
1230 {
1231 operands[1] = gen_compare_reg (NE, arc_compare_op0, arc_compare_op1);
1232 }")
1233
1234 (define_expand "sgt"
1235 [(set (match_operand:SI 0 "register_operand" "=r")
1236 (gt:SI (match_dup 1) (const_int 0)))]
1237 ""
1238 "
1239 {
1240 operands[1] = gen_compare_reg (GT, arc_compare_op0, arc_compare_op1);
1241 }")
1242
1243 (define_expand "sle"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (le:SI (match_dup 1) (const_int 0)))]
1246 ""
1247 "
1248 {
1249 operands[1] = gen_compare_reg (LE, arc_compare_op0, arc_compare_op1);
1250 }")
1251
1252 (define_expand "sge"
1253 [(set (match_operand:SI 0 "register_operand" "=r")
1254 (ge:SI (match_dup 1) (const_int 0)))]
1255 ""
1256 "
1257 {
1258 operands[1] = gen_compare_reg (GE, arc_compare_op0, arc_compare_op1);
1259 }")
1260
1261 (define_expand "slt"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (lt:SI (match_dup 1) (const_int 0)))]
1264 ""
1265 "
1266 {
1267 operands[1] = gen_compare_reg (LT, arc_compare_op0, arc_compare_op1);
1268 }")
1269
1270 (define_expand "sgtu"
1271 [(set (match_operand:SI 0 "register_operand" "=r")
1272 (gtu:SI (match_dup 1) (const_int 0)))]
1273 ""
1274 "
1275 {
1276 operands[1] = gen_compare_reg (GTU, arc_compare_op0, arc_compare_op1);
1277 }")
1278
1279 (define_expand "sleu"
1280 [(set (match_operand:SI 0 "register_operand" "=r")
1281 (leu:SI (match_dup 1) (const_int 0)))]
1282 ""
1283 "
1284 {
1285 operands[1] = gen_compare_reg (LEU, arc_compare_op0, arc_compare_op1);
1286 }")
1287
1288 (define_expand "sgeu"
1289 [(set (match_operand:SI 0 "register_operand" "=r")
1290 (geu:SI (match_dup 1) (const_int 0)))]
1291 ""
1292 "
1293 {
1294 operands[1] = gen_compare_reg (GEU, arc_compare_op0, arc_compare_op1);
1295 }")
1296
1297 (define_expand "sltu"
1298 [(set (match_operand:SI 0 "register_operand" "=r")
1299 (ltu:SI (match_dup 1) (const_int 0)))]
1300 ""
1301 "
1302 {
1303 operands[1] = gen_compare_reg (LTU, arc_compare_op0, arc_compare_op1);
1304 }") 1131 }")
1305 1132
1306 (define_insn "*scc_insn" 1133 (define_insn "*scc_insn"
1307 [(set (match_operand:SI 0 "register_operand" "=r") 1134 [(set (match_operand:SI 0 "register_operand" "=r")
1308 (match_operator:SI 1 "comparison_operator" [(reg 61) (const_int 0)]))] 1135 (match_operator:SI 1 "comparison_operator" [(reg 61) (const_int 0)]))]
1330 [(set_attr "type" "unary") 1157 [(set_attr "type" "unary")
1331 (set_attr "length" "2")]) 1158 (set_attr "length" "2")])
1332 1159
1333 ;; These control RTL generation for conditional jump insns 1160 ;; These control RTL generation for conditional jump insns
1334 1161
1335 (define_expand "beq" 1162 (define_expand "cbranchsi4"
1336 [(set (pc) 1163 [(set (match_dup 4)
1337 (if_then_else (eq (match_dup 1) (const_int 0)) 1164 (match_op_dup 5
1338 (label_ref (match_operand 0 "" "")) 1165 [(match_operand:SI 1 "register_operand" "")
1339 (pc)))] 1166 (match_operand:SI 2 "nonmemory_operand" "")]))
1167 (set (pc)
1168 (if_then_else
1169 (match_operator 0 "ordered_comparison_operator"
1170 [(match_dup 4)
1171 (const_int 0)])
1172 (label_ref (match_operand 3 "" ""))
1173 (pc)))]
1340 "" 1174 ""
1341 " 1175 "
1342 { 1176 {
1343 operands[1] = gen_compare_reg (EQ, arc_compare_op0, arc_compare_op1); 1177 operands[4] = gen_compare_reg (GET_CODE (operands[0]),
1344 }") 1178 operands[1], operands[2]);
1345 1179 operands[5] = gen_rtx_fmt_ee (COMPARE,
1346 (define_expand "bne" 1180 GET_MODE (operands[4]),
1347 [(set (pc) 1181 operands[1], operands[2]);
1348 (if_then_else (ne (match_dup 1) (const_int 0))
1349 (label_ref (match_operand 0 "" ""))
1350 (pc)))]
1351 ""
1352 "
1353 {
1354 operands[1] = gen_compare_reg (NE, arc_compare_op0, arc_compare_op1);
1355 }")
1356
1357 (define_expand "bgt"
1358 [(set (pc)
1359 (if_then_else (gt (match_dup 1) (const_int 0))
1360 (label_ref (match_operand 0 "" ""))
1361 (pc)))]
1362 ""
1363 "
1364 {
1365 operands[1] = gen_compare_reg (GT, arc_compare_op0, arc_compare_op1);
1366 }")
1367
1368 (define_expand "ble"
1369 [(set (pc)
1370 (if_then_else (le (match_dup 1) (const_int 0))
1371 (label_ref (match_operand 0 "" ""))
1372 (pc)))]
1373 ""
1374 "
1375 {
1376 operands[1] = gen_compare_reg (LE, arc_compare_op0, arc_compare_op1);
1377 }")
1378
1379 (define_expand "bge"
1380 [(set (pc)
1381 (if_then_else (ge (match_dup 1) (const_int 0))
1382 (label_ref (match_operand 0 "" ""))
1383 (pc)))]
1384 ""
1385 "
1386 {
1387 operands[1] = gen_compare_reg (GE, arc_compare_op0, arc_compare_op1);
1388 }")
1389
1390 (define_expand "blt"
1391 [(set (pc)
1392 (if_then_else (lt (match_dup 1) (const_int 0))
1393 (label_ref (match_operand 0 "" ""))
1394 (pc)))]
1395 ""
1396 "
1397 {
1398 operands[1] = gen_compare_reg (LT, arc_compare_op0, arc_compare_op1);
1399 }")
1400
1401 (define_expand "bgtu"
1402 [(set (pc)
1403 (if_then_else (gtu (match_dup 1) (const_int 0))
1404 (label_ref (match_operand 0 "" ""))
1405 (pc)))]
1406 ""
1407 "
1408 {
1409 operands[1] = gen_compare_reg (GTU, arc_compare_op0, arc_compare_op1);
1410 }")
1411
1412 (define_expand "bleu"
1413 [(set (pc)
1414 (if_then_else (leu (match_dup 1) (const_int 0))
1415 (label_ref (match_operand 0 "" ""))
1416 (pc)))]
1417 ""
1418 "
1419 {
1420 operands[1] = gen_compare_reg (LEU, arc_compare_op0, arc_compare_op1);
1421 }")
1422
1423 (define_expand "bgeu"
1424 [(set (pc)
1425 (if_then_else (geu (match_dup 1) (const_int 0))
1426 (label_ref (match_operand 0 "" ""))
1427 (pc)))]
1428 ""
1429 "
1430 {
1431 operands[1] = gen_compare_reg (GEU, arc_compare_op0, arc_compare_op1);
1432 }")
1433
1434 (define_expand "bltu"
1435 [(set (pc)
1436 (if_then_else (ltu (match_dup 1) (const_int 0))
1437 (label_ref (match_operand 0 "" ""))
1438 (pc)))]
1439 ""
1440 "
1441 {
1442 operands[1] = gen_compare_reg (LTU, arc_compare_op0, arc_compare_op1);
1443 }") 1182 }")
1444 1183
1445 ;; Now match both normal and inverted jump. 1184 ;; Now match both normal and inverted jump.
1446 1185
1447 (define_insn "*branch_insn" 1186 (define_insn "*branch_insn"