Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/avr/avr.md @ 55:77e2b8dfacca gcc-4.4.5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; -*- Mode: Scheme -*- 1 ;; -*- Mode: Scheme -*-
2 ;; Machine description for GNU compiler, 2 ;; Machine description for GNU compiler,
3 ;; for ATMEL AVR micro controllers. 3 ;; for ATMEL AVR micro controllers.
4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, 4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
5 ;; 2009 Free Software Foundation, Inc. 5 ;; 2009 Free Software Foundation, Inc.
6 ;; Contributed by Denis Chertykov (denisc@overta.ru) 6 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
7 7
8 ;; This file is part of GCC. 8 ;; This file is part of GCC.
9 9
10 ;; GCC is free software; you can redistribute it and/or modify 10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by 11 ;; it under the terms of the GNU General Public License as published by
26 ;; B Add 1 to REG number, MEM address or CONST_INT. 26 ;; B Add 1 to REG number, MEM address or CONST_INT.
27 ;; C Add 2. 27 ;; C Add 2.
28 ;; D Add 3. 28 ;; D Add 3.
29 ;; j Branch condition. 29 ;; j Branch condition.
30 ;; k Reverse branch condition. 30 ;; k Reverse branch condition.
31 ;;..m..Constant Direct Data memory address.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands. 32 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z) 33 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30) 34 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
35 ;;..x..Constant Direct Program memory address.
34 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL. 36 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
35 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL. 37 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
36 38
37 ;; UNSPEC usage: 39 ;; UNSPEC usage:
38 ;; 0 Length of a string, see "strlenhi". 40 ;; 0 Length of a string, see "strlenhi".
116 (const_int 2))] 118 (const_int 2))]
117 (const_int 2))) 119 (const_int 2)))
118 120
119 ;; Define mode iterator 121 ;; Define mode iterator
120 (define_mode_iterator QISI [(QI "") (HI "") (SI "")]) 122 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
123 (define_mode_iterator QIDI [(QI "") (HI "") (SI "") (DI "")])
121 124
122 ;;======================================================================== 125 ;;========================================================================
123 ;; The following is used by nonlocal_goto and setjmp. 126 ;; The following is used by nonlocal_goto and setjmp.
124 ;; The receiver pattern will create no instructions since internally 127 ;; The receiver pattern will create no instructions since internally
125 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28 128 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
233 operands[1] = copy_to_mode_reg(QImode, operand1); 236 operands[1] = copy_to_mode_reg(QImode, operand1);
234 ") 237 ")
235 238
236 (define_insn "*movqi" 239 (define_insn "*movqi"
237 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r") 240 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
238 (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))] 241 (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))]
239 "(register_operand (operands[0],QImode) 242 "(register_operand (operands[0],QImode)
240 || register_operand (operands[1], QImode) || const0_rtx == operands[1])" 243 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
241 "* return output_movqi (insn, operands, NULL);" 244 "* return output_movqi (insn, operands, NULL);"
242 [(set_attr "length" "1,1,5,5,1,1,4") 245 [(set_attr "length" "1,1,5,5,1,1,4")
243 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")]) 246 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
334 [(set_attr "length" "4") 337 [(set_attr "length" "4")
335 (set_attr "cc" "none")]) 338 (set_attr "cc" "none")])
336 339
337 (define_insn "*movhi" 340 (define_insn "*movhi"
338 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r") 341 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
339 (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))] 342 (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))]
340 "(register_operand (operands[0],HImode) 343 "(register_operand (operands[0],HImode)
341 || register_operand (operands[1],HImode) || const0_rtx == operands[1])" 344 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
342 "* return output_movhi (insn, operands, NULL);" 345 "* return output_movhi (insn, operands, NULL);"
343 [(set_attr "length" "2,6,7,2,6,5,2") 346 [(set_attr "length" "2,6,7,2,6,5,2")
344 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")]) 347 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
505 /* Compare with zero and jump if not equal. */ 508 /* Compare with zero and jump if not equal. */
506 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1, 509 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
507 label); 510 label);
508 /* Set jump probability based on loop count. */ 511 /* Set jump probability based on loop count. */
509 jump = get_last_insn (); 512 jump = get_last_insn ();
510 REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_BR_PROB, 513 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
511 GEN_INT (prob),
512 REG_NOTES (jump));
513 DONE; 514 DONE;
514 }") 515 }")
515 516
516 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 517 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
517 ;; memset (%0, %2, %1) 518 ;; memset (%0, %2, %1)
1051 1052
1052 ;; Generate libgcc.S calls ourselves, because: 1053 ;; Generate libgcc.S calls ourselves, because:
1053 ;; - we know exactly which registers are clobbered (for QI and HI 1054 ;; - we know exactly which registers are clobbered (for QI and HI
1054 ;; modes, some of the call-used registers are preserved) 1055 ;; modes, some of the call-used registers are preserved)
1055 ;; - we get both the quotient and the remainder at no extra cost 1056 ;; - we get both the quotient and the remainder at no extra cost
1056 1057 ;; - we split the patterns only after the first CSE passes because
1057 (define_expand "divmodqi4" 1058 ;; CSE has problems to operate on hard regs.
1058 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" "")) 1059 ;;
1059 (set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) 1060 (define_insn_and_split "divmodqi4"
1061 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1062 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
1063 (match_operand:QI 2 "pseudo_register_operand" "")))
1064 (set (match_operand:QI 3 "pseudo_register_operand" "")
1065 (mod:QI (match_dup 1) (match_dup 2)))
1066 (clobber (reg:QI 22))
1067 (clobber (reg:QI 23))
1068 (clobber (reg:QI 24))
1069 (clobber (reg:QI 25))])]
1070 ""
1071 "this divmodqi4 pattern should have been splitted;"
1072 ""
1073 [(set (reg:QI 24) (match_dup 1))
1074 (set (reg:QI 22) (match_dup 2))
1060 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22))) 1075 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1061 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22))) 1076 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1062 (clobber (reg:QI 22)) 1077 (clobber (reg:QI 22))
1063 (clobber (reg:QI 23))]) 1078 (clobber (reg:QI 23))])
1064 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24)) 1079 (set (match_dup 0) (reg:QI 24))
1065 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))] 1080 (set (match_dup 3) (reg:QI 25))]
1066 ""
1067 "") 1081 "")
1068 1082
1069 (define_insn "*divmodqi4_call" 1083 (define_insn "*divmodqi4_call"
1070 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22))) 1084 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1071 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22))) 1085 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1074 "" 1088 ""
1075 "%~call __divmodqi4" 1089 "%~call __divmodqi4"
1076 [(set_attr "type" "xcall") 1090 [(set_attr "type" "xcall")
1077 (set_attr "cc" "clobber")]) 1091 (set_attr "cc" "clobber")])
1078 1092
1079 (define_expand "udivmodqi4" 1093 (define_insn_and_split "udivmodqi4"
1080 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" "")) 1094 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1081 (set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) 1095 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
1096 (match_operand:QI 2 "pseudo_register_operand" "")))
1097 (set (match_operand:QI 3 "pseudo_register_operand" "")
1098 (umod:QI (match_dup 1) (match_dup 2)))
1099 (clobber (reg:QI 22))
1100 (clobber (reg:QI 23))
1101 (clobber (reg:QI 24))
1102 (clobber (reg:QI 25))])]
1103 ""
1104 "this udivmodqi4 pattern should have been splitted;"
1105 ""
1106 [(set (reg:QI 24) (match_dup 1))
1107 (set (reg:QI 22) (match_dup 2))
1082 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22))) 1108 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1083 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22))) 1109 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1084 (clobber (reg:QI 23))]) 1110 (clobber (reg:QI 23))])
1085 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24)) 1111 (set (match_dup 0) (reg:QI 24))
1086 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))] 1112 (set (match_dup 3) (reg:QI 25))]
1087 ""
1088 "") 1113 "")
1089 1114
1090 (define_insn "*udivmodqi4_call" 1115 (define_insn "*udivmodqi4_call"
1091 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22))) 1116 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1092 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22))) 1117 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1094 "" 1119 ""
1095 "%~call __udivmodqi4" 1120 "%~call __udivmodqi4"
1096 [(set_attr "type" "xcall") 1121 [(set_attr "type" "xcall")
1097 (set_attr "cc" "clobber")]) 1122 (set_attr "cc" "clobber")])
1098 1123
1099 (define_expand "divmodhi4" 1124 (define_insn_and_split "divmodhi4"
1100 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" "")) 1125 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1101 (set (reg:HI 22) (match_operand:HI 2 "register_operand" "")) 1126 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
1127 (match_operand:HI 2 "pseudo_register_operand" "")))
1128 (set (match_operand:HI 3 "pseudo_register_operand" "")
1129 (mod:HI (match_dup 1) (match_dup 2)))
1130 (clobber (reg:QI 21))
1131 (clobber (reg:HI 22))
1132 (clobber (reg:HI 24))
1133 (clobber (reg:HI 26))])]
1134 ""
1135 "this should have been splitted;"
1136 ""
1137 [(set (reg:HI 24) (match_dup 1))
1138 (set (reg:HI 22) (match_dup 2))
1102 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22))) 1139 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1103 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22))) 1140 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1104 (clobber (reg:HI 26)) 1141 (clobber (reg:HI 26))
1105 (clobber (reg:QI 21))]) 1142 (clobber (reg:QI 21))])
1106 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22)) 1143 (set (match_dup 0) (reg:HI 22))
1107 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))] 1144 (set (match_dup 3) (reg:HI 24))]
1108 "" 1145 "")
1109 "")
1110 1146
1111 (define_insn "*divmodhi4_call" 1147 (define_insn "*divmodhi4_call"
1112 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22))) 1148 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1113 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22))) 1149 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1114 (clobber (reg:HI 26)) 1150 (clobber (reg:HI 26))
1116 "" 1152 ""
1117 "%~call __divmodhi4" 1153 "%~call __divmodhi4"
1118 [(set_attr "type" "xcall") 1154 [(set_attr "type" "xcall")
1119 (set_attr "cc" "clobber")]) 1155 (set_attr "cc" "clobber")])
1120 1156
1121 (define_expand "udivmodhi4" 1157 (define_insn_and_split "udivmodhi4"
1122 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" "")) 1158 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1123 (set (reg:HI 22) (match_operand:HI 2 "register_operand" "")) 1159 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
1160 (match_operand:HI 2 "pseudo_register_operand" "")))
1161 (set (match_operand:HI 3 "pseudo_register_operand" "")
1162 (umod:HI (match_dup 1) (match_dup 2)))
1163 (clobber (reg:QI 21))
1164 (clobber (reg:HI 22))
1165 (clobber (reg:HI 24))
1166 (clobber (reg:HI 26))])]
1167 ""
1168 "this udivmodhi4 pattern should have been splitted.;"
1169 ""
1170 [(set (reg:HI 24) (match_dup 1))
1171 (set (reg:HI 22) (match_dup 2))
1124 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22))) 1172 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1125 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22))) 1173 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1126 (clobber (reg:HI 26)) 1174 (clobber (reg:HI 26))
1127 (clobber (reg:QI 21))]) 1175 (clobber (reg:QI 21))])
1128 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22)) 1176 (set (match_dup 0) (reg:HI 22))
1129 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))] 1177 (set (match_dup 3) (reg:HI 24))]
1130 ""
1131 "") 1178 "")
1132 1179
1133 (define_insn "*udivmodhi4_call" 1180 (define_insn "*udivmodhi4_call"
1134 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22))) 1181 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1135 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22))) 1182 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1138 "" 1185 ""
1139 "%~call __udivmodhi4" 1186 "%~call __udivmodhi4"
1140 [(set_attr "type" "xcall") 1187 [(set_attr "type" "xcall")
1141 (set_attr "cc" "clobber")]) 1188 (set_attr "cc" "clobber")])
1142 1189
1143 (define_expand "divmodsi4" 1190 (define_insn_and_split "divmodsi4"
1144 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" "")) 1191 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1145 (set (reg:SI 18) (match_operand:SI 2 "register_operand" "")) 1192 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
1193 (match_operand:SI 2 "pseudo_register_operand" "")))
1194 (set (match_operand:SI 3 "pseudo_register_operand" "")
1195 (mod:SI (match_dup 1) (match_dup 2)))
1196 (clobber (reg:SI 18))
1197 (clobber (reg:SI 22))
1198 (clobber (reg:HI 26))
1199 (clobber (reg:HI 30))])]
1200 ""
1201 "this divmodsi4 pattern should have been splitted;"
1202 ""
1203 [(set (reg:SI 22) (match_dup 1))
1204 (set (reg:SI 18) (match_dup 2))
1146 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18))) 1205 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1147 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18))) 1206 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1148 (clobber (reg:HI 26)) 1207 (clobber (reg:HI 26))
1149 (clobber (reg:HI 30))]) 1208 (clobber (reg:HI 30))])
1150 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18)) 1209 (set (match_dup 0) (reg:SI 18))
1151 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))] 1210 (set (match_dup 3) (reg:SI 22))]
1152 ""
1153 "") 1211 "")
1154 1212
1155 (define_insn "*divmodsi4_call" 1213 (define_insn "*divmodsi4_call"
1156 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18))) 1214 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1157 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18))) 1215 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1160 "" 1218 ""
1161 "%~call __divmodsi4" 1219 "%~call __divmodsi4"
1162 [(set_attr "type" "xcall") 1220 [(set_attr "type" "xcall")
1163 (set_attr "cc" "clobber")]) 1221 (set_attr "cc" "clobber")])
1164 1222
1165 (define_expand "udivmodsi4" 1223 (define_insn_and_split "udivmodsi4"
1166 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" "")) 1224 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1167 (set (reg:SI 18) (match_operand:SI 2 "register_operand" "")) 1225 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
1226 (match_operand:SI 2 "pseudo_register_operand" "")))
1227 (set (match_operand:SI 3 "pseudo_register_operand" "")
1228 (umod:SI (match_dup 1) (match_dup 2)))
1229 (clobber (reg:SI 18))
1230 (clobber (reg:SI 22))
1231 (clobber (reg:HI 26))
1232 (clobber (reg:HI 30))])]
1233 ""
1234 "this udivmodsi4 pattern should have been splitted;"
1235 ""
1236 [(set (reg:SI 22) (match_dup 1))
1237 (set (reg:SI 18) (match_dup 2))
1168 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18))) 1238 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1169 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18))) 1239 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1170 (clobber (reg:HI 26)) 1240 (clobber (reg:HI 26))
1171 (clobber (reg:HI 30))]) 1241 (clobber (reg:HI 30))])
1172 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18)) 1242 (set (match_dup 0) (reg:SI 18))
1173 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))] 1243 (set (match_dup 3) (reg:SI 22))]
1174 ""
1175 "") 1244 "")
1176 1245
1177 (define_insn "*udivmodsi4_call" 1246 (define_insn "*udivmodsi4_call"
1178 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18))) 1247 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1179 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18))) 1248 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1202 [(set (match_operand:HI 0 "register_operand" "=r,d,r") 1271 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1203 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0") 1272 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1204 (match_operand:HI 2 "nonmemory_operand" "r,i,M"))) 1273 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1205 (clobber (match_scratch:QI 3 "=X,X,&d"))] 1274 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1206 "" 1275 ""
1207 "*{ 1276 {
1208 if (which_alternative==0) 1277 if (which_alternative==0)
1209 return (AS2 (and,%A0,%A2) CR_TAB 1278 return ("and %A0,%A2" CR_TAB
1210 AS2 (and,%B0,%B2)); 1279 "and %B0,%B2");
1211 else if (which_alternative==1) 1280 else if (which_alternative==1)
1212 { 1281 {
1213 if (GET_CODE (operands[2]) == CONST_INT) 1282 if (GET_CODE (operands[2]) == CONST_INT)
1214 { 1283 {
1215 int mask = INTVAL (operands[2]); 1284 int mask = INTVAL (operands[2]);
1216 if ((mask & 0xff) != 0xff) 1285 if ((mask & 0xff) != 0xff)
1217 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands); 1286 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1218 if ((mask & 0xff00) != 0xff00) 1287 if ((mask & 0xff00) != 0xff00)
1219 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands); 1288 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1220 return \"\"; 1289 return "";
1221 } 1290 }
1222 return (AS2 (andi,%A0,lo8(%2)) CR_TAB 1291 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1223 AS2 (andi,%B0,hi8(%2))); 1292 AS2 (andi,%B0,hi8(%2)));
1224 } 1293 }
1225 return (AS2 (ldi,%3,lo8(%2)) CR_TAB 1294 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1226 AS2 (and,%A0,%3) CR_TAB 1295 "and %A0,%3" CR_TAB
1227 AS1 (clr,%B0)); 1296 AS1 (clr,%B0));
1228 }" 1297 }
1229 [(set_attr "length" "2,2,3") 1298 [(set_attr "length" "2,2,3")
1230 (set_attr "cc" "set_n,clobber,set_n")]) 1299 (set_attr "cc" "set_n,clobber,set_n")])
1231 1300
1232 (define_insn "andsi3" 1301 (define_insn "andsi3"
1233 [(set (match_operand:SI 0 "register_operand" "=r,d") 1302 [(set (match_operand:SI 0 "register_operand" "=r,d")
1234 (and:SI (match_operand:SI 1 "register_operand" "%0,0") 1303 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1235 (match_operand:SI 2 "nonmemory_operand" "r,i")))] 1304 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1236 "" 1305 ""
1237 "*{ 1306 {
1238 if (which_alternative==0) 1307 if (which_alternative==0)
1239 return (AS2 (and, %0,%2) CR_TAB 1308 return ("and %0,%2" CR_TAB
1240 AS2 (and, %B0,%B2) CR_TAB 1309 "and %B0,%B2" CR_TAB
1241 AS2 (and, %C0,%C2) CR_TAB 1310 "and %C0,%C2" CR_TAB
1242 AS2 (and, %D0,%D2)); 1311 "and %D0,%D2");
1243 else if (which_alternative==1) 1312 else if (which_alternative==1)
1244 { 1313 {
1245 if (GET_CODE (operands[2]) == CONST_INT) 1314 if (GET_CODE (operands[2]) == CONST_INT)
1246 { 1315 {
1247 HOST_WIDE_INT mask = INTVAL (operands[2]); 1316 HOST_WIDE_INT mask = INTVAL (operands[2]);
1251 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands); 1320 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1252 if ((mask & 0xff0000L) != 0xff0000L) 1321 if ((mask & 0xff0000L) != 0xff0000L)
1253 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands); 1322 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1254 if ((mask & 0xff000000L) != 0xff000000L) 1323 if ((mask & 0xff000000L) != 0xff000000L)
1255 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands); 1324 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1256 return \"\"; 1325 return "";
1257 } 1326 }
1258 return (AS2 (andi, %A0,lo8(%2)) CR_TAB 1327 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1259 AS2 (andi, %B0,hi8(%2)) CR_TAB 1328 AS2 (andi, %B0,hi8(%2)) CR_TAB
1260 AS2 (andi, %C0,hlo8(%2)) CR_TAB 1329 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1261 AS2 (andi, %D0,hhi8(%2))); 1330 AS2 (andi, %D0,hhi8(%2)));
1262 } 1331 }
1263 return \"bug\"; 1332 return "bug";
1264 }" 1333 }
1265 [(set_attr "length" "4,4") 1334 [(set_attr "length" "4,4")
1266 (set_attr "cc" "set_n,clobber")]) 1335 (set_attr "cc" "set_n,clobber")])
1267 1336
1268 (define_peephole2 ; andi 1337 (define_peephole2 ; andi
1269 [(set (match_operand:QI 0 "d_register_operand" "") 1338 [(set (match_operand:QI 0 "d_register_operand" "")
1295 (define_insn "iorhi3" 1364 (define_insn "iorhi3"
1296 [(set (match_operand:HI 0 "register_operand" "=r,d") 1365 [(set (match_operand:HI 0 "register_operand" "=r,d")
1297 (ior:HI (match_operand:HI 1 "register_operand" "%0,0") 1366 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1298 (match_operand:HI 2 "nonmemory_operand" "r,i")))] 1367 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1299 "" 1368 ""
1300 "*{ 1369 {
1301 if (which_alternative==0) 1370 if (which_alternative==0)
1302 return (AS2 (or,%A0,%A2) CR_TAB 1371 return ("or %A0,%A2" CR_TAB
1303 AS2 (or,%B0,%B2)); 1372 "or %B0,%B2");
1304 if (GET_CODE (operands[2]) == CONST_INT) 1373 if (GET_CODE (operands[2]) == CONST_INT)
1305 { 1374 {
1306 int mask = INTVAL (operands[2]); 1375 int mask = INTVAL (operands[2]);
1307 if (mask & 0xff) 1376 if (mask & 0xff)
1308 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands); 1377 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1309 if (mask & 0xff00) 1378 if (mask & 0xff00)
1310 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands); 1379 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1311 return \"\"; 1380 return "";
1312 } 1381 }
1313 return (AS2 (ori,%0,lo8(%2)) CR_TAB 1382 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1314 AS2 (ori,%B0,hi8(%2))); 1383 AS2 (ori,%B0,hi8(%2)));
1315 }" 1384 }
1316 [(set_attr "length" "2,2") 1385 [(set_attr "length" "2,2")
1317 (set_attr "cc" "set_n,clobber")]) 1386 (set_attr "cc" "set_n,clobber")])
1318 1387
1319 (define_insn "*iorhi3_clobber" 1388 (define_insn "*iorhi3_clobber"
1320 [(set (match_operand:HI 0 "register_operand" "=r,r") 1389 [(set (match_operand:HI 0 "register_operand" "=r,r")
1331 (define_insn "iorsi3" 1400 (define_insn "iorsi3"
1332 [(set (match_operand:SI 0 "register_operand" "=r,d") 1401 [(set (match_operand:SI 0 "register_operand" "=r,d")
1333 (ior:SI (match_operand:SI 1 "register_operand" "%0,0") 1402 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1334 (match_operand:SI 2 "nonmemory_operand" "r,i")))] 1403 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1335 "" 1404 ""
1336 "*{ 1405 {
1337 if (which_alternative==0) 1406 if (which_alternative==0)
1338 return (AS2 (or, %0,%2) CR_TAB 1407 return ("or %0,%2" CR_TAB
1339 AS2 (or, %B0,%B2) CR_TAB 1408 "or %B0,%B2" CR_TAB
1340 AS2 (or, %C0,%C2) CR_TAB 1409 "or %C0,%C2" CR_TAB
1341 AS2 (or, %D0,%D2)); 1410 "or %D0,%D2");
1342 if (GET_CODE (operands[2]) == CONST_INT) 1411 if (GET_CODE (operands[2]) == CONST_INT)
1343 { 1412 {
1344 HOST_WIDE_INT mask = INTVAL (operands[2]); 1413 HOST_WIDE_INT mask = INTVAL (operands[2]);
1345 if (mask & 0xff) 1414 if (mask & 0xff)
1346 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands); 1415 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1348 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands); 1417 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1349 if (mask & 0xff0000L) 1418 if (mask & 0xff0000L)
1350 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands); 1419 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1351 if (mask & 0xff000000L) 1420 if (mask & 0xff000000L)
1352 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands); 1421 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1353 return \"\"; 1422 return "";
1354 } 1423 }
1355 return (AS2 (ori, %A0,lo8(%2)) CR_TAB 1424 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1356 AS2 (ori, %B0,hi8(%2)) CR_TAB 1425 AS2 (ori, %B0,hi8(%2)) CR_TAB
1357 AS2 (ori, %C0,hlo8(%2)) CR_TAB 1426 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1358 AS2 (ori, %D0,hhi8(%2))); 1427 AS2 (ori, %D0,hhi8(%2)));
1359 }" 1428 }
1360 [(set_attr "length" "4,4") 1429 [(set_attr "length" "4,4")
1361 (set_attr "cc" "set_n,clobber")]) 1430 (set_attr "cc" "set_n,clobber")])
1362 1431
1363 (define_insn "*iorsi3_clobber" 1432 (define_insn "*iorsi3_clobber"
1364 [(set (match_operand:SI 0 "register_operand" "=r,r") 1433 [(set (match_operand:SI 0 "register_operand" "=r,r")
2200 ") 2269 ")
2201 2270
2202 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> 2271 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2203 ;; compare 2272 ;; compare
2204 2273
2205 (define_insn "tstqi" 2274 ; Optimize negated tests into reverse compare if overflow is undefined.
2275 (define_insn "*negated_tstqi"
2206 [(set (cc0) 2276 [(set (cc0)
2207 (match_operand:QI 0 "register_operand" "r"))] 2277 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
2208 "" 2278 (const_int 0)))]
2209 "tst %0" 2279 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2210 [(set_attr "cc" "compare")
2211 (set_attr "length" "1")])
2212
2213 (define_insn "*reversed_tstqi"
2214 [(set (cc0)
2215 (compare (const_int 0)
2216 (match_operand:QI 0 "register_operand" "r")))]
2217 ""
2218 "cp __zero_reg__,%0" 2280 "cp __zero_reg__,%0"
2219 [(set_attr "cc" "compare") 2281 [(set_attr "cc" "compare")
2220 (set_attr "length" "1")]) 2282 (set_attr "length" "1")])
2221 2283
2222 (define_insn "tsthi" 2284 (define_insn "*reversed_tstqi"
2223 [(set (cc0)
2224 (match_operand:HI 0 "register_operand" "!w,r"))]
2225 ""
2226 "* return out_tsthi (insn,NULL);"
2227 [(set_attr "cc" "compare,compare")
2228 (set_attr "length" "1,2")])
2229
2230 (define_insn "*reversed_tsthi"
2231 [(set (cc0) 2285 [(set (cc0)
2232 (compare (const_int 0) 2286 (compare (const_int 0)
2233 (match_operand:HI 0 "register_operand" "r")))] 2287 (match_operand:QI 0 "register_operand" "r")))]
2234 "" 2288 ""
2289 "cp __zero_reg__,%0"
2290 [(set_attr "cc" "compare")
2291 (set_attr "length" "2")])
2292
2293 (define_insn "*negated_tsthi"
2294 [(set (cc0)
2295 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
2296 (const_int 0)))]
2297 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2235 "cp __zero_reg__,%A0 2298 "cp __zero_reg__,%A0
2236 cpc __zero_reg__,%B0" 2299 cpc __zero_reg__,%B0"
2237 [(set_attr "cc" "compare") 2300 [(set_attr "cc" "compare")
2238 (set_attr "length" "2")]) 2301 (set_attr "length" "2")])
2239 2302
2240 (define_insn "tstsi" 2303 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
2304 ;; though it is unused, because this pattern is synthesized by avr_reorg.
2305 (define_insn "*reversed_tsthi"
2241 [(set (cc0) 2306 [(set (cc0)
2242 (match_operand:SI 0 "register_operand" "r"))] 2307 (compare (const_int 0)
2243 "" 2308 (match_operand:HI 0 "register_operand" "r")))
2244 "* return out_tstsi (insn,NULL);" 2309 (clobber (match_scratch:QI 1 "=X"))]
2245 [(set_attr "cc" "compare") 2310 ""
2246 (set_attr "length" "4")]) 2311 "cp __zero_reg__,%A0
2247 2312 cpc __zero_reg__,%B0"
2248 (define_insn "*reversed_tstsi" 2313 [(set_attr "cc" "compare")
2314 (set_attr "length" "2")])
2315
2316 (define_insn "*negated_tstsi"
2249 [(set (cc0) 2317 [(set (cc0)
2250 (compare (const_int 0) 2318 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
2251 (match_operand:SI 0 "register_operand" "r")))] 2319 (const_int 0)))]
2252 "" 2320 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2253 "cp __zero_reg__,%A0 2321 "cp __zero_reg__,%A0
2254 cpc __zero_reg__,%B0 2322 cpc __zero_reg__,%B0
2255 cpc __zero_reg__,%C0 2323 cpc __zero_reg__,%C0
2256 cpc __zero_reg__,%D0" 2324 cpc __zero_reg__,%D0"
2257 [(set_attr "cc" "compare") 2325 [(set_attr "cc" "compare")
2258 (set_attr "length" "4")]) 2326 (set_attr "length" "4")])
2259 2327
2260 2328 (define_insn "*reversed_tstsi"
2261 (define_insn "cmpqi"
2262 [(set (cc0) 2329 [(set (cc0)
2263 (compare (match_operand:QI 0 "register_operand" "r,d") 2330 (compare (const_int 0)
2264 (match_operand:QI 1 "nonmemory_operand" "r,i")))] 2331 (match_operand:SI 0 "register_operand" "r")))
2332 (clobber (match_scratch:QI 1 "=X"))]
2333 ""
2334 "cp __zero_reg__,%A0
2335 cpc __zero_reg__,%B0
2336 cpc __zero_reg__,%C0
2337 cpc __zero_reg__,%D0"
2338 [(set_attr "cc" "compare")
2339 (set_attr "length" "4")])
2340
2341
2342 (define_insn "*cmpqi"
2343 [(set (cc0)
2344 (compare (match_operand:QI 0 "register_operand" "r,r,d")
2345 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
2265 "" 2346 ""
2266 "@ 2347 "@
2348 tst %0
2267 cp %0,%1 2349 cp %0,%1
2268 cpi %0,lo8(%1)" 2350 cpi %0,lo8(%1)"
2269 [(set_attr "cc" "compare,compare") 2351 [(set_attr "cc" "compare,compare,compare")
2270 (set_attr "length" "1,1")]) 2352 (set_attr "length" "1,1,1")])
2271 2353
2272 (define_insn "*cmpqi_sign_extend" 2354 (define_insn "*cmpqi_sign_extend"
2273 [(set (cc0) 2355 [(set (cc0)
2274 (compare (sign_extend:HI 2356 (compare (sign_extend:HI
2275 (match_operand:QI 0 "register_operand" "d")) 2357 (match_operand:QI 0 "register_operand" "d"))
2277 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127" 2359 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2278 "cpi %0,lo8(%1)" 2360 "cpi %0,lo8(%1)"
2279 [(set_attr "cc" "compare") 2361 [(set_attr "cc" "compare")
2280 (set_attr "length" "1")]) 2362 (set_attr "length" "1")])
2281 2363
2282 (define_insn "cmphi" 2364 (define_insn "*cmphi"
2283 [(set (cc0) 2365 [(set (cc0)
2284 (compare (match_operand:HI 0 "register_operand" "r,d,d,r,r") 2366 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r")
2285 (match_operand:HI 1 "nonmemory_operand" "r,M,i,M,i"))) 2367 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i")))
2286 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))] 2368 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))]
2287 "" 2369 ""
2288 "*{ 2370 "*{
2289 switch (which_alternative) 2371 switch (which_alternative)
2290 { 2372 {
2291 case 0: 2373 case 0: case 1:
2374 return out_tsthi (insn, operands[0], NULL);
2375
2376 case 2:
2292 return (AS2 (cp,%A0,%A1) CR_TAB 2377 return (AS2 (cp,%A0,%A1) CR_TAB
2293 AS2 (cpc,%B0,%B1)); 2378 AS2 (cpc,%B0,%B1));
2294 case 1: 2379 case 3:
2295 if (reg_unused_after (insn, operands[0]) 2380 if (reg_unused_after (insn, operands[0])
2296 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 2381 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2297 && test_hard_reg_class (ADDW_REGS, operands[0])) 2382 && test_hard_reg_class (ADDW_REGS, operands[0]))
2298 return AS2 (sbiw,%0,%1); 2383 return AS2 (sbiw,%0,%1);
2299 else 2384 else
2300 return (AS2 (cpi,%0,%1) CR_TAB 2385 return (AS2 (cpi,%0,%1) CR_TAB
2301 AS2 (cpc,%B0,__zero_reg__)); 2386 AS2 (cpc,%B0,__zero_reg__));
2302 case 2: 2387 case 4:
2303 if (reg_unused_after (insn, operands[0])) 2388 if (reg_unused_after (insn, operands[0]))
2304 return (AS2 (subi,%0,lo8(%1)) CR_TAB 2389 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2305 AS2 (sbci,%B0,hi8(%1))); 2390 AS2 (sbci,%B0,hi8(%1)));
2306 else 2391 else
2307 return (AS2 (ldi, %2,hi8(%1)) CR_TAB 2392 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2308 AS2 (cpi, %A0,lo8(%1)) CR_TAB 2393 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2309 AS2 (cpc, %B0,%2)); 2394 AS2 (cpc, %B0,%2));
2310 case 3: 2395 case 5:
2311 return (AS2 (ldi, %2,lo8(%1)) CR_TAB 2396 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2312 AS2 (cp, %A0,%2) CR_TAB 2397 AS2 (cp, %A0,%2) CR_TAB
2313 AS2 (cpc, %B0,__zero_reg__)); 2398 AS2 (cpc, %B0,__zero_reg__));
2314 2399
2315 case 4: 2400 case 6:
2316 return (AS2 (ldi, %2,lo8(%1)) CR_TAB 2401 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2317 AS2 (cp, %A0,%2) CR_TAB 2402 AS2 (cp, %A0,%2) CR_TAB
2318 AS2 (ldi, %2,hi8(%1)) CR_TAB 2403 AS2 (ldi, %2,hi8(%1)) CR_TAB
2319 AS2 (cpc, %B0,%2)); 2404 AS2 (cpc, %B0,%2));
2320 } 2405 }
2321 return \"bug\"; 2406 return \"bug\";
2322 }" 2407 }"
2323 [(set_attr "cc" "compare,compare,compare,compare,compare") 2408 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare")
2324 (set_attr "length" "2,2,3,3,4")]) 2409 (set_attr "length" "1,2,2,2,3,3,4")])
2325 2410
2326 2411
2327 (define_insn "cmpsi" 2412 (define_insn "*cmpsi"
2328 [(set (cc0) 2413 [(set (cc0)
2329 (compare (match_operand:SI 0 "register_operand" "r,d,d,r,r") 2414 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r")
2330 (match_operand:SI 1 "nonmemory_operand" "r,M,i,M,i"))) 2415 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i")))
2331 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))] 2416 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))]
2332 "" 2417 ""
2333 "*{ 2418 "*{
2334 switch (which_alternative) 2419 switch (which_alternative)
2335 { 2420 {
2336 case 0: 2421 case 0:
2422 return out_tstsi (insn, operands[0], NULL);
2423
2424 case 1:
2337 return (AS2 (cp,%A0,%A1) CR_TAB 2425 return (AS2 (cp,%A0,%A1) CR_TAB
2338 AS2 (cpc,%B0,%B1) CR_TAB 2426 AS2 (cpc,%B0,%B1) CR_TAB
2339 AS2 (cpc,%C0,%C1) CR_TAB 2427 AS2 (cpc,%C0,%C1) CR_TAB
2340 AS2 (cpc,%D0,%D1)); 2428 AS2 (cpc,%D0,%D1));
2341 case 1: 2429 case 2:
2342 if (reg_unused_after (insn, operands[0]) 2430 if (reg_unused_after (insn, operands[0])
2343 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 2431 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2344 && test_hard_reg_class (ADDW_REGS, operands[0])) 2432 && test_hard_reg_class (ADDW_REGS, operands[0]))
2345 return (AS2 (sbiw,%0,%1) CR_TAB 2433 return (AS2 (sbiw,%0,%1) CR_TAB
2346 AS2 (cpc,%C0,__zero_reg__) CR_TAB 2434 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2348 else 2436 else
2349 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB 2437 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2350 AS2 (cpc,%B0,__zero_reg__) CR_TAB 2438 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2351 AS2 (cpc,%C0,__zero_reg__) CR_TAB 2439 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2352 AS2 (cpc,%D0,__zero_reg__)); 2440 AS2 (cpc,%D0,__zero_reg__));
2353 case 2: 2441 case 3:
2354 if (reg_unused_after (insn, operands[0])) 2442 if (reg_unused_after (insn, operands[0]))
2355 return (AS2 (subi,%A0,lo8(%1)) CR_TAB 2443 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2356 AS2 (sbci,%B0,hi8(%1)) CR_TAB 2444 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2357 AS2 (sbci,%C0,hlo8(%1)) CR_TAB 2445 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2358 AS2 (sbci,%D0,hhi8(%1))); 2446 AS2 (sbci,%D0,hhi8(%1)));
2362 AS2 (cpc, %B0,%2) CR_TAB 2450 AS2 (cpc, %B0,%2) CR_TAB
2363 AS2 (ldi, %2,hlo8(%1)) CR_TAB 2451 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2364 AS2 (cpc, %C0,%2) CR_TAB 2452 AS2 (cpc, %C0,%2) CR_TAB
2365 AS2 (ldi, %2,hhi8(%1)) CR_TAB 2453 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2366 AS2 (cpc, %D0,%2)); 2454 AS2 (cpc, %D0,%2));
2367 case 3: 2455 case 4:
2368 return (AS2 (ldi,%2,lo8(%1)) CR_TAB 2456 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2369 AS2 (cp,%A0,%2) CR_TAB 2457 AS2 (cp,%A0,%2) CR_TAB
2370 AS2 (cpc,%B0,__zero_reg__) CR_TAB 2458 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2371 AS2 (cpc,%C0,__zero_reg__) CR_TAB 2459 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2372 AS2 (cpc,%D0,__zero_reg__)); 2460 AS2 (cpc,%D0,__zero_reg__));
2373 case 4: 2461 case 5:
2374 return (AS2 (ldi, %2,lo8(%1)) CR_TAB 2462 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2375 AS2 (cp, %A0,%2) CR_TAB 2463 AS2 (cp, %A0,%2) CR_TAB
2376 AS2 (ldi, %2,hi8(%1)) CR_TAB 2464 AS2 (ldi, %2,hi8(%1)) CR_TAB
2377 AS2 (cpc, %B0,%2) CR_TAB 2465 AS2 (cpc, %B0,%2) CR_TAB
2378 AS2 (ldi, %2,hlo8(%1)) CR_TAB 2466 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2380 AS2 (ldi, %2,hhi8(%1)) CR_TAB 2468 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2381 AS2 (cpc, %D0,%2)); 2469 AS2 (cpc, %D0,%2));
2382 } 2470 }
2383 return \"bug\"; 2471 return \"bug\";
2384 }" 2472 }"
2385 [(set_attr "cc" "compare,compare,compare,compare,compare") 2473 [(set_attr "cc" "compare,compare,compare,compare,compare,compare")
2386 (set_attr "length" "4,4,7,5,8")]) 2474 (set_attr "length" "4,4,4,7,5,8")])
2387 2475
2388 ; Optimize negated tests into reverse compare if overflow is undefined.
2389 (define_insn_and_split "negated_tst<mode>"
2390 [(set (cc0)
2391 (neg:QISI (match_operand:QISI 0 "register_operand")))]
2392
2393 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2394 "#"
2395 ""
2396 [(set (cc0)
2397 (compare (const_int 0)
2398 (match_dup 0)))]
2399 "")
2400 2476
2401 ;; ---------------------------------------------------------------------- 2477 ;; ----------------------------------------------------------------------
2402 ;; JUMP INSTRUCTIONS 2478 ;; JUMP INSTRUCTIONS
2403 ;; ---------------------------------------------------------------------- 2479 ;; ----------------------------------------------------------------------
2404 ;; Conditional jump instructions 2480 ;; Conditional jump instructions
2405 2481
2406 (define_expand "beq" 2482 (define_expand "cbranchsi4"
2407 [(set (pc) 2483 [(parallel [(set (cc0)
2408 (if_then_else (eq (cc0) (const_int 0)) 2484 (compare (match_operand:SI 1 "register_operand" "")
2409 (label_ref (match_operand 0 "" "")) 2485 (match_operand:SI 2 "nonmemory_operand" "")))
2410 (pc)))] 2486 (clobber (match_scratch:QI 4 ""))])
2411 "" 2487 (set (pc)
2412 "") 2488 (if_then_else
2413 2489 (match_operator 0 "ordered_comparison_operator" [(cc0)
2414 (define_expand "bne" 2490 (const_int 0)])
2415 [(set (pc) 2491 (label_ref (match_operand 3 "" ""))
2416 (if_then_else (ne (cc0) (const_int 0)) 2492 (pc)))]
2417 (label_ref (match_operand 0 "" "")) 2493 "")
2418 (pc)))] 2494
2419 "" 2495 (define_expand "cbranchhi4"
2420 "") 2496 [(parallel [(set (cc0)
2421 2497 (compare (match_operand:HI 1 "register_operand" "")
2422 (define_expand "bge" 2498 (match_operand:HI 2 "nonmemory_operand" "")))
2423 [(set (pc) 2499 (clobber (match_scratch:QI 4 ""))])
2424 (if_then_else (ge (cc0) (const_int 0)) 2500 (set (pc)
2425 (label_ref (match_operand 0 "" "")) 2501 (if_then_else
2426 (pc)))] 2502 (match_operator 0 "ordered_comparison_operator" [(cc0)
2427 "" 2503 (const_int 0)])
2428 "") 2504 (label_ref (match_operand 3 "" ""))
2429 2505 (pc)))]
2430 (define_expand "bgeu" 2506 "")
2431 [(set (pc) 2507
2432 (if_then_else (geu (cc0) (const_int 0)) 2508 (define_expand "cbranchqi4"
2433 (label_ref (match_operand 0 "" "")) 2509 [(set (cc0)
2434 (pc)))] 2510 (compare (match_operand:QI 1 "register_operand" "")
2435 "" 2511 (match_operand:QI 2 "nonmemory_operand" "")))
2436 "") 2512 (set (pc)
2437 2513 (if_then_else
2438 (define_expand "blt" 2514 (match_operator 0 "ordered_comparison_operator" [(cc0)
2439 [(set (pc) 2515 (const_int 0)])
2440 (if_then_else (lt (cc0) (const_int 0)) 2516 (label_ref (match_operand 3 "" ""))
2441 (label_ref (match_operand 0 "" "")) 2517 (pc)))]
2442 (pc)))] 2518 "")
2443 "" 2519
2444 "")
2445
2446 (define_expand "bltu"
2447 [(set (pc)
2448 (if_then_else (ltu (cc0) (const_int 0))
2449 (label_ref (match_operand 0 "" ""))
2450 (pc)))]
2451 ""
2452 "")
2453
2454
2455
2456 /****************************************************************
2457 AVR not have following conditional jumps: LE,LEU,GT,GTU.
2458 Convert them all to proper jumps.
2459 *****************************************************************/
2460
2461 (define_expand "ble"
2462 [(set (pc)
2463 (if_then_else (le (cc0) (const_int 0))
2464 (label_ref (match_operand 0 "" ""))
2465 (pc)))]
2466 ""
2467 "")
2468
2469 (define_expand "bleu"
2470 [(set (pc)
2471 (if_then_else (leu (cc0) (const_int 0))
2472 (label_ref (match_operand 0 "" ""))
2473 (pc)))]
2474 ""
2475 "")
2476
2477 (define_expand "bgt"
2478 [(set (pc)
2479 (if_then_else (gt (cc0) (const_int 0))
2480 (label_ref (match_operand 0 "" ""))
2481 (pc)))]
2482 ""
2483 "")
2484
2485 (define_expand "bgtu"
2486 [(set (pc)
2487 (if_then_else (gtu (cc0) (const_int 0))
2488 (label_ref (match_operand 0 "" ""))
2489 (pc)))]
2490 ""
2491 "")
2492 2520
2493 ;; Test a single bit in a QI/HI/SImode register. 2521 ;; Test a single bit in a QI/HI/SImode register.
2494 (define_insn "*sbrx_branch" 2522 ;; Combine will create zero extract patterns for single bit tests.
2523 ;; permit any mode in source pattern by using VOIDmode.
2524
2525 (define_insn "*sbrx_branch<mode>"
2495 [(set (pc) 2526 [(set (pc)
2496 (if_then_else 2527 (if_then_else
2497 (match_operator 0 "eqne_operator" 2528 (match_operator 0 "eqne_operator"
2498 [(zero_extract:HI 2529 [(zero_extract:QIDI
2499 (match_operand:QI 1 "register_operand" "r") 2530 (match_operand:VOID 1 "register_operand" "r")
2500 (const_int 1) 2531 (const_int 1)
2501 (match_operand 2 "const_int_operand" "n")) 2532 (match_operand 2 "const_int_operand" "n"))
2502 (const_int 0)]) 2533 (const_int 0)])
2503 (label_ref (match_operand 3 "" "")) 2534 (label_ref (match_operand 3 "" ""))
2504 (pc)))] 2535 (pc)))]
2511 (if_then_else (eq_attr "mcu_mega" "no") 2542 (if_then_else (eq_attr "mcu_mega" "no")
2512 (const_int 2) 2543 (const_int 2)
2513 (const_int 4)))) 2544 (const_int 4))))
2514 (set_attr "cc" "clobber")]) 2545 (set_attr "cc" "clobber")])
2515 2546
2516 (define_insn "*sbrx_and_branchhi" 2547 ;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns.
2548 ;; or for old peepholes.
2549 ;; Fixme - bitwise Mask will not work for DImode
2550
2551 (define_insn "*sbrx_and_branch<mode>"
2517 [(set (pc) 2552 [(set (pc)
2518 (if_then_else 2553 (if_then_else
2519 (match_operator 0 "eqne_operator" 2554 (match_operator 0 "eqne_operator"
2520 [(and:HI 2555 [(and:QISI
2521 (match_operand:HI 1 "register_operand" "r") 2556 (match_operand:QISI 1 "register_operand" "r")
2522 (match_operand:HI 2 "single_one_operand" "n")) 2557 (match_operand:QISI 2 "single_one_operand" "n"))
2523 (const_int 0)]) 2558 (const_int 0)])
2524 (label_ref (match_operand 3 "" "")) 2559 (label_ref (match_operand 3 "" ""))
2525 (pc)))] 2560 (pc)))]
2526 "" 2561 ""
2527 "* return avr_out_sbxx_branch (insn, operands);" 2562 {
2563 HOST_WIDE_INT bitnumber;
2564 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
2565 operands[2] = GEN_INT (bitnumber);
2566 return avr_out_sbxx_branch (insn, operands);
2567 }
2528 [(set (attr "length") 2568 [(set (attr "length")
2529 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) 2569 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2530 (le (minus (pc) (match_dup 3)) (const_int 2046))) 2570 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2531 (const_int 2) 2571 (const_int 2)
2532 (if_then_else (eq_attr "mcu_mega" "no") 2572 (if_then_else (eq_attr "mcu_mega" "no")
2533 (const_int 2) 2573 (const_int 2)
2534 (const_int 4)))) 2574 (const_int 4))))
2535 (set_attr "cc" "clobber")]) 2575 (set_attr "cc" "clobber")])
2536 2576
2537 (define_insn "*sbrx_and_branchsi"
2538 [(set (pc)
2539 (if_then_else
2540 (match_operator 0 "eqne_operator"
2541 [(and:SI
2542 (match_operand:SI 1 "register_operand" "r")
2543 (match_operand:SI 2 "single_one_operand" "n"))
2544 (const_int 0)])
2545 (label_ref (match_operand 3 "" ""))
2546 (pc)))]
2547 ""
2548 "* return avr_out_sbxx_branch (insn, operands);"
2549 [(set (attr "length")
2550 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2551 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2552 (const_int 2)
2553 (if_then_else (eq_attr "mcu_mega" "no")
2554 (const_int 2)
2555 (const_int 4))))
2556 (set_attr "cc" "clobber")])
2557
2558 ;; Convert sign tests to bit 7/15/31 tests that match the above insns. 2577 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2559 (define_peephole2 2578 (define_peephole2
2560 [(set (cc0) (match_operand:QI 0 "register_operand" "")) 2579 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2580 (const_int 0)))
2561 (set (pc) (if_then_else (ge (cc0) (const_int 0)) 2581 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2562 (label_ref (match_operand 1 "" "")) 2582 (label_ref (match_operand 1 "" ""))
2563 (pc)))] 2583 (pc)))]
2564 "" 2584 ""
2565 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) 2585 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2569 (label_ref (match_dup 1)) 2589 (label_ref (match_dup 1))
2570 (pc)))] 2590 (pc)))]
2571 "") 2591 "")
2572 2592
2573 (define_peephole2 2593 (define_peephole2
2574 [(set (cc0) (match_operand:QI 0 "register_operand" "")) 2594 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2595 (const_int 0)))
2575 (set (pc) (if_then_else (lt (cc0) (const_int 0)) 2596 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2576 (label_ref (match_operand 1 "" "")) 2597 (label_ref (match_operand 1 "" ""))
2577 (pc)))] 2598 (pc)))]
2578 "" 2599 ""
2579 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) 2600 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2583 (label_ref (match_dup 1)) 2604 (label_ref (match_dup 1))
2584 (pc)))] 2605 (pc)))]
2585 "") 2606 "")
2586 2607
2587 (define_peephole2 2608 (define_peephole2
2588 [(set (cc0) (match_operand:HI 0 "register_operand" "")) 2609 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2610 (const_int 0)))
2611 (clobber (match_operand:HI 2 ""))])
2589 (set (pc) (if_then_else (ge (cc0) (const_int 0)) 2612 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2590 (label_ref (match_operand 1 "" "")) 2613 (label_ref (match_operand 1 "" ""))
2591 (pc)))] 2614 (pc)))]
2592 "" 2615 ""
2593 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) 2616 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2595 (label_ref (match_dup 1)) 2618 (label_ref (match_dup 1))
2596 (pc)))] 2619 (pc)))]
2597 "") 2620 "")
2598 2621
2599 (define_peephole2 2622 (define_peephole2
2600 [(set (cc0) (match_operand:HI 0 "register_operand" "")) 2623 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2624 (const_int 0)))
2625 (clobber (match_operand:HI 2 ""))])
2601 (set (pc) (if_then_else (lt (cc0) (const_int 0)) 2626 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2602 (label_ref (match_operand 1 "" "")) 2627 (label_ref (match_operand 1 "" ""))
2603 (pc)))] 2628 (pc)))]
2604 "" 2629 ""
2605 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) 2630 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2607 (label_ref (match_dup 1)) 2632 (label_ref (match_dup 1))
2608 (pc)))] 2633 (pc)))]
2609 "") 2634 "")
2610 2635
2611 (define_peephole2 2636 (define_peephole2
2612 [(set (cc0) (match_operand:SI 0 "register_operand" "")) 2637 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2638 (const_int 0)))
2639 (clobber (match_operand:SI 2 ""))])
2613 (set (pc) (if_then_else (ge (cc0) (const_int 0)) 2640 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2614 (label_ref (match_operand 1 "" "")) 2641 (label_ref (match_operand 1 "" ""))
2615 (pc)))] 2642 (pc)))]
2616 "" 2643 ""
2617 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) 2644 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2619 (label_ref (match_dup 1)) 2646 (label_ref (match_dup 1))
2620 (pc)))] 2647 (pc)))]
2621 "operands[2] = GEN_INT (-2147483647 - 1);") 2648 "operands[2] = GEN_INT (-2147483647 - 1);")
2622 2649
2623 (define_peephole2 2650 (define_peephole2
2624 [(set (cc0) (match_operand:SI 0 "register_operand" "")) 2651 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2652 (const_int 0)))
2653 (clobber (match_operand:SI 2 ""))])
2625 (set (pc) (if_then_else (lt (cc0) (const_int 0)) 2654 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2626 (label_ref (match_operand 1 "" "")) 2655 (label_ref (match_operand 1 "" ""))
2627 (pc)))] 2656 (pc)))]
2628 "" 2657 ""
2629 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) 2658 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2648 "* 2677 "*
2649 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);" 2678 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2650 [(set_attr "type" "branch") 2679 [(set_attr "type" "branch")
2651 (set_attr "cc" "clobber")]) 2680 (set_attr "cc" "clobber")])
2652 2681
2682 ;; ****************************************************************
2683 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
2684 ;; Convert them all to proper jumps.
2685 ;; ****************************************************************/
2686
2653 (define_insn "difficult_branch" 2687 (define_insn "difficult_branch"
2654 [(set (pc) 2688 [(set (pc)
2655 (if_then_else (match_operator 1 "difficult_comparison_operator" 2689 (if_then_else (match_operator 1 "difficult_comparison_operator"
2656 [(cc0) 2690 [(cc0)
2657 (const_int 0)]) 2691 (const_int 0)])
2698 [(set (pc) 2732 [(set (pc)
2699 (label_ref (match_operand 0 "" "")))] 2733 (label_ref (match_operand 0 "" "")))]
2700 "" 2734 ""
2701 "*{ 2735 "*{
2702 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1) 2736 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2703 return AS1 (jmp,%0); 2737 return AS1 (jmp,%x0);
2704 return AS1 (rjmp,%0); 2738 return AS1 (rjmp,%x0);
2705 }" 2739 }"
2706 [(set (attr "length") 2740 [(set (attr "length")
2707 (if_then_else (match_operand 0 "symbol_ref_operand" "") 2741 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2708 (if_then_else (eq_attr "mcu_mega" "no") 2742 (if_then_else (eq_attr "mcu_mega" "no")
2709 (const_int 1) 2743 (const_int 1)
2751 return (AS2 (mov, r30, %A0) CR_TAB 2785 return (AS2 (mov, r30, %A0) CR_TAB
2752 AS2 (mov, r31, %B0) CR_TAB 2786 AS2 (mov, r31, %B0) CR_TAB
2753 \"%!icall\"); 2787 \"%!icall\");
2754 } 2788 }
2755 else if (which_alternative==2) 2789 else if (which_alternative==2)
2756 return AS1(%~call,%c0); 2790 return AS1(%~call,%x0);
2757 return (AS2 (ldi,r30,lo8(%0)) CR_TAB 2791 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
2758 AS2 (ldi,r31,hi8(%0)) CR_TAB 2792 AS2 (ldi,r31,hi8(%0)) CR_TAB
2759 \"%!icall\"); 2793 \"%!icall\");
2760 }" 2794 }"
2761 [(set_attr "cc" "clobber,clobber,clobber,clobber") 2795 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2788 return (AS2 (mov, r30, %A1) CR_TAB 2822 return (AS2 (mov, r30, %A1) CR_TAB
2789 AS2 (mov, r31, %B1) CR_TAB 2823 AS2 (mov, r31, %B1) CR_TAB
2790 \"%!icall\"); 2824 \"%!icall\");
2791 } 2825 }
2792 else if (which_alternative==2) 2826 else if (which_alternative==2)
2793 return AS1(%~call,%c1); 2827 return AS1(%~call,%x1);
2794 return (AS2 (ldi, r30, lo8(%1)) CR_TAB 2828 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
2795 AS2 (ldi, r31, hi8(%1)) CR_TAB 2829 AS2 (ldi, r31, hi8(%1)) CR_TAB
2796 \"%!icall\"); 2830 \"%!icall\");
2797 }" 2831 }"
2798 [(set_attr "cc" "clobber,clobber,clobber,clobber") 2832 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2812 "nop" 2846 "nop"
2813 [(set_attr "cc" "none") 2847 [(set_attr "cc" "none")
2814 (set_attr "length" "1")]) 2848 (set_attr "length" "1")])
2815 2849
2816 ; indirect jump 2850 ; indirect jump
2817 (define_insn "indirect_jump" 2851
2852 (define_expand "indirect_jump"
2853 [(set (pc) (match_operand:HI 0 "nonmemory_operand" ""))]
2854 ""
2855 " if ((!AVR_HAVE_JMP_CALL) && !register_operand(operand0, HImode))
2856 {
2857 operands[0] = copy_to_mode_reg(HImode, operand0);
2858 }"
2859 )
2860
2861 ; indirect jump
2862 (define_insn "*jcindirect_jump"
2863 [(set (pc) (match_operand:HI 0 "immediate_operand" "i"))]
2864 ""
2865 "@
2866 %~jmp %x0"
2867 [(set_attr "length" "2")
2868 (set_attr "cc" "none")])
2869
2870 ;;
2871 (define_insn "*njcindirect_jump"
2818 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))] 2872 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2819 "!AVR_HAVE_EIJMP_EICALL" 2873 "!AVR_HAVE_EIJMP_EICALL"
2820 "@ 2874 "@
2821 ijmp 2875 ijmp
2822 push %A0\;push %B0\;ret" 2876 push %A0\;push %B0\;ret"
2850 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 2904 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2851 UNSPEC_INDEX_JMP)) 2905 UNSPEC_INDEX_JMP))
2852 (use (label_ref (match_operand 1 "" ""))) 2906 (use (label_ref (match_operand 1 "" "")))
2853 (clobber (match_dup 0))] 2907 (clobber (match_dup 0))]
2854 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES" 2908 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2855 "jmp __tablejump2__" 2909 "%~jmp __tablejump2__"
2856 [(set_attr "length" "2") 2910 [(set_attr "length" "2")
2857 (set_attr "cc" "clobber")]) 2911 (set_attr "cc" "clobber")])
2858 2912
2859 (define_insn "*tablejump_enh" 2913 (define_insn "*tablejump_enh"
2860 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 2914 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2933 (and:QI (mem:QI (match_dup 0)) 2987 (and:QI (mem:QI (match_dup 0))
2934 (match_operand:QI 1 "single_zero_operand" "n")))] 2988 (match_operand:QI 1 "single_zero_operand" "n")))]
2935 "(optimize > 0)" 2989 "(optimize > 0)"
2936 { 2990 {
2937 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff)); 2991 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2938 return AS2 (cbi,%0-0x20,%2); 2992 return AS2 (cbi,%m0-0x20,%2);
2939 } 2993 }
2940 [(set_attr "length" "1") 2994 [(set_attr "length" "1")
2941 (set_attr "cc" "none")]) 2995 (set_attr "cc" "none")])
2942 2996
2943 (define_insn "*sbi" 2997 (define_insn "*sbi"
2945 (ior:QI (mem:QI (match_dup 0)) 2999 (ior:QI (mem:QI (match_dup 0))
2946 (match_operand:QI 1 "single_one_operand" "n")))] 3000 (match_operand:QI 1 "single_one_operand" "n")))]
2947 "(optimize > 0)" 3001 "(optimize > 0)"
2948 { 3002 {
2949 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff)); 3003 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2950 return AS2 (sbi,%0-0x20,%2); 3004 return AS2 (sbi,%m0-0x20,%2);
2951 } 3005 }
2952 [(set_attr "length" "1") 3006 [(set_attr "length" "1")
2953 (set_attr "cc" "none")]) 3007 (set_attr "cc" "none")])
2954 3008
2955 ;; Lower half of the I/O space - use sbic/sbis directly. 3009 ;; Lower half of the I/O space - use sbic/sbis directly.
3148 return (AS1 (brcs,.+4) CR_TAB 3202 return (AS1 (brcs,.+4) CR_TAB
3149 AS1 (jmp,%1)); 3203 AS1 (jmp,%1));
3150 }") 3204 }")
3151 3205
3152 (define_peephole 3206 (define_peephole
3153 [(set (cc0) (match_operand:QI 0 "register_operand" "")) 3207 [(set (cc0)
3208 (compare (match_operand:QI 0 "register_operand" "")
3209 (const_int 0)))
3154 (set (pc) 3210 (set (pc)
3155 (if_then_else (eq (cc0) (const_int 0)) 3211 (if_then_else (eq (cc0) (const_int 0))
3156 (label_ref (match_operand 1 "" "")) 3212 (label_ref (match_operand 1 "" ""))
3157 (pc)))] 3213 (pc)))]
3158 "jump_over_one_insn_p (insn, operands[1])" 3214 "jump_over_one_insn_p (insn, operands[1])"