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comparison gcc/config/bfin/bfin.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
136 (UNSPEC_FUNCDESC_GOT17M4 9) 136 (UNSPEC_FUNCDESC_GOT17M4 9)
137 (UNSPEC_LSETUP_END 10) 137 (UNSPEC_LSETUP_END 10)
138 ;; Distinguish a 32-bit version of an insn from a 16-bit version. 138 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
139 (UNSPEC_32BIT 11) 139 (UNSPEC_32BIT 11)
140 (UNSPEC_NOP 12) 140 (UNSPEC_NOP 12)
141 (UNSPEC_ONES 12)]) 141 (UNSPEC_ONES 13)
142 (UNSPEC_ATOMIC 14)])
142 143
143 (define_constants 144 (define_constants
144 [(UNSPEC_VOLATILE_EH_RETURN 0) 145 [(UNSPEC_VOLATILE_CSYNC 1)
145 (UNSPEC_VOLATILE_CSYNC 1)
146 (UNSPEC_VOLATILE_SSYNC 2) 146 (UNSPEC_VOLATILE_SSYNC 2)
147 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3) 147 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)
148 (UNSPEC_VOLATILE_STORE_EH_HANDLER 4) 148 (UNSPEC_VOLATILE_STORE_EH_HANDLER 4)
149 (UNSPEC_VOLATILE_DUMMY 5)]) 149 (UNSPEC_VOLATILE_DUMMY 5)
150 (UNSPEC_VOLATILE_STALL 6)])
150 151
151 (define_constants 152 (define_constants
152 [(MACFLAG_NONE 0) 153 [(MACFLAG_NONE 0)
153 (MACFLAG_T 1) 154 (MACFLAG_T 1)
154 (MACFLAG_FU 2) 155 (MACFLAG_FU 2)
161 (MACFLAG_S2RND 9) 162 (MACFLAG_S2RND 9)
162 (MACFLAG_ISS2 10) 163 (MACFLAG_ISS2 10)
163 (MACFLAG_IH 11)]) 164 (MACFLAG_IH 11)])
164 165
165 (define_attr "type" 166 (define_attr "type"
166 "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" 167 "move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall"
167 (const_string "misc")) 168 (const_string "misc"))
168 169
169 (define_attr "addrtype" "32bit,preg,ireg" 170 (define_attr "addrtype" "32bit,preg,spreg,ireg"
170 (cond [(and (eq_attr "type" "mcld") 171 (cond [(and (eq_attr "type" "mcld")
171 (and (match_operand 0 "d_register_operand" "") 172 (and (match_operand 0 "dp_register_operand" "")
172 (match_operand 1 "mem_p_address_operand" ""))) 173 (match_operand 1 "mem_p_address_operand" "")))
173 (const_string "preg") 174 (const_string "preg")
174 (and (eq_attr "type" "mcld") 175 (and (eq_attr "type" "mcld")
175 (and (match_operand 0 "d_register_operand" "") 176 (and (match_operand 0 "dp_register_operand" "")
177 (match_operand 1 "mem_spfp_address_operand" "")))
178 (const_string "spreg")
179 (and (eq_attr "type" "mcld")
180 (and (match_operand 0 "dp_register_operand" "")
176 (match_operand 1 "mem_i_address_operand" ""))) 181 (match_operand 1 "mem_i_address_operand" "")))
177 (const_string "ireg") 182 (const_string "ireg")
178 (and (eq_attr "type" "mcst") 183 (and (eq_attr "type" "mcst")
179 (and (match_operand 1 "d_register_operand" "") 184 (and (match_operand 1 "dp_register_operand" "")
180 (match_operand 0 "mem_p_address_operand" ""))) 185 (match_operand 0 "mem_p_address_operand" "")))
181 (const_string "preg") 186 (const_string "preg")
182 (and (eq_attr "type" "mcst") 187 (and (eq_attr "type" "mcst")
183 (and (match_operand 1 "d_register_operand" "") 188 (and (match_operand 1 "dp_register_operand" "")
189 (match_operand 0 "mem_spfp_address_operand" "")))
190 (const_string "spreg")
191 (and (eq_attr "type" "mcst")
192 (and (match_operand 1 "dp_register_operand" "")
184 (match_operand 0 "mem_i_address_operand" ""))) 193 (match_operand 0 "mem_i_address_operand" "")))
185 (const_string "ireg")] 194 (const_string "ireg")]
186 (const_string "32bit"))) 195 (const_string "32bit")))
196
197 (define_attr "storereg" "preg,other"
198 (cond [(and (eq_attr "type" "mcst")
199 (match_operand 1 "p_register_operand" ""))
200 (const_string "preg")]
201 (const_string "other")))
187 202
188 ;; Scheduling definitions 203 ;; Scheduling definitions
189 204
190 (define_automaton "bfin") 205 (define_automaton "bfin")
191 206
197 ;; only one of the 16-bit slots can use a P register in an address, 212 ;; only one of the 16-bit slots can use a P register in an address,
198 ;; and only one them can be a store. 213 ;; and only one them can be a store.
199 (define_cpu_unit "store" "bfin") 214 (define_cpu_unit "store" "bfin")
200 (define_cpu_unit "pregs" "bfin") 215 (define_cpu_unit "pregs" "bfin")
201 216
217 ;; A dummy unit used to delay scheduling of loads after a conditional
218 ;; branch.
219 (define_cpu_unit "load" "bfin")
220
221 ;; A logical unit used to work around anomaly 05000074.
222 (define_cpu_unit "anomaly_05000074" "bfin")
223
202 (define_reservation "core" "slot0+slot1+slot2") 224 (define_reservation "core" "slot0+slot1+slot2")
203 225
204 (define_insn_reservation "alu" 1 226 (define_insn_reservation "alu" 1
205 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") 227 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
206 "core") 228 "core")
211 233
212 (define_insn_reservation "dsp32" 1 234 (define_insn_reservation "dsp32" 1
213 (eq_attr "type" "dsp32") 235 (eq_attr "type" "dsp32")
214 "slot0") 236 "slot0")
215 237
238 (define_insn_reservation "dsp32shiftimm" 1
239 (and (eq_attr "type" "dsp32shiftimm")
240 (eq (symbol_ref "ENABLE_WA_05000074")
241 (const_int 0)))
242 "slot0")
243
244 (define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1
245 (and (eq_attr "type" "dsp32shiftimm")
246 (ne (symbol_ref "ENABLE_WA_05000074")
247 (const_int 0)))
248 "slot0+anomaly_05000074")
249
216 (define_insn_reservation "load32" 1 250 (define_insn_reservation "load32" 1
217 (and (not (eq_attr "seq_insns" "multi")) 251 (and (not (eq_attr "seq_insns" "multi"))
218 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit"))) 252 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
219 "core") 253 "core+load")
220 254
221 (define_insn_reservation "loadp" 1 255 (define_insn_reservation "loadp" 1
222 (and (not (eq_attr "seq_insns" "multi")) 256 (and (not (eq_attr "seq_insns" "multi"))
223 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg"))) 257 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
224 "(slot1|slot2)+pregs") 258 "slot1+pregs+load")
259
260 (define_insn_reservation "loadsp" 1
261 (and (not (eq_attr "seq_insns" "multi"))
262 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg")))
263 "slot1+pregs")
225 264
226 (define_insn_reservation "loadi" 1 265 (define_insn_reservation "loadi" 1
227 (and (not (eq_attr "seq_insns" "multi")) 266 (and (not (eq_attr "seq_insns" "multi"))
228 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg"))) 267 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
229 "(slot1|slot2)") 268 "(slot1|slot2)+load")
230 269
231 (define_insn_reservation "store32" 1 270 (define_insn_reservation "store32" 1
232 (and (not (eq_attr "seq_insns" "multi")) 271 (and (not (eq_attr "seq_insns" "multi"))
233 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit"))) 272 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
234 "core") 273 "core")
235 274
236 (define_insn_reservation "storep" 1 275 (define_insn_reservation "storep" 1
237 (and (not (eq_attr "seq_insns" "multi")) 276 (and (and (not (eq_attr "seq_insns" "multi"))
238 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg"))) 277 (and (eq_attr "type" "mcst")
239 "(slot1|slot2)+pregs+store") 278 (ior (eq_attr "addrtype" "preg")
279 (eq_attr "addrtype" "spreg"))))
280 (ior (eq (symbol_ref "ENABLE_WA_05000074")
281 (const_int 0))
282 (eq_attr "storereg" "other")))
283 "slot1+pregs+store")
284
285 (define_insn_reservation "storep_anomaly_05000074" 1
286 (and (and (not (eq_attr "seq_insns" "multi"))
287 (and (eq_attr "type" "mcst")
288 (ior (eq_attr "addrtype" "preg")
289 (eq_attr "addrtype" "spreg"))))
290 (and (ne (symbol_ref "ENABLE_WA_05000074")
291 (const_int 0))
292 (eq_attr "storereg" "preg")))
293 "slot1+anomaly_05000074+pregs+store")
240 294
241 (define_insn_reservation "storei" 1 295 (define_insn_reservation "storei" 1
242 (and (not (eq_attr "seq_insns" "multi")) 296 (and (and (not (eq_attr "seq_insns" "multi"))
243 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg"))) 297 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
298 (ior (eq (symbol_ref "ENABLE_WA_05000074")
299 (const_int 0))
300 (eq_attr "storereg" "other")))
244 "(slot1|slot2)+store") 301 "(slot1|slot2)+store")
302
303 (define_insn_reservation "storei_anomaly_05000074" 1
304 (and (and (not (eq_attr "seq_insns" "multi"))
305 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
306 (and (ne (symbol_ref "ENABLE_WA_05000074")
307 (const_int 0))
308 (eq_attr "storereg" "preg")))
309 "((slot1+anomaly_05000074)|slot2)+store")
245 310
246 (define_insn_reservation "multi" 2 311 (define_insn_reservation "multi" 2
247 (eq_attr "seq_insns" "multi") 312 (eq_attr "seq_insns" "multi")
248 "core") 313 "core")
314
315 (define_insn_reservation "load_stall1" 1
316 (and (eq_attr "type" "stall")
317 (match_operand 0 "const1_operand" ""))
318 "core+load*2")
319
320 (define_insn_reservation "load_stall3" 1
321 (and (eq_attr "type" "stall")
322 (match_operand 0 "const3_operand" ""))
323 "core+load*4")
249 324
250 (absence_set "slot0" "slot1,slot2") 325 (absence_set "slot0" "slot1,slot2")
251 (absence_set "slot1" "slot2") 326 (absence_set "slot1" "slot2")
252 327
253 ;; Make sure genautomata knows about the maximum latency that can be produced 328 ;; Make sure genautomata knows about the maximum latency that can be produced
301 (const_int 4) (const_int 2)) 376 (const_int 4) (const_int 2))
302 377
303 (eq_attr "type" "move") (const_int 2) 378 (eq_attr "type" "move") (const_int 2)
304 379
305 (eq_attr "type" "dsp32") (const_int 4) 380 (eq_attr "type" "dsp32") (const_int 4)
381 (eq_attr "type" "dsp32shiftimm") (const_int 4)
306 (eq_attr "type" "call") (const_int 4) 382 (eq_attr "type" "call") (const_int 4)
307 383
308 (eq_attr "type" "br") 384 (eq_attr "type" "br")
309 (if_then_else (and 385 (if_then_else (and
310 (le (minus (match_dup 0) (pc)) (const_int 4092)) 386 (le (minus (match_dup 0) (pc)) (const_int 4092))
530 ;; The first alternative is used to make reload choose a limited register 606 ;; The first alternative is used to make reload choose a limited register
531 ;; class when faced with a movsi_insn that had its input operand replaced 607 ;; class when faced with a movsi_insn that had its input operand replaced
532 ;; with a PLUS. We generally require fewer secondary reloads this way. 608 ;; with a PLUS. We generally require fewer secondary reloads this way.
533 609
534 (define_insn "*movsi_insn" 610 (define_insn "*movsi_insn"
535 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,da,x,x,x,da,mr") 611 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
536 (match_operand:SI 1 "general_operand" "da,x*y,xKs7,xKsh,xKuh,ix,mr,da"))] 612 (match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
537 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG" 613 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
538 "@ 614 "@
615 %0 = %1;
616 %0 = %1;
539 %0 = %1; 617 %0 = %1;
540 %0 = %1; 618 %0 = %1;
541 %0 = %1 (X); 619 %0 = %1 (X);
542 %0 = %1 (X); 620 %0 = %1 (X);
543 %0 = %1 (Z); 621 %0 = %1 (Z);
544 # 622 #
545 %0 = %1%! 623 %0 = %1%!
546 %0 = %1%!" 624 %0 = %1%!"
547 [(set_attr "type" "move,move,mvi,mvi,mvi,*,mcld,mcst") 625 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
548 (set_attr "length" "2,2,2,4,4,*,*,*")]) 626 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
549 627
550 (define_insn "*movsi_insn32" 628 (define_insn "*movsi_insn32"
551 [(set (match_operand:SI 0 "register_operand" "=d,d") 629 [(set (match_operand:SI 0 "register_operand" "=d,d")
552 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))] 630 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
553 "" 631 ""
554 "@ 632 "@
555 %0 = ROT %1 BY 0%! 633 %0 = ROT %1 BY 0%!
556 %0 = %0 -|- %0%!" 634 %0 = %0 -|- %0%!"
557 [(set_attr "type" "dsp32")]) 635 [(set_attr "type" "dsp32shiftimm,dsp32")])
558 636
559 (define_split 637 (define_split
560 [(set (match_operand:SI 0 "d_register_operand" "") 638 [(set (match_operand:SI 0 "d_register_operand" "")
561 (const_int 0))] 639 (const_int 0))]
562 "splitting_for_sched && !optimize_size" 640 "splitting_for_sched && !optimize_size"
675 (match_operand:SI 1 "nonmemory_operand" "d,n"))] 753 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
676 "" 754 ""
677 "@ 755 "@
678 %d0 = %h1 << 0%! 756 %d0 = %h1 << 0%!
679 %d0 = %1;" 757 %d0 = %1;"
680 [(set_attr "type" "dsp32,mvi")]) 758 [(set_attr "type" "dsp32shiftimm,mvi")])
681 759
682 (define_expand "insv" 760 (define_expand "insv"
683 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") 761 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
684 (match_operand:SI 1 "immediate_operand" "") 762 (match_operand:SI 1 "immediate_operand" "")
685 (match_operand:SI 2 "immediate_operand" "")) 763 (match_operand:SI 2 "immediate_operand" ""))
1585 #" 1663 #"
1586 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" 1664 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1587 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) 1665 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1588 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] 1666 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1589 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" 1667 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1590 [(set_attr "type" "shft,dsp32,shft,shft,*")]) 1668 [(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")])
1591 1669
1592 (define_insn "ashrsi3" 1670 (define_insn "ashrsi3"
1593 [(set (match_operand:SI 0 "register_operand" "=d,d") 1671 [(set (match_operand:SI 0 "register_operand" "=d,d")
1594 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") 1672 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1595 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))] 1673 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1596 "" 1674 ""
1597 "@ 1675 "@
1598 %0 >>>= %2; 1676 %0 >>>= %2;
1599 %0 = %1 >>> %2%!" 1677 %0 = %1 >>> %2%!"
1600 [(set_attr "type" "shft,dsp32")]) 1678 [(set_attr "type" "shft,dsp32shiftimm")])
1601 1679
1602 (define_insn "rotl16" 1680 (define_insn "rotl16"
1603 [(set (match_operand:SI 0 "register_operand" "=d") 1681 [(set (match_operand:SI 0 "register_operand" "=d")
1604 (rotate:SI (match_operand:SI 1 "register_operand" "d") 1682 (rotate:SI (match_operand:SI 1 "register_operand" "d")
1605 (const_int 16)))] 1683 (const_int 16)))]
1636 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31)))) 1714 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1637 (set (reg:BI REG_CC) 1715 (set (reg:BI REG_CC)
1638 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))] 1716 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1639 "" 1717 ""
1640 "%0 = ROT %1 BY -1%!" 1718 "%0 = ROT %1 BY -1%!"
1641 [(set_attr "type" "dsp32")]) 1719 [(set_attr "type" "dsp32shiftimm")])
1642 1720
1643 (define_insn "rol_one" 1721 (define_insn "rol_one"
1644 [(set (match_operand:SI 0 "register_operand" "+d") 1722 [(set (match_operand:SI 0 "register_operand" "+d")
1645 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) 1723 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1646 (zero_extend:SI (reg:BI REG_CC)))) 1724 (zero_extend:SI (reg:BI REG_CC))))
1647 (set (reg:BI REG_CC) 1725 (set (reg:BI REG_CC)
1648 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] 1726 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1649 "" 1727 ""
1650 "%0 = ROT %1 BY 1%!" 1728 "%0 = ROT %1 BY 1%!"
1651 [(set_attr "type" "dsp32")]) 1729 [(set_attr "type" "dsp32shiftimm")])
1652 1730
1653 (define_expand "lshrdi3" 1731 (define_expand "lshrdi3"
1654 [(set (match_operand:DI 0 "register_operand" "") 1732 [(set (match_operand:DI 0 "register_operand" "")
1655 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 1733 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1656 (match_operand:DI 2 "general_operand" "")))] 1734 (match_operand:DI 2 "general_operand" "")))]
1721 "" 1799 ""
1722 "@ 1800 "@
1723 %0 >>= %2; 1801 %0 >>= %2;
1724 %0 = %1 >> %2%! 1802 %0 = %1 >> %2%!
1725 %0 = %1 >> %2;" 1803 %0 = %1 >> %2;"
1726 [(set_attr "type" "shft,dsp32,shft")]) 1804 [(set_attr "type" "shft,dsp32shiftimm,shft")])
1727 1805
1728 (define_insn "lshrpdi3" 1806 (define_insn "lshrpdi3"
1729 [(set (match_operand:PDI 0 "register_operand" "=e") 1807 [(set (match_operand:PDI 0 "register_operand" "=e")
1730 (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0") 1808 (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1731 (match_operand:SI 2 "nonmemory_operand" "Ku5")))] 1809 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1732 "" 1810 ""
1733 "%0 = %1 >> %2%!" 1811 "%0 = %1 >> %2%!"
1734 [(set_attr "type" "dsp32")]) 1812 [(set_attr "type" "dsp32shiftimm")])
1735 1813
1736 (define_insn "ashrpdi3" 1814 (define_insn "ashrpdi3"
1737 [(set (match_operand:PDI 0 "register_operand" "=e") 1815 [(set (match_operand:PDI 0 "register_operand" "=e")
1738 (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0") 1816 (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1739 (match_operand:SI 2 "nonmemory_operand" "Ku5")))] 1817 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1740 "" 1818 ""
1741 "%0 = %1 >>> %2%!" 1819 "%0 = %1 >>> %2%!"
1742 [(set_attr "type" "dsp32")]) 1820 [(set_attr "type" "dsp32shiftimm")])
1743 1821
1744 ;; A pattern to reload the equivalent of 1822 ;; A pattern to reload the equivalent of
1745 ;; (set (Dreg) (plus (FP) (large_constant))) 1823 ;; (set (Dreg) (plus (FP) (large_constant)))
1746 ;; or 1824 ;; or
1747 ;; (set (dagreg) (plus (FP) (arbitrary_constant))) 1825 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1761 emit_insn (gen_addsi3 (scratch, scratch, fp_op)); 1839 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1762 emit_move_insn (primary, scratch); 1840 emit_move_insn (primary, scratch);
1763 DONE; 1841 DONE;
1764 }) 1842 })
1765 1843
1766 (define_insn "reload_inpdi" 1844 (define_mode_iterator AREG [PDI V2PDI])
1767 [(set (match_operand:PDI 0 "register_operand" "=e") 1845
1768 (match_operand:PDI 1 "memory_operand" "m")) 1846 (define_insn "reload_in<mode>"
1847 [(set (match_operand:AREG 0 "register_operand" "=e")
1848 (match_operand:AREG 1 "memory_operand" "m"))
1769 (clobber (match_operand:SI 2 "register_operand" "=d"))] 1849 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1770 "" 1850 ""
1771 { 1851 {
1772 rtx xops[4]; 1852 rtx xops[4];
1773 xops[0] = operands[0]; 1853 xops[0] = operands[0];
1781 } 1861 }
1782 [(set_attr "seq_insns" "multi") 1862 [(set_attr "seq_insns" "multi")
1783 (set_attr "type" "mcld") 1863 (set_attr "type" "mcld")
1784 (set_attr "length" "12")]) 1864 (set_attr "length" "12")])
1785 1865
1786 (define_insn "reload_outpdi" 1866 (define_insn "reload_out<mode>"
1787 [(set (match_operand:PDI 0 "memory_operand" "=m") 1867 [(set (match_operand:AREG 0 "memory_operand" "=m")
1788 (match_operand:PDI 1 "register_operand" "e")) 1868 (match_operand:AREG 1 "register_operand" "e"))
1789 (clobber (match_operand:SI 2 "register_operand" "=d"))] 1869 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1790 "" 1870 ""
1791 { 1871 {
1792 rtx xops[4]; 1872 rtx xops[4];
1793 xops[0] = operands[1]; 1873 xops[0] = operands[1];
1906 (set (match_dup 0) 1986 (set (match_dup 0)
1907 (plus (match_dup 0) 1987 (plus (match_dup 0)
1908 (const_int -1))) 1988 (const_int -1)))
1909 (unspec [(const_int 0)] UNSPEC_LSETUP_END) 1989 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1910 (clobber (match_scratch:SI 2 "=&r"))] 1990 (clobber (match_scratch:SI 2 "=&r"))]
1911 "reload_completed" 1991 "splitting_loops"
1912 [(set (match_dup 2) (match_dup 0)) 1992 [(set (match_dup 2) (match_dup 0))
1913 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 1993 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1914 (set (match_dup 0) (match_dup 2)) 1994 (set (match_dup 0) (match_dup 2))
1915 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0))) 1995 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1916 (set (pc) 1996 (set (pc)
2002 2082
2003 (define_insn "*call_symbol_fdpic" 2083 (define_insn "*call_symbol_fdpic"
2004 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) 2084 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2005 (match_operand 1 "general_operand" "g")) 2085 (match_operand 1 "general_operand" "g"))
2006 (use (match_operand:SI 2 "register_operand" "Z")) 2086 (use (match_operand:SI 2 "register_operand" "Z"))
2007 (use (match_operand 3 "" ""))] 2087 (use (match_operand 3 "" ""))
2088 (clobber (reg:SI REG_RETS))]
2008 "! SIBLING_CALL_P (insn) 2089 "! SIBLING_CALL_P (insn)
2009 && GET_CODE (operands[0]) == SYMBOL_REF 2090 && GET_CODE (operands[0]) == SYMBOL_REF
2010 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))" 2091 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
2011 "call %0;" 2092 "call %0;"
2012 [(set_attr "type" "call") 2093 [(set_attr "type" "call")
2028 (define_insn "*call_value_symbol_fdpic" 2109 (define_insn "*call_value_symbol_fdpic"
2029 [(set (match_operand 0 "register_operand" "=d") 2110 [(set (match_operand 0 "register_operand" "=d")
2030 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) 2111 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2031 (match_operand 2 "general_operand" "g"))) 2112 (match_operand 2 "general_operand" "g")))
2032 (use (match_operand:SI 3 "register_operand" "Z")) 2113 (use (match_operand:SI 3 "register_operand" "Z"))
2033 (use (match_operand 4 "" ""))] 2114 (use (match_operand 4 "" ""))
2115 (clobber (reg:SI REG_RETS))]
2034 "! SIBLING_CALL_P (insn) 2116 "! SIBLING_CALL_P (insn)
2035 && GET_CODE (operands[1]) == SYMBOL_REF 2117 && GET_CODE (operands[1]) == SYMBOL_REF
2036 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))" 2118 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
2037 "call %1;" 2119 "call %1;"
2038 [(set_attr "type" "call") 2120 [(set_attr "type" "call")
2054 2136
2055 (define_insn "*call_insn_fdpic" 2137 (define_insn "*call_insn_fdpic"
2056 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y")) 2138 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
2057 (match_operand 1 "general_operand" "g")) 2139 (match_operand 1 "general_operand" "g"))
2058 (use (match_operand:SI 2 "register_operand" "Z")) 2140 (use (match_operand:SI 2 "register_operand" "Z"))
2059 (use (match_operand 3 "" ""))] 2141 (use (match_operand 3 "" ""))
2142 (clobber (reg:SI REG_RETS))]
2060 "! SIBLING_CALL_P (insn)" 2143 "! SIBLING_CALL_P (insn)"
2061 "call (%0);" 2144 "call (%0);"
2062 [(set_attr "type" "call") 2145 [(set_attr "type" "call")
2063 (set_attr "length" "2")]) 2146 (set_attr "length" "2")])
2064 2147
2076 (define_insn "*call_value_insn_fdpic" 2159 (define_insn "*call_value_insn_fdpic"
2077 [(set (match_operand 0 "register_operand" "=d") 2160 [(set (match_operand 0 "register_operand" "=d")
2078 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y")) 2161 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
2079 (match_operand 2 "general_operand" "g"))) 2162 (match_operand 2 "general_operand" "g")))
2080 (use (match_operand:SI 3 "register_operand" "Z")) 2163 (use (match_operand:SI 3 "register_operand" "Z"))
2081 (use (match_operand 4 "" ""))] 2164 (use (match_operand 4 "" ""))
2165 (clobber (reg:SI REG_RETS))]
2082 "! SIBLING_CALL_P (insn)" 2166 "! SIBLING_CALL_P (insn)"
2083 "call (%1);" 2167 "call (%1);"
2084 [(set_attr "type" "call") 2168 [(set_attr "type" "call")
2085 (set_attr "length" "2")]) 2169 (set_attr "length" "2")])
2086 2170
2097 (set_attr "length" "2")]) 2181 (set_attr "length" "2")])
2098 2182
2099 (define_insn "*call_symbol" 2183 (define_insn "*call_symbol"
2100 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q")) 2184 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2101 (match_operand 1 "general_operand" "g")) 2185 (match_operand 1 "general_operand" "g"))
2102 (use (match_operand 2 "" ""))] 2186 (use (match_operand 2 "" ""))
2187 (clobber (reg:SI REG_RETS))]
2103 "! SIBLING_CALL_P (insn) 2188 "! SIBLING_CALL_P (insn)
2104 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) 2189 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2105 && GET_CODE (operands[0]) == SYMBOL_REF 2190 && GET_CODE (operands[0]) == SYMBOL_REF
2106 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))" 2191 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2107 "call %0;" 2192 "call %0;"
2123 2208
2124 (define_insn "*call_value_symbol" 2209 (define_insn "*call_value_symbol"
2125 [(set (match_operand 0 "register_operand" "=d") 2210 [(set (match_operand 0 "register_operand" "=d")
2126 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q")) 2211 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2127 (match_operand 2 "general_operand" "g"))) 2212 (match_operand 2 "general_operand" "g")))
2128 (use (match_operand 3 "" ""))] 2213 (use (match_operand 3 "" ""))
2214 (clobber (reg:SI REG_RETS))]
2129 "! SIBLING_CALL_P (insn) 2215 "! SIBLING_CALL_P (insn)
2130 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY) 2216 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2131 && GET_CODE (operands[1]) == SYMBOL_REF 2217 && GET_CODE (operands[1]) == SYMBOL_REF
2132 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))" 2218 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2133 "call %1;" 2219 "call %1;"
2149 (set_attr "length" "4")]) 2235 (set_attr "length" "4")])
2150 2236
2151 (define_insn "*call_insn" 2237 (define_insn "*call_insn"
2152 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a")) 2238 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
2153 (match_operand 1 "general_operand" "g")) 2239 (match_operand 1 "general_operand" "g"))
2154 (use (match_operand 2 "" ""))] 2240 (use (match_operand 2 "" ""))
2241 (clobber (reg:SI REG_RETS))]
2155 "! SIBLING_CALL_P (insn)" 2242 "! SIBLING_CALL_P (insn)"
2156 "call (%0);" 2243 "call (%0);"
2157 [(set_attr "type" "call") 2244 [(set_attr "type" "call")
2158 (set_attr "length" "2")]) 2245 (set_attr "length" "2")])
2159 2246
2169 2256
2170 (define_insn "*call_value_insn" 2257 (define_insn "*call_value_insn"
2171 [(set (match_operand 0 "register_operand" "=d") 2258 [(set (match_operand 0 "register_operand" "=d")
2172 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a")) 2259 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
2173 (match_operand 2 "general_operand" "g"))) 2260 (match_operand 2 "general_operand" "g")))
2174 (use (match_operand 3 "" ""))] 2261 (use (match_operand 3 "" ""))
2262 (clobber (reg:SI REG_RETS))]
2175 "! SIBLING_CALL_P (insn)" 2263 "! SIBLING_CALL_P (insn)"
2176 "call (%1);" 2264 "call (%1);"
2177 [(set_attr "type" "call") 2265 [(set_attr "type" "call")
2178 (set_attr "length" "2")]) 2266 (set_attr "length" "2")])
2179 2267
2251 }) 2339 })
2252 2340
2253 ;; Conditional branch patterns 2341 ;; Conditional branch patterns
2254 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu 2342 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2255 2343
2256 ;; The only outcome of this pattern is that global variables
2257 ;; bfin_compare_op[01] are set for use in bcond patterns.
2258
2259 (define_expand "cmpbi"
2260 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
2261 (match_operand:BI 1 "immediate_operand" "")))]
2262 ""
2263 {
2264 bfin_compare_op0 = operands[0];
2265 bfin_compare_op1 = operands[1];
2266 DONE;
2267 })
2268
2269 (define_expand "cmpsi"
2270 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2271 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
2272 ""
2273 {
2274 bfin_compare_op0 = operands[0];
2275 bfin_compare_op1 = operands[1];
2276 DONE;
2277 })
2278
2279 (define_insn "compare_eq" 2344 (define_insn "compare_eq"
2280 [(set (match_operand:BI 0 "register_operand" "=C,C") 2345 [(set (match_operand:BI 0 "register_operand" "=C,C")
2281 (eq:BI (match_operand:SI 1 "register_operand" "d,a") 2346 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2282 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] 2347 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2283 "" 2348 ""
2321 (ltu:BI (match_operand:SI 1 "register_operand" "d,a") 2386 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2322 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] 2387 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2323 "" 2388 ""
2324 "cc =%1<%2 (iu);" 2389 "cc =%1<%2 (iu);"
2325 [(set_attr "type" "compare")]) 2390 [(set_attr "type" "compare")])
2326
2327 (define_expand "beq"
2328 [(set (match_dup 1) (match_dup 2))
2329 (set (pc)
2330 (if_then_else (match_dup 3)
2331 (label_ref (match_operand 0 "" ""))
2332 (pc)))]
2333 ""
2334 {
2335 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2336 operands[1] = bfin_cc_rtx; /* hard register: CC */
2337 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2338 /* If we have a BImode input, then we already have a compare result, and
2339 do not need to emit another comparison. */
2340 if (GET_MODE (bfin_compare_op0) == BImode)
2341 {
2342 gcc_assert (bfin_compare_op1 == const0_rtx);
2343 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2344 DONE;
2345 }
2346
2347 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2348 })
2349
2350 (define_expand "bne"
2351 [(set (match_dup 1) (match_dup 2))
2352 (set (pc)
2353 (if_then_else (match_dup 3)
2354 (label_ref (match_operand 0 "" ""))
2355 (pc)))]
2356 ""
2357 {
2358 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2359 /* If we have a BImode input, then we already have a compare result, and
2360 do not need to emit another comparison. */
2361 if (GET_MODE (bfin_compare_op0) == BImode)
2362 {
2363 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2364
2365 gcc_assert (bfin_compare_op1 == const0_rtx);
2366 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2367 DONE;
2368 }
2369
2370 operands[1] = bfin_cc_rtx; /* hard register: CC */
2371 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2372 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2373 })
2374
2375 (define_expand "bgt"
2376 [(set (match_dup 1) (match_dup 2))
2377 (set (pc)
2378 (if_then_else (match_dup 3)
2379 (label_ref (match_operand 0 "" ""))
2380 (pc)))]
2381 ""
2382 {
2383 operands[1] = bfin_cc_rtx;
2384 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2385 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2386 })
2387
2388 (define_expand "bgtu"
2389 [(set (match_dup 1) (match_dup 2))
2390 (set (pc)
2391 (if_then_else (match_dup 3)
2392 (label_ref (match_operand 0 "" ""))
2393 (pc)))]
2394 ""
2395 {
2396 operands[1] = bfin_cc_rtx;
2397 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2398 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2399 })
2400
2401 (define_expand "blt"
2402 [(set (match_dup 1) (match_dup 2))
2403 (set (pc)
2404 (if_then_else (match_dup 3)
2405 (label_ref (match_operand 0 "" ""))
2406 (pc)))]
2407 ""
2408 {
2409 operands[1] = bfin_cc_rtx;
2410 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2411 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2412 })
2413
2414 (define_expand "bltu"
2415 [(set (match_dup 1) (match_dup 2))
2416 (set (pc)
2417 (if_then_else (match_dup 3)
2418 (label_ref (match_operand 0 "" ""))
2419 (pc)))]
2420 ""
2421 {
2422 operands[1] = bfin_cc_rtx;
2423 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2424 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2425 })
2426 2391
2427 ;; Same as above, but and CC with the overflow bit generated by the first 2392 ;; Same as above, but and CC with the overflow bit generated by the first
2428 ;; multiplication. 2393 ;; multiplication.
2429 (define_insn "flag_mul_macv2hi_parts_acconly_andcc0" 2394 (define_insn "flag_mul_macv2hi_parts_acconly_andcc0"
2430 [(set (match_operand:PDI 0 "register_operand" "=B,e,e") 2395 [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
2486 } 2451 }
2487 [(set_attr "type" "misc") 2452 [(set_attr "type" "misc")
2488 (set_attr "length" "6") 2453 (set_attr "length" "6")
2489 (set_attr "seq_insns" "multi")]) 2454 (set_attr "seq_insns" "multi")])
2490 2455
2491 (define_expand "bge" 2456 (define_expand "cbranchsi4"
2492 [(set (match_dup 1) (match_dup 2)) 2457 [(set (pc)
2493 (set (pc) 2458 (if_then_else (match_operator 0 "ordered_comparison_operator"
2494 (if_then_else (match_dup 3) 2459 [(match_operand:SI 1 "register_operand" "")
2495 (label_ref (match_operand 0 "" "")) 2460 (match_operand:SI 2 "reg_or_const_int_operand" "")])
2496 (pc)))] 2461 (label_ref (match_operand 3 "" ""))
2497 "" 2462 (pc)))]
2498 { 2463 ""
2499 operands[1] = bfin_cc_rtx; 2464 {
2500 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); 2465 rtx bi_compare = bfin_gen_compare (operands[0], SImode);
2501 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); 2466 emit_jump_insn (gen_cbranchbi4 (bi_compare, bfin_cc_rtx, CONST0_RTX (BImode),
2502 }) 2467 operands[3]));
2503 2468 DONE;
2504 (define_expand "bgeu"
2505 [(set (match_dup 1) (match_dup 2))
2506 (set (pc)
2507 (if_then_else (match_dup 3)
2508 (label_ref (match_operand 0 "" ""))
2509 (pc)))]
2510 ""
2511 {
2512 operands[1] = bfin_cc_rtx;
2513 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2514 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2515 })
2516
2517 (define_expand "ble"
2518 [(set (match_dup 1) (match_dup 2))
2519 (set (pc)
2520 (if_then_else (match_dup 3)
2521 (label_ref (match_operand 0 "" ""))
2522 (pc)))]
2523 ""
2524 {
2525 operands[1] = bfin_cc_rtx;
2526 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2527 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2528 })
2529
2530 (define_expand "bleu"
2531 [(set (match_dup 1) (match_dup 2))
2532 (set (pc)
2533 (if_then_else (match_dup 3)
2534 (label_ref (match_operand 0 "" ""))
2535 (pc)))
2536 ]
2537 ""
2538 {
2539 operands[1] = bfin_cc_rtx;
2540 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2541 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2542 }) 2469 })
2543 2470
2544 (define_insn "cbranchbi4" 2471 (define_insn "cbranchbi4"
2545 [(set (pc) 2472 [(set (pc)
2546 (if_then_else 2473 (if_then_else
2547 (match_operator 0 "bfin_cbranch_operator" 2474 (match_operator 0 "bfin_bimode_comparison_operator"
2548 [(match_operand:BI 1 "register_operand" "C") 2475 [(match_operand:BI 1 "register_operand" "C")
2549 (match_operand:BI 2 "immediate_operand" "P0")]) 2476 (match_operand:BI 2 "immediate_operand" "P0")])
2550 (label_ref (match_operand 3 "" "")) 2477 (label_ref (match_operand 3 "" ""))
2551 (pc)))] 2478 (pc)))]
2552 "" 2479 ""
2560 ;; bfin_reorg for details. 2487 ;; bfin_reorg for details.
2561 2488
2562 (define_insn "cbranch_predicted_taken" 2489 (define_insn "cbranch_predicted_taken"
2563 [(set (pc) 2490 [(set (pc)
2564 (if_then_else 2491 (if_then_else
2565 (match_operator 0 "bfin_cbranch_operator" 2492 (match_operator 0 "bfin_bimode_comparison_operator"
2566 [(match_operand:BI 1 "register_operand" "C") 2493 [(match_operand:BI 1 "register_operand" "C")
2567 (match_operand:BI 2 "immediate_operand" "P0")]) 2494 (match_operand:BI 2 "immediate_operand" "P0")])
2568 (label_ref (match_operand 3 "" "")) 2495 (label_ref (match_operand 3 "" ""))
2569 (pc))) 2496 (pc)))
2570 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] 2497 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2576 [(set_attr "type" "brcc")]) 2503 [(set_attr "type" "brcc")])
2577 2504
2578 (define_insn "cbranch_with_nops" 2505 (define_insn "cbranch_with_nops"
2579 [(set (pc) 2506 [(set (pc)
2580 (if_then_else 2507 (if_then_else
2581 (match_operator 0 "bfin_cbranch_operator" 2508 (match_operator 0 "bfin_bimode_comparison_operator"
2582 [(match_operand:BI 1 "register_operand" "C") 2509 [(match_operand:BI 1 "register_operand" "C")
2583 (match_operand:BI 2 "immediate_operand" "P0")]) 2510 (match_operand:BI 2 "immediate_operand" "P0")])
2584 (label_ref (match_operand 3 "" "")) 2511 (label_ref (match_operand 3 "" ""))
2585 (pc))) 2512 (pc)))
2586 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] 2513 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2590 return ""; 2517 return "";
2591 } 2518 }
2592 [(set_attr "type" "brcc") 2519 [(set_attr "type" "brcc")
2593 (set_attr "length" "8")]) 2520 (set_attr "length" "8")])
2594 2521
2595 ;; setcc insns. */ 2522 ;; setcc insns.
2596 (define_expand "seq" 2523
2597 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3))) 2524 (define_expand "cstorebi4"
2525 [(set (match_dup 4)
2526 (match_operator:BI 1 "bfin_bimode_comparison_operator"
2527 [(match_operand:BI 2 "register_operand" "")
2528 (match_operand:BI 3 "reg_or_const_int_operand" "")]))
2598 (set (match_operand:SI 0 "register_operand" "") 2529 (set (match_operand:SI 0 "register_operand" "")
2599 (ne:SI (match_dup 1) (const_int 0)))] 2530 (ne:SI (match_dup 4) (const_int 0)))]
2600 "" 2531 ""
2601 { 2532 {
2602 operands[2] = bfin_compare_op0; 2533 /* It could be expanded as a movbisi instruction, but the portable
2603 operands[3] = bfin_compare_op1; 2534 alternative produces better code. */
2604 operands[1] = bfin_cc_rtx; 2535 if (GET_CODE (operands[1]) == NE)
2536 FAIL;
2537
2538 operands[4] = bfin_cc_rtx;
2605 }) 2539 })
2606 2540
2607 (define_expand "slt" 2541 (define_expand "cstoresi4"
2608 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3))) 2542 [(set (match_operand:SI 0 "register_operand")
2609 (set (match_operand:SI 0 "register_operand" "") 2543 (match_operator:SI 1 "ordered_comparison_operator"
2610 (ne:SI (match_dup 1) (const_int 0)))] 2544 [(match_operand:SI 2 "register_operand" "")
2611 "" 2545 (match_operand:SI 3 "reg_or_const_int_operand" "")]))]
2612 { 2546 ""
2613 operands[2] = bfin_compare_op0; 2547 {
2614 operands[3] = bfin_compare_op1; 2548 rtx bi_compare, test;
2615 operands[1] = bfin_cc_rtx; 2549
2616 }) 2550 if (!bfin_direct_comparison_operator (operands[1], SImode))
2617 2551 {
2618 (define_expand "sle" 2552 if (!register_operand (operands[3], SImode)
2619 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3))) 2553 || GET_CODE (operands[1]) == NE)
2620 (set (match_operand:SI 0 "register_operand" "") 2554 FAIL;
2621 (ne:SI (match_dup 1) (const_int 0)))] 2555 test = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
2622 "" 2556 SImode, operands[3], operands[2]);
2623 { 2557 }
2624 operands[2] = bfin_compare_op0; 2558 else
2625 operands[3] = bfin_compare_op1; 2559 test = operands[1];
2626 operands[1] = bfin_cc_rtx; 2560
2627 }) 2561 bi_compare = bfin_gen_compare (test, SImode);
2628 2562 gcc_assert (GET_CODE (bi_compare) == NE);
2629 (define_expand "sltu" 2563 emit_insn (gen_movbisi (operands[0], bfin_cc_rtx));
2630 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3))) 2564 DONE;
2631 (set (match_operand:SI 0 "register_operand" "")
2632 (ne:SI (match_dup 1) (const_int 0)))]
2633 ""
2634 {
2635 operands[2] = bfin_compare_op0;
2636 operands[3] = bfin_compare_op1;
2637 operands[1] = bfin_cc_rtx;
2638 })
2639
2640 (define_expand "sleu"
2641 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2642 (set (match_operand:SI 0 "register_operand" "")
2643 (ne:SI (match_dup 1) (const_int 0)))]
2644 ""
2645 {
2646 operands[2] = bfin_compare_op0;
2647 operands[3] = bfin_compare_op1;
2648 operands[1] = bfin_cc_rtx;
2649 }) 2565 })
2650 2566
2651 (define_insn "nop" 2567 (define_insn "nop"
2652 [(const_int 0)] 2568 [(const_int 0)]
2653 "" 2569 ""
2672 (const_int 0)))] 2588 (const_int 0)))]
2673 "" 2589 ""
2674 "CC = %1;" 2590 "CC = %1;"
2675 [(set_attr "length" "2")]) 2591 [(set_attr "length" "2")])
2676 2592
2677 (define_insn "movbisi" 2593 (define_insn_and_split "movbisi"
2678 [(set (match_operand:SI 0 "register_operand" "=d") 2594 [(set (match_operand:SI 0 "register_operand" "=d")
2679 (ne:SI (match_operand:BI 1 "register_operand" "C") 2595 (ne:SI (match_operand:BI 1 "register_operand" "C")
2680 (const_int 0)))] 2596 (const_int 0)))]
2681 "" 2597 ""
2682 "%0 = CC;" 2598 "#"
2683 [(set_attr "length" "2")]) 2599 ""
2600 [(set (match_operand:SI 0 "register_operand" "")
2601 (zero_extend:SI (match_operand:BI 1 "register_operand" "")))]
2602 "")
2684 2603
2685 (define_insn "notbi" 2604 (define_insn "notbi"
2686 [(set (match_operand:BI 0 "register_operand" "=C") 2605 [(set (match_operand:BI 0 "register_operand" "=C")
2687 (eq:BI (match_operand:BI 1 "register_operand" " 0") 2606 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2688 (const_int 0)))] 2607 (const_int 0)))]
2738 [(const_int 1)] 2657 [(const_int 1)]
2739 "" 2658 ""
2740 "bfin_expand_epilogue (0, 0, 1); DONE;") 2659 "bfin_expand_epilogue (0, 0, 1); DONE;")
2741 2660
2742 (define_expand "eh_return" 2661 (define_expand "eh_return"
2743 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")] 2662 [(use (match_operand:SI 0 "register_operand" ""))]
2744 UNSPEC_VOLATILE_EH_RETURN)]
2745 "" 2663 ""
2746 { 2664 {
2747 emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0])); 2665 emit_insn (gen_eh_store_handler (EH_RETURN_HANDLER_RTX, operands[0]));
2748 emit_jump_insn (gen_eh_return_internal ()); 2666 emit_jump_insn (gen_eh_return_internal ());
2749 emit_barrier (); 2667 emit_barrier ();
2757 "" 2675 ""
2758 "%0 = %1%!" 2676 "%0 = %1%!"
2759 [(set_attr "type" "mcst")]) 2677 [(set_attr "type" "mcst")])
2760 2678
2761 (define_insn_and_split "eh_return_internal" 2679 (define_insn_and_split "eh_return_internal"
2762 [(set (pc) 2680 [(eh_return)]
2763 (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))]
2764 "" 2681 ""
2765 "#" 2682 "#"
2766 "reload_completed" 2683 "epilogue_completed"
2767 [(const_int 1)] 2684 [(const_int 1)]
2768 "bfin_expand_epilogue (1, 1, 0); DONE;") 2685 "bfin_expand_epilogue (1, 1, 0); DONE;")
2769 2686
2770 (define_insn "link" 2687 (define_insn "link"
2771 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) 2688 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2809 return ""; 2726 return "";
2810 }) 2727 })
2811 2728
2812 (define_insn "return_internal" 2729 (define_insn "return_internal"
2813 [(return) 2730 [(return)
2814 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)] 2731 (use (match_operand 0 "register_operand" ""))]
2815 "reload_completed" 2732 "reload_completed"
2816 { 2733 {
2817 switch (INTVAL (operands[0])) 2734 switch (REGNO (operands[0]))
2818 { 2735 {
2819 case EXCPT_HANDLER: 2736 case REG_RETX:
2820 return "rtx;"; 2737 return "rtx;";
2821 case NMI_HANDLER: 2738 case REG_RETN:
2822 return "rtn;"; 2739 return "rtn;";
2823 case INTERRUPT_HANDLER: 2740 case REG_RETI:
2824 return "rti;"; 2741 return "rti;";
2825 case SUBROUTINE: 2742 case REG_RETS:
2826 return "rts;"; 2743 return "rts;";
2827 } 2744 }
2828 gcc_unreachable (); 2745 gcc_unreachable ();
2829 }) 2746 })
2830 2747
2748 ;; When used at a location where CC contains 1, causes a speculative load
2749 ;; that is later cancelled. This is used for certain workarounds in
2750 ;; interrupt handler prologues.
2831 (define_insn "dummy_load" 2751 (define_insn "dummy_load"
2832 [(unspec_volatile [(match_operand 0 "register_operand" "a") 2752 [(unspec_volatile [(match_operand 0 "register_operand" "a")
2833 (match_operand 1 "register_operand" "C")] 2753 (match_operand 1 "register_operand" "C")]
2834 UNSPEC_VOLATILE_DUMMY)] 2754 UNSPEC_VOLATILE_DUMMY)]
2835 "" 2755 ""
2836 "if cc jump 4;\n\tr7 = [%0];" 2756 "if cc jump 4;\n\tr7 = [%0];"
2837 [(set_attr "type" "misc") 2757 [(set_attr "type" "misc")
2838 (set_attr "length" "4") 2758 (set_attr "length" "4")
2839 (set_attr "seq_insns" "multi")]) 2759 (set_attr "seq_insns" "multi")])
2760
2761 ;; A placeholder insn inserted before the final scheduling pass. It is used
2762 ;; to improve scheduling of loads when workarounds for speculative loads are
2763 ;; needed, by not placing them in the first few cycles after a conditional
2764 ;; branch.
2765 (define_insn "stall"
2766 [(unspec_volatile [(match_operand 0 "const_int_operand" "P1P3")]
2767 UNSPEC_VOLATILE_STALL)]
2768 ""
2769 ""
2770 [(set_attr "type" "stall")])
2840 2771
2841 (define_insn "csync" 2772 (define_insn "csync"
2842 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)] 2773 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2843 "" 2774 ""
2844 "csync;" 2775 "csync;"
2875 (match_operand:HI 2 "register_operand" "d") 2806 (match_operand:HI 2 "register_operand" "d")
2876 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") 2807 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2877 (parallel [(const_int 1)]))))] 2808 (parallel [(const_int 1)]))))]
2878 "" 2809 ""
2879 "%h0 = %h2 << 0%!" 2810 "%h0 = %h2 << 0%!"
2880 [(set_attr "type" "dsp32")]) 2811 [(set_attr "type" "dsp32shiftimm")])
2881 2812
2882 (define_insn "movhiv2hi_high" 2813 (define_insn "movhiv2hi_high"
2883 [(set (match_operand:V2HI 0 "register_operand" "=d") 2814 [(set (match_operand:V2HI 0 "register_operand" "=d")
2884 (vec_concat:V2HI 2815 (vec_concat:V2HI
2885 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0") 2816 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2886 (parallel [(const_int 0)])) 2817 (parallel [(const_int 0)]))
2887 (match_operand:HI 2 "register_operand" "d")))] 2818 (match_operand:HI 2 "register_operand" "d")))]
2888 "" 2819 ""
2889 "%d0 = %h2 << 0%!" 2820 "%d0 = %h2 << 0%!"
2890 [(set_attr "type" "dsp32")]) 2821 [(set_attr "type" "dsp32shiftimm")])
2891 2822
2892 ;; No earlyclobber on alternative two since our sequence ought to be safe. 2823 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2893 ;; The order of operands is intentional to match the VDSP builtin (high word 2824 ;; The order of operands is intentional to match the VDSP builtin (high word
2894 ;; is passed first). 2825 ;; is passed first).
2895 (define_insn_and_split "composev2hi" 2826 (define_insn_and_split "composev2hi"
2908 (set (match_dup 0) 2839 (set (match_dup 0)
2909 (vec_concat:V2HI 2840 (vec_concat:V2HI
2910 (match_dup 2) 2841 (match_dup 2)
2911 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))] 2842 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2912 "" 2843 ""
2913 [(set_attr "type" "dsp32")]) 2844 [(set_attr "type" "dsp32shiftimm")])
2914 2845
2915 ; Like composev2hi, but operating on elements of V2HI vectors. 2846 ; Like composev2hi, but operating on elements of V2HI vectors.
2916 ; Useful on its own, and as a combiner bridge for the multiply and 2847 ; Useful on its own, and as a combiner bridge for the multiply and
2917 ; mac patterns. 2848 ; mac patterns.
2918 (define_insn "packv2hi" 2849 (define_insn "packv2hi"
2931 %h0 = %d1 << 0%! 2862 %h0 = %d1 << 0%!
2932 %0 = PACK (%h2,%h1)%! 2863 %0 = PACK (%h2,%h1)%!
2933 %0 = PACK (%h2,%d1)%! 2864 %0 = PACK (%h2,%d1)%!
2934 %0 = PACK (%d2,%h1)%! 2865 %0 = PACK (%d2,%h1)%!
2935 %0 = PACK (%d2,%d1)%!" 2866 %0 = PACK (%d2,%d1)%!"
2936 [(set_attr "type" "dsp32")]) 2867 [(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")])
2937 2868
2938 (define_insn "movv2hi_hi" 2869 (define_insn "movv2hi_hi"
2939 [(set (match_operand:HI 0 "register_operand" "=d,d,d") 2870 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2940 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d") 2871 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2941 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))] 2872 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2942 "" 2873 ""
2943 "@ 2874 "@
2944 /* optimized out */ 2875 /* optimized out */
2945 %h0 = %h1 << 0%! 2876 %h0 = %h1 << 0%!
2946 %h0 = %d1 << 0%!" 2877 %h0 = %d1 << 0%!"
2947 [(set_attr "type" "dsp32")]) 2878 [(set_attr "type" "dsp32shiftimm")])
2948 2879
2949 (define_expand "movv2hi_hi_low" 2880 (define_expand "movv2hi_hi_low"
2950 [(set (match_operand:HI 0 "register_operand" "") 2881 [(set (match_operand:HI 0 "register_operand" "")
2951 (vec_select:HI (match_operand:V2HI 1 "register_operand" "") 2882 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2952 (parallel [(const_int 0)])))] 2883 (parallel [(const_int 0)])))]
2960 "" 2891 ""
2961 "") 2892 "")
2962 2893
2963 ;; Unusual arithmetic operations on 16-bit registers. 2894 ;; Unusual arithmetic operations on 16-bit registers.
2964 2895
2965 (define_insn "ssaddhi3" 2896 (define_code_iterator sp_or_sm [ss_plus ss_minus])
2897 (define_code_attr spm_string [(ss_plus "+") (ss_minus "-")])
2898 (define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")])
2899
2900 (define_insn "ss<spm_name>hi3"
2966 [(set (match_operand:HI 0 "register_operand" "=d") 2901 [(set (match_operand:HI 0 "register_operand" "=d")
2967 (ss_plus:HI (match_operand:HI 1 "register_operand" "d") 2902 (sp_or_sm:HI (match_operand:HI 1 "register_operand" "d")
2968 (match_operand:HI 2 "register_operand" "d")))] 2903 (match_operand:HI 2 "register_operand" "d")))]
2969 "" 2904 ""
2970 "%h0 = %h1 + %h2 (S)%!" 2905 "%h0 = %h1 <spm_string> %h2 (S)%!"
2971 [(set_attr "type" "dsp32")]) 2906 [(set_attr "type" "dsp32")])
2972 2907
2973 (define_insn "ssaddhi3_parts" 2908 (define_insn "ss<spm_name>hi3_parts"
2974 [(set (vec_select:HI 2909 [(set (match_operand:HI 0 "register_operand" "=d")
2975 (match_operand:V2HI 0 "register_operand" "d") 2910 (sp_or_sm:HI (vec_select:HI
2976 (parallel [(match_operand 3 "const01_operand" "P0P1")])) 2911 (match_operand:V2HI 1 "register_operand" "d")
2977 (ss_plus:HI (vec_select:HI 2912 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2978 (match_operand:V2HI 1 "register_operand" "d") 2913 (vec_select:HI
2979 (parallel [(match_operand 4 "const01_operand" "P0P1")])) 2914 (match_operand:V2HI 2 "register_operand" "d")
2980 (vec_select:HI 2915 (parallel [(match_operand 4 "const01_operand" "P0P1")]))))]
2981 (match_operand:V2HI 2 "register_operand" "d") 2916 ""
2982 (parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
2983 ""
2984 { 2917 {
2985 const char *templates[] = { 2918 const char *templates[] = {
2986 "%h0 = %h1 + %h2 (S)%!", 2919 "%h0 = %h1 <spm_string> %h2 (S)%!",
2987 "%d0 = %h1 + %h2 (S)%!", 2920 "%h0 = %d1 <spm_string> %h2 (S)%!",
2988 "%h0 = %d1 + %h2 (S)%!", 2921 "%h0 = %h1 <spm_string> %d2 (S)%!",
2989 "%d0 = %d1 + %h2 (S)%!", 2922 "%h0 = %d1 <spm_string> %d2 (S)%!" };
2990 "%h0 = %h1 + %d2 (S)%!", 2923 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
2991 "%d0 = %h1 + %d2 (S)%!",
2992 "%h0 = %d1 + %d2 (S)%!",
2993 "%d0 = %d1 + %d2 (S)%!" };
2994 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
2995 + (INTVAL (operands[5]) << 2);
2996 return templates[alt]; 2924 return templates[alt];
2997 } 2925 }
2998 [(set_attr "type" "dsp32")]) 2926 [(set_attr "type" "dsp32")])
2999 2927
3000 (define_insn "sssubhi3_parts" 2928 (define_insn "ss<spm_name>hi3_low_parts"
3001 [(set (vec_select:HI 2929 [(set (match_operand:V2HI 0 "register_operand" "=d")
3002 (match_operand:V2HI 0 "register_operand" "d") 2930 (vec_concat:V2HI
3003 (parallel [(match_operand 3 "const01_operand" "P0P1")])) 2931 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
3004 (ss_minus:HI (vec_select:HI 2932 (parallel [(const_int 0)]))
3005 (match_operand:V2HI 1 "register_operand" "d") 2933 (sp_or_sm:HI (vec_select:HI
3006 (parallel [(match_operand 4 "const01_operand" "P0P1")])) 2934 (match_operand:V2HI 2 "register_operand" "d")
3007 (vec_select:HI 2935 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3008 (match_operand:V2HI 2 "register_operand" "d") 2936 (vec_select:HI
3009 (parallel [(match_operand 5 "const01_operand" "P0P1")]))))] 2937 (match_operand:V2HI 3 "register_operand" "d")
3010 "" 2938 (parallel [(match_operand 5 "const01_operand" "P0P1")])))))]
2939 ""
3011 { 2940 {
3012 const char *templates[] = { 2941 const char *templates[] = {
3013 "%h0 = %h1 - %h2 (S)%!", 2942 "%h0 = %h2 <spm_string> %h3 (S)%!",
3014 "%d0 = %h1 - %h2 (S)%!", 2943 "%h0 = %d2 <spm_string> %h3 (S)%!",
3015 "%h0 = %d1 - %h2 (S)%!", 2944 "%h0 = %h2 <spm_string> %d3 (S)%!",
3016 "%d0 = %d1 - %h2 (S)%!", 2945 "%h0 = %d2 <spm_string> %d3 (S)%!" };
3017 "%h0 = %h1 - %d2 (S)%!", 2946 int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
3018 "%d0 = %h1 - %d2 (S)%!",
3019 "%h0 = %d1 - %d2 (S)%!",
3020 "%d0 = %d1 - %d2 (S)%!" };
3021 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3022 + (INTVAL (operands[5]) << 2);
3023 return templates[alt]; 2947 return templates[alt];
3024 } 2948 }
3025 [(set_attr "type" "dsp32")]) 2949 [(set_attr "type" "dsp32")])
3026 2950
3027 (define_insn "sssubhi3" 2951 (define_insn "ss<spm_name>hi3_high_parts"
3028 [(set (match_operand:HI 0 "register_operand" "=d") 2952 [(set (match_operand:V2HI 0 "register_operand" "=d")
3029 (ss_minus:HI (match_operand:HI 1 "register_operand" "d") 2953 (vec_concat:V2HI
3030 (match_operand:HI 2 "register_operand" "d")))] 2954 (sp_or_sm:HI (vec_select:HI
3031 "" 2955 (match_operand:V2HI 2 "register_operand" "d")
3032 "%h0 = %h1 - %h2 (S)%!" 2956 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2957 (vec_select:HI
2958 (match_operand:V2HI 3 "register_operand" "d")
2959 (parallel [(match_operand 5 "const01_operand" "P0P1")])))
2960 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2961 (parallel [(const_int 1)]))))]
2962 ""
2963 {
2964 const char *templates[] = {
2965 "%d0 = %h2 <spm_string> %h3 (S)%!",
2966 "%d0 = %d2 <spm_string> %h3 (S)%!",
2967 "%d0 = %h2 <spm_string> %d3 (S)%!",
2968 "%d0 = %d2 <spm_string> %d3 (S)%!" };
2969 int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
2970 return templates[alt];
2971 }
3033 [(set_attr "type" "dsp32")]) 2972 [(set_attr "type" "dsp32")])
3034 2973
3035 ;; V2HI vector insns 2974 ;; V2HI vector insns
3036 2975
3037 (define_insn "addv2hi3" 2976 (define_insn "addv2hi3"
3237 "" 3176 ""
3238 "%h0 = %h1 * %h2 %M3%!" 3177 "%h0 = %h1 * %h2 %M3%!"
3239 [(set_attr "type" "dsp32")]) 3178 [(set_attr "type" "dsp32")])
3240 3179
3241 (define_insn "flag_mulhi_parts" 3180 (define_insn "flag_mulhi_parts"
3242 [(set (vec_select:HI 3181 [(set (match_operand:HI 0 "register_operand" "=d")
3243 (match_operand:V2HI 0 "register_operand" "d")
3244 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3245 (unspec:HI [(vec_select:HI 3182 (unspec:HI [(vec_select:HI
3246 (match_operand:V2HI 1 "register_operand" "d") 3183 (match_operand:V2HI 1 "register_operand" "d")
3247 (parallel [(match_operand 4 "const01_operand" "P0P1")])) 3184 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3248 (vec_select:HI 3185 (vec_select:HI
3249 (match_operand:V2HI 2 "register_operand" "d") 3186 (match_operand:V2HI 2 "register_operand" "d")
3250 (parallel [(match_operand 5 "const01_operand" "P0P1")])) 3187 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3251 (match_operand 6 "const_int_operand" "n")] 3188 (match_operand 5 "const_int_operand" "n")]
3252 UNSPEC_MUL_WITH_FLAG))] 3189 UNSPEC_MUL_WITH_FLAG))]
3253 "" 3190 ""
3254 { 3191 {
3255 const char *templates[] = { 3192 const char *templates[] = {
3256 "%h0 = %h1 * %h2 %M6%!", 3193 "%h0 = %h1 * %h2 %M5%!",
3257 "%d0 = %h1 * %h2 %M6%!", 3194 "%h0 = %d1 * %h2 %M5%!",
3258 "%h0 = %d1 * %h2 %M6%!", 3195 "%h0 = %h1 * %d2 %M5%!",
3259 "%d0 = %d1 * %h2 %M6%!", 3196 "%h0 = %d1 * %d2 %M5%!" };
3260 "%h0 = %h1 * %d2 %M6%!", 3197 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3261 "%d0 = %h1 * %d2 %M6%!",
3262 "%h0 = %d1 * %d2 %M6%!",
3263 "%d0 = %d1 * %d2 %M6%!" };
3264 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3265 + (INTVAL (operands[5]) << 2);
3266 return templates[alt]; 3198 return templates[alt];
3267 } 3199 }
3268 [(set_attr "type" "dsp32")]) 3200 [(set_attr "type" "dsp32")])
3269 3201
3270 (define_insn "flag_mulhisi" 3202 (define_insn "flag_mulhisi"
4205 "" 4137 ""
4206 "@ 4138 "@
4207 %0 = ASHIFT %1 BY %h2 (V, S)%! 4139 %0 = ASHIFT %1 BY %h2 (V, S)%!
4208 %0 = %1 << %2 (V,S)%! 4140 %0 = %1 << %2 (V,S)%!
4209 %0 = %1 >>> %N2 (V,S)%!" 4141 %0 = %1 >>> %N2 (V,S)%!"
4210 [(set_attr "type" "dsp32")]) 4142 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4211 4143
4212 (define_insn "ssashifthi3" 4144 (define_insn "ssashifthi3"
4213 [(set (match_operand:HI 0 "register_operand" "=d,d,d") 4145 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4214 (if_then_else:HI 4146 (if_then_else:HI
4215 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) 4147 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4219 "" 4151 ""
4220 "@ 4152 "@
4221 %0 = ASHIFT %1 BY %h2 (V, S)%! 4153 %0 = ASHIFT %1 BY %h2 (V, S)%!
4222 %0 = %1 << %2 (V,S)%! 4154 %0 = %1 << %2 (V,S)%!
4223 %0 = %1 >>> %N2 (V,S)%!" 4155 %0 = %1 >>> %N2 (V,S)%!"
4224 [(set_attr "type" "dsp32")]) 4156 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4225 4157
4226 (define_insn "ssashiftsi3" 4158 (define_insn "ssashiftsi3"
4227 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 4159 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4228 (if_then_else:SI 4160 (if_then_else:SI
4229 (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0)) 4161 (lt (match_operand:HI 2 "reg_or_const_int_operand" "d,Ku5,Ks5") (const_int 0))
4233 "" 4165 ""
4234 "@ 4166 "@
4235 %0 = ASHIFT %1 BY %h2 (S)%! 4167 %0 = ASHIFT %1 BY %h2 (S)%!
4236 %0 = %1 << %2 (S)%! 4168 %0 = %1 << %2 (S)%!
4237 %0 = %1 >>> %N2 (S)%!" 4169 %0 = %1 >>> %N2 (S)%!"
4238 [(set_attr "type" "dsp32")]) 4170 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4239 4171
4240 (define_insn "lshiftv2hi3" 4172 (define_insn "lshiftv2hi3"
4241 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d") 4173 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
4242 (if_then_else:V2HI 4174 (if_then_else:V2HI
4243 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) 4175 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4247 "" 4179 ""
4248 "@ 4180 "@
4249 %0 = LSHIFT %1 BY %h2 (V)%! 4181 %0 = LSHIFT %1 BY %h2 (V)%!
4250 %0 = %1 << %2 (V)%! 4182 %0 = %1 << %2 (V)%!
4251 %0 = %1 >> %N2 (V)%!" 4183 %0 = %1 >> %N2 (V)%!"
4252 [(set_attr "type" "dsp32")]) 4184 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4253 4185
4254 (define_insn "lshifthi3" 4186 (define_insn "lshifthi3"
4255 [(set (match_operand:HI 0 "register_operand" "=d,d,d") 4187 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4256 (if_then_else:HI 4188 (if_then_else:HI
4257 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0)) 4189 (lt (match_operand:HI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4261 "" 4193 ""
4262 "@ 4194 "@
4263 %0 = LSHIFT %1 BY %h2 (V)%! 4195 %0 = LSHIFT %1 BY %h2 (V)%!
4264 %0 = %1 << %2 (V)%! 4196 %0 = %1 << %2 (V)%!
4265 %0 = %1 >> %N2 (V)%!" 4197 %0 = %1 >> %N2 (V)%!"
4266 [(set_attr "type" "dsp32")]) 4198 [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
4267 4199
4268 ;; Load without alignment exception (masking off low bits) 4200 ;; Load without alignment exception (masking off low bits)
4269 4201
4270 (define_insn "loadbytes" 4202 (define_insn "loadbytes"
4271 [(set (match_operand:SI 0 "register_operand" "=d") 4203 [(set (match_operand:SI 0 "register_operand" "=d")
4273 (const_int -4))))] 4205 (const_int -4))))]
4274 "" 4206 ""
4275 "DISALGNEXCPT || %0 = [%1];" 4207 "DISALGNEXCPT || %0 = [%1];"
4276 [(set_attr "type" "mcld") 4208 [(set_attr "type" "mcld")
4277 (set_attr "length" "8")]) 4209 (set_attr "length" "8")])
4210
4211 (include "sync.md")