Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/bfin/predicates.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Fri, 12 Feb 2010 23:39:51 +0900 |
parents | a06113de4d67 |
children | 04ced10e8804 |
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52:c156f1bd5cd9 | 55:77e2b8dfacca |
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57 | 57 |
58 (define_predicate "const01_operand" | 58 (define_predicate "const01_operand" |
59 (and (match_code "const_int") | 59 (and (match_code "const_int") |
60 (match_test "op == const0_rtx || op == const1_rtx"))) | 60 (match_test "op == const0_rtx || op == const1_rtx"))) |
61 | 61 |
62 (define_predicate "const1_operand" | |
63 (and (match_code "const_int") | |
64 (match_test "op == const1_rtx"))) | |
65 | |
66 (define_predicate "const3_operand" | |
67 (and (match_code "const_int") | |
68 (match_test "INTVAL (op) == 3"))) | |
69 | |
62 (define_predicate "vec_shift_operand" | 70 (define_predicate "vec_shift_operand" |
63 (ior (and (match_code "const_int") | 71 (ior (and (match_code "const_int") |
64 (match_test "INTVAL (op) >= -16 && INTVAL (op) < 15")) | 72 (match_test "INTVAL (op) >= -16 && INTVAL (op) < 15")) |
65 (match_operand 0 "register_operand"))) | 73 (match_operand 0 "register_operand"))) |
66 | 74 |
77 | 85 |
78 ;; Return nonzero if OP is a D register. | 86 ;; Return nonzero if OP is a D register. |
79 (define_predicate "d_register_operand" | 87 (define_predicate "d_register_operand" |
80 (and (match_code "reg") | 88 (and (match_code "reg") |
81 (match_test "D_REGNO_P (REGNO (op))"))) | 89 (match_test "D_REGNO_P (REGNO (op))"))) |
90 | |
91 (define_predicate "p_register_operand" | |
92 (and (match_code "reg") | |
93 (match_test "P_REGNO_P (REGNO (op))"))) | |
94 | |
95 (define_predicate "dp_register_operand" | |
96 (and (match_code "reg") | |
97 (match_test "D_REGNO_P (REGNO (op)) || P_REGNO_P (REGNO (op))"))) | |
82 | 98 |
83 ;; Return nonzero if OP is a LC register. | 99 ;; Return nonzero if OP is a LC register. |
84 (define_predicate "lc_register_operand" | 100 (define_predicate "lc_register_operand" |
85 (and (match_code "reg") | 101 (and (match_code "reg") |
86 (match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1"))) | 102 (match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1"))) |
170 || op == frame_pointer_rtx | 186 || op == frame_pointer_rtx |
171 || (REGNO (op) >= FIRST_PSEUDO_REGISTER | 187 || (REGNO (op) >= FIRST_PSEUDO_REGISTER |
172 && REGNO (op) <= LAST_VIRTUAL_REGISTER)); | 188 && REGNO (op) <= LAST_VIRTUAL_REGISTER)); |
173 }) | 189 }) |
174 | 190 |
175 ;; Test for an operator valid in a conditional branch | 191 ;; Test for an operator valid in a BImode conditional branch |
176 (define_predicate "bfin_cbranch_operator" | 192 (define_predicate "bfin_bimode_comparison_operator" |
177 (match_code "eq,ne")) | 193 (match_code "eq,ne")) |
178 | 194 |
179 ;; The following two are used to compute the addrtype attribute. They return | 195 ;; Test for an operator whose result is accessible with movbisi. |
196 (define_predicate "bfin_direct_comparison_operator" | |
197 (match_code "eq,lt,le,leu,ltu")) | |
198 | |
199 ;; The following three are used to compute the addrtype attribute. They return | |
180 ;; true if passed a memory address usable for a 16-bit load or store using a | 200 ;; true if passed a memory address usable for a 16-bit load or store using a |
181 ;; P or I register, respectively. If neither matches, we know we have a | 201 ;; P or I register, respectively. If neither matches, we know we have a |
182 ;; 32-bit instruction. | 202 ;; 32-bit instruction. |
203 ;; We subdivide the P case into normal P registers, and SP/FP. We can assume | |
204 ;; that speculative loads through SP and FP are no problem, so this has | |
205 ;; an effect on the anomaly workaround code. | |
206 | |
183 (define_predicate "mem_p_address_operand" | 207 (define_predicate "mem_p_address_operand" |
184 (match_code "mem") | 208 (match_code "mem") |
185 { | 209 { |
186 if (effective_address_32bit_p (op, mode)) | 210 if (effective_address_32bit_p (op, mode)) |
187 return 0; | 211 return 0; |
188 op = XEXP (op, 0); | 212 op = XEXP (op, 0); |
189 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | 213 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) |
190 op = XEXP (op, 0); | 214 op = XEXP (op, 0); |
191 gcc_assert (REG_P (op)); | 215 gcc_assert (REG_P (op)); |
192 return PREG_P (op); | 216 return PREG_P (op) && op != stack_pointer_rtx && op != frame_pointer_rtx; |
217 }) | |
218 | |
219 (define_predicate "mem_spfp_address_operand" | |
220 (match_code "mem") | |
221 { | |
222 if (effective_address_32bit_p (op, mode)) | |
223 return 0; | |
224 op = XEXP (op, 0); | |
225 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
226 op = XEXP (op, 0); | |
227 gcc_assert (REG_P (op)); | |
228 return op == stack_pointer_rtx || op == frame_pointer_rtx; | |
193 }) | 229 }) |
194 | 230 |
195 (define_predicate "mem_i_address_operand" | 231 (define_predicate "mem_i_address_operand" |
196 (match_code "mem") | 232 (match_code "mem") |
197 { | 233 { |