Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/crx/crx.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Fri, 12 Feb 2010 23:39:51 +0900 |
parents | a06113de4d67 |
children |
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52:c156f1bd5cd9 | 55:77e2b8dfacca |
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61 | 61 |
62 (define_predicate "reg_or_sym_operand" | 62 (define_predicate "reg_or_sym_operand" |
63 (ior (match_code "symbol_ref") | 63 (ior (match_code "symbol_ref") |
64 (match_operand 0 "register_operand"))) | 64 (match_operand 0 "register_operand"))) |
65 | 65 |
66 (define_predicate "cc_reg_operand" | |
67 (and (match_code "reg") | |
68 (match_test "REGNO (op) == CC_REGNUM"))) | |
69 | |
66 (define_predicate "nosp_reg_operand" | 70 (define_predicate "nosp_reg_operand" |
67 (and (match_operand 0 "register_operand") | 71 (and (match_operand 0 "register_operand") |
68 (match_test "REGNO (op) != SP_REGNUM"))) | 72 (match_test "REGNO (op) != SP_REGNUM"))) |
69 | 73 |
70 (define_predicate "store_operand" | 74 (define_predicate "store_operand" |
104 (define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")]) | 108 (define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")]) |
105 (define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")]) | 109 (define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")]) |
106 | 110 |
107 (define_code_iterator mima_oprnd [smax umax smin umin]) | 111 (define_code_iterator mima_oprnd [smax umax smin umin]) |
108 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")]) | 112 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")]) |
109 | |
110 (define_code_iterator any_cond [eq ne gt gtu lt ltu ge geu le leu]) | |
111 | 113 |
112 ;; Addition Instructions | 114 ;; Addition Instructions |
113 | 115 |
114 (define_insn "adddi3" | 116 (define_insn "adddi3" |
115 [(set (match_operand:DI 0 "register_operand" "=r,r") | 117 [(set (match_operand:DI 0 "register_operand" "=r,r") |
520 } | 522 } |
521 ) | 523 ) |
522 | 524 |
523 ;; Compare and Branch Instructions | 525 ;; Compare and Branch Instructions |
524 | 526 |
527 (define_insn "cbranchcc4" | |
528 [(set (pc) | |
529 (if_then_else (match_operator 0 "ordered_comparison_operator" | |
530 [(match_operand:CC 1 "cc_reg_operand" "r") | |
531 (match_operand 2 "cst4_operand" "L")]) | |
532 (label_ref (match_operand 3 "")) | |
533 (pc)))] | |
534 "" | |
535 "b%d0\t%l3" | |
536 [(set_attr "length" "6")] | |
537 ) | |
538 | |
525 (define_insn "cbranch<mode>4" | 539 (define_insn "cbranch<mode>4" |
526 [(set (pc) | 540 [(set (pc) |
527 (if_then_else (match_operator 0 "comparison_operator" | 541 (if_then_else (match_operator 0 "ordered_comparison_operator" |
528 [(match_operand:CRXIM 1 "register_operand" "r") | 542 [(match_operand:CRXIM 1 "register_operand" "r") |
529 (match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")]) | 543 (match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")]) |
530 (label_ref (match_operand 3 "" "")) | 544 (label_ref (match_operand 3 "" "")) |
531 (pc))) | 545 (pc))) |
532 (clobber (reg:CC CC_REGNUM))] | 546 (clobber (reg:CC CC_REGNUM))] |
533 "" | 547 "" |
534 "cmpb%d0<tIsa>\t%2, %1, %l3" | 548 "cmpb%d0<tIsa>\t%2, %1, %l3" |
535 [(set_attr "length" "6")] | 549 [(set_attr "length" "6")] |
536 ) | 550 ) |
537 | 551 |
538 ;; Compare Instructions | 552 |
539 | 553 ;; Scond Instructions |
540 (define_expand "cmp<mode>" | 554 |
555 (define_expand "cstore<mode>4" | |
541 [(set (reg:CC CC_REGNUM) | 556 [(set (reg:CC CC_REGNUM) |
542 (compare:CC (match_operand:CRXIM 0 "register_operand" "") | 557 (compare:CC (match_operand:CRXIM 2 "register_operand" "") |
543 (match_operand:CRXIM 1 "nonmemory_operand" "")))] | 558 (match_operand:CRXIM 3 "nonmemory_operand" ""))) |
544 "" | 559 (set (match_operand:SI 0 "register_operand") |
545 { | 560 (match_operator:SI 1 "ordered_comparison_operator" |
546 crx_compare_op0 = operands[0]; | 561 [(reg:CC CC_REGNUM) (const_int 0)]))] |
547 crx_compare_op1 = operands[1]; | 562 "" |
548 DONE; | 563 "" |
549 } | |
550 ) | 564 ) |
551 | 565 |
552 (define_insn "cmp<mode>_internal" | 566 (define_insn "cmp<mode>_internal" |
553 [(set (reg:CC CC_REGNUM) | 567 [(set (reg:CC CC_REGNUM) |
554 (compare:CC (match_operand:CRXIM 0 "register_operand" "r,r") | 568 (compare:CC (match_operand:CRXIM 0 "register_operand" "r,r") |
556 "" | 570 "" |
557 "cmp<tIsa>\t%1, %0" | 571 "cmp<tIsa>\t%1, %0" |
558 [(set_attr "length" "2,<lImmArith>")] | 572 [(set_attr "length" "2,<lImmArith>")] |
559 ) | 573 ) |
560 | 574 |
561 ;; Conditional Branch Instructions | |
562 | |
563 (define_expand "b<code>" | |
564 [(set (pc) | |
565 (if_then_else (any_cond (reg:CC CC_REGNUM) | |
566 (const_int 0)) | |
567 (label_ref (match_operand 0 "")) | |
568 (pc)))] | |
569 "" | |
570 { | |
571 crx_expand_branch (<CODE>, operands[0]); | |
572 DONE; | |
573 } | |
574 ) | |
575 | |
576 (define_insn "bCOND_internal" | |
577 [(set (pc) | |
578 (if_then_else (match_operator 0 "comparison_operator" | |
579 [(reg:CC CC_REGNUM) | |
580 (const_int 0)]) | |
581 (label_ref (match_operand 1 "")) | |
582 (pc)))] | |
583 "" | |
584 "b%d0\t%l1" | |
585 [(set_attr "length" "6")] | |
586 ) | |
587 | |
588 ;; Scond Instructions | |
589 | |
590 (define_expand "s<code>" | |
591 [(set (match_operand:SI 0 "register_operand") | |
592 (any_cond:SI (reg:CC CC_REGNUM) (const_int 0)))] | |
593 "" | |
594 { | |
595 crx_expand_scond (<CODE>, operands[0]); | |
596 DONE; | |
597 } | |
598 ) | |
599 | |
600 (define_insn "sCOND_internal" | 575 (define_insn "sCOND_internal" |
601 [(set (match_operand:SI 0 "register_operand" "=r") | 576 [(set (match_operand:SI 0 "register_operand" "=r") |
602 (match_operator:SI 1 "comparison_operator" | 577 (match_operator:SI 1 "ordered_comparison_operator" |
603 [(reg:CC CC_REGNUM) (const_int 0)]))] | 578 [(reg:CC CC_REGNUM) (const_int 0)]))] |
604 "" | 579 "" |
605 "s%d1\t%0" | 580 "s%d1\t%0" |
606 [(set_attr "length" "2")] | 581 [(set_attr "length" "2")] |
607 ) | 582 ) |