CbC/CbC_gcc: gcc/config/ia64/ia64.c comparison

comparison gcc/config/ia64/ia64.c @ 55:77e2b8dfacca gcc-4.4.5

update it from 4.4.3 to 4.5.0

author	ryoma <e075725@ie.u-ryukyu.ac.jp>
date	Fri, 12 Feb 2010 23:39:51 +0900
parents	3bfb6c00c1e0
children	b7f97abdc517

comparison

equal deleted inserted replaced

-:c156f1bd5cd9
+:77e2b8dfacca
 /* Definitions of target machine for GNU compiler.
 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
-2009  Free Software Foundation, Inc.
+2009
+Free Software Foundation, Inc.
 Contributed by James E. Wilson <wilson@cygnus.com> and
 		  David Mosberger <davidm@hpl.hp.com>.
 This file is part of GCC.
 #include "optabs.h"
 #include "except.h"
 #include "function.h"
 #include "ggc.h"
 #include "basic-block.h"
+#include "libfuncs.h"
 #include "toplev.h"
 #include "sched-int.h"
 #include "timevar.h"
 #include "target.h"
 #include "target-def.h"
 #include "sel-sched.h"
 /* This is used for communication between ASM_OUTPUT_LABEL and
 ASM_OUTPUT_LABELREF.  */
 int ia64_asm_output_label = 0;
-/* Define the information needed to generate branch and scc insns.  This is
-stored from the compare operation.  */
-struct rtx_def * ia64_compare_op0;
-struct rtx_def * ia64_compare_op1;
 /* Register names for ia64_expand_prologue.  */
 static const char * const ia64_reg_numbers[96] =
 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
 static rtx gen_movdi_x (rtx, rtx, rtx);
 static rtx gen_fr_spill_x (rtx, rtx, rtx);
 static rtx gen_fr_restore_x (rtx, rtx, rtx);
+static bool ia64_can_eliminate (const int, const int);
 static enum machine_mode hfa_element_mode (const_tree, bool);
 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
 					 tree, int *, int);
 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
 				   tree, bool);
 ATTRIBUTE_UNUSED;
 static void ia64_vms_init_libfuncs (void)
 ATTRIBUTE_UNUSED;
 static void ia64_soft_fp_init_libfuncs (void)
 ATTRIBUTE_UNUSED;
+static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
+ATTRIBUTE_UNUSED;
+static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
+ATTRIBUTE_UNUSED;
 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
 static void ia64_encode_section_info (tree, rtx, int);
 static rtx ia64_struct_value_rtx (tree, int);
 static const char *ia64_mangle_type (const_tree);
 static const char *ia64_invalid_conversion (const_tree, const_tree);
 static const char *ia64_invalid_unary_op (int, const_tree);
 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
 static enum machine_mode ia64_c_mode_for_suffix (char);
+static enum machine_mode ia64_promote_function_mode (const_tree,
+						     enum machine_mode,
+						     int *,
+						     const_tree,
+						     int);
+static void ia64_trampoline_init (rtx, tree, rtx);
+static void ia64_override_options_after_change (void);
 /* Table of valid machine attributes.  */
 static const struct attribute_spec ia64_attribute_table[] =
 {
 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
 { "syscall_linkage", 0, 0, false, true,  true,  NULL },
 { "model",	       1, 1, true, false, false, ia64_handle_model_attribute },
+#if TARGET_ABI_OPEN_VMS
+{ "common_object",   1, 1, true, false, false, ia64_vms_common_object_attribute},
+#endif
 { "version_id",      1, 1, true, false, false,
 ia64_handle_version_id_attribute },
 { NULL,	       0, 0, false, false, false, NULL }
 };
 #ifdef HAVE_AS_TLS
 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
 #endif
-/* ??? ABI doesn't allow us to define this.  */
+#undef TARGET_PROMOTE_FUNCTION_MODE
-#if 0
+#define TARGET_PROMOTE_FUNCTION_MODE ia64_promote_function_mode
-#undef TARGET_PROMOTE_FUNCTION_ARGS
-#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
-#endif
-/* ??? ABI doesn't allow us to define this.  */
-#if 0
-#undef TARGET_PROMOTE_FUNCTION_RETURN
-#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
-#endif
 /* ??? Investigate.  */
 #if 0
 #undef TARGET_PROMOTE_PROTOTYPES
 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
 #undef TARGET_C_MODE_FOR_SUFFIX
 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
+#undef TARGET_CAN_ELIMINATE
+#define TARGET_CAN_ELIMINATE ia64_can_eliminate
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
+#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
+#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
 struct gcc_target targetm = TARGET_INITIALIZER;
 typedef enum
 {
 ADDR_AREA_NORMAL,	/* normal address area */
 {
 addr_area = ADDR_AREA_SMALL;
 }
 else
 {
-warning (OPT_Wattributes, "invalid argument of %qs attribute",
+warning (OPT_Wattributes, "invalid argument of %qE attribute",
-	       IDENTIFIER_POINTER (name));
+	       name);
 *no_add_attrs = true;
 }
 switch (TREE_CODE (decl))
 {
 case VAR_DECL:
 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
 	   == FUNCTION_DECL)
 	  && !TREE_STATIC (decl))
 	{
-	  error ("%Jan address area attribute cannot be specified for "
+	  error_at (DECL_SOURCE_LOCATION (decl),
-		 "local variables", decl);
+		    "an address area attribute cannot be specified for "
+		    "local variables");
 	  *no_add_attrs = true;
 	}
 area = ia64_get_addr_area (decl);
 if (area != ADDR_AREA_NORMAL && addr_area != area)
 	{
 	  *no_add_attrs = true;
 	}
 break;
 case FUNCTION_DECL:
-error ("%Jaddress area attribute cannot be specified for functions",
+error_at (DECL_SOURCE_LOCATION (decl),
-	     decl);
+		"address area attribute cannot be specified for "
+		"functions");
 *no_add_attrs = true;
 break;
 default:
-warning (OPT_Wattributes, "%qs attribute ignored",
+warning (OPT_Wattributes, "%qE attribute ignored",
-	       IDENTIFIER_POINTER (name));
+	       name);
 *no_add_attrs = true;
 break;
 }
 return NULL_TREE;
+}
+/* The section must have global and overlaid attributes.  */
+#define SECTION_VMS_OVERLAY SECTION_MACH_DEP
+/* Part of the low level implementation of DEC Ada pragma Common_Object which
+enables the shared use of variables stored in overlaid linker areas
+corresponding to the use of Fortran COMMON.  */
+static tree
+ia64_vms_common_object_attribute (tree *node, tree name, tree args,
+				  int flags ATTRIBUTE_UNUSED,
+				  bool *no_add_attrs)
+{
+tree decl = *node;
+tree id, val;
+if (! DECL_P (decl))
+abort ();
+DECL_COMMON (decl) = 1;
+id = TREE_VALUE (args);
+if (TREE_CODE (id) == IDENTIFIER_NODE)
+val = build_string (IDENTIFIER_LENGTH (id), IDENTIFIER_POINTER (id));
+else if (TREE_CODE (id) == STRING_CST)
+val = id;
+else
+{
+	warning (OPT_Wattributes,
+		 "%qE attribute requires a string constant argument", name);
+	*no_add_attrs = true;
+	return NULL_TREE;
+}
+DECL_SECTION_NAME (decl) = val;
+return NULL_TREE;
+}
+/* Part of the low level implementation of DEC Ada pragma Common_Object.  */
+void
+ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
+				     unsigned HOST_WIDE_INT size,
+				     unsigned int align)
+{
+tree attr = DECL_ATTRIBUTES (decl);
+/* As common_object attribute set DECL_SECTION_NAME check it before
+looking up the attribute.  */
+if (DECL_SECTION_NAME (decl) && attr)
+attr = lookup_attribute ("common_object", attr);
+else
+attr = NULL_TREE;
+if (!attr)
+{
+/*  Code from elfos.h.  */
+fprintf (file, "%s", COMMON_ASM_OP);
+assemble_name (file, name);
+fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
+	       size, align / BITS_PER_UNIT);
+}
+else
+{
+ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
+ASM_OUTPUT_LABEL (file, name);
+ASM_OUTPUT_SKIP (file, size ? size : 1);
+}
+}
+/* Definition of TARGET_ASM_NAMED_SECTION for VMS.  */
+void
+ia64_vms_elf_asm_named_section (const char *name, unsigned int flags,
+				tree decl)
+{
+if (!(flags & SECTION_VMS_OVERLAY))
+{
+default_elf_asm_named_section (name, flags, decl);
+return;
+}
+if (flags != (SECTION_VMS_OVERLAY | SECTION_WRITE))
+abort ();
+if (flags & SECTION_DECLARED)
+{
+fprintf (asm_out_file, "\t.section\t%s\n", name);
+return;
+}
+fprintf (asm_out_file, "\t.section\t%s,\"awgO\"\n", name);
 }
 static void
 ia64_encode_addr_area (tree decl, rtx symbol)
 {
 /* Return the TLS model to use for ADDR.  */
 static enum tls_model
 tls_symbolic_operand_type (rtx addr)
 {
-enum tls_model tls_kind = 0;
+enum tls_model tls_kind = TLS_MODEL_NONE;
 if (GET_CODE (addr) == CONST)
 {
 if (GET_CODE (XEXP (addr, 0)) == PLUS
 	  && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
 case CONST_INT:
 case LABEL_REF:
 return true;
 case CONST_DOUBLE:
-if (GET_MODE (x) == VOIDmode)
+if (GET_MODE (x) == VOIDmode || GET_MODE (x) == SFmode
+	  || GET_MODE (x) == DFmode)
 	return true;
 return satisfies_constraint_G (x);
 case CONST:
 case SYMBOL_REF:
 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP)				\
 if (GET_CODE (EXP) == MEM						\
 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY			\
 	  || GET_CODE (XEXP (EXP, 0)) == POST_INC			\
 	  || GET_CODE (XEXP (EXP, 0)) == POST_DEC))			\
-REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC,			\
+add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
-					  XEXP (XEXP (EXP, 0), 0),	\
-					  REG_NOTES (INSN))
 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
 }
 return false;
 }
-/* Emit comparison instruction if necessary, returning the expression
+/* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
-that holds the compare result in the proper mode.  */
+with the expression that holds the compare result (in VOIDmode).  */
 static GTY(()) rtx cmptf_libfunc;
-rtx
+void
-ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
+ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
 {
-rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
+enum rtx_code code = GET_CODE (*expr);
 rtx cmp;
 /* If we have a BImode input, then we already have a compare result, and
 do not need to emit another comparison.  */
-if (GET_MODE (op0) == BImode)
+if (GET_MODE (*op0) == BImode)
 {
-gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
+gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
-cmp = op0;
+cmp = *op0;
 }
 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
 magic number as its third argument, that indicates what to do.
 The return value is an integer to be compared against zero.  */
-else if (TARGET_HPUX && GET_MODE (op0) == TFmode)
+else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
 {
 enum qfcmp_magic {
 	QCMP_INV = 1,	/* Raise FP_INVALID on SNaN as a side effect.  */
 	QCMP_UNORD = 2,
 	QCMP_EQ = 4,
 	QCMP_LT = 8,
 	QCMP_GT = 16
-} magic;
+};
+int magic;
 enum rtx_code ncode;
 rtx ret, insns;
-gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
+gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
 switch (code)
 	{
 	  /* 1 = equal, 0 = not equal.  Equality operators do
 	     not raise FP_INVALID when given an SNaN operand.  */
 	case EQ:        magic = QCMP_EQ;                  ncode = NE; break;
 	}
 start_sequence ();
 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
-				     op0, TFmode, op1, TFmode,
+				     *op0, TFmode, *op1, TFmode,
 				     GEN_INT (magic), DImode);
 cmp = gen_reg_rtx (BImode);
 emit_insn (gen_rtx_SET (VOIDmode, cmp,
 			      gen_rtx_fmt_ee (ncode, BImode,
 					      ret, const0_rtx)));
 insns = get_insns ();
 end_sequence ();
 emit_libcall_block (insns, cmp, cmp,
-			  gen_rtx_fmt_ee (code, BImode, op0, op1));
+			  gen_rtx_fmt_ee (code, BImode, *op0, *op1));
 code = NE;
 }
 else
 {
 cmp = gen_reg_rtx (BImode);
 emit_insn (gen_rtx_SET (VOIDmode, cmp,
-			      gen_rtx_fmt_ee (code, BImode, op0, op1)));
+			      gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
 code = NE;
 }
-return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
+*expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
+*op0 = cmp;
+*op1 = const0_rtx;
 }
 /* Generate an integral vector comparison.  Return true if the condition has
 been reversed, and so the sense of the comparison should be inverted.  */
 	{
 	case V2SImode:
 	  {
 	    rtx t1, t2, mask;
-	    /* Subtract (-(INT MAX) - 1) from both operands to make
+	    /* Perform a parallel modulo subtraction.  */
-	       them signed.  */
+	    t1 = gen_reg_rtx (V2SImode);
-	    mask = GEN_INT (0x80000000);
+	    emit_insn (gen_subv2si3 (t1, op0, op1));
+	    /* Extract the original sign bit of op0.  */
+	    mask = GEN_INT (-0x80000000);
 	    mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
-	    mask = force_reg (mode, mask);
+	    mask = force_reg (V2SImode, mask);
-	    t1 = gen_reg_rtx (mode);
+	    t2 = gen_reg_rtx (V2SImode);
-	    emit_insn (gen_subv2si3 (t1, op0, mask));
+	    emit_insn (gen_andv2si3 (t2, op0, mask));
-	    t2 = gen_reg_rtx (mode);
-	    emit_insn (gen_subv2si3 (t2, op1, mask));
+	    /* XOR it back into the result of the subtraction.  This results
-	    op0 = t1;
+	       in the sign bit set iff we saw unsigned underflow.  */
-	    op1 = t2;
+	    x = gen_reg_rtx (V2SImode);
+	    emit_insn (gen_xorv2si3 (x, t1, t2));
 	    code = GT;
+	    op0 = x;
+	    op1 = CONST0_RTX (mode);
 	  }
 	  break;
 	case V8QImode:
 	case V4HImode:
 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
 }
 if (sibcall_p)
 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
+if (TARGET_ABI_OPEN_VMS)
+use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
+	     gen_rtx_REG (DImode, GR_REG (25)));
 }
 static void
 reg_emitted (enum ia64_frame_regs r)
 {
 }
 static bool
 is_emitted (int regno)
 {
-enum ia64_frame_regs r;
+unsigned int r;
 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
 if (emitted_frame_related_regs[r] == regno)
 return true;
 return false;
 COPY_HARD_REG_SET (current_frame_info.mask, mask);
 current_frame_info.n_spilled = n_spilled;
 current_frame_info.initialized = reload_completed;
 }
+/* Worker function for TARGET_CAN_ELIMINATE.  */
+bool
+ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
+{
+return (to == BR_REG (0) ? current_function_is_leaf : true);
+}
 /* Compute the initial difference between the specified pair of registers.  */
 HOST_WIDE_INT
 ia64_initial_elimination_offset (int from, int to)
 {
 	  *spill_fill_data.prev_addr[iter]
 	    = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
 				   gen_rtx_PLUS (DImode,
 						 spill_fill_data.iter_reg[iter],
 						 disp_rtx));
-	  REG_NOTES (spill_fill_data.prev_insn[iter])
+	  add_reg_note (spill_fill_data.prev_insn[iter],
-	    = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
+			REG_INC, spill_fill_data.iter_reg[iter]);
-				 REG_NOTES (spill_fill_data.prev_insn[iter]));
 	}
 else
 	{
 	  /* ??? Could use register post_modify for loads.  */
 	  if (!satisfies_constraint_I (disp_rtx))
 	{
 	  base = stack_pointer_rtx;
 	  off = current_frame_info.total_size - cfa_off;
 	}
-REG_NOTES (insn)
+add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-	= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+		    gen_rtx_SET (VOIDmode,
-		gen_rtx_SET (VOIDmode,
+				 gen_rtx_MEM (GET_MODE (reg),
-			     gen_rtx_MEM (GET_MODE (reg),
+					      plus_constant (base, off)),
-					  plus_constant (base, off)),
+				 frame_reg));
-			     frame_reg),
-		REG_NOTES (insn));
 }
 }
 static void
 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
 if (! frame_pointer_needed)
 	{
 	  RTX_FRAME_RELATED_P (insn) = 1;
 	  if (GET_CODE (offset) != CONST_INT)
-	    {
+	    add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-	      REG_NOTES (insn)
+			  gen_rtx_SET (VOIDmode,
-		= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+				       stack_pointer_rtx,
-			gen_rtx_SET (VOIDmode,
+				       gen_rtx_PLUS (DImode,
-				     stack_pointer_rtx,
+						     stack_pointer_rtx,
-				     gen_rtx_PLUS (DImode,
+						     frame_size_rtx)));
-						   stack_pointer_rtx,
-						   frame_size_rtx)),
-			REG_NOTES (insn));
-	    }
 	}
 /* ??? At this point we must generate a magic insn that appears to
 	 modify the stack pointer, the frame pointer, and all spill
 	 iterators.  This would allow the most scheduling freedom.  For
 	  insn = emit_move_insn (alt_reg, reg);
 	  /* ??? Denote pr spill/fill by a DImode move that modifies all
 	     64 hard registers.  */
 	  RTX_FRAME_RELATED_P (insn) = 1;
-	  REG_NOTES (insn)
+	  add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-	    = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+			gen_rtx_SET (VOIDmode, alt_reg, reg));
-			gen_rtx_SET (VOIDmode, alt_reg, reg),
-			REG_NOTES (insn));
 	  /* Even if we're not going to generate an epilogue, we still
 	     need to save the register so that EH works.  */
 	  if (! epilogue_p)
 	    emit_insn (gen_prologue_use (alt_reg));
 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
 				    offset));
 RTX_FRAME_RELATED_P (insn) = 1;
 if (GET_CODE (offset) != CONST_INT)
-	{
+	add_reg_note (insn, REG_FRAME_RELATED_EXPR,
-	  REG_NOTES (insn)
+		      gen_rtx_SET (VOIDmode,
-	    = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+				   stack_pointer_rtx,
-			gen_rtx_SET (VOIDmode,
+				   gen_rtx_PLUS (DImode,
-				     stack_pointer_rtx,
+						 stack_pointer_rtx,
-				     gen_rtx_PLUS (DImode,
+						 frame_size_rtx)));
-						   stack_pointer_rtx,
-						   frame_size_rtx)),
-			REG_NOTES (insn));
-	}
 }
 if (cfun->machine->ia64_eh_epilogue_bsp)
 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
 int
 ia64_hard_regno_rename_ok (int from, int to)
 {
 /* Don't clobber any of the registers we reserved for the prologue.  */
-enum ia64_frame_regs r;
+unsigned int r;
 for (r = reg_fp; r <= reg_save_ar_lc; r++)
 if (to == current_frame_info.r[r]
 || from == current_frame_info.r[r]
 || to == emitted_frame_related_regs[r]
 	    + current_frame_info.n_local_regs + regno - OUT_REG (0));
 else
 return regno;
 }
-void
+/* Implement TARGET_TRAMPOLINE_INIT.
-ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
-{
+The trampoline should set the static chain pointer to value placed
-rtx addr_reg, eight = GEN_INT (8);
+into the trampoline and should branch to the specified routine.
+To make the normal indirect-subroutine calling convention work,
+the trampoline must look like a function descriptor; the first
+word being the target address and the second being the target's
+global pointer.
+We abuse the concept of a global pointer by arranging for it
+to point to the data we need to load.  The complete trampoline
+has the following form:
+		+-------------------+ \
+	TRAMP:	| __ia64_trampoline | |
+		+-------------------+  > fake function descriptor
+		| TRAMP+16          | |
+		+-------------------+ /
+		| target descriptor |
+		+-------------------+
+		| static link	    |
+		+-------------------+
+*/
+static void
+ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
+{
+rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
+rtx addr, addr_reg, tramp, eight = GEN_INT (8);
 /* The Intel assembler requires that the global __ia64_trampoline symbol
 be declared explicitly */
 if (!TARGET_GNU_AS)
 {
 					      "__ia64_trampoline");
 	}
 }
 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
-addr = convert_memory_address (Pmode, addr);
+addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
 fnaddr = convert_memory_address (Pmode, fnaddr);
 static_chain = convert_memory_address (Pmode, static_chain);
 /* Load up our iterator.  */
-addr_reg = gen_reg_rtx (Pmode);
+addr_reg = copy_to_reg (addr);
-emit_move_insn (addr_reg, addr);
+m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
 /* The first two words are the fake descriptor:
 __ia64_trampoline, ADDR+16.  */
-emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
+tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
-		  gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
+if (TARGET_ABI_OPEN_VMS)
+{
+/* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
+	 in the Macro-32 compiler) and changed the semantics of the LTOFF22
+	 relocation against function symbols to make it identical to the
+	 LTOFF_FPTR22 relocation.  Emit the latter directly to stay within
+	 strict ELF and dereference to get the bare code address.  */
+rtx reg = gen_reg_rtx (Pmode);
+SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
+emit_move_insn (reg, tramp);
+emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
+tramp = reg;
+}
+emit_move_insn (m_tramp, tramp);
 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
+m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
-emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
-		  copy_to_reg (plus_constant (addr, 16)));
+emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (addr, 16)));
 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
+m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
 /* The third word is the target descriptor.  */
-emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
+emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
+m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
 /* The fourth word is the static chain.  */
-emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
+emit_move_insn (m_tramp, static_chain);
 }
 /* Do any needed setup for a variadic function.  CUM has not been updated
 for the last named argument which has type TYPE and mode MODE.
 all as if they had 16 byte alignment.  Such aggregates can occur
 only if gcc extensions are used.  */
 static int
 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
 {
-if ((cum->words & 1) == 0)
+/* No registers are skipped on VMS.  */
+if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
 return 0;
 if (type
 && TREE_CODE (type) != INTEGER_TYPE
 && TREE_CODE (type) != REAL_TYPE)
 {
 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
 int words = ia64_function_arg_words (type, mode);
 int offset = ia64_function_arg_offset (cum, type, words);
 enum machine_mode hfa_mode = VOIDmode;
+/* For OPEN VMS, emit the instruction setting up the argument register here,
+when we know this will be together with the other arguments setup related
+insns.  This is not the conceptually best place to do this, but this is
+the easiest as we have convenient access to cumulative args info.  */
+if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
+&& named == 1)
+{
+unsigned HOST_WIDE_INT regval = cum->words;
+int i;
+for (i = 0; i < 8; i++)
+	regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
+emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
+		      GEN_INT (regval));
+}
 /* If all argument slots are used, then it must go on the stack.  */
 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
 return 0;
 	    int_regs++;
 	  else if (gr_size > UNITS_PER_WORD)
 	    int_regs += gr_size / UNITS_PER_WORD;
 	}
 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
+}
+/* On OpenVMS variable argument is either in Rn or Fn.  */
+else if (TARGET_ABI_OPEN_VMS && named == 0)
+{
+if (FLOAT_MODE_P (mode))
+	return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
+else
+	return gen_rtx_REG (mode, basereg + cum->words);
 }
 /* Integral and aggregates go in general registers.  If we have run out of
 FR registers, then FP values must also go in general registers.  This can
 happen when we have a SFmode HFA.  */
 return 0;
 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
 }
+/* Return ivms_arg_type based on machine_mode.  */
+static enum ivms_arg_type
+ia64_arg_type (enum machine_mode mode)
+{
+switch (mode)
+{
+case SFmode:
+return FS;
+case DFmode:
+return FT;
+default:
+return I64;
+}
+}
 /* Update CUM to point after this argument.  This is patterned after
 ia64_function_arg.  */
 void
 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
 int offset = ia64_function_arg_offset (cum, type, words);
 enum machine_mode hfa_mode = VOIDmode;
 /* If all arg slots are already full, then there is nothing to do.  */
 if (cum->words >= MAX_ARGUMENT_SLOTS)
-return;
+{
+cum->words += words + offset;
+return;
+}
+cum->atypes[cum->words] = ia64_arg_type (mode);
 cum->words += words + offset;
 /* Check for and handle homogeneous FP aggregates.  */
 if (type)
 hfa_mode = hfa_element_mode (type, 0);
 	  args_byte_size += hfa_size;
 	  fp_regs++;
 	}
 cum->fp_regs = fp_regs;
+}
+/* On OpenVMS variable argument is either in Rn or Fn.  */
+else if (TARGET_ABI_OPEN_VMS && named == 0)
+{
+cum->int_regs = cum->words;
+cum->fp_regs = cum->words;
 }
 /* Integral and aggregates go in general registers.  So do TFmode FP values.
 If we have run out of FR registers, then other FP values must also go in
 general registers.  This can happen when we have a SFmode HFA.  */
 }
 /* Return rtx for register that holds the function return value.  */
 rtx
-ia64_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
+ia64_function_value (const_tree valtype, const_tree func)
 {
 enum machine_mode mode;
 enum machine_mode hfa_mode;
+int unsignedp;
 mode = TYPE_MODE (valtype);
 hfa_mode = hfa_element_mode (valtype, 0);
 if (hfa_mode != VOIDmode)
 	      offset += UNITS_PER_WORD;
 	    }
 	  return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
 	}
+mode = ia64_promote_function_mode (valtype, mode, &unsignedp,
+					 func ? TREE_TYPE (func) : NULL_TREE,
+					 true);
 return gen_rtx_REG (mode, GR_RET_FIRST);
 }
 }
 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
 D	Print an FP comparison operator.
 E    Print 32 - constant, for SImode shifts as extract.
 e    Print 64 - constant, for DImode rotates.
 F	A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
 a floating point register emitted normally.
+G	A floating point constant.
 I	Invert a predicate register by adding 1.
 J    Select the proper predicate register for a condition.
 j    Select the inverse predicate register for a condition.
 O	Append .acq for volatile load.
 P	Postincrement of a MEM.
 	  str = reg_names [REGNO (x)];
 	}
 fputs (str, file);
 return;
+case 'G':
+{
+	long val[4];
+	REAL_VALUE_TYPE rv;
+	REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+	real_to_target (val, &rv, GET_MODE (x));
+	if (GET_MODE (x) == SFmode)
+	  fprintf (file, "0x%08lx", val[0] & 0xffffffff);
+	else if (GET_MODE (x) == DFmode)
+	  fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
+					  & 0xffffffff,
+					 (WORDS_BIG_ENDIAN ? val[1] : val[0])
+					  & 0xffffffff);
+	else
+	  output_operand_lossage ("invalid %%G mode");
+}
+return;
 case 'I':
 fputs (reg_names [REGNO (x) + 1], file);
 return;
 case 'J':
 /* Implement TARGET_HANDLE_OPTION.  */
 static bool
 ia64_handle_option (size_t code, const char *arg, int value)
 {
-static bool warned_itanium1_deprecated;
 switch (code)
 {
 case OPT_mfixed_range_:
 fix_range (arg);
 return true;
 	    const char *name;		/* processor name or nickname.  */
 	    enum processor_type processor;
 	  }
 	const processor_alias_table[] =
 	  {
-	    {"itanium", PROCESSOR_ITANIUM},
-	    {"itanium1", PROCESSOR_ITANIUM},
-	    {"merced", PROCESSOR_ITANIUM},
 	    {"itanium2", PROCESSOR_ITANIUM2},
 	    {"mckinley", PROCESSOR_ITANIUM2},
 	  };
 	int const pta_size = ARRAY_SIZE (processor_alias_table);
 	int i;
 	for (i = 0; i < pta_size; i++)
 	  if (!strcmp (arg, processor_alias_table[i].name))
 	    {
 	      ia64_tune = processor_alias_table[i].processor;
-	      if (ia64_tune == PROCESSOR_ITANIUM
-		  && ! warned_itanium1_deprecated)
-		{
-		  inform (0,
-			  "value %<%s%> for -mtune= switch is deprecated",
-			  arg);
-		  inform (0, "GCC 4.4 is the last release with "
-			  "Itanium1 tuning support");
-		  warned_itanium1_deprecated = true;
-		}
 	      break;
 	    }
 	if (i == pta_size)
 	  error ("bad value %<%s%> for -mtune= switch", arg);
 	return true;
 ia64_override_options (void)
 {
 if (TARGET_AUTO_PIC)
 target_flags |= MASK_CONST_GP;
-if (TARGET_INLINE_SQRT == INL_MIN_LAT)
+/* Numerous experiment shows that IRA based loop pressure
-{
+calculation works better for RTL loop invariant motion on targets
-warning (0, "not yet implemented: latency-optimized inline square root");
+with enough (>= 32) registers.  It is an expensive optimization.
-TARGET_INLINE_SQRT = INL_MAX_THR;
+So it is on only for peak performance.  */
-}
+if (optimize >= 3)
+flag_ira_loop_pressure = 1;
-ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
-flag_schedule_insns_after_reload = 0;
-if (optimize >= 3
-&& ! sel_sched_switch_set)
-{
-flag_selective_scheduling2 = 1;
-flag_sel_sched_pipelining = 1;
-}
-if (mflag_sched_control_spec == 2)
-{
-/* Control speculation is on by default for the selective scheduler,
-but not for the Haifa scheduler.  */
-mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
-}
-if (flag_sel_sched_pipelining && flag_auto_inc_dec)
-{
-/* FIXME: remove this when we'd implement breaking autoinsns as
-a transformation.  */
-flag_auto_inc_dec = 0;
-}
 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
 init_machine_status = ia64_init_machine_status;
 if (align_functions <= 0)
 align_functions = 64;
 if (align_loops <= 0)
 align_loops = 32;
+if (TARGET_ABI_OPEN_VMS)
+flag_no_common = 1;
+ia64_override_options_after_change();
+}
+/* Implement targetm.override_options_after_change.  */
+static void
+ia64_override_options_after_change (void)
+{
+ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
+flag_schedule_insns_after_reload = 0;
+if (optimize >= 3
+&& ! sel_sched_switch_set)
+{
+flag_selective_scheduling2 = 1;
+flag_sel_sched_pipelining = 1;
+}
+if (mflag_sched_control_spec == 2)
+{
+/* Control speculation is on by default for the selective scheduler,
+but not for the Haifa scheduler.  */
+mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
+}
+if (flag_sel_sched_pipelining && flag_auto_inc_dec)
+{
+/* FIXME: remove this when we'd implement breaking autoinsns as
+a transformation.  */
+flag_auto_inc_dec = 0;
+}
 }
 /* Initialize the record of emitted frame related registers.  */
 void ia64_init_expanders (void)
 static enum attr_itanium_class
 ia64_safe_itanium_class (rtx insn)
 {
 if (recog_memoized (insn) >= 0)
 return get_attr_itanium_class (insn);
+else if (DEBUG_INSN_P (insn))
+return ITANIUM_CLASS_IGNORE;
 else
 return ITANIUM_CLASS_UNKNOWN;
 }
 static enum attr_type
 memset (&flags, 0, sizeof (flags));
 switch (GET_CODE (insn))
 {
 case NOTE:
+case DEBUG_INSN:
 break;
 case BARRIER:
 /* A barrier doesn't imply an instruction group boundary.  */
 break;
 	       && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
 	{
 	  init_insn_group_barriers ();
 	  last_label = 0;
 	}
-else if (INSN_P (insn))
+else if (NONDEBUG_INSN_P (insn))
 	{
 	  insns_since_last_label = 1;
 	  if (group_barrier_needed (insn))
 	    {
 	  if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
 	    emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
 	  init_insn_group_barriers ();
 	}
-else if (INSN_P (insn))
+else if (NONDEBUG_INSN_P (insn))
 	{
 	  if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
 	    init_insn_group_barriers ();
 	  else if (group_barrier_needed (insn))
 	    {
 /* The following variable value is length of the arrays `clocks' and
 `add_cycles'. */
 static int clocks_length;
-/* The following array element values are cycles on which the
-corresponding insn will be issued.  The array is used only for
-Itanium1.  */
-static int *clocks;
-/* The following array element values are numbers of cycles should be
-added to improve insn scheduling for MM_insns for Itanium1.  */
-static int *add_cycles;
 /* The following variable value is number of data speculations in progress.  */
 static int pending_data_specs = 0;
 /* Number of memory references on current and three future processor cycles.  */
 static int
 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
 		     int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
 		     int *pn_ready, int clock_var)
 {
-if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
-clocks [INSN_UID (last_scheduled_insn)] = clock_var;
 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
 				 clock_var, 1);
 }
 /* We are about to issue INSN.  Return the number of insns left on the
 if (DONE_SPEC (insn) & BEGIN_DATA)
 	pending_data_specs++;
 if (CHECK_SPEC (insn) & BEGIN_DATA)
 	pending_data_specs--;
 }
+if (DEBUG_INSN_P (insn))
+return 1;
 last_scheduled_insn = insn;
 memcpy (prev_cycle_state, curr_state, dfa_state_size);
 if (reload_completed)
 {
 		    int clock, int *sort_p)
 {
 int setup_clocks_p = FALSE;
 gcc_assert (insn && INSN_P (insn));
+if (DEBUG_INSN_P (insn))
+return 0;
 /* When a group barrier is needed for insn, last_scheduled_insn
 should be set.  */
 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
 || last_scheduled_insn);
 	}
 }
 else if (reload_completed)
 setup_clocks_p = TRUE;
-if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
-&& GET_CODE (PATTERN (insn)) != ASM_INPUT
-&& asm_noperands (PATTERN (insn)) < 0)
-{
-enum attr_itanium_class c = ia64_safe_itanium_class (insn);
-if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
-	{
-	  sd_iterator_def sd_it;
-	  dep_t dep;
-	  int d = -1;
-	  FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
-	    if (DEP_TYPE (dep) == REG_DEP_TRUE)
-	      {
-		enum attr_itanium_class dep_class;
-		rtx dep_insn = DEP_PRO (dep);
-		dep_class = ia64_safe_itanium_class (dep_insn);
-		if ((dep_class == ITANIUM_CLASS_MMMUL
-		     || dep_class == ITANIUM_CLASS_MMSHF)
-		    && last_clock - clocks [INSN_UID (dep_insn)] < 4
-		    && (d < 0
-			|| last_clock - clocks [INSN_UID (dep_insn)] < d))
-		  d = last_clock - clocks [INSN_UID (dep_insn)];
-	      }
-	  if (d >= 0)
-	    add_cycles [INSN_UID (insn)] = 3 - d;
-	}
-}
 return 0;
 }
 /* Implement targetm.sched.h_i_d_extended hook.
 Extend internal data structures.  */
 ia64_h_i_d_extended (void)
 {
 if (stops_p != NULL)
 {
 int new_clocks_length = get_max_uid () * 3 / 2;
 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
-if (ia64_tune == PROCESSOR_ITANIUM)
-	{
-	  clocks = (int *) xrecalloc (clocks, new_clocks_length, clocks_length,
-				      sizeof (int));
-	  add_cycles = (int *) xrecalloc (add_cycles, new_clocks_length,
-					  clocks_length, sizeof (int));
-	}
 clocks_length = new_clocks_length;
 }
 }
 static int
 insert_bundle_state (struct bundle_state *bundle_state)
 {
 void **entry_ptr;
-entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
+entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT);
 if (*entry_ptr == NULL)
 {
 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
 *entry_ptr = (void *) bundle_state;
 	      gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
 			  || code == CODE_FOR_nop_b);
 	      if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
 		note = NULL_RTX;
 	      else
-		REG_NOTES (insn)
+		add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
-		  = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0),
-				       REG_NOTES (insn));
 	    }
 	}
 }
 #endif
 }
 best sequence and then, moving back in EBB, insert templates for
 the best alternative.  The templates are taken from querying
 automaton state for each insn in chosen bundle states.
 So the algorithm makes two (forward and backward) passes through
-EBB.  There is an additional forward pass through EBB for Itanium1
+EBB.  */
-processor.  This pass inserts more nops to make dependency between
-a producer insn and MMMUL/MMSHF at least 4 cycles long.  */
 static void
 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
 {
 struct bundle_state *curr_state, *next_state, *best_state;
 	  bundle_end_p
 	    = (only_bundle_end_p || next_insn == NULL_RTX
 	       || (GET_MODE (next_insn) == TImode
 		   && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
 	  if (type == TYPE_F || type == TYPE_B || type == TYPE_L
-	      || type == TYPE_S
+	      || type == TYPE_S)
-	      /* We need to insert 2 nops for cases like M_MII.  To
-		 guarantee issuing all insns on the same cycle for
-		 Itanium 1, we need to issue 2 nops after the first M
-		 insn (MnnMII where n is a nop insn).  */
-	      || ((type == TYPE_M || type == TYPE_A)
-		  && ia64_tune == PROCESSOR_ITANIUM
-		  && !bundle_end_p && pos == 1))
 	    issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
 				 only_bundle_end_p);
 	  issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
 			       only_bundle_end_p);
 	  issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
 		? -1 : curr_state->originator->unique_num),
 	       curr_state->cost,
 	       curr_state->before_nops_num, curr_state->after_nops_num,
 	       curr_state->accumulated_insns_num, curr_state->branch_deviation,
 	       curr_state->middle_bundle_stops,
-	       (ia64_tune == PROCESSOR_ITANIUM
+	       ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
-		? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
-		: ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
 	       INSN_UID (insn));
 	  }
 }
 /* We should find a solution because the 2nd insn scheduling has
 	      ? -1 : curr_state->originator->unique_num),
 	     curr_state->cost,
 	     curr_state->before_nops_num, curr_state->after_nops_num,
 	     curr_state->accumulated_insns_num, curr_state->branch_deviation,
 	     curr_state->middle_bundle_stops,
-	     (ia64_tune == PROCESSOR_ITANIUM
+	     ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
-	      ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
-	      : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
 	     INSN_UID (insn));
 	}
 /* Find the position in the current bundle window.  The window can
 	 contain at most two bundles.  Two bundle window means that
 	 the processor will make two bundle rotation.  */
 	      template0 = template1;
 	      template1 = -1;
 	    }
 	}
 }
-if (ia64_tune == PROCESSOR_ITANIUM)
-/* Insert additional cycles for MM-insns (MMMUL and MMSHF).
-Itanium1 has a strange design, if the distance between an insn
-and dependent MM-insn is less 4 then we have a 6 additional
-cycles stall.  So we make the distance equal to 4 cycles if it
-is less.  */
-for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
-	 insn != NULL_RTX;
-	 insn = next_insn)
-{
-	gcc_assert (INSN_P (insn)
-		    && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
-		    && GET_CODE (PATTERN (insn)) != USE
-		    && GET_CODE (PATTERN (insn)) != CLOBBER);
-	next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
-	if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
-	  /* We found a MM-insn which needs additional cycles.  */
-	  {
-	    rtx last;
-	    int i, j, n;
-	    int pred_stop_p;
-	    /* Now we are searching for a template of the bundle in
-	       which the MM-insn is placed and the position of the
-	       insn in the bundle (0, 1, 2).  Also we are searching
-	       for that there is a stop before the insn.  */
-	    last = prev_active_insn (insn);
-	    pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
-	    if (pred_stop_p)
-	      last = prev_active_insn (last);
-	    n = 0;
-	    for (;; last = prev_active_insn (last))
-	      if (recog_memoized (last) == CODE_FOR_bundle_selector)
-		{
-		  template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
-		  if (template0 == 9)
-		    /* The insn is in MLX bundle.  Change the template
-		       onto MFI because we will add nops before the
-		       insn.  It simplifies subsequent code a lot.  */
-		    PATTERN (last)
-		      = gen_bundle_selector (const2_rtx); /* -> MFI */
-		  break;
-		}
-	      else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
-		       && (ia64_safe_itanium_class (last)
-			   != ITANIUM_CLASS_IGNORE))
-		n++;
-	    /* Some check of correctness: the stop is not at the
-	       bundle start, there are no more 3 insns in the bundle,
-	       and the MM-insn is not at the start of bundle with
-	       template MLX.  */
-	    gcc_assert ((!pred_stop_p || n)
-			&& n <= 2
-			&& (template0 != 9 || !n));
-	    /* Put nops after the insn in the bundle.  */
-	    for (j = 3 - n; j > 0; j --)
-	      ia64_emit_insn_before (gen_nop (), insn);
-	    /* It takes into account that we will add more N nops
-	       before the insn lately -- please see code below.  */
-	    add_cycles [INSN_UID (insn)]--;
-	    if (!pred_stop_p || add_cycles [INSN_UID (insn)])
-	      ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
-				     insn);
-	    if (pred_stop_p)
-	      add_cycles [INSN_UID (insn)]--;
-	    for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
-	      {
-		/* Insert "MII;" template.  */
-		ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
-				       insn);
-		ia64_emit_insn_before (gen_nop (), insn);
-		ia64_emit_insn_before (gen_nop (), insn);
-		if (i > 1)
-		  {
-		    /* To decrease code size, we use "MI;I;"
-		       template.  */
-		    ia64_emit_insn_before
-		      (gen_insn_group_barrier (GEN_INT (3)), insn);
-		    i--;
-		  }
-		ia64_emit_insn_before (gen_nop (), insn);
-		ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
-				       insn);
-	      }
-	    /* Put the MM-insn in the same slot of a bundle with the
-	       same template as the original one.  */
-	    ia64_add_bundle_selector_before (template0, insn);
-	    /* To put the insn in the same slot, add necessary number
-	       of nops.  */
-	    for (j = n; j > 0; j --)
-	      ia64_emit_insn_before (gen_nop (), insn);
-	    /* Put the stop if the original bundle had it.  */
-	    if (pred_stop_p)
-	      ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
-				     insn);
-	  }
-}
 #ifdef ENABLE_CHECKING
 {
 /* Assert right calculation of middle_bundle_stops.  */
 int num = best_state->middle_bundle_stops;
 	  init_insn_group_barriers ();
 	  seen_good_insn = 0;
 	  need_barrier_p = 0;
 	  prev_insn = NULL_RTX;
 	}
-else if (INSN_P (insn))
+else if (NONDEBUG_INSN_P (insn))
 	{
 	  if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
 	    {
 	      init_insn_group_barriers ();
 	      seen_good_insn = 0;
 ia64_nop = make_insn_raw (gen_nop ());
 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
 recog_memoized (ia64_nop);
 clocks_length = get_max_uid () + 1;
 stops_p = XCNEWVEC (char, clocks_length);
-if (ia64_tune == PROCESSOR_ITANIUM)
-	{
-	  clocks = XCNEWVEC (int, clocks_length);
-	  add_cycles = XCNEWVEC (int, clocks_length);
-	}
 if (ia64_tune == PROCESSOR_ITANIUM2)
 	{
 	  pos_1 = get_cpu_unit_code ("2_1");
 	  pos_2 = get_cpu_unit_code ("2_2");
 	  pos_3 = get_cpu_unit_code ("2_3");
 compute_alignments ();
 /* We cannot reuse this one because it has been corrupted by the
 	 evil glat.  */
 finish_bundle_states ();
-if (ia64_tune == PROCESSOR_ITANIUM)
-	{
-	  free (add_cycles);
-	  free (clocks);
-	}
 free (stops_p);
 stops_p = NULL;
 emit_insn_group_barriers (dump_file);
 ia64_final_schedule = 0;
 int saw_stop = 0;
 insn = get_last_insn ();
 if (! INSN_P (insn))
 insn = prev_active_insn (insn);
-/* Skip over insns that expand to nothing.  */
+if (insn)
-while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
+	{
-{
+	  /* Skip over insns that expand to nothing.  */
-	  if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
+	  while (GET_CODE (insn) == INSN
-	      && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
+		 && get_attr_empty (insn) == EMPTY_YES)
-	    saw_stop = 1;
+	    {
-	  insn = prev_active_insn (insn);
+	      if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
-	}
+		  && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
-if (GET_CODE (insn) == CALL_INSN)
+		saw_stop = 1;
-	{
+	      insn = prev_active_insn (insn);
-	  if (! saw_stop)
+	    }
-	    emit_insn (gen_insn_group_barrier (GEN_INT (3)));
+	  if (GET_CODE (insn) == CALL_INSN)
-	  emit_insn (gen_break_f ());
+	    {
-	  emit_insn (gen_insn_group_barrier (GEN_INT (3)));
+	      if (! saw_stop)
+		emit_insn (gen_insn_group_barrier (GEN_INT (3)));
+	      emit_insn (gen_break_f ());
+	      emit_insn (gen_insn_group_barrier (GEN_INT (3)));
+	    }
 	}
 }
 emit_predicate_relation_info ();
 /* Return true if REGNO is used by the frame unwinder.  */
 int
 ia64_eh_uses (int regno)
 {
-enum ia64_frame_regs r;
+unsigned int r;
 if (! reload_completed)
 return 0;
 if (regno == 0)
 }
 /* Define the CFA after INSN with the steady-state definition.  */
 static void
-ia64_dwarf2out_def_steady_cfa (rtx insn)
+ia64_dwarf2out_def_steady_cfa (rtx insn, bool frame)
 {
 rtx fp = frame_pointer_needed
 ? hard_frame_pointer_rtx
 : stack_pointer_rtx;
+const char *label = ia64_emit_deleted_label_after_insn (insn);
+if (!frame)
+return;
 dwarf2out_def_cfa
-(ia64_emit_deleted_label_after_insn (insn),
+(label, REGNO (fp),
-REGNO (fp),
 ia64_initial_elimination_offset
 (REGNO (arg_pointer_rtx), REGNO (fp))
 + ARG_POINTER_CFA_OFFSET (current_function_decl));
 }
 	    {
 	      gcc_assert (!frame_pointer_needed);
 	      if (unwind)
 		fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
 			 -INTVAL (op1));
-	      if (frame)
+	      ia64_dwarf2out_def_steady_cfa (insn, frame);
-		ia64_dwarf2out_def_steady_cfa (insn);
 	    }
 	  else
 	    process_epilogue (asm_out_file, insn, unwind, frame);
 	}
 else
 	  gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
 		      && frame_pointer_needed);
 	  if (unwind)
 	    fprintf (asm_out_file, "\t.vframe r%d\n",
 		     ia64_dbx_register_number (dest_regno));
-	  if (frame)
+	  ia64_dwarf2out_def_steady_cfa (insn, frame);
-	    ia64_dwarf2out_def_steady_cfa (insn);
 	  return 1;
 	default:
 	  /* Everything else should indicate being stored to memory.  */
 	  gcc_unreachable ();
 		{
 		  fprintf (asm_out_file, "\t.body\n");
 		  fprintf (asm_out_file, "\t.copy_state %d\n",
 			   cfun->machine->state_num);
 		}
-	      if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
+	      if (IA64_CHANGE_CFA_IN_EPILOGUE)
-		ia64_dwarf2out_def_steady_cfa (insn);
+		ia64_dwarf2out_def_steady_cfa (insn, frame);
 	      need_copy_state = false;
 	    }
 	}
 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
 {
 IA64_BUILTIN_BSP,
 IA64_BUILTIN_COPYSIGNQ,
 IA64_BUILTIN_FABSQ,
 IA64_BUILTIN_FLUSHRS,
-IA64_BUILTIN_INFQ
+IA64_BUILTIN_INFQ,
+IA64_BUILTIN_HUGE_VALQ
 };
 void
 ia64_init_builtins (void)
 {
 /* TFmode support builtins.  */
 ftype = build_function_type (float128_type, void_list_node);
 add_builtin_function ("__builtin_infq", ftype,
 			    IA64_BUILTIN_INFQ, BUILT_IN_MD,
+			    NULL, NULL_TREE);
+add_builtin_function ("__builtin_huge_valq", ftype,
+			    IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
 			    NULL, NULL_TREE);
 ftype = build_function_type_list (float128_type,
 					float128_type,
 					NULL_TREE);
 }
 else
 /* Under HPUX, this is a synonym for "long double".  */
 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
 					       "__float128");
+/* Fwrite on VMS is non-standard.  */
+if (TARGET_ABI_OPEN_VMS)
+{
+implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
+implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
+}
 #define def_builtin(name, type, code)					\
 add_builtin_function ((name), (type), (code), BUILT_IN_MD,	\
 		       NULL, NULL_TREE)
 case IA64_BUILTIN_FLUSHRS:
 emit_insn (gen_flushrs ());
 return const0_rtx;
 case IA64_BUILTIN_INFQ:
+case IA64_BUILTIN_HUGE_VALQ:
 {
 	REAL_VALUE_TYPE inf;
 	rtx tmp;
 	real_inf (&inf);
 {
 /* maybe_assemble_visibility will return 1 if the assembler
 	 visibility directive is output.  */
 int need_visibility = ((*targetm.binds_local_p) (decl)
 			     && maybe_assemble_visibility (decl));
+#ifdef DO_CRTL_NAMES
+DO_CRTL_NAMES;
+#endif
 /* GNU as does not need anything here, but the HP linker does
 	 need something for external functions.  */
 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
 	  && TREE_CODE (decl) == FUNCTION_DECL)
 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
+abort_libfunc = init_one_libfunc ("decc$abort");
+memcmp_libfunc = init_one_libfunc ("decc$memcmp");
+#ifdef MEM_LIBFUNCS_INIT
+MEM_LIBFUNCS_INIT;
+#endif
 }
 /* Rename the TFmode libfuncs available from soft-fp in glibc using
 the HPUX conventions.  */
 static void
 ia64_soft_fp_init_libfuncs (void)
 {
 }
+static bool
+ia64_vms_valid_pointer_mode (enum machine_mode mode)
+{
+return (mode == SImode || mode == DImode);
+}
 /* For HPUX, it is illegal to have relocations in shared segments.  */
 static int
 ia64_hpux_reloc_rw_mask (void)
 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
 || strcmp (name, ".sbss") == 0
 || strncmp (name, ".sbss.", 6) == 0
 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
 flags = SECTION_SMALL;
+#if TARGET_ABI_OPEN_VMS
+if (decl && DECL_ATTRIBUTES (decl)
+&& lookup_attribute ("common_object", DECL_ATTRIBUTES (decl)))
+flags |= SECTION_VMS_OVERLAY;
+#endif
 flags |= default_section_type_flags (decl, name, reloc);
 return flags;
 }
 insn = get_insns ();
 shorten_branches (insn);
 final_start_function (insn, file, 1);
 final (insn, file, 1);
 final_end_function ();
-free_after_compilation (cfun);
 reload_completed = 0;
 epilogue_completed = 0;
 }
 static rtx
 ia64_struct_value_rtx (tree fntype,
 		       int incoming ATTRIBUTE_UNUSED)
 {
-if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
+if (TARGET_ABI_OPEN_VMS ||
+(fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
 return NULL_RTX;
 return gen_rtx_REG (Pmode, GR_REG (8));
 }
 static bool
 return XFmode;
 return VOIDmode;
 }
+static enum machine_mode
+ia64_promote_function_mode (const_tree type,
+			    enum machine_mode mode,
+			    int *punsignedp,
+			    const_tree funtype,
+			    int for_return)
+{
+/* Special processing required for OpenVMS ...  */
+if (!TARGET_ABI_OPEN_VMS)
+return default_promote_function_mode(type, mode, punsignedp, funtype,
+					 for_return);
+/* HP OpenVMS Calling Standard dated June, 2004, that describes
+HP OpenVMS I64 Version 8.2EFT,
+chapter 4 "OpenVMS I64 Conventions"
+section 4.7 "Procedure Linkage"
+subsection 4.7.5.2, "Normal Register Parameters"
+"Unsigned integral (except unsigned 32-bit), set, and VAX floating-point
+values passed in registers are zero-filled; signed integral values as
+well as unsigned 32-bit integral values are sign-extended to 64 bits.
+For all other types passed in the general registers, unused bits are
+undefined."  */
+if (!AGGREGATE_TYPE_P (type)
+&& GET_MODE_CLASS (mode) == MODE_INT
+&& GET_MODE_SIZE (mode) < UNITS_PER_WORD)
+{
+if (mode == SImode)
+	*punsignedp = 0;
+return DImode;
+}
+else
+return promote_mode (type, mode, punsignedp);
+}
+static GTY(()) rtx ia64_dconst_0_5_rtx;
+rtx
+ia64_dconst_0_5 (void)
+{
+if (! ia64_dconst_0_5_rtx)
+{
+REAL_VALUE_TYPE rv;
+real_from_string (&rv, "0.5");
+ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
+}
+return ia64_dconst_0_5_rtx;
+}
+static GTY(()) rtx ia64_dconst_0_375_rtx;
+rtx
+ia64_dconst_0_375 (void)
+{
+if (! ia64_dconst_0_375_rtx)
+{
+REAL_VALUE_TYPE rv;
+real_from_string (&rv, "0.375");
+ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
+}
+return ia64_dconst_0_375_rtx;
+}
 #include "gt-ia64.h"

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/ia64/ia64.c @ 55:77e2b8dfacca gcc-4.4.5