Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/m32r/m32r.md @ 55:77e2b8dfacca gcc-4.4.5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Machine description of the Renesas M32R cpu for GNU C compiler 1 ;; Machine description of the Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005, 2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005,
3 ; 2007, 2008 Free Software Foundation, Inc. 3 ; 2007, 2008, 2009 Free Software Foundation, Inc.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published 8 ;; under the terms of the GNU General Public License as published
248 } 248 }
249 249
250 /* Everything except mem = const or mem = mem can be done easily. 250 /* Everything except mem = const or mem = mem can be done easily.
251 Objects in the small data area are handled too. */ 251 Objects in the small data area are handled too. */
252 252
253 if (GET_CODE (operands[0]) == MEM) 253 if (MEM_P (operands[0]))
254 operands[1] = force_reg (QImode, operands[1]); 254 operands[1] = force_reg (QImode, operands[1]);
255 }") 255 }")
256 256
257 (define_insn "*movqi_insn" 257 (define_insn "*movqi_insn"
258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m") 258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
287 } 287 }
288 } 288 }
289 289
290 /* Everything except mem = const or mem = mem can be done easily. */ 290 /* Everything except mem = const or mem = mem can be done easily. */
291 291
292 if (GET_CODE (operands[0]) == MEM) 292 if (MEM_P (operands[0]))
293 operands[1] = force_reg (HImode, operands[1]); 293 operands[1] = force_reg (HImode, operands[1]);
294 }") 294 }")
295 295
296 (define_insn "*movhi_insn" 296 (define_insn "*movhi_insn"
297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m") 297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
339 } 339 }
340 } 340 }
341 341
342 /* Everything except mem = const or mem = mem can be done easily. */ 342 /* Everything except mem = const or mem = mem can be done easily. */
343 343
344 if (GET_CODE (operands[0]) == MEM) 344 if (MEM_P (operands[0]))
345 operands[1] = force_reg (SImode, operands[1]); 345 operands[1] = force_reg (SImode, operands[1]);
346 346
347 /* Small Data Area reference? */ 347 /* Small Data Area reference? */
348 if (small_data_operand (operands[1], SImode)) 348 if (small_data_operand (operands[1], SImode))
349 { 349 {
365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m") 365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))] 366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" 367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
368 "* 368 "*
369 { 369 {
370 if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG) 370 if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
371 { 371 {
372 switch (GET_CODE (operands[1])) 372 switch (GET_CODE (operands[1]))
373 { 373 {
374 HOST_WIDE_INT value;
375
376 default: 374 default:
377 break; 375 break;
378 376
379 case REG: 377 case REG:
380 case SUBREG: 378 case SUBREG:
407 405
408 return \"#\"; 406 return \"#\";
409 } 407 }
410 } 408 }
411 409
412 else if (GET_CODE (operands[0]) == MEM 410 else if (MEM_P (operands[0])
413 && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)) 411 && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
414 { 412 {
415 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 413 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
416 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) 414 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
417 return \"push %1\"; 415 return \"push %1\";
418 416
583 } 581 }
584 } 582 }
585 583
586 /* Everything except mem = const or mem = mem can be done easily. */ 584 /* Everything except mem = const or mem = mem can be done easily. */
587 585
588 if (GET_CODE (operands[0]) == MEM) 586 if (MEM_P (operands[0]))
589 operands[1] = force_reg (DImode, operands[1]); 587 operands[1] = force_reg (DImode, operands[1]);
590 }") 588 }")
591 589
592 (define_insn "*movdi_insn" 590 (define_insn "*movdi_insn"
593 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m") 591 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
624 } 622 }
625 } 623 }
626 624
627 /* Everything except mem = const or mem = mem can be done easily. */ 625 /* Everything except mem = const or mem = mem can be done easily. */
628 626
629 if (GET_CODE (operands[0]) == MEM) 627 if (MEM_P (operands[0]))
630 operands[1] = force_reg (SFmode, operands[1]); 628 operands[1] = force_reg (SFmode, operands[1]);
631 }") 629 }")
632 630
633 (define_insn "*movsf_insn" 631 (define_insn "*movsf_insn"
634 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m") 632 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
676 } 674 }
677 } 675 }
678 676
679 /* Everything except mem = const or mem = mem can be done easily. */ 677 /* Everything except mem = const or mem = mem can be done easily. */
680 678
681 if (GET_CODE (operands[0]) == MEM) 679 if (MEM_P (operands[0]))
682 operands[1] = force_reg (DFmode, operands[1]); 680 operands[1] = force_reg (DFmode, operands[1]);
683 }") 681 }")
684 682
685 (define_insn "*movdf_insn" 683 (define_insn "*movdf_insn"
686 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m") 684 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
1034 if (optimize_size 1032 if (optimize_size
1035 && m32r_not_same_reg (operands[0], operands[1]) 1033 && m32r_not_same_reg (operands[0], operands[1])
1036 && satisfies_constraint_I (operands[2])) 1034 && satisfies_constraint_I (operands[2]))
1037 return \"#\"; 1035 return \"#\";
1038 1036
1039 else if (GET_CODE (operands[2]) == CONST_INT) 1037 else if (CONST_INT_P (operands[2]))
1040 return \"and3 %0,%1,%#%X2\"; 1038 return \"and3 %0,%1,%#%X2\";
1041 1039
1042 return \"and %0,%2\"; 1040 return \"and %0,%2\";
1043 }" 1041 }"
1044 [(set_attr "type" "int2,int4") 1042 [(set_attr "type" "int2,int4")
1065 if (optimize_size 1063 if (optimize_size
1066 && m32r_not_same_reg (operands[0], operands[1]) 1064 && m32r_not_same_reg (operands[0], operands[1])
1067 && satisfies_constraint_I (operands[2])) 1065 && satisfies_constraint_I (operands[2]))
1068 return \"#\"; 1066 return \"#\";
1069 1067
1070 else if (GET_CODE (operands[2]) == CONST_INT) 1068 else if (CONST_INT_P (operands[2]))
1071 return \"or3 %0,%1,%#%X2\"; 1069 return \"or3 %0,%1,%#%X2\";
1072 1070
1073 return \"or %0,%2\"; 1071 return \"or %0,%2\";
1074 }" 1072 }"
1075 [(set_attr "type" "int2,int4") 1073 [(set_attr "type" "int2,int4")
1096 if (optimize_size 1094 if (optimize_size
1097 && m32r_not_same_reg (operands[0], operands[1]) 1095 && m32r_not_same_reg (operands[0], operands[1])
1098 && satisfies_constraint_I (operands[2])) 1096 && satisfies_constraint_I (operands[2]))
1099 return \"#\"; 1097 return \"#\";
1100 1098
1101 else if (GET_CODE (operands[2]) == CONST_INT) 1099 else if (CONST_INT_P (operands[2]))
1102 return \"xor3 %0,%1,%#%X2\"; 1100 return \"xor3 %0,%1,%#%X2\";
1103 1101
1104 return \"xor %0,%2\"; 1102 return \"xor %0,%2\";
1105 }" 1103 }"
1106 [(set_attr "type" "int2,int4") 1104 [(set_attr "type" "int2,int4")
1177 ;; emit RTL for both the compare and the branch. 1175 ;; emit RTL for both the compare and the branch.
1178 ;; 1176 ;;
1179 ;; On the m32r it is more efficient to use the bxxz instructions and 1177 ;; On the m32r it is more efficient to use the bxxz instructions and
1180 ;; thus merge the compare and branch into one instruction, so they are 1178 ;; thus merge the compare and branch into one instruction, so they are
1181 ;; preferred. 1179 ;; preferred.
1182
1183 (define_expand "cmpsi"
1184 [(set (reg:CC 17)
1185 (compare:CC (match_operand:SI 0 "register_operand" "")
1186 (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
1187 ""
1188 "
1189 {
1190 m32r_compare_op0 = operands[0];
1191 m32r_compare_op1 = operands[1];
1192 DONE;
1193 }")
1194 1180
1195 (define_insn "cmp_eqsi_zero_insn" 1181 (define_insn "cmp_eqsi_zero_insn"
1196 [(set (reg:CC 17) 1182 [(set (reg:CC 17)
1197 (eq:CC (match_operand:SI 0 "register_operand" "r,r") 1183 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1198 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))] 1184 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
1254 [(set_attr "type" "int2,int4") 1240 [(set_attr "type" "int2,int4")
1255 (set_attr "length" "2,4")]) 1241 (set_attr "length" "2,4")])
1256 1242
1257 ;; These control RTL generation for conditional jump insns. 1243 ;; These control RTL generation for conditional jump insns.
1258 1244
1259 (define_expand "beq" 1245 (define_expand "cbranchsi4"
1246 ; the comparison is emitted by gen_compare if needed.
1260 [(set (pc) 1247 [(set (pc)
1261 (if_then_else (match_dup 1) 1248 (if_then_else (match_operator 0 "ordered_comparison_operator"
1262 (label_ref (match_operand 0 "" "")) 1249 [(match_operand:SI 1 "register_operand" "")
1250 (match_operand:SI 2 "reg_or_cmp_int16_operand" "")])
1251 (label_ref (match_operand 3 "" ""))
1263 (pc)))] 1252 (pc)))]
1264 "" 1253 ""
1265 " 1254 "
1266 { 1255 {
1267 operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE); 1256 operands[0] = gen_compare (GET_CODE (operands[0]), operands[1], operands[2], FALSE);
1268 }") 1257 operands[1] = XEXP (operands[0], 0);
1269 1258 operands[2] = XEXP (operands[0], 1);
1270 (define_expand "bne"
1271 [(set (pc)
1272 (if_then_else (match_dup 1)
1273 (label_ref (match_operand 0 "" ""))
1274 (pc)))]
1275 ""
1276 "
1277 {
1278 operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
1279 }")
1280
1281 (define_expand "bgt"
1282 [(set (pc)
1283 (if_then_else (match_dup 1)
1284 (label_ref (match_operand 0 "" ""))
1285 (pc)))]
1286 ""
1287 "
1288 {
1289 operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
1290 }")
1291
1292 (define_expand "ble"
1293 [(set (pc)
1294 (if_then_else (match_dup 1)
1295 (label_ref (match_operand 0 "" ""))
1296 (pc)))]
1297 ""
1298 "
1299 {
1300 operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
1301 }")
1302
1303 (define_expand "bge"
1304 [(set (pc)
1305 (if_then_else (match_dup 1)
1306 (label_ref (match_operand 0 "" ""))
1307 (pc)))]
1308 ""
1309 "
1310 {
1311 operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
1312 }")
1313
1314 (define_expand "blt"
1315 [(set (pc)
1316 (if_then_else (match_dup 1)
1317 (label_ref (match_operand 0 "" ""))
1318 (pc)))]
1319 ""
1320 "
1321 {
1322 operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
1323 }")
1324
1325 (define_expand "bgtu"
1326 [(set (pc)
1327 (if_then_else (match_dup 1)
1328 (label_ref (match_operand 0 "" ""))
1329 (pc)))]
1330 ""
1331 "
1332 {
1333 operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1334 }")
1335
1336 (define_expand "bleu"
1337 [(set (pc)
1338 (if_then_else (match_dup 1)
1339 (label_ref (match_operand 0 "" ""))
1340 (pc)))]
1341 ""
1342 "
1343 {
1344 operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1345 }")
1346
1347 (define_expand "bgeu"
1348 [(set (pc)
1349 (if_then_else (match_dup 1)
1350 (label_ref (match_operand 0 "" ""))
1351 (pc)))]
1352 ""
1353 "
1354 {
1355 operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1356 }")
1357
1358 (define_expand "bltu"
1359 [(set (pc)
1360 (if_then_else (match_dup 1)
1361 (label_ref (match_operand 0 "" ""))
1362 (pc)))]
1363 ""
1364 "
1365 {
1366 operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1367 }") 1259 }")
1368 1260
1369 ;; Now match both normal and inverted jump. 1261 ;; Now match both normal and inverted jump.
1370 1262
1371 (define_insn "*branch_insn" 1263 (define_insn "*branch_insn"
1595 (const_int 4) 1487 (const_int 4)
1596 (const_int 8)))]) 1488 (const_int 8)))])
1597 1489
1598 ;; S<cc> operations to set a register to 1/0 based on a comparison 1490 ;; S<cc> operations to set a register to 1/0 based on a comparison
1599 1491
1600 (define_expand "seq" 1492 (define_expand "cstoresi4"
1601 [(match_operand:SI 0 "register_operand" "")] 1493 [(match_operand:SI 0 "register_operand" "")
1602 "" 1494 (match_operator:SI 1 "ordered_comparison_operator"
1603 " 1495 [(match_operand:SI 2 "register_operand" "")
1604 { 1496 (match_operand:SI 3 "reg_or_cmp_int16_operand" "")])]
1605 rtx op0 = operands[0]; 1497 ""
1606 rtx op1 = m32r_compare_op0; 1498 "
1607 rtx op2 = m32r_compare_op1; 1499 {
1608 enum machine_mode mode = GET_MODE (op0); 1500 if (GET_MODE (operands[0]) != SImode)
1609
1610 if (mode != SImode)
1611 FAIL; 1501 FAIL;
1612 1502
1613 if (! register_operand (op1, mode)) 1503 if (!gen_cond_store (GET_CODE (operands[1]),
1614 op1 = force_reg (mode, op1); 1504 operands[0], operands[2], operands[3]))
1615 1505 FAIL;
1616 if (TARGET_M32RX || TARGET_M32R2) 1506
1617 {
1618 if (! reg_or_zero_operand (op2, mode))
1619 op2 = force_reg (mode, op2);
1620
1621 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
1622 DONE;
1623 }
1624 if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
1625 {
1626 emit_insn (gen_seq_zero_insn (op0, op1));
1627 DONE;
1628 }
1629
1630 if (! reg_or_eq_int16_operand (op2, mode))
1631 op2 = force_reg (mode, op2);
1632
1633 emit_insn (gen_seq_insn (op0, op1, op2));
1634 DONE; 1507 DONE;
1635 }") 1508 }")
1636 1509
1637 (define_insn "seq_insn_m32rx" 1510 (define_insn "seq_insn_m32rx"
1638 [(set (match_operand:SI 0 "register_operand" "=r") 1511 [(set (match_operand:SI 0 "register_operand" "=r")
1711 rtx op1 = operands[1]; 1584 rtx op1 = operands[1];
1712 rtx op2 = operands[2]; 1585 rtx op2 = operands[2];
1713 rtx op3 = operands[3]; 1586 rtx op3 = operands[3];
1714 HOST_WIDE_INT value; 1587 HOST_WIDE_INT value;
1715 1588
1716 if (GET_CODE (op2) == REG && GET_CODE (op3) == REG 1589 if (REG_P (op2) && REG_P (op3)
1717 && REGNO (op2) == REGNO (op3)) 1590 && REGNO (op2) == REGNO (op3))
1718 { 1591 {
1719 op1 = operands[2]; 1592 op1 = operands[2];
1720 op2 = operands[1]; 1593 op2 = operands[1];
1721 } 1594 }
1722 1595
1723 start_sequence (); 1596 start_sequence ();
1724 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG 1597 if (REG_P (op1) && REG_P (op3)
1725 && REGNO (op1) != REGNO (op3)) 1598 && REGNO (op1) != REGNO (op3))
1726 { 1599 {
1727 emit_move_insn (op3, op1); 1600 emit_move_insn (op3, op1);
1728 op1 = op3; 1601 op1 = op3;
1729 } 1602 }
1735 1608
1736 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx)); 1609 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
1737 emit_insn (gen_movcc_insn (op0)); 1610 emit_insn (gen_movcc_insn (op0));
1738 operands[4] = get_insns (); 1611 operands[4] = get_insns ();
1739 end_sequence (); 1612 end_sequence ();
1740 }")
1741
1742 (define_expand "sne"
1743 [(match_operand:SI 0 "register_operand" "")]
1744 ""
1745 "
1746 {
1747 rtx op0 = operands[0];
1748 rtx op1 = m32r_compare_op0;
1749 rtx op2 = m32r_compare_op1;
1750 enum machine_mode mode = GET_MODE (op0);
1751
1752 if (mode != SImode)
1753 FAIL;
1754
1755 if (GET_CODE (op2) != CONST_INT
1756 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
1757 {
1758 rtx reg;
1759
1760 if (reload_completed || reload_in_progress)
1761 FAIL;
1762
1763 reg = gen_reg_rtx (SImode);
1764 emit_insn (gen_xorsi3 (reg, op1, op2));
1765 op1 = reg;
1766
1767 if (! register_operand (op1, mode))
1768 op1 = force_reg (mode, op1);
1769
1770 emit_insn (gen_sne_zero_insn (op0, op1));
1771 DONE;
1772 }
1773 else
1774 FAIL;
1775 }") 1613 }")
1776 1614
1777 (define_insn "sne_zero_insn" 1615 (define_insn "sne_zero_insn"
1778 [(set (match_operand:SI 0 "register_operand" "=r") 1616 [(set (match_operand:SI 0 "register_operand" "=r")
1779 (ne:SI (match_operand:SI 1 "register_operand" "r") 1617 (ne:SI (match_operand:SI 1 "register_operand" "r")
1799 (match_dup 1))) 1637 (match_dup 1)))
1800 (set (match_dup 0) 1638 (set (match_dup 0)
1801 (ne:SI (reg:CC 17) (const_int 0)))] 1639 (ne:SI (reg:CC 17) (const_int 0)))]
1802 "") 1640 "")
1803 1641
1804 (define_expand "slt"
1805 [(match_operand:SI 0 "register_operand" "")]
1806 ""
1807 "
1808 {
1809 rtx op0 = operands[0];
1810 rtx op1 = m32r_compare_op0;
1811 rtx op2 = m32r_compare_op1;
1812 enum machine_mode mode = GET_MODE (op0);
1813
1814 if (mode != SImode)
1815 FAIL;
1816
1817 if (! register_operand (op1, mode))
1818 op1 = force_reg (mode, op1);
1819
1820 if (! reg_or_int16_operand (op2, mode))
1821 op2 = force_reg (mode, op2);
1822
1823 emit_insn (gen_slt_insn (op0, op1, op2));
1824 DONE;
1825 }")
1826
1827 (define_insn "slt_insn" 1642 (define_insn "slt_insn"
1828 [(set (match_operand:SI 0 "register_operand" "=r,r") 1643 [(set (match_operand:SI 0 "register_operand" "=r,r")
1829 (lt:SI (match_operand:SI 1 "register_operand" "r,r") 1644 (lt:SI (match_operand:SI 1 "register_operand" "r,r")
1830 (match_operand:SI 2 "reg_or_int16_operand" "r,J"))) 1645 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1831 (clobber (reg:CC 17))] 1646 (clobber (reg:CC 17))]
1845 (match_dup 2))) 1660 (match_dup 2)))
1846 (set (match_dup 0) 1661 (set (match_dup 0)
1847 (ne:SI (reg:CC 17) (const_int 0)))] 1662 (ne:SI (reg:CC 17) (const_int 0)))]
1848 "") 1663 "")
1849 1664
1850 (define_expand "sle"
1851 [(match_operand:SI 0 "register_operand" "")]
1852 ""
1853 "
1854 {
1855 rtx op0 = operands[0];
1856 rtx op1 = m32r_compare_op0;
1857 rtx op2 = m32r_compare_op1;
1858 enum machine_mode mode = GET_MODE (op0);
1859
1860 if (mode != SImode)
1861 FAIL;
1862
1863 if (! register_operand (op1, mode))
1864 op1 = force_reg (mode, op1);
1865
1866 if (GET_CODE (op2) == CONST_INT)
1867 {
1868 HOST_WIDE_INT value = INTVAL (op2);
1869 if (value >= 2147483647)
1870 {
1871 emit_move_insn (op0, const1_rtx);
1872 DONE;
1873 }
1874
1875 op2 = GEN_INT (value+1);
1876 if (value < -32768 || value >= 32767)
1877 op2 = force_reg (mode, op2);
1878
1879 emit_insn (gen_slt_insn (op0, op1, op2));
1880 DONE;
1881 }
1882
1883 if (! register_operand (op2, mode))
1884 op2 = force_reg (mode, op2);
1885
1886 emit_insn (gen_sle_insn (op0, op1, op2));
1887 DONE;
1888 }")
1889
1890 (define_insn "sle_insn" 1665 (define_insn "sle_insn"
1891 [(set (match_operand:SI 0 "register_operand" "=r") 1666 [(set (match_operand:SI 0 "register_operand" "=r")
1892 (le:SI (match_operand:SI 1 "register_operand" "r") 1667 (le:SI (match_operand:SI 1 "register_operand" "r")
1893 (match_operand:SI 2 "register_operand" "r"))) 1668 (match_operand:SI 2 "register_operand" "r")))
1894 (clobber (reg:CC 17))] 1669 (clobber (reg:CC 17))]
1931 (const_int -1))) 1706 (const_int -1)))
1932 (set (match_dup 0) 1707 (set (match_dup 0)
1933 (neg:SI (match_dup 0)))] 1708 (neg:SI (match_dup 0)))]
1934 "") 1709 "")
1935 1710
1936 (define_expand "sgt"
1937 [(match_operand:SI 0 "register_operand" "")]
1938 ""
1939 "
1940 {
1941 rtx op0 = operands[0];
1942 rtx op1 = m32r_compare_op0;
1943 rtx op2 = m32r_compare_op1;
1944 enum machine_mode mode = GET_MODE (op0);
1945
1946 if (mode != SImode)
1947 FAIL;
1948
1949 if (! register_operand (op1, mode))
1950 op1 = force_reg (mode, op1);
1951
1952 if (! register_operand (op2, mode))
1953 op2 = force_reg (mode, op2);
1954
1955 emit_insn (gen_slt_insn (op0, op2, op1));
1956 DONE;
1957 }")
1958
1959 (define_expand "sge"
1960 [(match_operand:SI 0 "register_operand" "")]
1961 ""
1962 "
1963 {
1964 rtx op0 = operands[0];
1965 rtx op1 = m32r_compare_op0;
1966 rtx op2 = m32r_compare_op1;
1967 enum machine_mode mode = GET_MODE (op0);
1968
1969 if (mode != SImode)
1970 FAIL;
1971
1972 if (! register_operand (op1, mode))
1973 op1 = force_reg (mode, op1);
1974
1975 if (! reg_or_int16_operand (op2, mode))
1976 op2 = force_reg (mode, op2);
1977
1978 emit_insn (gen_sge_insn (op0, op1, op2));
1979 DONE;
1980 }")
1981
1982 (define_insn "sge_insn" 1711 (define_insn "sge_insn"
1983 [(set (match_operand:SI 0 "register_operand" "=r,r") 1712 [(set (match_operand:SI 0 "register_operand" "=r,r")
1984 (ge:SI (match_operand:SI 1 "register_operand" "r,r") 1713 (ge:SI (match_operand:SI 1 "register_operand" "r,r")
1985 (match_operand:SI 2 "reg_or_int16_operand" "r,J"))) 1714 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1986 (clobber (reg:CC 17))] 1715 (clobber (reg:CC 17))]
2023 (const_int -1))) 1752 (const_int -1)))
2024 (set (match_dup 0) 1753 (set (match_dup 0)
2025 (neg:SI (match_dup 0)))] 1754 (neg:SI (match_dup 0)))]
2026 "") 1755 "")
2027 1756
2028 (define_expand "sltu"
2029 [(match_operand:SI 0 "register_operand" "")]
2030 ""
2031 "
2032 {
2033 rtx op0 = operands[0];
2034 rtx op1 = m32r_compare_op0;
2035 rtx op2 = m32r_compare_op1;
2036 enum machine_mode mode = GET_MODE (op0);
2037
2038 if (mode != SImode)
2039 FAIL;
2040
2041 if (! register_operand (op1, mode))
2042 op1 = force_reg (mode, op1);
2043
2044 if (! reg_or_int16_operand (op2, mode))
2045 op2 = force_reg (mode, op2);
2046
2047 emit_insn (gen_sltu_insn (op0, op1, op2));
2048 DONE;
2049 }")
2050
2051 (define_insn "sltu_insn" 1757 (define_insn "sltu_insn"
2052 [(set (match_operand:SI 0 "register_operand" "=r,r") 1758 [(set (match_operand:SI 0 "register_operand" "=r,r")
2053 (ltu:SI (match_operand:SI 1 "register_operand" "r,r") 1759 (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
2054 (match_operand:SI 2 "reg_or_int16_operand" "r,J"))) 1760 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2055 (clobber (reg:CC 17))] 1761 (clobber (reg:CC 17))]
2069 (match_dup 2))) 1775 (match_dup 2)))
2070 (set (match_dup 0) 1776 (set (match_dup 0)
2071 (ne:SI (reg:CC 17) (const_int 0)))] 1777 (ne:SI (reg:CC 17) (const_int 0)))]
2072 "") 1778 "")
2073 1779
2074 (define_expand "sleu"
2075 [(match_operand:SI 0 "register_operand" "")]
2076 ""
2077 "
2078 {
2079 rtx op0 = operands[0];
2080 rtx op1 = m32r_compare_op0;
2081 rtx op2 = m32r_compare_op1;
2082 enum machine_mode mode = GET_MODE (op0);
2083
2084 if (mode != SImode)
2085 FAIL;
2086
2087 if (GET_CODE (op2) == CONST_INT)
2088 {
2089 HOST_WIDE_INT value = INTVAL (op2);
2090 if (value >= 2147483647)
2091 {
2092 emit_move_insn (op0, const1_rtx);
2093 DONE;
2094 }
2095
2096 op2 = GEN_INT (value+1);
2097 if (value < 0 || value >= 32767)
2098 op2 = force_reg (mode, op2);
2099
2100 emit_insn (gen_sltu_insn (op0, op1, op2));
2101 DONE;
2102 }
2103
2104 if (! register_operand (op2, mode))
2105 op2 = force_reg (mode, op2);
2106
2107 emit_insn (gen_sleu_insn (op0, op1, op2));
2108 DONE;
2109 }")
2110
2111 (define_insn "sleu_insn" 1780 (define_insn "sleu_insn"
2112 [(set (match_operand:SI 0 "register_operand" "=r") 1781 [(set (match_operand:SI 0 "register_operand" "=r")
2113 (leu:SI (match_operand:SI 1 "register_operand" "r") 1782 (leu:SI (match_operand:SI 1 "register_operand" "r")
2114 (match_operand:SI 2 "register_operand" "r"))) 1783 (match_operand:SI 2 "register_operand" "r")))
2115 (clobber (reg:CC 17))] 1784 (clobber (reg:CC 17))]
2151 (plus:SI (match_dup 0) 1820 (plus:SI (match_dup 0)
2152 (const_int -1))) 1821 (const_int -1)))
2153 (set (match_dup 0) 1822 (set (match_dup 0)
2154 (neg:SI (match_dup 0)))] 1823 (neg:SI (match_dup 0)))]
2155 "") 1824 "")
2156
2157 (define_expand "sgtu"
2158 [(match_operand:SI 0 "register_operand" "")]
2159 ""
2160 "
2161 {
2162 rtx op0 = operands[0];
2163 rtx op1 = m32r_compare_op0;
2164 rtx op2 = m32r_compare_op1;
2165 enum machine_mode mode = GET_MODE (op0);
2166
2167 if (mode != SImode)
2168 FAIL;
2169
2170 if (! register_operand (op1, mode))
2171 op1 = force_reg (mode, op1);
2172
2173 if (! register_operand (op2, mode))
2174 op2 = force_reg (mode, op2);
2175
2176 emit_insn (gen_sltu_insn (op0, op2, op1));
2177 DONE;
2178 }")
2179
2180 (define_expand "sgeu"
2181 [(match_operand:SI 0 "register_operand" "")]
2182 ""
2183 "
2184 {
2185 rtx op0 = operands[0];
2186 rtx op1 = m32r_compare_op0;
2187 rtx op2 = m32r_compare_op1;
2188 enum machine_mode mode = GET_MODE (op0);
2189
2190 if (mode != SImode)
2191 FAIL;
2192
2193 if (! register_operand (op1, mode))
2194 op1 = force_reg (mode, op1);
2195
2196 if (! reg_or_int16_operand (op2, mode))
2197 op2 = force_reg (mode, op2);
2198
2199 emit_insn (gen_sgeu_insn (op0, op1, op2));
2200 DONE;
2201 }")
2202 1825
2203 (define_insn "sgeu_insn" 1826 (define_insn "sgeu_insn"
2204 [(set (match_operand:SI 0 "register_operand" "=r,r") 1827 [(set (match_operand:SI 0 "register_operand" "=r,r")
2205 (geu:SI (match_operand:SI 1 "register_operand" "r,r") 1828 (geu:SI (match_operand:SI 1 "register_operand" "r,r")
2206 (match_operand:SI 2 "reg_or_int16_operand" "r,J"))) 1829 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2544 { 2167 {
2545 if (! zero_and_one (operands [2], operands [3])) 2168 if (! zero_and_one (operands [2], operands [3]))
2546 FAIL; 2169 FAIL;
2547 2170
2548 /* Generate the comparison that will set the carry flag. */ 2171 /* Generate the comparison that will set the carry flag. */
2549 operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0, 2172 operands[1] = gen_compare (GET_CODE (operands[1]), XEXP (operands[1], 0),
2550 m32r_compare_op1, TRUE); 2173 XEXP (operands[1], 1), TRUE);
2551 2174
2552 /* See other movsicc pattern below for reason why. */ 2175 /* See other movsicc pattern below for reason why. */
2553 emit_insn (gen_blockage ()); 2176 emit_insn (gen_blockage ());
2554 }") 2177 }")
2555 2178