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comparison gcc/config/m68hc11/m68hc11.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
160 ;; break the comparison. This can happen if the auto-inc register 160 ;; break the comparison. This can happen if the auto-inc register
161 ;; does not happen to be a hard register (i.e., reloading occurs). 161 ;; does not happen to be a hard register (i.e., reloading occurs).
162 ;; An offsetable memory operand should be ok. The 'tst_operand' and 162 ;; An offsetable memory operand should be ok. The 'tst_operand' and
163 ;; 'cmp_operand' predicates take care of this rule. 163 ;; 'cmp_operand' predicates take care of this rule.
164 ;; 164 ;;
165 (define_expand "tstsi"
166 [(set (cc0)
167 (match_operand:SI 0 "tst_operand" ""))]
168 ""
169 "
170 {
171 m68hc11_compare_op0 = operands[0];
172 m68hc11_compare_op1 = const0_rtx;
173 DONE;
174 }")
175
176 (define_expand "tsthi"
177 [(set (cc0)
178 (match_operand:HI 0 "tst_operand" ""))]
179 ""
180 "
181 {
182 m68hc11_compare_op0 = operands[0];
183 m68hc11_compare_op1 = const0_rtx;
184 DONE;
185 }")
186 165
187 (define_insn "tsthi_1" 166 (define_insn "tsthi_1"
188 [(set (cc0) 167 [(set (cc0)
189 (match_operand:HI 0 "tst_operand" "dx,*y"))] 168 (compare (match_operand:HI 0 "tst_operand" "dx,*y")
169 (const_int 0)))]
190 "" 170 ""
191 "* 171 "*
192 { 172 {
193 if (D_REG_P (operands[0]) && !TARGET_M6812) 173 if (D_REG_P (operands[0]) && !TARGET_M6812)
194 return \"std\\t%t0\"; 174 return \"std\\t%t0\";
195 else 175 else
196 return \"cp%0\\t#0\"; 176 return \"cp%0\\t#0\";
197 }") 177 }")
198 178
199 (define_expand "tstqi"
200 [(set (cc0)
201 (match_operand:QI 0 "tst_operand" ""))]
202 ""
203 "
204 {
205 m68hc11_compare_op0 = operands[0];
206 m68hc11_compare_op1 = const0_rtx;
207 DONE;
208 }")
209
210 ;; 179 ;;
211 ;; Split pattern for (tst:QI) on an address register. 180 ;; Split pattern for (tst:QI) on an address register.
212 ;; 181 ;;
213 (define_split 182 (define_split
214 [(set (cc0) 183 [(set (cc0)
215 (match_operand:QI 0 "hard_addr_reg_operand" ""))] 184 (compare (match_operand:QI 0 "hard_addr_reg_operand" "")
185 (const_int 0)))]
216 "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode" 186 "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode"
217 [(parallel [(set (reg:HI D_REGNUM) (match_dup 1)) 187 [(parallel [(set (reg:HI D_REGNUM) (match_dup 1))
218 (set (match_dup 1) (reg:HI D_REGNUM))]) 188 (set (match_dup 1) (reg:HI D_REGNUM))])
219 (set (cc0) (reg:QI D_REGNUM)) 189 (set (cc0) (compare (reg:QI D_REGNUM)
190 (const_int 0)))
220 (parallel [(set (reg:HI D_REGNUM) (match_dup 1)) 191 (parallel [(set (reg:HI D_REGNUM) (match_dup 1))
221 (set (match_dup 1) (reg:HI D_REGNUM))])] 192 (set (match_dup 1) (reg:HI D_REGNUM))])]
222 "operands[1] = gen_rtx_REG (HImode, REGNO (operands[0]));") 193 "operands[1] = gen_rtx_REG (HImode, REGNO (operands[0]));")
223 194
224 (define_insn "tstqi_1" 195 (define_insn "tstqi_1"
225 [(set (cc0) 196 [(set (cc0)
226 (match_operand:QI 0 "tst_operand" "m,d,*A,!u"))] 197 (compare (match_operand:QI 0 "tst_operand" "m,d,*A,!u")
198 (const_int 0)))]
227 "" 199 ""
228 "* 200 "*
229 { 201 {
230 if (A_REG_P (operands[0])) 202 if (A_REG_P (operands[0]))
231 return \"#\"; 203 return \"#\";
250 ;; restored after the real compare. A pattern+split is defined to 222 ;; restored after the real compare. A pattern+split is defined to
251 ;; avoid problems with the flow+cse register pass which are made 223 ;; avoid problems with the flow+cse register pass which are made
252 ;; after Z register replacement. 224 ;; after Z register replacement.
253 ;; 225 ;;
254 (define_insn_and_split "tstqi_z_used" 226 (define_insn_and_split "tstqi_z_used"
255 [(set (cc0) 227 [(set (cc0) (compare (match_operand:QI 0 "tst_operand" "m")
256 (match_operand:QI 0 "tst_operand" "m")) 228 (const_int 0)))
257 (use (match_operand:HI 1 "hard_reg_operand" "dxy")) 229 (use (match_operand:HI 1 "hard_reg_operand" "dxy"))
258 (use (reg:HI SOFT_Z_REGNUM))] 230 (use (reg:HI SOFT_Z_REGNUM))]
259 "" 231 ""
260 "#" 232 "#"
261 "z_replacement_completed == 2" 233 "z_replacement_completed == 2"
262 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1)) 234 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
263 (set (match_dup 1) (match_dup 2)) 235 (set (match_dup 1) (match_dup 2))
264 (set (cc0) (match_dup 0)) 236 (set (cc0) (compare (match_dup 0)
237 (const_int 0)))
265 (set (match_dup 1) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))] 238 (set (match_dup 1) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))]
266 "operands[2] = gen_rtx_REG (HImode, SOFT_Z_REGNUM);") 239 "operands[2] = gen_rtx_REG (HImode, SOFT_Z_REGNUM);")
267 240
268 241
269 ;;-------------------------------------------------------------------- 242 ;;--------------------------------------------------------------------
270 ;;- Compare 243 ;;- Compare
271 ;;-------------------------------------------------------------------- 244 ;;--------------------------------------------------------------------
272
273 (define_expand "cmpsi"
274 [(set (cc0)
275 (compare (match_operand:SI 0 "tst_operand" "")
276 (match_operand:SI 1 "cmp_operand" "")))]
277 ""
278 "
279 {
280 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
281 operands[0] = force_reg (SImode, operands[0]);
282
283 m68hc11_compare_op0 = operands[0];
284 m68hc11_compare_op1 = operands[1];
285 DONE;
286 }")
287 245
288 ;; 246 ;;
289 ;; Comparison of a hard register with another one is provided because 247 ;; Comparison of a hard register with another one is provided because
290 ;; it helps GCC to avoid to spill a pseudo hard register. 248 ;; it helps GCC to avoid to spill a pseudo hard register.
291 ;; We use a temporary in page 0, this is equivalent to a pseudo hard reg. 249 ;; We use a temporary in page 0, this is equivalent to a pseudo hard reg.
313 && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))" 271 && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
314 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1)) 272 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
315 (set (cc0) 273 (set (cc0)
316 (compare (match_dup 0) (mem:HI (post_inc:HI (reg:HI SP_REGNUM)))))] 274 (compare (match_dup 0) (mem:HI (post_inc:HI (reg:HI SP_REGNUM)))))]
317 "") 275 "")
318
319 (define_expand "cmphi"
320 [(set (cc0)
321 (compare (match_operand:HI 0 "tst_operand" "")
322 (match_operand:HI 1 "cmp_operand" "")))]
323 ""
324 "
325 {
326 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
327 operands[0] = force_reg (HImode, operands[0]);
328
329 m68hc11_compare_op0 = operands[0];
330 m68hc11_compare_op1 = operands[1];
331 DONE;
332 }")
333 276
334 (define_insn "cmphi_1_hc12" 277 (define_insn "cmphi_1_hc12"
335 [(set (cc0) 278 [(set (cc0)
336 (compare (match_operand:HI 0 "tst_operand" 279 (compare (match_operand:HI 0 "tst_operand"
337 "d,?xy,xyd,?xy,d,m,!u,dxy,dxy") 280 "d,?xy,xyd,?xy,d,m,!u,dxy,dxy")
417 (compare (match_dup 0) (match_dup 2)))] 360 (compare (match_dup 0) (match_dup 2)))]
418 "operands[2] = gen_rtx_REG (QImode, SOFT_TMP_REGNUM); 361 "operands[2] = gen_rtx_REG (QImode, SOFT_TMP_REGNUM);
419 operands[3] = gen_rtx_REG (HImode, SOFT_TMP_REGNUM); 362 operands[3] = gen_rtx_REG (HImode, SOFT_TMP_REGNUM);
420 operands[4] = gen_rtx_REG (HImode, REGNO (operands[1]));") 363 operands[4] = gen_rtx_REG (HImode, REGNO (operands[1]));")
421 364
422 (define_expand "cmpqi"
423 [(set (cc0)
424 (compare (match_operand:QI 0 "tst_operand" "")
425 (match_operand:QI 1 "cmp_operand" "")))]
426 ""
427 "
428 {
429 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
430 operands[0] = force_reg (QImode, operands[0]);
431
432 m68hc11_compare_op0 = operands[0];
433 m68hc11_compare_op1 = operands[1];
434 DONE;
435 }")
436
437 (define_insn "bitcmpqi" 365 (define_insn "bitcmpqi"
438 [(set (cc0) 366 [(set (cc0)
439 (and:QI (match_operand:QI 0 "tst_operand" "d,d,d,m,!u") 367 (compare (and:QI (match_operand:QI 0 "tst_operand" "d,d,d,m,!u")
440 (match_operand:QI 1 "cmp_operand" "im,*B,u,d,d")))] 368 (match_operand:QI 1 "cmp_operand" "im,*B,u,d,d"))
369 (const_int 0)))]
441 "" 370 ""
442 "@ 371 "@
443 bitb\\t%b1 372 bitb\\t%b1
444 # 373 #
445 bitb\\t%b1 374 bitb\\t%b1
446 bitb\\t%b0 375 bitb\\t%b0
447 bitb\\t%b0") 376 bitb\\t%b0")
448 377
449 (define_split /* "bitcmpqi" */ 378 (define_split /* "bitcmpqi" */
450 [(set (cc0) 379 [(set (cc0)
451 (and:QI (match_operand:QI 0 "tst_operand" "") 380 (compare (and:QI (match_operand:QI 0 "tst_operand" "")
452 (match_operand:QI 1 "hard_addr_reg_operand" "")))] 381 (match_operand:QI 1 "hard_addr_reg_operand" ""))
382 (const_int 0)))]
453 "z_replacement_completed == 2" 383 "z_replacement_completed == 2"
454 [(set (match_dup 3) (match_dup 2)) 384 [(set (match_dup 3) (match_dup 2))
455 (set (cc0) (and:QI (match_dup 0) (match_dup 4)))] 385 (set (cc0) (and:QI (match_dup 0) (match_dup 4)))]
456 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[1])); 386 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));
457 operands[3] = gen_rtx_REG (HImode, SOFT_TMP_REGNUM); 387 operands[3] = gen_rtx_REG (HImode, SOFT_TMP_REGNUM);
458 operands[4] = gen_rtx_REG (QImode, SOFT_TMP_REGNUM);") 388 operands[4] = gen_rtx_REG (QImode, SOFT_TMP_REGNUM);")
459 389
460 (define_insn_and_split "bitcmpqi_z_used" 390 (define_insn_and_split "bitcmpqi_z_used"
461 [(set (cc0) 391 [(set (cc0)
462 (and:QI (match_operand:QI 0 "tst_operand" "d,m") 392 (compare (and:QI (match_operand:QI 0 "tst_operand" "d,m")
463 (match_operand:QI 1 "cmp_operand" "m,d"))) 393 (match_operand:QI 1 "cmp_operand" "m,d"))
394 (const_int 0)))
464 (use (match_operand:HI 2 "hard_reg_operand" "xy,xy")) 395 (use (match_operand:HI 2 "hard_reg_operand" "xy,xy"))
465 (use (reg:HI SOFT_Z_REGNUM))] 396 (use (reg:HI SOFT_Z_REGNUM))]
466 "" 397 ""
467 "#" 398 "#"
468 "z_replacement_completed == 2" 399 "z_replacement_completed == 2"
472 (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))] 403 (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))]
473 "operands[3] = gen_rtx_REG (HImode, SOFT_Z_REGNUM);") 404 "operands[3] = gen_rtx_REG (HImode, SOFT_Z_REGNUM);")
474 405
475 (define_insn "bitcmphi" 406 (define_insn "bitcmphi"
476 [(set (cc0) 407 [(set (cc0)
477 (and:HI (match_operand:HI 0 "tst_operand" "d") 408 (compare (and:HI (match_operand:HI 0 "tst_operand" "d")
478 (match_operand:HI 1 "const_int_operand" "i")))] 409 (match_operand:HI 1 "const_int_operand" "i"))
410 (const_int 0)))]
479 "(INTVAL (operands[1]) & 0x0ff) == 0 411 "(INTVAL (operands[1]) & 0x0ff) == 0
480 || (INTVAL (operands[1]) & 0x0ff00) == 0" 412 || (INTVAL (operands[1]) & 0x0ff00) == 0"
481 "* 413 "*
482 { 414 {
483 if ((INTVAL (operands[1]) & 0x0ff) == 0) 415 if ((INTVAL (operands[1]) & 0x0ff) == 0)
486 return \"bitb\\t%1\"; 418 return \"bitb\\t%1\";
487 }") 419 }")
488 420
489 (define_insn "bitcmpqi_12" 421 (define_insn "bitcmpqi_12"
490 [(set (cc0) 422 [(set (cc0)
491 (zero_extract (match_operand:HI 0 "tst_operand" "d") 423 (compare (zero_extract:HI (match_operand:HI 0 "tst_operand" "d")
492 (match_operand:HI 1 "const_int_operand" "i") 424 (match_operand:HI 1 "const_int_operand" "i")
493 (match_operand:HI 2 "const_int_operand" "i")))] 425 (match_operand:HI 2 "const_int_operand" "i"))
426 (const_int 0)))]
494 "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8 427 "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8
495 || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16) 428 || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16)
496 && (unsigned) INTVAL (operands[2]) >= 8)" 429 && (unsigned) INTVAL (operands[2]) >= 8)"
497 "* 430 "*
498 { 431 {
6132 [(set (pc) 6065 [(set (pc)
6133 (label_ref (match_operand 0 "" "")))] 6066 (label_ref (match_operand 0 "" "")))]
6134 "" 6067 ""
6135 "bra\\t%l0") 6068 "bra\\t%l0")
6136 6069
6137 (define_expand "beq" 6070 (define_expand "cbranchsi4"
6138 [(set (pc) 6071 [(set (cc0)
6139 (if_then_else (eq (cc0) 6072 (compare (match_operand:SI 1 "tst_operand" "")
6140 (const_int 0)) 6073 (match_operand:SI 2 "cmp_operand" "")))
6141 (label_ref (match_operand 0 "" "")) 6074 (set (pc)
6075 (if_then_else (match_operator 0 "ordered_comparison_operator"
6076 [(cc0) (const_int 0)])
6077 (label_ref (match_operand 3 "" ""))
6142 (pc)))] 6078 (pc)))]
6143 "" 6079 ""
6144 " 6080 "
6145 { 6081 {
6146 m68hc11_expand_compare_and_branch (EQ, m68hc11_compare_op0, 6082 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
6147 m68hc11_compare_op1, 6083 operands[1] = force_reg (SImode, operands[1]);
6148 operands[0]); 6084
6085 m68hc11_expand_compare_and_branch (GET_CODE (operands[0]), operands[1],
6086 operands[2], operands[3]);
6149 DONE; 6087 DONE;
6150 }") 6088 }")
6151 6089
6152 (define_expand "bne" 6090 (define_expand "cbranchhi4"
6153 [(set (pc) 6091 [(set (cc0)
6154 (if_then_else (ne (cc0) 6092 (compare (match_operand:HI 1 "tst_operand" "")
6155 (const_int 0)) 6093 (match_operand:HI 2 "cmp_operand" "")))
6156 (label_ref (match_operand 0 "" "")) 6094 (set (pc)
6095 (if_then_else (match_operator 0 "ordered_comparison_operator"
6096 [(cc0) (const_int 0)])
6097 (label_ref (match_operand 3 "" ""))
6157 (pc)))] 6098 (pc)))]
6158 "" 6099 ""
6159 " 6100 "
6160 { 6101 {
6161 m68hc11_expand_compare_and_branch (NE, m68hc11_compare_op0, 6102 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
6162 m68hc11_compare_op1, 6103 operands[1] = force_reg (HImode, operands[1]);
6163 operands[0]); 6104
6105 m68hc11_expand_compare_and_branch (GET_CODE (operands[0]), operands[1],
6106 operands[2], operands[3]);
6164 DONE; 6107 DONE;
6165 }") 6108 }")
6166 6109
6167 (define_expand "bgt" 6110 (define_expand "cbranchqi4"
6168 [(set (pc) 6111 [(set (cc0)
6169 (if_then_else (gt (cc0) 6112 (compare (match_operand:QI 1 "tst_operand" "")
6170 (const_int 0)) 6113 (match_operand:QI 2 "cmp_operand" "")))
6171 (label_ref (match_operand 0 "" "")) 6114 (set (pc)
6115 (if_then_else (match_operator 0 "ordered_comparison_operator"
6116 [(cc0) (const_int 0)])
6117 (label_ref (match_operand 3 "" ""))
6172 (pc)))] 6118 (pc)))]
6173 "" 6119 ""
6174 " 6120 "
6175 { 6121 {
6176 m68hc11_expand_compare_and_branch (GT, m68hc11_compare_op0, 6122 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
6177 m68hc11_compare_op1, 6123 operands[1] = force_reg (QImode, operands[1]);
6178 operands[0]); 6124
6125 m68hc11_expand_compare_and_branch (GET_CODE (operands[0]), operands[1],
6126 operands[2], operands[3]);
6179 DONE; 6127 DONE;
6180 }") 6128 }")
6181 6129
6182 (define_expand "bgtu"
6183 [(set (pc)
6184 (if_then_else (gtu (cc0)
6185 (const_int 0))
6186 (label_ref (match_operand 0 "" ""))
6187 (pc)))]
6188 ""
6189 "
6190 {
6191 m68hc11_expand_compare_and_branch (GTU, m68hc11_compare_op0,
6192 m68hc11_compare_op1,
6193 operands[0]);
6194 DONE;
6195 }")
6196
6197 (define_expand "blt"
6198 [(set (pc)
6199 (if_then_else (lt (cc0)
6200 (const_int 0))
6201 (label_ref (match_operand 0 "" ""))
6202 (pc)))]
6203 ""
6204 "
6205 {
6206 m68hc11_expand_compare_and_branch (LT, m68hc11_compare_op0,
6207 m68hc11_compare_op1,
6208 operands[0]);
6209 DONE;
6210 }")
6211
6212 (define_expand "bltu"
6213 [(set (pc)
6214 (if_then_else (ltu (cc0)
6215 (const_int 0))
6216 (label_ref (match_operand 0 "" ""))
6217 (pc)))]
6218 ""
6219 "
6220 {
6221 m68hc11_expand_compare_and_branch (LTU, m68hc11_compare_op0,
6222 m68hc11_compare_op1,
6223 operands[0]);
6224 DONE;
6225 }")
6226
6227 (define_expand "bge"
6228 [(set (pc)
6229 (if_then_else (ge (cc0)
6230 (const_int 0))
6231 (label_ref (match_operand 0 "" ""))
6232 (pc)))]
6233 ""
6234 "
6235 {
6236 m68hc11_expand_compare_and_branch (GE, m68hc11_compare_op0,
6237 m68hc11_compare_op1,
6238 operands[0]);
6239 DONE;
6240 }")
6241
6242 (define_expand "bgeu"
6243 [(set (pc)
6244 (if_then_else (geu (cc0)
6245 (const_int 0))
6246 (label_ref (match_operand 0 "" ""))
6247 (pc)))]
6248 ""
6249 "
6250 {
6251 m68hc11_expand_compare_and_branch (GEU, m68hc11_compare_op0,
6252 m68hc11_compare_op1,
6253 operands[0]);
6254 DONE;
6255 }")
6256
6257 (define_expand "ble"
6258 [(set (pc)
6259 (if_then_else (le (cc0)
6260 (const_int 0))
6261 (label_ref (match_operand 0 "" ""))
6262 (pc)))]
6263 ""
6264 "
6265 {
6266 m68hc11_expand_compare_and_branch (LE, m68hc11_compare_op0,
6267 m68hc11_compare_op1,
6268 operands[0]);
6269 DONE;
6270 }")
6271
6272 (define_expand "bleu"
6273 [(set (pc)
6274 (if_then_else (leu (cc0)
6275 (const_int 0))
6276 (label_ref (match_operand 0 "" ""))
6277 (pc)))]
6278 ""
6279 "
6280 {
6281 m68hc11_expand_compare_and_branch (LEU, m68hc11_compare_op0,
6282 m68hc11_compare_op1,
6283 operands[0]);
6284 DONE;
6285 }")
6286 6130
6287 ;; 6131 ;;
6288 ;; Test and branch instructions for 68HC12 for EQ and NE. 6132 ;; Test and branch instructions for 68HC12 for EQ and NE.
6289 ;; 'z' must not appear in the constraints because the z replacement 6133 ;; 'z' must not appear in the constraints because the z replacement
6290 ;; pass does not know how to restore the replacement register. 6134 ;; pass does not know how to restore the replacement register.
7089 (define_peephole2 6933 (define_peephole2
7090 [(set (match_operand:HI 0 "hard_reg_operand" "") 6934 [(set (match_operand:HI 0 "hard_reg_operand" "")
7091 (plus:HI (match_dup 0) 6935 (plus:HI (match_dup 0)
7092 (match_operand:HI 1 "const_int_operand" ""))) 6936 (match_operand:HI 1 "const_int_operand" "")))
7093 (set (cc0) 6937 (set (cc0)
7094 (match_operand:QI 2 "memory_operand" ""))] 6938 (compare (match_operand:QI 2 "memory_operand" "")
6939 (const_int 0)))]
7095 "TARGET_AUTO_INC_DEC 6940 "TARGET_AUTO_INC_DEC
7096 && (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1) 6941 && (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1)
7097 && reg_mentioned_p (operands[0], operands[2])" 6942 && reg_mentioned_p (operands[0], operands[2])"
7098 [(set (cc0) (match_dup 3))] 6943 [(set (cc0)
6944 (compare (match_dup 3)
6945 (const_int 0)))]
7099 "if (INTVAL (operands[1]) == 1) 6946 "if (INTVAL (operands[1]) == 1)
7100 operands[3] = gen_rtx_MEM (QImode, 6947 operands[3] = gen_rtx_MEM (QImode,
7101 gen_rtx_PRE_INC (HImode, operands[0])); 6948 gen_rtx_PRE_INC (HImode, operands[0]));
7102 else 6949 else
7103 operands[3] = gen_rtx_MEM (QImode, 6950 operands[3] = gen_rtx_MEM (QImode,
7324 (define_peephole2 7171 (define_peephole2
7325 [(set (match_operand:HI 0 "hard_reg_operand" "") 7172 [(set (match_operand:HI 0 "hard_reg_operand" "")
7326 (match_operand:HI 1 "hard_reg_operand" "")) 7173 (match_operand:HI 1 "hard_reg_operand" ""))
7327 (set (match_dup 1) (plus:HI (match_dup 1) 7174 (set (match_dup 1) (plus:HI (match_dup 1)
7328 (match_operand:HI 2 "const_int_operand" ""))) 7175 (match_operand:HI 2 "const_int_operand" "")))
7329 (set (cc0) (match_dup 0))] 7176 (set (cc0) (compare (match_dup 0)
7177 (const_int 0)))]
7330 "peep2_reg_dead_p (3, operands[0]) && !Z_REG_P (operands[1])" 7178 "peep2_reg_dead_p (3, operands[0]) && !Z_REG_P (operands[1])"
7331 [(set (match_dup 1) (plus:HI (match_dup 1) (match_dup 2))) 7179 [(set (match_dup 1) (plus:HI (match_dup 1) (match_dup 2)))
7332 (set (cc0) (compare (match_dup 1) (match_dup 2)))] 7180 (set (cc0) (compare (match_dup 1) (match_dup 2)))]
7333 "") 7181 "")
7334 7182
7337 (match_operand:HI 1 "hard_reg_operand" "")) 7185 (match_operand:HI 1 "hard_reg_operand" ""))
7338 (set (match_operand:HI 2 "hard_reg_operand" "") 7186 (set (match_operand:HI 2 "hard_reg_operand" "")
7339 (plus:HI (match_dup 2) 7187 (plus:HI (match_dup 2)
7340 (match_operand:HI 3 "const_int_operand" ""))) 7188 (match_operand:HI 3 "const_int_operand" "")))
7341 (set (match_operand:HI 4 "memory_operand" "") (match_dup 2)) 7189 (set (match_operand:HI 4 "memory_operand" "") (match_dup 2))
7342 (set (cc0) (match_operand:HI 5 "hard_reg_operand" ""))] 7190 (set (cc0) (compare (match_operand:HI 5 "hard_reg_operand" "")
7191 (const_int 0)))]
7343 "peep2_reg_dead_p (4, operands[5]) && !Z_REG_P (operands[2]) 7192 "peep2_reg_dead_p (4, operands[5]) && !Z_REG_P (operands[2])
7344 && !reg_mentioned_p (operands[2], operands[4]) 7193 && !reg_mentioned_p (operands[2], operands[4])
7345 7194
7346 && ((rtx_equal_p (operands[5], operands[0]) 7195 && ((rtx_equal_p (operands[5], operands[0])
7347 && rtx_equal_p (operands[2], operands[1])) 7196 && rtx_equal_p (operands[2], operands[1]))