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comparison gcc/config/m68k/m68k.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;;- Machine description for GNU compiler, Motorola 68000 Version 1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008 3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc. 4 ;; Free Software Foundation, Inc.
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
8 ;; GCC is free software; you can redistribute it and/or modify 8 ;; GCC is free software; you can redistribute it and/or modify
114 [(UNSPEC_SIN 1) 114 [(UNSPEC_SIN 1)
115 (UNSPEC_COS 2) 115 (UNSPEC_COS 2)
116 (UNSPEC_GOT 3) 116 (UNSPEC_GOT 3)
117 (UNSPEC_IB 4) 117 (UNSPEC_IB 4)
118 (UNSPEC_TIE 5) 118 (UNSPEC_TIE 5)
119 (UNSPEC_GOTOFF 6) 119 (UNSPEC_RELOC16 6)
120 (UNSPEC_RELOC32 7)
120 ]) 121 ])
121 122
122 ;; UNSPEC_VOLATILE usage: 123 ;; UNSPEC_VOLATILE usage:
123 124
124 (define_constants 125 (define_constants
298 299
299 ;; We don't want to allow a constant operand for test insns because 300 ;; We don't want to allow a constant operand for test insns because
300 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 301 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
301 ;; be folded while optimizing anyway. 302 ;; be folded while optimizing anyway.
302 303
303 (define_expand "tstdi" 304 (define_insn "tstdi"
304 [(parallel [(set (cc0)
305 (match_operand:DI 0 "nonimmediate_operand" ""))
306 (clobber (match_scratch:SI 1 ""))
307 (clobber (match_scratch:DI 2 ""))])]
308 ""
309 "m68k_last_compare_had_fp_operands = 0;")
310
311 (define_insn ""
312 [(set (cc0) 305 [(set (cc0)
313 (match_operand:DI 0 "nonimmediate_operand" "am,d")) 306 (compare (match_operand:DI 0 "nonimmediate_operand" "am,d")
307 (const_int 0)))
314 (clobber (match_scratch:SI 1 "=X,d")) 308 (clobber (match_scratch:SI 1 "=X,d"))
315 (clobber (match_scratch:DI 2 "=d,X"))] 309 (clobber (match_scratch:DI 2 "=d,X"))]
316 "" 310 ""
317 { 311 {
318 if (which_alternative == 0) 312 if (which_alternative == 0)
337 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part. 331 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
338 */ 332 */
339 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0"; 333 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
340 }) 334 })
341 335
342 (define_expand "tstsi"
343 [(set (cc0)
344 (match_operand:SI 0 "nonimmediate_operand" ""))]
345 ""
346 "m68k_last_compare_had_fp_operands = 0;")
347
348 ;; If you think that the 68020 does not support tstl a0, 336 ;; If you think that the 68020 does not support tstl a0,
349 ;; reread page B-167 of the 68020 manual more carefully. 337 ;; reread page B-167 of the 68020 manual more carefully.
350 (define_insn "*tstsi_internal_68020_cf" 338 (define_insn "*tstsi_internal_68020_cf"
351 [(set (cc0) 339 [(set (cc0)
352 (match_operand:SI 0 "nonimmediate_operand" "rm"))] 340 (compare (match_operand:SI 0 "nonimmediate_operand" "rm")
341 (const_int 0)))]
353 "TARGET_68020 || TARGET_COLDFIRE" 342 "TARGET_68020 || TARGET_COLDFIRE"
354 "tst%.l %0" 343 "tst%.l %0"
355 [(set_attr "type" "tst_l")]) 344 [(set_attr "type" "tst_l")])
356 345
357 ;; On an address reg, cmpw may replace cmpl. 346 ;; On an address reg, cmpw may replace cmpl.
358 (define_insn "*tstsi_internal" 347 (define_insn "*tstsi_internal"
359 [(set (cc0) 348 [(set (cc0)
360 (match_operand:SI 0 "nonimmediate_operand" "dm,r"))] 349 (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r")
350 (const_int 0)))]
361 "!(TARGET_68020 || TARGET_COLDFIRE)" 351 "!(TARGET_68020 || TARGET_COLDFIRE)"
362 "@ 352 "@
363 tst%.l %0 353 tst%.l %0
364 cmp%.w #0,%0" 354 cmp%.w #0,%0"
365 [(set_attr "type" "tst_l,cmp")]) 355 [(set_attr "type" "tst_l,cmp")])
366 356
367 ;; This can't use an address register, because comparisons 357 ;; This can't use an address register, because comparisons
368 ;; with address registers as second operand always test the whole word. 358 ;; with address registers as second operand always test the whole word.
369 (define_expand "tsthi"
370 [(set (cc0)
371 (match_operand:HI 0 "nonimmediate_operand" ""))]
372 ""
373 "m68k_last_compare_had_fp_operands = 0;")
374
375 (define_insn "*tsthi_internal" 359 (define_insn "*tsthi_internal"
376 [(set (cc0) 360 [(set (cc0)
377 (match_operand:HI 0 "nonimmediate_operand" "dm"))] 361 (compare (match_operand:HI 0 "nonimmediate_operand" "dm")
362 (const_int 0)))]
378 "" 363 ""
379 "tst%.w %0" 364 "tst%.w %0"
380 [(set_attr "type" "tst")]) 365 [(set_attr "type" "tst")])
381 366
382 (define_expand "tstqi"
383 [(set (cc0)
384 (match_operand:QI 0 "nonimmediate_operand" ""))]
385 ""
386 "m68k_last_compare_had_fp_operands = 0;")
387
388 (define_insn "*tstqi_internal" 367 (define_insn "*tstqi_internal"
389 [(set (cc0) 368 [(set (cc0)
390 (match_operand:QI 0 "nonimmediate_operand" "dm"))] 369 (compare (match_operand:QI 0 "nonimmediate_operand" "dm")
370 (const_int 0)))]
391 "" 371 ""
392 "tst%.b %0" 372 "tst%.b %0"
393 [(set_attr "type" "tst")]) 373 [(set_attr "type" "tst")])
394 374
395 (define_expand "tst<mode>"
396 [(set (cc0)
397 (match_operand:FP 0 "general_operand" ""))]
398 "TARGET_HARD_FLOAT"
399 {
400 m68k_last_compare_had_fp_operands = 1;
401 })
402
403 (define_insn "tst<mode>_68881" 375 (define_insn "tst<mode>_68881"
404 [(set (cc0) 376 [(set (cc0)
405 (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))] 377 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m")
378 (match_operand:FP 1 "const0_operand" "H")))]
406 "TARGET_68881" 379 "TARGET_68881"
407 { 380 {
408 cc_status.flags = CC_IN_68881; 381 cc_status.flags = CC_IN_68881;
409 if (FP_REG_P (operands[0])) 382 if (FP_REG_P (operands[0]))
410 return "ftst%.x %0"; 383 return "ftst%.x %0";
412 } 385 }
413 [(set_attr "type" "ftst")]) 386 [(set_attr "type" "ftst")])
414 387
415 (define_insn "tst<mode>_cf" 388 (define_insn "tst<mode>_cf"
416 [(set (cc0) 389 [(set (cc0)
417 (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))] 390 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U")
391 (match_operand:FP 1 "const0_operand" "H")))]
418 "TARGET_COLDFIRE_FPU" 392 "TARGET_COLDFIRE_FPU"
419 { 393 {
420 cc_status.flags = CC_IN_68881; 394 cc_status.flags = CC_IN_68881;
421 if (FP_REG_P (operands[0])) 395 if (FP_REG_P (operands[0]))
422 return "ftst%.d %0"; 396 return "ftst%.d %0";
425 [(set_attr "type" "ftst")]) 399 [(set_attr "type" "ftst")])
426 400
427 401
428 ;; compare instructions. 402 ;; compare instructions.
429 403
430 (define_expand "cmpdi" 404 (define_insn "*cmpdi_internal"
431 [(parallel 405 [(set (cc0)
432 [(set (cc0) 406 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
433 (compare (match_operand:DI 0 "nonimmediate_operand" "") 407 (match_operand:DI 2 "general_operand" "d,0")))
434 (match_operand:DI 1 "general_operand" ""))) 408 (clobber (match_scratch:DI 0 "=d,d"))]
435 (clobber (match_scratch:DI 2 ""))])]
436 ""
437 "m68k_last_compare_had_fp_operands = 0;")
438
439 (define_insn ""
440 [(set (cc0)
441 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
442 (match_operand:DI 2 "general_operand" "d,0")))
443 (clobber (match_scratch:DI 0 "=d,d"))]
444 "" 409 ""
445 { 410 {
446 if (rtx_equal_p (operands[0], operands[1])) 411 if (rtx_equal_p (operands[0], operands[1]))
447 return "sub%.l %R2,%R0\;subx%.l %2,%0"; 412 return "sub%.l %R2,%R0\;subx%.l %2,%0";
448 else 413 else
450 cc_status.flags |= CC_REVERSED; /*|*/ 415 cc_status.flags |= CC_REVERSED; /*|*/
451 return "sub%.l %R1,%R0\;subx%.l %1,%0"; 416 return "sub%.l %R1,%R0\;subx%.l %1,%0";
452 } 417 }
453 }) 418 })
454 419
455 (define_expand "cmpsi" 420 (define_insn "cmpdi"
421 [(set (cc0)
422 (compare (match_operand:DI 0 "nonimmediate_operand")
423 (match_operand:DI 1 "general_operand")))
424 (clobber (match_scratch:DI 2))]
425 ""
426 "")
427
428
429 (define_expand "cbranchdi4"
430 [(set (pc)
431 (if_then_else (match_operator 0 "ordered_comparison_operator"
432 [(match_operand:DI 1 "nonimmediate_operand")
433 (match_operand:DI 2 "general_operand")])
434 (label_ref (match_operand 3 ""))
435 (pc)))]
436 ""
437 {
438 if (operands[2] == const0_rtx)
439 emit_insn (gen_tstdi (operands[1]));
440 else
441 emit_insn (gen_cmpdi (operands[1], operands[2]));
442 operands[1] = cc0_rtx;
443 operands[2] = const0_rtx;
444 })
445
446 (define_expand "cstoredi4"
447 [(set (match_operand:QI 0 "register_operand")
448 (match_operator:QI 1 "ordered_comparison_operator"
449 [(match_operand:DI 2 "nonimmediate_operand")
450 (match_operand:DI 3 "general_operand")]))]
451 ""
452 {
453 if (operands[3] == const0_rtx)
454 emit_insn (gen_tstdi (operands[2]));
455 else
456 emit_insn (gen_cmpdi (operands[2], operands[3]));
457 operands[2] = cc0_rtx;
458 operands[3] = const0_rtx;
459 })
460
461
462 (define_expand "cbranchsi4"
456 [(set (cc0) 463 [(set (cc0)
457 (compare (match_operand:SI 0 "nonimmediate_operand" "") 464 (compare (match_operand:SI 1 "nonimmediate_operand" "")
458 (match_operand:SI 1 "general_operand" "")))] 465 (match_operand:SI 2 "general_operand" "")))
459 "" 466 (set (pc)
460 { 467 (if_then_else (match_operator 0 "ordered_comparison_operator"
461 m68k_last_compare_had_fp_operands = 0; 468 [(cc0) (const_int 0)])
462 }) 469 (label_ref (match_operand 3 ""))
470 (pc)))]
471 ""
472 "")
473
474 (define_expand "cstoresi4"
475 [(set (cc0)
476 (compare (match_operand:SI 2 "nonimmediate_operand" "")
477 (match_operand:SI 3 "general_operand" "")))
478 (set (match_operand:QI 0 "register_operand")
479 (match_operator:QI 1 "ordered_comparison_operator"
480 [(cc0) (const_int 0)]))]
481 ""
482 "")
483
463 484
464 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes. 485 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
465 (define_insn "" 486 (define_insn ""
466 [(set (cc0) 487 [(set (cc0)
467 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>") 488 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
498 } 519 }
499 return "cmp%.l %d1,%d0"; 520 return "cmp%.l %d1,%d0";
500 } 521 }
501 [(set_attr "type" "cmp_l")]) 522 [(set_attr "type" "cmp_l")])
502 523
503 (define_expand "cmphi" 524 (define_expand "cbranchhi4"
504 [(set (cc0) 525 [(set (cc0)
505 (compare (match_operand:HI 0 "nonimmediate_src_operand" "") 526 (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
506 (match_operand:HI 1 "general_src_operand" "")))] 527 (match_operand:HI 2 "m68k_subword_comparison_operand" "")))
507 "!TARGET_COLDFIRE" 528 (set (pc)
508 "m68k_last_compare_had_fp_operands = 0;") 529 (if_then_else (match_operator 0 "ordered_comparison_operator"
530 [(cc0) (const_int 0)])
531 (label_ref (match_operand 3 ""))
532 (pc)))]
533 ""
534 "")
535
536 (define_expand "cstorehi4"
537 [(set (cc0)
538 (compare (match_operand:HI 2 "nonimmediate_operand" "")
539 (match_operand:HI 3 "m68k_subword_comparison_operand" "")))
540 (set (match_operand:QI 0 "register_operand")
541 (match_operator:QI 1 "ordered_comparison_operator"
542 [(cc0) (const_int 0)]))]
543 ""
544 "")
509 545
510 (define_insn "" 546 (define_insn ""
511 [(set (cc0) 547 [(set (cc0)
512 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>") 548 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
513 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))] 549 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
522 return "cmp%.w %d0,%d1"; 558 return "cmp%.w %d0,%d1";
523 } 559 }
524 return "cmp%.w %d1,%d0"; 560 return "cmp%.w %d1,%d0";
525 }) 561 })
526 562
527 (define_expand "cmpqi" 563 (define_expand "cbranchqi4"
528 [(set (cc0) 564 [(set (cc0)
529 (compare (match_operand:QI 0 "nonimmediate_src_operand" "") 565 (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
530 (match_operand:QI 1 "general_src_operand" "")))] 566 (match_operand:QI 2 "m68k_subword_comparison_operand" "")))
531 "!TARGET_COLDFIRE" 567 (set (pc)
532 "m68k_last_compare_had_fp_operands = 0;") 568 (if_then_else (match_operator 0 "ordered_comparison_operator"
569 [(cc0) (const_int 0)])
570 (label_ref (match_operand 3 ""))
571 (pc)))]
572 ""
573 "")
574
575 (define_expand "cstoreqi4"
576 [(set (cc0)
577 (compare (match_operand:QI 2 "nonimmediate_src_operand" "")
578 (match_operand:QI 3 "m68k_subword_comparison_operand" "")))
579 (set (match_operand:QI 0 "register_operand")
580 (match_operator:QI 1 "ordered_comparison_operator"
581 [(cc0) (const_int 0)]))]
582 ""
583 "")
533 584
534 (define_insn "" 585 (define_insn ""
535 [(set (cc0) 586 [(set (cc0)
536 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>") 587 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
537 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))] 588 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
546 return "cmp%.b %d0,%d1"; 597 return "cmp%.b %d0,%d1";
547 } 598 }
548 return "cmp%.b %d1,%d0"; 599 return "cmp%.b %d1,%d0";
549 }) 600 })
550 601
551 (define_expand "cmp<mode>" 602 (define_expand "cbranch<mode>4"
552 [(set (cc0) 603 [(set (cc0)
553 (compare (match_operand:FP 0 "register_operand" "") 604 (compare (match_operand:FP 1 "register_operand" "")
554 (match_operand:FP 1 "fp_src_operand" "")))] 605 (match_operand:FP 2 "fp_src_operand" "")))
606 (set (pc)
607 (if_then_else (match_operator 0 "comparison_operator"
608 [(cc0) (const_int 0)])
609 (label_ref (match_operand 3 ""))
610 (pc)))]
555 "TARGET_HARD_FLOAT" 611 "TARGET_HARD_FLOAT"
556 "m68k_last_compare_had_fp_operands = 1;") 612 "")
613
614 (define_expand "cstore<mode>4"
615 [(set (cc0)
616 (compare (match_operand:FP 2 "register_operand" "")
617 (match_operand:FP 3 "fp_src_operand" "")))
618 (set (match_operand:QI 0 "register_operand")
619 (match_operator:QI 1 "m68k_cstore_comparison_operator"
620 [(cc0) (const_int 0)]))]
621 "TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)"
622 "if (TARGET_COLDFIRE && operands[2] != const0_rtx)
623 FAIL;")
557 624
558 (define_insn "*cmp<mode>_68881" 625 (define_insn "*cmp<mode>_68881"
559 [(set (cc0) 626 [(set (cc0)
560 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF") 627 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
561 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))] 628 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))]
586 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is 653 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
587 ;; specified as a constant, so we must disable all patterns that may extract 654 ;; specified as a constant, so we must disable all patterns that may extract
588 ;; from a MEM at a constant bit position if we can't use this as a constraint. 655 ;; from a MEM at a constant bit position if we can't use this as a constraint.
589 656
590 (define_insn "" 657 (define_insn ""
591 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS") 658 [(set
592 (const_int 1) 659 (cc0)
593 (minus:SI (const_int 7) 660 (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand" "oS")
594 (match_operand:SI 1 "general_operand" "di"))))] 661 (const_int 1)
662 (minus:SI (const_int 7)
663 (match_operand:SI 1 "general_operand" "di")))
664 (const_int 0)))]
595 "!TARGET_COLDFIRE" 665 "!TARGET_COLDFIRE"
596 { 666 {
597 return output_btst (operands, operands[1], operands[0], insn, 7); 667 return output_btst (operands, operands[1], operands[0], insn, 7);
598 }) 668 })
599 669
600 ;; This is the same as the above pattern except for the constraints. The 'i' 670 ;; This is the same as the above pattern except for the constraints. The 'i'
601 ;; has been deleted. 671 ;; has been deleted.
602 672
603 (define_insn "" 673 (define_insn ""
604 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o") 674 [(set
605 (const_int 1) 675 (cc0)
606 (minus:SI (const_int 7) 676 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
607 (match_operand:SI 1 "general_operand" "d"))))] 677 (const_int 1)
678 (minus:SI (const_int 7)
679 (match_operand:SI 1 "general_operand" "d")))
680 (const_int 0)))]
608 "TARGET_COLDFIRE" 681 "TARGET_COLDFIRE"
609 { 682 {
610 return output_btst (operands, operands[1], operands[0], insn, 7); 683 return output_btst (operands, operands[1], operands[0], insn, 7);
611 }) 684 })
612 685
613 (define_insn "" 686 (define_insn ""
614 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d") 687 [(set
615 (const_int 1) 688 (cc0)
616 (minus:SI (const_int 31) 689 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
617 (match_operand:SI 1 "general_operand" "di"))))] 690 (const_int 1)
691 (minus:SI (const_int 31)
692 (match_operand:SI 1 "general_operand" "di")))
693 (const_int 0)))]
618 "" 694 ""
619 { 695 {
620 return output_btst (operands, operands[1], operands[0], insn, 31); 696 return output_btst (operands, operands[1], operands[0], insn, 31);
621 }) 697 })
622 698
623 ;; The following two patterns are like the previous two 699 ;; The following two patterns are like the previous two
624 ;; except that they use the fact that bit-number operands 700 ;; except that they use the fact that bit-number operands
625 ;; are automatically masked to 3 or 5 bits. 701 ;; are automatically masked to 3 or 5 bits.
626 702
627 (define_insn "" 703 (define_insn ""
628 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o") 704 [(set
629 (const_int 1) 705 (cc0)
630 (minus:SI (const_int 7) 706 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
631 (and:SI 707 (const_int 1)
632 (match_operand:SI 1 "register_operand" "d") 708 (minus:SI (const_int 7)
633 (const_int 7)))))] 709 (and:SI
710 (match_operand:SI 1 "register_operand" "d")
711 (const_int 7))))
712 (const_int 0)))]
634 "" 713 ""
635 { 714 {
636 return output_btst (operands, operands[1], operands[0], insn, 7); 715 return output_btst (operands, operands[1], operands[0], insn, 7);
637 }) 716 })
638 717
639 (define_insn "" 718 (define_insn ""
640 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d") 719 [(set
641 (const_int 1) 720 (cc0)
642 (minus:SI (const_int 31) 721 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
643 (and:SI 722 (const_int 1)
644 (match_operand:SI 1 "register_operand" "d") 723 (minus:SI (const_int 31)
645 (const_int 31)))))] 724 (and:SI
725 (match_operand:SI 1 "register_operand" "d")
726 (const_int 31))))
727 (const_int 0)))]
646 "" 728 ""
647 { 729 {
648 return output_btst (operands, operands[1], operands[0], insn, 31); 730 return output_btst (operands, operands[1], operands[0], insn, 31);
649 }) 731 })
650 732
651 ;; Nonoffsettable mem refs are ok in this one pattern 733 ;; Nonoffsettable mem refs are ok in this one pattern
652 ;; since we don't try to adjust them. 734 ;; since we don't try to adjust them.
653 (define_insn "" 735 (define_insn ""
654 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m") 736 [(set
655 (const_int 1) 737 (cc0)
656 (match_operand:SI 1 "const_int_operand" "n")))] 738 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
739 (const_int 1)
740 (match_operand:SI 1 "const_int_operand" "n"))
741 (const_int 0)))]
657 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE" 742 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
658 { 743 {
659 operands[1] = GEN_INT (7 - INTVAL (operands[1])); 744 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
660 return output_btst (operands, operands[1], operands[0], insn, 7); 745 return output_btst (operands, operands[1], operands[0], insn, 7);
661 }) 746 })
662 747
663 (define_insn "" 748 (define_insn ""
664 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do") 749 [(set
665 (const_int 1) 750 (cc0)
666 (match_operand:SI 1 "const_int_operand" "n")))] 751 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
752 (const_int 1)
753 (match_operand:SI 1 "const_int_operand" "n"))
754 (const_int 0)))]
667 "!TARGET_COLDFIRE" 755 "!TARGET_COLDFIRE"
668 { 756 {
669 if (GET_CODE (operands[0]) == MEM) 757 if (GET_CODE (operands[0]) == MEM)
670 { 758 {
671 operands[0] = adjust_address (operands[0], QImode, 759 operands[0] = adjust_address (operands[0], QImode,
679 767
680 ;; This is the same as the above pattern except for the constraints. 768 ;; This is the same as the above pattern except for the constraints.
681 ;; The 'o' has been replaced with 'Q'. 769 ;; The 'o' has been replaced with 'Q'.
682 770
683 (define_insn "" 771 (define_insn ""
684 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ") 772 [(set
685 (const_int 1) 773 (cc0)
686 (match_operand:SI 1 "const_int_operand" "n")))] 774 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ")
775 (const_int 1)
776 (match_operand:SI 1 "const_int_operand" "n"))
777 (const_int 0)))]
687 "TARGET_COLDFIRE" 778 "TARGET_COLDFIRE"
688 { 779 {
689 if (GET_CODE (operands[0]) == MEM) 780 if (GET_CODE (operands[0]) == MEM)
690 { 781 {
691 operands[0] = adjust_address (operands[0], QImode, 782 operands[0] = adjust_address (operands[0], QImode,
777 (match_operand:SI 1 "" ""))] 868 (match_operand:SI 1 "" ""))]
778 "" 869 ""
779 { 870 {
780 rtx tmp, base, offset; 871 rtx tmp, base, offset;
781 872
782 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) 873 /* Recognize the case where operand[1] is a reference to thread-local
874 data and load its address to a register. */
875 if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false))
876 {
877 rtx tmp = operands[1];
878 rtx addend = NULL;
879
880 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
881 {
882 addend = XEXP (XEXP (tmp, 0), 1);
883 tmp = XEXP (XEXP (tmp, 0), 0);
884 }
885
886 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
887 gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
888
889 tmp = m68k_legitimize_tls_address (tmp);
890
891 if (addend)
892 {
893 if (!REG_P (tmp))
894 {
895 rtx reg;
896
897 reg = gen_reg_rtx (Pmode);
898 emit_move_insn (reg, tmp);
899 tmp = reg;
900 }
901
902 tmp = gen_rtx_PLUS (SImode, tmp, addend);
903 }
904
905 operands[1] = tmp;
906 }
907 else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
783 { 908 {
784 /* The source is an address which requires PIC relocation. 909 /* The source is an address which requires PIC relocation.
785 Call legitimize_pic_address with the source, mode, and a relocation 910 Call legitimize_pic_address with the source, mode, and a relocation
786 register (a new pseudo, or the final destination if reload_in_progress 911 register (a new pseudo, or the final destination if reload_in_progress
787 is set). Then fall through normally */ 912 is set). Then fall through normally */
2336 2461
2337 "! TARGET_COLDFIRE" 2462 "! TARGET_COLDFIRE"
2338 "* return output_addsi3 (operands);") 2463 "* return output_addsi3 (operands);")
2339 2464
2340 (define_insn_and_split "*addsi3_5200" 2465 (define_insn_and_split "*addsi3_5200"
2341 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a,m,r, ?a, ?a,?a,?a") 2466 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a")
2342 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0,0,0, a, a, r, a") 2467 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a")
2343 (match_operand:SI 2 "general_src_operand" " I, L, J,d,mrKi,Cj, r, a, J")))] 2468 (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))]
2344 "TARGET_COLDFIRE" 2469 "TARGET_COLDFIRE"
2345 { 2470 {
2346 switch (which_alternative) 2471 switch (which_alternative)
2347 { 2472 {
2348 case 0: 2473 case 0:
2380 (match_dup 2)) 2505 (match_dup 2))
2381 (set (match_dup 0) 2506 (set (match_dup 0)
2382 (plus:SI (match_dup 0) 2507 (plus:SI (match_dup 0)
2383 (match_dup 1)))] 2508 (match_dup 1)))]
2384 "" 2509 ""
2385 [(set_attr "type" "aluq_l,aluq_l,lea,alu_l,alu_l,*,lea,lea,lea") 2510 [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea")
2386 (set_attr "opy" "2,2,*,2,2,*,*,*,*") 2511 (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *")
2387 (set_attr "opy_type" "*,*,mem5,*,*,*,mem6,mem6,mem5")]) 2512 (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")])
2388 2513
2389 (define_insn "" 2514 (define_insn ""
2390 [(set (match_operand:SI 0 "nonimmediate_operand" "=a") 2515 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2391 (plus:SI (match_operand:SI 1 "general_operand" "0") 2516 (plus:SI (match_operand:SI 1 "general_operand" "0")
2392 (sign_extend:SI 2517 (sign_extend:SI
5241 "!TARGET_COLDFIRE" 5366 "!TARGET_COLDFIRE"
5242 "lsr%.b %1,%0") 5367 "lsr%.b %1,%0")
5243 5368
5244 ;; rotate instructions 5369 ;; rotate instructions
5245 5370
5371 (define_insn "rotlsi_16"
5372 [(set (match_operand:SI 0 "register_operand" "=d")
5373 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5374 (const_int 16)))]
5375 ""
5376 "swap %0"
5377 [(set_attr "type" "shift")])
5378
5246 (define_insn "rotlsi3" 5379 (define_insn "rotlsi3"
5247 [(set (match_operand:SI 0 "register_operand" "=d") 5380 [(set (match_operand:SI 0 "register_operand" "=d")
5248 (rotate:SI (match_operand:SI 1 "register_operand" "0") 5381 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5249 (match_operand:SI 2 "general_operand" "dINO")))] 5382 (match_operand:SI 2 "general_operand" "dINO")))]
5250 "!TARGET_COLDFIRE" 5383 "!TARGET_COLDFIRE"
5749 5882
5750 ;; Special patterns for optimizing bit-field instructions. 5883 ;; Special patterns for optimizing bit-field instructions.
5751 5884
5752 (define_insn "" 5885 (define_insn ""
5753 [(set (cc0) 5886 [(set (cc0)
5754 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 5887 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5755 (match_operand:SI 1 "const_int_operand" "n") 5888 (match_operand:SI 1 "const_int_operand" "n")
5756 (match_operand:SI 2 "general_operand" "dn")))] 5889 (match_operand:SI 2 "general_operand" "dn"))
5890 (const_int 0)))]
5757 "TARGET_68020 && TARGET_BITFIELD" 5891 "TARGET_68020 && TARGET_BITFIELD"
5758 { 5892 {
5759 if (operands[1] == const1_rtx 5893 if (operands[1] == const1_rtx
5760 && GET_CODE (operands[2]) == CONST_INT) 5894 && GET_CODE (operands[2]) == CONST_INT)
5761 { 5895 {
5774 5908
5775 5909
5776 ;;; now handle the register cases 5910 ;;; now handle the register cases
5777 (define_insn "" 5911 (define_insn ""
5778 [(set (cc0) 5912 [(set (cc0)
5779 (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 5913 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5780 (match_operand:SI 1 "const_int_operand" "n") 5914 (match_operand:SI 1 "const_int_operand" "n")
5781 (match_operand:SI 2 "general_operand" "dn")))] 5915 (match_operand:SI 2 "general_operand" "dn"))
5916 (const_int 0)))]
5782 "TARGET_68020 && TARGET_BITFIELD" 5917 "TARGET_68020 && TARGET_BITFIELD"
5783 { 5918 {
5784 if (operands[1] == const1_rtx 5919 if (operands[1] == const1_rtx
5785 && GET_CODE (operands[2]) == CONST_INT) 5920 && GET_CODE (operands[2]) == CONST_INT)
5786 { 5921 {
5796 return "bftst %0{%b2:%b1}"; 5931 return "bftst %0{%b2:%b1}";
5797 }) 5932 })
5798 5933
5799 (define_insn "scc0_di" 5934 (define_insn "scc0_di"
5800 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 5935 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5801 (match_operator 1 "valid_dbcc_comparison_p" 5936 (match_operator 1 "ordered_comparison_operator"
5802 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] 5937 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5803 "! TARGET_COLDFIRE" 5938 "! TARGET_COLDFIRE"
5804 { 5939 {
5805 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); 5940 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5806 }) 5941 })
5807 5942
5808 (define_insn "scc0_di_5200" 5943 (define_insn "scc0_di_5200"
5809 [(set (match_operand:QI 0 "nonimmediate_operand" "=d") 5944 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5810 (match_operator 1 "valid_dbcc_comparison_p" 5945 (match_operator 1 "ordered_comparison_operator"
5811 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] 5946 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5812 "TARGET_COLDFIRE" 5947 "TARGET_COLDFIRE"
5813 { 5948 {
5814 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); 5949 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5815 }) 5950 })
5816 5951
5817 (define_insn "scc_di" 5952 (define_insn "scc_di"
5818 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm") 5953 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5819 (match_operator 1 "valid_dbcc_comparison_p" 5954 (match_operator 1 "ordered_comparison_operator"
5820 [(match_operand:DI 2 "general_operand" "ro,r") 5955 [(match_operand:DI 2 "general_operand" "ro,r")
5821 (match_operand:DI 3 "general_operand" "r,ro")]))] 5956 (match_operand:DI 3 "general_operand" "r,ro")]))]
5822 "! TARGET_COLDFIRE" 5957 "! TARGET_COLDFIRE"
5823 { 5958 {
5824 return output_scc_di (operands[1], operands[2], operands[3], operands[0]); 5959 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5825 }) 5960 })
5826 5961
5827 (define_insn "scc_di_5200" 5962 (define_insn "scc_di_5200"
5828 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d") 5963 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5829 (match_operator 1 "valid_dbcc_comparison_p" 5964 (match_operator 1 "ordered_comparison_operator"
5830 [(match_operand:DI 2 "general_operand" "ro,r") 5965 [(match_operand:DI 2 "general_operand" "ro,r")
5831 (match_operand:DI 3 "general_operand" "r,ro")]))] 5966 (match_operand:DI 3 "general_operand" "r,ro")]))]
5832 "TARGET_COLDFIRE" 5967 "TARGET_COLDFIRE"
5833 { 5968 {
5834 return output_scc_di (operands[1], operands[2], operands[3], operands[0]); 5969 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5836 5971
5837 ;; Note that operand 0 of an SCC insn is supported in the hardware as 5972 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5838 ;; memory, but we cannot allow it to be in memory in case the address 5973 ;; memory, but we cannot allow it to be in memory in case the address
5839 ;; needs to be reloaded. 5974 ;; needs to be reloaded.
5840 5975
5841 (define_expand "seq"
5842 [(set (match_operand:QI 0 "register_operand" "")
5843 (eq:QI (cc0) (const_int 0)))]
5844 ""
5845 {
5846 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5847 && m68k_last_compare_had_fp_operands)
5848 {
5849 m68k_last_compare_had_fp_operands = 0;
5850 FAIL;
5851 }
5852 })
5853
5854 (define_insn "" 5976 (define_insn ""
5855 [(set (match_operand:QI 0 "register_operand" "=d") 5977 [(set (match_operand:QI 0 "register_operand" "=d")
5856 (eq:QI (cc0) (const_int 0)))] 5978 (eq:QI (cc0) (const_int 0)))]
5857 "" 5979 ""
5858 { 5980 {
5859 cc_status = cc_prev_status; 5981 cc_status = cc_prev_status;
5860 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0"); 5982 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5861 }) 5983 })
5862 5984
5863 (define_expand "sne"
5864 [(set (match_operand:QI 0 "register_operand" "")
5865 (ne:QI (cc0) (const_int 0)))]
5866 ""
5867 {
5868 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5869 && m68k_last_compare_had_fp_operands)
5870 {
5871 m68k_last_compare_had_fp_operands = 0;
5872 FAIL;
5873 }
5874 })
5875
5876 (define_insn "" 5985 (define_insn ""
5877 [(set (match_operand:QI 0 "register_operand" "=d") 5986 [(set (match_operand:QI 0 "register_operand" "=d")
5878 (ne:QI (cc0) (const_int 0)))] 5987 (ne:QI (cc0) (const_int 0)))]
5879 "" 5988 ""
5880 { 5989 {
5881 cc_status = cc_prev_status; 5990 cc_status = cc_prev_status;
5882 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0"); 5991 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5883 }) 5992 })
5884 5993
5885 (define_expand "sgt"
5886 [(set (match_operand:QI 0 "register_operand" "")
5887 (gt:QI (cc0) (const_int 0)))]
5888 ""
5889 {
5890 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5891 && m68k_last_compare_had_fp_operands)
5892 {
5893 m68k_last_compare_had_fp_operands = 0;
5894 FAIL;
5895 }
5896 })
5897
5898 (define_insn "" 5994 (define_insn ""
5899 [(set (match_operand:QI 0 "register_operand" "=d") 5995 [(set (match_operand:QI 0 "register_operand" "=d")
5900 (gt:QI (cc0) (const_int 0)))] 5996 (gt:QI (cc0) (const_int 0)))]
5901 "" 5997 ""
5902 { 5998 {
5903 cc_status = cc_prev_status; 5999 cc_status = cc_prev_status;
5904 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0); 6000 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5905 }) 6001 })
5906 6002
5907 (define_expand "sgtu"
5908 [(set (match_operand:QI 0 "register_operand" "")
5909 (gtu:QI (cc0) (const_int 0)))]
5910 ""
5911 "")
5912
5913 (define_insn "" 6003 (define_insn ""
5914 [(set (match_operand:QI 0 "register_operand" "=d") 6004 [(set (match_operand:QI 0 "register_operand" "=d")
5915 (gtu:QI (cc0) (const_int 0)))] 6005 (gtu:QI (cc0) (const_int 0)))]
5916 "" 6006 ""
5917 { 6007 {
5918 cc_status = cc_prev_status; 6008 cc_status = cc_prev_status;
5919 return "shi %0"; 6009 return "shi %0";
5920 }) 6010 })
5921 6011
5922 (define_expand "slt"
5923 [(set (match_operand:QI 0 "register_operand" "")
5924 (lt:QI (cc0) (const_int 0)))]
5925 ""
5926 {
5927 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5928 && m68k_last_compare_had_fp_operands)
5929 {
5930 m68k_last_compare_had_fp_operands = 0;
5931 FAIL;
5932 }
5933 })
5934
5935 (define_insn "" 6012 (define_insn ""
5936 [(set (match_operand:QI 0 "register_operand" "=d") 6013 [(set (match_operand:QI 0 "register_operand" "=d")
5937 (lt:QI (cc0) (const_int 0)))] 6014 (lt:QI (cc0) (const_int 0)))]
5938 "" 6015 ""
5939 { 6016 {
5940 cc_status = cc_prev_status; 6017 cc_status = cc_prev_status;
5941 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0"); 6018 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5942 }) 6019 })
5943 6020
5944 (define_expand "sltu"
5945 [(set (match_operand:QI 0 "register_operand" "")
5946 (ltu:QI (cc0) (const_int 0)))]
5947 ""
5948 "")
5949
5950 (define_insn "" 6021 (define_insn ""
5951 [(set (match_operand:QI 0 "register_operand" "=d") 6022 [(set (match_operand:QI 0 "register_operand" "=d")
5952 (ltu:QI (cc0) (const_int 0)))] 6023 (ltu:QI (cc0) (const_int 0)))]
5953 "" 6024 ""
5954 { 6025 {
5955 cc_status = cc_prev_status; 6026 cc_status = cc_prev_status;
5956 return "scs %0"; 6027 return "scs %0";
5957 }) 6028 })
5958 6029
5959 (define_expand "sge"
5960 [(set (match_operand:QI 0 "register_operand" "")
5961 (ge:QI (cc0) (const_int 0)))]
5962 ""
5963 {
5964 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5965 && m68k_last_compare_had_fp_operands)
5966 {
5967 m68k_last_compare_had_fp_operands = 0;
5968 FAIL;
5969 }
5970 })
5971
5972 (define_insn "" 6030 (define_insn ""
5973 [(set (match_operand:QI 0 "register_operand" "=d") 6031 [(set (match_operand:QI 0 "register_operand" "=d")
5974 (ge:QI (cc0) (const_int 0)))] 6032 (ge:QI (cc0) (const_int 0)))]
5975 "" 6033 ""
5976 { 6034 {
5977 cc_status = cc_prev_status; 6035 cc_status = cc_prev_status;
5978 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0"); 6036 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
5979 }) 6037 })
5980
5981 (define_expand "sgeu"
5982 [(set (match_operand:QI 0 "register_operand" "")
5983 (geu:QI (cc0) (const_int 0)))]
5984 ""
5985 "")
5986 6038
5987 (define_insn "*scc" 6039 (define_insn "*scc"
5988 [(set (match_operand:QI 0 "register_operand" "=d") 6040 [(set (match_operand:QI 0 "register_operand" "=d")
5989 (geu:QI (cc0) (const_int 0)))] 6041 (geu:QI (cc0) (const_int 0)))]
5990 "" 6042 ""
5992 cc_status = cc_prev_status; 6044 cc_status = cc_prev_status;
5993 return "scc %0"; 6045 return "scc %0";
5994 } 6046 }
5995 [(set_attr "type" "scc")]) 6047 [(set_attr "type" "scc")])
5996 6048
5997 (define_expand "sle"
5998 [(set (match_operand:QI 0 "register_operand" "")
5999 (le:QI (cc0) (const_int 0)))]
6000 ""
6001 {
6002 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
6003 && m68k_last_compare_had_fp_operands)
6004 {
6005 m68k_last_compare_had_fp_operands = 0;
6006 FAIL;
6007 }
6008 })
6009
6010 (define_insn "" 6049 (define_insn ""
6011 [(set (match_operand:QI 0 "register_operand" "=d") 6050 [(set (match_operand:QI 0 "register_operand" "=d")
6012 (le:QI (cc0) (const_int 0)))] 6051 (le:QI (cc0) (const_int 0)))]
6013 "" 6052 ""
6014 { 6053 {
6015 cc_status = cc_prev_status; 6054 cc_status = cc_prev_status;
6016 OUTPUT_JUMP ("sle %0", "fsle %0", 0); 6055 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
6017 }) 6056 })
6018
6019 (define_expand "sleu"
6020 [(set (match_operand:QI 0 "register_operand" "")
6021 (leu:QI (cc0) (const_int 0)))]
6022 ""
6023 "")
6024 6057
6025 (define_insn "*sls" 6058 (define_insn "*sls"
6026 [(set (match_operand:QI 0 "register_operand" "=d") 6059 [(set (match_operand:QI 0 "register_operand" "=d")
6027 (leu:QI (cc0) (const_int 0)))] 6060 (leu:QI (cc0) (const_int 0)))]
6028 "" 6061 ""
6029 { 6062 {
6030 cc_status = cc_prev_status; 6063 cc_status = cc_prev_status;
6031 return "sls %0"; 6064 return "sls %0";
6032 } 6065 }
6033 [(set_attr "type" "scc")]) 6066 [(set_attr "type" "scc")])
6034
6035 (define_expand "sordered"
6036 [(set (match_operand:QI 0 "register_operand" "")
6037 (ordered:QI (cc0) (const_int 0)))]
6038 "TARGET_68881 && !TUNE_68060"
6039 {
6040 gcc_assert (m68k_last_compare_had_fp_operands);
6041 m68k_last_compare_had_fp_operands = 0;
6042 })
6043 6067
6044 (define_insn "*sordered_1" 6068 (define_insn "*sordered_1"
6045 [(set (match_operand:QI 0 "register_operand" "=d") 6069 [(set (match_operand:QI 0 "register_operand" "=d")
6046 (ordered:QI (cc0) (const_int 0)))] 6070 (ordered:QI (cc0) (const_int 0)))]
6047 "TARGET_68881 && !TUNE_68060" 6071 "TARGET_68881 && !TUNE_68060"
6048 { 6072 {
6049 cc_status = cc_prev_status; 6073 cc_status = cc_prev_status;
6050 return "fsor %0"; 6074 return "fsor %0";
6051 }) 6075 })
6052 6076
6053 (define_expand "sunordered"
6054 [(set (match_operand:QI 0 "register_operand" "")
6055 (unordered:QI (cc0) (const_int 0)))]
6056 "TARGET_68881 && !TUNE_68060"
6057 {
6058 gcc_assert (m68k_last_compare_had_fp_operands);
6059 m68k_last_compare_had_fp_operands = 0;
6060 })
6061
6062 (define_insn "*sunordered_1" 6077 (define_insn "*sunordered_1"
6063 [(set (match_operand:QI 0 "register_operand" "=d") 6078 [(set (match_operand:QI 0 "register_operand" "=d")
6064 (unordered:QI (cc0) (const_int 0)))] 6079 (unordered:QI (cc0) (const_int 0)))]
6065 "TARGET_68881 && !TUNE_68060" 6080 "TARGET_68881 && !TUNE_68060"
6066 { 6081 {
6067 cc_status = cc_prev_status; 6082 cc_status = cc_prev_status;
6068 return "fsun %0"; 6083 return "fsun %0";
6069 }) 6084 })
6070 6085
6071 (define_expand "suneq"
6072 [(set (match_operand:QI 0 "register_operand" "")
6073 (uneq:QI (cc0) (const_int 0)))]
6074 "TARGET_68881 && !TUNE_68060"
6075 {
6076 gcc_assert (m68k_last_compare_had_fp_operands);
6077 m68k_last_compare_had_fp_operands = 0;
6078 })
6079
6080 (define_insn "*suneq_1" 6086 (define_insn "*suneq_1"
6081 [(set (match_operand:QI 0 "register_operand" "=d") 6087 [(set (match_operand:QI 0 "register_operand" "=d")
6082 (uneq:QI (cc0) (const_int 0)))] 6088 (uneq:QI (cc0) (const_int 0)))]
6083 "TARGET_68881 && !TUNE_68060" 6089 "TARGET_68881 && !TUNE_68060"
6084 { 6090 {
6085 cc_status = cc_prev_status; 6091 cc_status = cc_prev_status;
6086 return "fsueq %0"; 6092 return "fsueq %0";
6087 }) 6093 })
6088 6094
6089 (define_expand "sunge"
6090 [(set (match_operand:QI 0 "register_operand" "")
6091 (unge:QI (cc0) (const_int 0)))]
6092 "TARGET_68881 && !TUNE_68060"
6093 {
6094 gcc_assert (m68k_last_compare_had_fp_operands);
6095 m68k_last_compare_had_fp_operands = 0;
6096 })
6097
6098 (define_insn "*sunge_1" 6095 (define_insn "*sunge_1"
6099 [(set (match_operand:QI 0 "register_operand" "=d") 6096 [(set (match_operand:QI 0 "register_operand" "=d")
6100 (unge:QI (cc0) (const_int 0)))] 6097 (unge:QI (cc0) (const_int 0)))]
6101 "TARGET_68881 && !TUNE_68060" 6098 "TARGET_68881 && !TUNE_68060"
6102 { 6099 {
6103 cc_status = cc_prev_status; 6100 cc_status = cc_prev_status;
6104 return "fsuge %0"; 6101 return "fsuge %0";
6105 }) 6102 })
6106 6103
6107 (define_expand "sungt"
6108 [(set (match_operand:QI 0 "register_operand" "")
6109 (ungt:QI (cc0) (const_int 0)))]
6110 "TARGET_68881 && !TUNE_68060"
6111 {
6112 gcc_assert (m68k_last_compare_had_fp_operands);
6113 m68k_last_compare_had_fp_operands = 0;
6114 })
6115
6116 (define_insn "*sungt_1" 6104 (define_insn "*sungt_1"
6117 [(set (match_operand:QI 0 "register_operand" "=d") 6105 [(set (match_operand:QI 0 "register_operand" "=d")
6118 (ungt:QI (cc0) (const_int 0)))] 6106 (ungt:QI (cc0) (const_int 0)))]
6119 "TARGET_68881 && !TUNE_68060" 6107 "TARGET_68881 && !TUNE_68060"
6120 { 6108 {
6121 cc_status = cc_prev_status; 6109 cc_status = cc_prev_status;
6122 return "fsugt %0"; 6110 return "fsugt %0";
6123 }) 6111 })
6124 6112
6125 (define_expand "sunle"
6126 [(set (match_operand:QI 0 "register_operand" "")
6127 (unle:QI (cc0) (const_int 0)))]
6128 "TARGET_68881 && !TUNE_68060"
6129 {
6130 gcc_assert (m68k_last_compare_had_fp_operands);
6131 m68k_last_compare_had_fp_operands = 0;
6132 })
6133
6134 (define_insn "*sunle_1" 6113 (define_insn "*sunle_1"
6135 [(set (match_operand:QI 0 "register_operand" "=d") 6114 [(set (match_operand:QI 0 "register_operand" "=d")
6136 (unle:QI (cc0) (const_int 0)))] 6115 (unle:QI (cc0) (const_int 0)))]
6137 "TARGET_68881 && !TUNE_68060" 6116 "TARGET_68881 && !TUNE_68060"
6138 { 6117 {
6139 cc_status = cc_prev_status; 6118 cc_status = cc_prev_status;
6140 return "fsule %0"; 6119 return "fsule %0";
6141 }) 6120 })
6142 6121
6143 (define_expand "sunlt"
6144 [(set (match_operand:QI 0 "register_operand" "")
6145 (unlt:QI (cc0) (const_int 0)))]
6146 "TARGET_68881 && !TUNE_68060"
6147 {
6148 gcc_assert (m68k_last_compare_had_fp_operands);
6149 m68k_last_compare_had_fp_operands = 0;
6150 })
6151
6152 (define_insn "*sunlt_1" 6122 (define_insn "*sunlt_1"
6153 [(set (match_operand:QI 0 "register_operand" "=d") 6123 [(set (match_operand:QI 0 "register_operand" "=d")
6154 (unlt:QI (cc0) (const_int 0)))] 6124 (unlt:QI (cc0) (const_int 0)))]
6155 "TARGET_68881 && !TUNE_68060" 6125 "TARGET_68881 && !TUNE_68060"
6156 { 6126 {
6157 cc_status = cc_prev_status; 6127 cc_status = cc_prev_status;
6158 return "fsult %0"; 6128 return "fsult %0";
6159 })
6160
6161 (define_expand "sltgt"
6162 [(set (match_operand:QI 0 "register_operand" "")
6163 (ltgt:QI (cc0) (const_int 0)))]
6164 "TARGET_68881 && !TUNE_68060"
6165 {
6166 gcc_assert (m68k_last_compare_had_fp_operands);
6167 m68k_last_compare_had_fp_operands = 0;
6168 }) 6129 })
6169 6130
6170 (define_insn "*sltgt_1" 6131 (define_insn "*sltgt_1"
6171 [(set (match_operand:QI 0 "register_operand" "=d") 6132 [(set (match_operand:QI 0 "register_operand" "=d")
6172 (ltgt:QI (cc0) (const_int 0)))] 6133 (ltgt:QI (cc0) (const_int 0)))]
7756 [(trap_if (const_int 1) (const_int 7))] 7717 [(trap_if (const_int 1) (const_int 7))]
7757 "" 7718 ""
7758 "trap #7" 7719 "trap #7"
7759 [(set_attr "type" "trap")]) 7720 [(set_attr "type" "trap")])
7760 7721
7761 (define_expand "conditional_trap" 7722 (define_expand "ctrapdi4"
7762 [(trap_if (match_operator 0 "valid_dbcc_comparison_p" 7723 [(trap_if (match_operator 0 "ordered_comparison_operator"
7763 [(cc0) (const_int 0)]) 7724 [(cc0) (const_int 0)])
7764 (match_operand:SI 1 "const_int_operand" "I"))] 7725 (match_operand:SI 3 "const1_operand" ""))]
7765 "TARGET_68020" 7726 "TARGET_68020"
7766 { 7727 {
7767 if (m68k_last_compare_had_fp_operands) 7728 if (operands[2] == const0_rtx)
7768 { 7729 emit_insn (gen_tstdi (operands[1]));
7769 m68k_last_compare_had_fp_operands = 0; 7730 else
7770 FAIL; 7731 emit_insn (gen_cmpdi (operands[1], operands[2]));
7771 } 7732 operands[1] = cc0_rtx;
7772 }) 7733 operands[2] = const0_rtx;
7734 })
7735
7736 (define_expand "ctrapsi4"
7737 [(set (cc0)
7738 (compare (match_operand:SI 1 "nonimmediate_operand" "")
7739 (match_operand:SI 2 "general_operand" "")))
7740 (trap_if (match_operator 0 "ordered_comparison_operator"
7741 [(cc0) (const_int 0)])
7742 (match_operand:SI 3 "const1_operand" ""))]
7743 "TARGET_68020"
7744 "")
7745
7746 (define_expand "ctraphi4"
7747 [(set (cc0)
7748 (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
7749 (match_operand:HI 2 "general_src_operand" "")))
7750 (trap_if (match_operator 0 "ordered_comparison_operator"
7751 [(cc0) (const_int 0)])
7752 (match_operand:SI 3 "const1_operand" ""))]
7753 "TARGET_68020"
7754 "")
7755
7756 (define_expand "ctrapqi4"
7757 [(set (cc0)
7758 (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
7759 (match_operand:QI 2 "general_src_operand" "")))
7760 (trap_if (match_operator 0 "ordered_comparison_operator"
7761 [(cc0) (const_int 0)])
7762 (match_operand:SI 3 "const1_operand" ""))]
7763 "TARGET_68020"
7764 "")
7773 7765
7774 (define_insn "*conditional_trap" 7766 (define_insn "*conditional_trap"
7775 [(trap_if (match_operator 0 "valid_dbcc_comparison_p" 7767 [(trap_if (match_operator 0 "ordered_comparison_operator"
7776 [(cc0) (const_int 0)]) 7768 [(cc0) (const_int 0)])
7777 (match_operand:SI 1 "const_int_operand" "I"))] 7769 (match_operand:SI 1 "const1_operand" "I"))]
7778 "TARGET_68020 && ! flags_in_68881 ()" 7770 "TARGET_68020 && ! flags_in_68881 ()"
7779 { 7771 {
7780 switch (GET_CODE (operands[0])) 7772 switch (GET_CODE (operands[0]))
7781 { 7773 {
7782 case EQ: return "trapeq"; 7774 case EQ: return "trapeq";