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comparison gcc/config/mcore/mcore.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
301 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r") 301 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
302 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))] 302 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
303 "" 303 ""
304 "cmphs %1,%0") 304 "cmphs %1,%0")
305 305
306 ;; We save the compare operands in the cmpxx patterns and use them when
307 ;; we generate the branch.
308
309 ;; We accept constants here, in case we can modify them to ones which
310 ;; are more efficient to load. E.g. change 'x <= 62' to 'x < 63'.
311
312 (define_expand "cmpsi"
313 [(set (reg:CC 17) (compare:CC (match_operand:SI 0 "mcore_compare_operand" "")
314 (match_operand:SI 1 "nonmemory_operand" "")))]
315 ""
316 "
317 { arch_compare_op0 = operands[0];
318 arch_compare_op1 = operands[1];
319 DONE;
320 }")
321
322 ;; ------------------------------------------------------------------------- 306 ;; -------------------------------------------------------------------------
323 ;; Logical operations 307 ;; Logical operations
324 ;; ------------------------------------------------------------------------- 308 ;; -------------------------------------------------------------------------
325 309
326 ;; Logical AND clearing a single bit. andsi3 knows that we have this 310 ;; Logical AND clearing a single bit. andsi3 knows that we have this
1477 1461
1478 ;; ------------------------------------------------------------------------ 1462 ;; ------------------------------------------------------------------------
1479 ;; Define the real conditional branch instructions. 1463 ;; Define the real conditional branch instructions.
1480 ;; ------------------------------------------------------------------------ 1464 ;; ------------------------------------------------------------------------
1481 1465
1466 ;; At top-level, condition test are eq/ne, because we
1467 ;; are comparing against the condition register (which
1468 ;; has the result of the true relational test
1469
1482 (define_insn "branch_true" 1470 (define_insn "branch_true"
1483 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0)) 1471 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1484 (label_ref (match_operand 0 "" "")) 1472 (label_ref (match_operand 0 "" ""))
1485 (pc)))] 1473 (pc)))]
1486 "" 1474 ""
1511 "jbt %l0" 1499 "jbt %l0"
1512 [(set_attr "type" "brcond")]) 1500 [(set_attr "type" "brcond")])
1513 1501
1514 ;; Conditional branch insns 1502 ;; Conditional branch insns
1515 1503
1516 ;; At top-level, condition test are eq/ne, because we 1504 (define_expand "cbranchsi4"
1517 ;; are comparing against the condition register (which 1505 [(set (pc)
1518 ;; has the result of the true relational test 1506 (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
1519 1507 [(match_operand:SI 1 "mcore_compare_operand")
1520 ; There is no beq compare, so we reverse the branch arms. 1508 (match_operand:SI 2 "nonmemory_operand")])
1521 1509 (label_ref (match_operand 3 ""))
1522 (define_expand "beq" 1510 (pc)))]
1523 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1524 (pc)
1525 (label_ref (match_operand 0 "" ""))))]
1526 "" 1511 ""
1527 " 1512 "
1528 { 1513 {
1529 operands[1] = mcore_gen_compare_reg (EQ); 1514 bool invert;
1515 invert = mcore_gen_compare (GET_CODE (operands[0]),
1516 operands[1], operands[2]);
1517
1518 if (invert)
1519 emit_jump_insn (gen_branch_false (operands[3]));
1520 else
1521 emit_jump_insn (gen_branch_true (operands[3]));
1522 DONE;
1530 }") 1523 }")
1531 1524
1532 (define_expand "bne" 1525
1533 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1534 (label_ref (match_operand 0 "" ""))
1535 (pc)))]
1536 ""
1537 "
1538 {
1539 operands[1] = mcore_gen_compare_reg (NE);
1540 }")
1541
1542 ; check whether (GT A imm) can become (LE A imm) with the branch reversed.
1543 ; if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
1544
1545 (define_expand "bgt"
1546 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1547 (label_ref (match_operand 0 "" ""))
1548 (pc)))]
1549 ""
1550 "
1551 {
1552 if (mcore_modify_comparison (LE))
1553 {
1554 emit_jump_insn (gen_reverse_blt (operands[0]));
1555 DONE;
1556 }
1557 operands[1] = mcore_gen_compare_reg (GT);
1558 }")
1559
1560 ; There is no ble compare, so we reverse the branch arms.
1561 ; reversed the condition and branch arms for ble -- the check_dbra_loop()
1562 ; transformation assumes that ble uses a branch-true with the label as
1563 ; as the target. BRC
1564
1565 ; check whether (LE A imm) can become (LT A imm + 1).
1566
1567 (define_expand "ble"
1568 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
1569 (label_ref (match_operand 0 "" ""))
1570 (pc)))]
1571 ""
1572 "
1573 {
1574 if (mcore_modify_comparison (LE))
1575 {
1576 emit_jump_insn (gen_blt (operands[0]));
1577 DONE;
1578 }
1579 operands[1] = mcore_gen_compare_reg (LE);
1580 }")
1581
1582 ; make generating a reversed blt simple
1583 (define_expand "reverse_blt"
1584 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1585 (pc)
1586 (label_ref (match_operand 0 "" ""))))]
1587 ""
1588 "
1589 {
1590 operands[1] = mcore_gen_compare_reg (LT);
1591 }")
1592
1593 (define_expand "blt"
1594 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1595 (label_ref (match_operand 0 "" ""))
1596 (pc)))]
1597 ""
1598 "
1599 {
1600 operands[1] = mcore_gen_compare_reg (LT);
1601 }")
1602
1603 ; There is no bge compare, so we reverse the branch arms.
1604
1605 (define_expand "bge"
1606 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1607 (pc)
1608 (label_ref (match_operand 0 "" ""))))]
1609 ""
1610 "
1611 {
1612 operands[1] = mcore_gen_compare_reg (GE);
1613 }")
1614
1615 ; There is no gtu compare, so we reverse the branch arms
1616
1617 ;(define_expand "bgtu"
1618 ; [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1619 ; (pc)
1620 ; (label_ref (match_operand 0 "" ""))))]
1621 ; ""
1622 ; "
1623 ;{
1624 ; if (GET_CODE (arch_compare_op1) == CONST_INT
1625 ; && INTVAL (arch_compare_op1) == 0)
1626 ; operands[1] = mcore_gen_compare_reg (NE);
1627 ; else
1628 ; { if (mcore_modify_comparison (GTU))
1629 ; {
1630 ; emit_jump_insn (gen_bgeu (operands[0]));
1631 ; DONE;
1632 ; }
1633 ; operands[1] = mcore_gen_compare_reg (LEU);
1634 ; }
1635 ;}")
1636
1637 (define_expand "bgtu"
1638 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1639 (pc)
1640 (label_ref (match_operand 0 "" ""))))]
1641 ""
1642 "
1643 {
1644 if (GET_CODE (arch_compare_op1) == CONST_INT
1645 && INTVAL (arch_compare_op1) == 0)
1646 {
1647 /* The inverse of '> 0' for an unsigned test is
1648 '== 0' but we do not have such an instruction available.
1649 Instead we must reverse the branch (back to the normal
1650 ordering) and test '!= 0'. */
1651
1652 operands[1] = mcore_gen_compare_reg (NE);
1653
1654 emit_jump_insn (gen_rtx_SET (VOIDmode,
1655 pc_rtx,
1656 gen_rtx_IF_THEN_ELSE (VOIDmode,
1657 gen_rtx_NE (VOIDmode,
1658 operands[1],
1659 const0_rtx),
1660 gen_rtx_LABEL_REF (VOIDmode,operands[0]),
1661 pc_rtx)));
1662 DONE;
1663 }
1664 operands[1] = mcore_gen_compare_reg (GTU);
1665 }")
1666
1667
1668 (define_expand "bleu"
1669 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1670 (label_ref (match_operand 0 "" ""))
1671 (pc)))]
1672 ""
1673 "
1674 {
1675 operands[1] = mcore_gen_compare_reg (LEU);
1676 }")
1677
1678 ; There is no bltu compare, so we reverse the branch arms
1679 (define_expand "bltu"
1680 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1681 (pc)
1682 (label_ref (match_operand 0 "" ""))))]
1683 ""
1684 "
1685 {
1686 operands[1] = mcore_gen_compare_reg (LTU);
1687 }")
1688
1689 (define_expand "bgeu"
1690 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1691 (label_ref (match_operand 0 "" ""))
1692 (pc)))]
1693 ""
1694 "
1695 {
1696
1697 operands[1] = mcore_gen_compare_reg (GEU);
1698 }")
1699 1526
1700 ;; ------------------------------------------------------------------------ 1527 ;; ------------------------------------------------------------------------
1701 ;; Jump and linkage insns 1528 ;; Jump and linkage insns
1702 ;; ------------------------------------------------------------------------ 1529 ;; ------------------------------------------------------------------------
1703 1530
1851 [(set (reg:CC 17) 1678 [(set (reg:CC 17)
1852 (lt:CC (match_dup 1) (const_int 1))) 1679 (lt:CC (match_dup 1) (const_int 1)))
1853 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))]) 1680 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
1854 1681
1855 1682
1856 (define_expand "seq" 1683 (define_expand "cstoresi4"
1857 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "") 1684 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1858 (eq:SI (match_dup 1) (const_int 0)))] 1685 (match_operator:SI 1 "ordered_comparison_operator"
1686 [(match_operand:SI 2 "mcore_compare_operand" "")
1687 (match_operand:SI 3 "nonmemory_operand" "")]))]
1859 "" 1688 ""
1860 " 1689 "
1861 { 1690 {
1862 operands[1] = mcore_gen_compare_reg (NE); 1691 bool invert;
1863 }") 1692 invert = mcore_gen_compare (GET_CODE (operands[1]),
1864 1693 operands[2], operands[3]);
1865 (define_expand "sne" 1694
1866 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "") 1695 if (invert)
1867 (ne:SI (match_dup 1) (const_int 0)))] 1696 emit_insn (gen_mvcv (operands[0]));
1868 "" 1697 else
1869 " 1698 emit_insn (gen_mvc (operands[0]));
1870 { 1699 DONE;
1871 operands[1] = mcore_gen_compare_reg (NE);
1872 }")
1873
1874 (define_expand "slt"
1875 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1876 (ne:SI (match_dup 1) (const_int 0)))]
1877 ""
1878 "
1879 {
1880 operands[1] = mcore_gen_compare_reg (LT);
1881 }")
1882
1883 ; make generating a LT with the comparison reversed easy. BRC
1884 (define_expand "reverse_slt"
1885 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1886 (eq:SI (match_dup 1) (const_int 0)))]
1887 ""
1888 "
1889 {
1890 operands[1] = mcore_gen_compare_reg (LT);
1891 }")
1892
1893 (define_expand "sge"
1894 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1895 (eq:SI (match_dup 1) (const_int 0)))]
1896 ""
1897 "
1898 {
1899 operands[1] = mcore_gen_compare_reg (LT);
1900 }")
1901
1902 ; check whether (GT A imm) can become (LE A imm) with the comparison
1903 ; reversed. if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
1904
1905 (define_expand "sgt"
1906 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1907 (ne:SI (match_dup 1) (const_int 0)))]
1908 ""
1909 "
1910 {
1911 if (mcore_modify_comparison (LE))
1912 {
1913 emit_insn (gen_reverse_slt (operands[0]));
1914 DONE;
1915 }
1916
1917 operands[1] = mcore_gen_compare_reg (GT);
1918 }")
1919
1920 (define_expand "sle"
1921 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1922 (eq:SI (match_dup 1) (const_int 0)))]
1923 ""
1924 "
1925 {
1926 if (mcore_modify_comparison (LE))
1927 {
1928 emit_insn (gen_slt (operands[0]));
1929 DONE;
1930 }
1931 operands[1] = mcore_gen_compare_reg (GT);
1932 }")
1933
1934 (define_expand "sltu"
1935 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1936 (eq:SI (match_dup 1) (const_int 0)))]
1937 ""
1938 "
1939 {
1940 operands[1] = mcore_gen_compare_reg (GEU);
1941 }")
1942
1943 (define_expand "sgeu"
1944 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1945 (ne:SI (match_dup 1) (const_int 0)))]
1946 ""
1947 "
1948 {
1949 operands[1] = mcore_gen_compare_reg (GEU);
1950 }")
1951
1952 (define_expand "sgtu"
1953 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1954 (eq:SI (match_dup 1) (const_int 0)))]
1955 ""
1956 "
1957 {
1958 operands[1] = mcore_gen_compare_reg (LEU);
1959 }")
1960
1961 (define_expand "sleu"
1962 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1963 (ne:SI (match_dup 1) (const_int 0)))]
1964 ""
1965 "
1966 {
1967 operands[1] = mcore_gen_compare_reg (LEU);
1968 }") 1700 }")
1969 1701
1970 (define_insn "incscc" 1702 (define_insn "incscc"
1971 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r") 1703 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1972 (plus:SI (ne (reg:CC 17) (const_int 0)) 1704 (plus:SI (ne (reg:CC 17) (const_int 0))
3306 { 3038 {
3307 rtx out_label = 0; 3039 rtx out_label = 0;
3308 rtx loop_label = gen_label_rtx (); 3040 rtx loop_label = gen_label_rtx ();
3309 rtx step = gen_reg_rtx (Pmode); 3041 rtx step = gen_reg_rtx (Pmode);
3310 rtx tmp = gen_reg_rtx (Pmode); 3042 rtx tmp = gen_reg_rtx (Pmode);
3311 rtx memref; 3043 rtx test, memref;
3312 3044
3313 #if 1 3045 #if 1
3314 emit_insn (gen_movsi (tmp, operands[1])); 3046 emit_insn (gen_movsi (tmp, operands[1]));
3315 emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP))); 3047 emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP)));
3316 3048
3317 if (GET_CODE (operands[1]) != CONST_INT) 3049 if (GET_CODE (operands[1]) != CONST_INT)
3318 { 3050 {
3319 out_label = gen_label_rtx (); 3051 out_label = gen_label_rtx ();
3320 emit_insn (gen_cmpsi (step, tmp)); /* quick out */ 3052 test = gen_rtx_GEU (VOIDmode, step, tmp); /* quick out */
3321 emit_jump_insn (gen_bgeu (out_label)); 3053 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, out_label));
3322 } 3054 }
3323 3055
3324 /* Run a loop that steps it incrementally. */ 3056 /* Run a loop that steps it incrementally. */
3325 emit_label (loop_label); 3057 emit_label (loop_label);
3326 3058
3330 MEM_VOLATILE_P (memref) = 1; 3062 MEM_VOLATILE_P (memref) = 1;
3331 emit_insn(gen_movsi(memref, stack_pointer_rtx)); 3063 emit_insn(gen_movsi(memref, stack_pointer_rtx));
3332 emit_insn(gen_subsi3(tmp, tmp, step)); 3064 emit_insn(gen_subsi3(tmp, tmp, step));
3333 3065
3334 /* Loop condition -- going back up. */ 3066 /* Loop condition -- going back up. */
3335 emit_insn (gen_cmpsi (step, tmp)); 3067 test = gen_rtx_LTU (VOIDmode, step, tmp);
3336 emit_jump_insn (gen_bltu (loop_label)); 3068 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, loop_label));
3337 3069
3338 if (out_label) 3070 if (out_label)
3339 emit_label (out_label); 3071 emit_label (out_label);
3340 3072
3341 /* Bump the residual. */ 3073 /* Bump the residual. */