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comparison gcc/config/pa/pa.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents 3bfb6c00c1e0
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
651 (include "constraints.md") 651 (include "constraints.md")
652 652
653 ;; Compare instructions. 653 ;; Compare instructions.
654 ;; This controls RTL generation and register allocation. 654 ;; This controls RTL generation and register allocation.
655 655
656 ;; We generate RTL for comparisons and branches by having the cmpxx
657 ;; patterns store away the operands. Then, the scc and bcc patterns
658 ;; emit RTL for both the compare and the branch.
659 ;;
660
661 (define_expand "cmpdi"
662 [(set (reg:CC 0)
663 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
664 (match_operand:DI 1 "register_operand" "")))]
665 "TARGET_64BIT"
666
667 "
668 {
669 hppa_compare_op0 = operands[0];
670 hppa_compare_op1 = operands[1];
671 hppa_branch_type = CMP_SI;
672 DONE;
673 }")
674
675 (define_expand "cmpsi"
676 [(set (reg:CC 0)
677 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
678 (match_operand:SI 1 "arith5_operand" "")))]
679 ""
680 "
681 {
682 hppa_compare_op0 = operands[0];
683 hppa_compare_op1 = operands[1];
684 hppa_branch_type = CMP_SI;
685 DONE;
686 }")
687
688 (define_expand "cmpsf"
689 [(set (reg:CCFP 0)
690 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
691 (match_operand:SF 1 "reg_or_0_operand" "")))]
692 "! TARGET_SOFT_FLOAT"
693 "
694 {
695 hppa_compare_op0 = operands[0];
696 hppa_compare_op1 = operands[1];
697 hppa_branch_type = CMP_SF;
698 DONE;
699 }")
700
701 (define_expand "cmpdf"
702 [(set (reg:CCFP 0)
703 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
704 (match_operand:DF 1 "reg_or_0_operand" "")))]
705 "! TARGET_SOFT_FLOAT"
706 "
707 {
708 hppa_compare_op0 = operands[0];
709 hppa_compare_op1 = operands[1];
710 hppa_branch_type = CMP_DF;
711 DONE;
712 }")
713
714 (define_insn "" 656 (define_insn ""
715 [(set (reg:CCFP 0) 657 [(set (reg:CCFP 0)
716 (match_operator:CCFP 2 "comparison_operator" 658 (match_operator:CCFP 2 "comparison_operator"
717 [(match_operand:SF 0 "reg_or_0_operand" "fG") 659 [(match_operand:SF 0 "reg_or_0_operand" "fG")
718 (match_operand:SF 1 "reg_or_0_operand" "fG")]))] 660 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
765 [(set_attr "length" "4") 707 [(set_attr "length" "4")
766 (set_attr "type" "fpcc")]) 708 (set_attr "type" "fpcc")])
767 709
768 ;; scc insns. 710 ;; scc insns.
769 711
770 (define_expand "seq" 712 (define_expand "cstoresi4"
771 [(set (match_operand:SI 0 "register_operand" "") 713 [(set (match_operand:SI 0 "register_operand")
772 (eq:SI (match_dup 1) 714 (match_operator:SI 1 "ordered_comparison_operator"
773 (match_dup 2)))] 715 [(match_operand:SI 2 "reg_or_0_operand" "")
716 (match_operand:SI 3 "arith5_operand" "")]))]
774 "!TARGET_64BIT" 717 "!TARGET_64BIT"
775 " 718 "")
776 {
777 /* fp scc patterns rarely match, and are not a win on the PA. */
778 if (hppa_branch_type != CMP_SI)
779 FAIL;
780 /* set up operands from compare. */
781 operands[1] = hppa_compare_op0;
782 operands[2] = hppa_compare_op1;
783 /* fall through and generate default code */
784 }")
785
786 (define_expand "sne"
787 [(set (match_operand:SI 0 "register_operand" "")
788 (ne:SI (match_dup 1)
789 (match_dup 2)))]
790 "!TARGET_64BIT"
791 "
792 {
793 /* fp scc patterns rarely match, and are not a win on the PA. */
794 if (hppa_branch_type != CMP_SI)
795 FAIL;
796 operands[1] = hppa_compare_op0;
797 operands[2] = hppa_compare_op1;
798 }")
799
800 (define_expand "slt"
801 [(set (match_operand:SI 0 "register_operand" "")
802 (lt:SI (match_dup 1)
803 (match_dup 2)))]
804 "!TARGET_64BIT"
805 "
806 {
807 /* fp scc patterns rarely match, and are not a win on the PA. */
808 if (hppa_branch_type != CMP_SI)
809 FAIL;
810 operands[1] = hppa_compare_op0;
811 operands[2] = hppa_compare_op1;
812 }")
813
814 (define_expand "sgt"
815 [(set (match_operand:SI 0 "register_operand" "")
816 (gt:SI (match_dup 1)
817 (match_dup 2)))]
818 "!TARGET_64BIT"
819 "
820 {
821 /* fp scc patterns rarely match, and are not a win on the PA. */
822 if (hppa_branch_type != CMP_SI)
823 FAIL;
824 operands[1] = hppa_compare_op0;
825 operands[2] = hppa_compare_op1;
826 }")
827
828 (define_expand "sle"
829 [(set (match_operand:SI 0 "register_operand" "")
830 (le:SI (match_dup 1)
831 (match_dup 2)))]
832 "!TARGET_64BIT"
833 "
834 {
835 /* fp scc patterns rarely match, and are not a win on the PA. */
836 if (hppa_branch_type != CMP_SI)
837 FAIL;
838 operands[1] = hppa_compare_op0;
839 operands[2] = hppa_compare_op1;
840 }")
841
842 (define_expand "sge"
843 [(set (match_operand:SI 0 "register_operand" "")
844 (ge:SI (match_dup 1)
845 (match_dup 2)))]
846 "!TARGET_64BIT"
847 "
848 {
849 /* fp scc patterns rarely match, and are not a win on the PA. */
850 if (hppa_branch_type != CMP_SI)
851 FAIL;
852 operands[1] = hppa_compare_op0;
853 operands[2] = hppa_compare_op1;
854 }")
855
856 (define_expand "sltu"
857 [(set (match_operand:SI 0 "register_operand" "")
858 (ltu:SI (match_dup 1)
859 (match_dup 2)))]
860 "!TARGET_64BIT"
861 "
862 {
863 if (hppa_branch_type != CMP_SI)
864 FAIL;
865 operands[1] = hppa_compare_op0;
866 operands[2] = hppa_compare_op1;
867 }")
868
869 (define_expand "sgtu"
870 [(set (match_operand:SI 0 "register_operand" "")
871 (gtu:SI (match_dup 1)
872 (match_dup 2)))]
873 "!TARGET_64BIT"
874 "
875 {
876 if (hppa_branch_type != CMP_SI)
877 FAIL;
878 operands[1] = hppa_compare_op0;
879 operands[2] = hppa_compare_op1;
880 }")
881
882 (define_expand "sleu"
883 [(set (match_operand:SI 0 "register_operand" "")
884 (leu:SI (match_dup 1)
885 (match_dup 2)))]
886 "!TARGET_64BIT"
887 "
888 {
889 if (hppa_branch_type != CMP_SI)
890 FAIL;
891 operands[1] = hppa_compare_op0;
892 operands[2] = hppa_compare_op1;
893 }")
894
895 (define_expand "sgeu"
896 [(set (match_operand:SI 0 "register_operand" "")
897 (geu:SI (match_dup 1)
898 (match_dup 2)))]
899 "!TARGET_64BIT"
900 "
901 {
902 if (hppa_branch_type != CMP_SI)
903 FAIL;
904 operands[1] = hppa_compare_op0;
905 operands[2] = hppa_compare_op1;
906 }")
907 719
908 ;; Instruction canonicalization puts immediate operands second, which 720 ;; Instruction canonicalization puts immediate operands second, which
909 ;; is the reverse of what we want. 721 ;; is the reverse of what we want.
910 722
911 (define_insn "scc" 723 (define_insn "scc"
1344 ;;; Experimental conditional move patterns 1156 ;;; Experimental conditional move patterns
1345 1157
1346 (define_expand "movsicc" 1158 (define_expand "movsicc"
1347 [(set (match_operand:SI 0 "register_operand" "") 1159 [(set (match_operand:SI 0 "register_operand" "")
1348 (if_then_else:SI 1160 (if_then_else:SI
1349 (match_operator 1 "comparison_operator" 1161 (match_operand 1 "comparison_operator" "")
1350 [(match_dup 4)
1351 (match_dup 5)])
1352 (match_operand:SI 2 "reg_or_cint_move_operand" "") 1162 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1353 (match_operand:SI 3 "reg_or_cint_move_operand" "")))] 1163 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1354 "" 1164 ""
1355 " 1165 "
1356 { 1166 {
1357 enum rtx_code code = GET_CODE (operands[1]); 1167 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1358 1168 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1359 if (hppa_branch_type != CMP_SI)
1360 FAIL; 1169 FAIL;
1361
1362 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1363 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1364 FAIL;
1365
1366 /* operands[1] is currently the result of compare_from_rtx. We want to
1367 emit a compare of the original operands. */
1368 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1369 operands[4] = hppa_compare_op0;
1370 operands[5] = hppa_compare_op1;
1371 }") 1170 }")
1372 1171
1373 ;; We used to accept any register for op1. 1172 ;; We used to accept any register for op1.
1374 ;; 1173 ;;
1375 ;; However, it loses sometimes because the compiler will end up using 1174 ;; However, it loses sometimes because the compiler will end up using
1417 (set_attr "length" "8,8,8,8,8,8,8,8")]) 1216 (set_attr "length" "8,8,8,8,8,8,8,8")])
1418 1217
1419 (define_expand "movdicc" 1218 (define_expand "movdicc"
1420 [(set (match_operand:DI 0 "register_operand" "") 1219 [(set (match_operand:DI 0 "register_operand" "")
1421 (if_then_else:DI 1220 (if_then_else:DI
1422 (match_operator 1 "comparison_operator" 1221 (match_operand 1 "comparison_operator" "")
1423 [(match_dup 4)
1424 (match_dup 5)])
1425 (match_operand:DI 2 "reg_or_cint_move_operand" "") 1222 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1426 (match_operand:DI 3 "reg_or_cint_move_operand" "")))] 1223 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1427 "TARGET_64BIT" 1224 "TARGET_64BIT"
1428 " 1225 "
1429 { 1226 {
1430 enum rtx_code code = GET_CODE (operands[1]); 1227 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1431 1228 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1432 if (hppa_branch_type != CMP_SI)
1433 FAIL; 1229 FAIL;
1434
1435 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1436 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1437 FAIL;
1438
1439 /* operands[1] is currently the result of compare_from_rtx. We want to
1440 emit a compare of the original operands. */
1441 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1442 operands[4] = hppa_compare_op0;
1443 operands[5] = hppa_compare_op1;
1444 }") 1230 }")
1445 1231
1446 ; We need the first constraint alternative in order to avoid 1232 ; We need the first constraint alternative in order to avoid
1447 ; earlyclobbers on all other alternatives. 1233 ; earlyclobbers on all other alternatives.
1448 (define_insn "" 1234 (define_insn ""
1484 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift") 1270 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1485 (set_attr "length" "8,8,8,8,8,8,8,8")]) 1271 (set_attr "length" "8,8,8,8,8,8,8,8")])
1486 1272
1487 ;; Conditional Branches 1273 ;; Conditional Branches
1488 1274
1489 (define_expand "beq" 1275 (define_expand "cbranchdi4"
1490 [(set (pc) 1276 [(set (pc)
1491 (if_then_else (eq (match_dup 1) (match_dup 2)) 1277 (if_then_else (match_operator 0 "ordered_comparison_operator"
1492 (label_ref (match_operand 0 "" "")) 1278 [(match_operand:DI 1 "reg_or_0_operand" "")
1279 (match_operand:DI 2 "register_operand" "")])
1280 (label_ref (match_operand 3 "" ""))
1493 (pc)))] 1281 (pc)))]
1282 "TARGET_64BIT"
1283 "")
1284
1285 (define_expand "cbranchsi4"
1286 [(set (pc)
1287 (if_then_else (match_operator 0 "ordered_comparison_operator"
1288 [(match_operand:SI 1 "reg_or_0_operand" "")
1289 (match_operand:SI 2 "arith5_operand" "")])
1290 (label_ref (match_operand 3 "" ""))
1291 (pc)))]
1292 ""
1293 "")
1294
1295 (define_expand "cbranchsf4"
1296 [(set (pc)
1297 (if_then_else (match_operator 0 "comparison_operator"
1298 [(match_operand:SF 1 "reg_or_0_operand" "")
1299 (match_operand:SF 2 "reg_or_0_operand" "")])
1300 (label_ref (match_operand 3 "" ""))
1301 (pc)))]
1494 "" 1302 ""
1495 " 1303 "
1496 { 1304 {
1497 if (hppa_branch_type != CMP_SI) 1305 emit_bcond_fp (operands);
1498 {
1499 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1500 emit_bcond_fp (NE, operands[0]);
1501 DONE;
1502 }
1503 /* set up operands from compare. */
1504 operands[1] = hppa_compare_op0;
1505 operands[2] = hppa_compare_op1;
1506 /* fall through and generate default code */
1507 }")
1508
1509 (define_expand "bne"
1510 [(set (pc)
1511 (if_then_else (ne (match_dup 1) (match_dup 2))
1512 (label_ref (match_operand 0 "" ""))
1513 (pc)))]
1514 ""
1515 "
1516 {
1517 if (hppa_branch_type != CMP_SI)
1518 {
1519 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1520 emit_bcond_fp (NE, operands[0]);
1521 DONE;
1522 }
1523 operands[1] = hppa_compare_op0;
1524 operands[2] = hppa_compare_op1;
1525 }")
1526
1527 (define_expand "bgt"
1528 [(set (pc)
1529 (if_then_else (gt (match_dup 1) (match_dup 2))
1530 (label_ref (match_operand 0 "" ""))
1531 (pc)))]
1532 ""
1533 "
1534 {
1535 if (hppa_branch_type != CMP_SI)
1536 {
1537 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1538 emit_bcond_fp (NE, operands[0]);
1539 DONE;
1540 }
1541 operands[1] = hppa_compare_op0;
1542 operands[2] = hppa_compare_op1;
1543 }")
1544
1545 (define_expand "blt"
1546 [(set (pc)
1547 (if_then_else (lt (match_dup 1) (match_dup 2))
1548 (label_ref (match_operand 0 "" ""))
1549 (pc)))]
1550 ""
1551 "
1552 {
1553 if (hppa_branch_type != CMP_SI)
1554 {
1555 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1556 emit_bcond_fp (NE, operands[0]);
1557 DONE;
1558 }
1559 operands[1] = hppa_compare_op0;
1560 operands[2] = hppa_compare_op1;
1561 }")
1562
1563 (define_expand "bge"
1564 [(set (pc)
1565 (if_then_else (ge (match_dup 1) (match_dup 2))
1566 (label_ref (match_operand 0 "" ""))
1567 (pc)))]
1568 ""
1569 "
1570 {
1571 if (hppa_branch_type != CMP_SI)
1572 {
1573 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1574 emit_bcond_fp (NE, operands[0]);
1575 DONE;
1576 }
1577 operands[1] = hppa_compare_op0;
1578 operands[2] = hppa_compare_op1;
1579 }")
1580
1581 (define_expand "ble"
1582 [(set (pc)
1583 (if_then_else (le (match_dup 1) (match_dup 2))
1584 (label_ref (match_operand 0 "" ""))
1585 (pc)))]
1586 ""
1587 "
1588 {
1589 if (hppa_branch_type != CMP_SI)
1590 {
1591 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1592 emit_bcond_fp (NE, operands[0]);
1593 DONE;
1594 }
1595 operands[1] = hppa_compare_op0;
1596 operands[2] = hppa_compare_op1;
1597 }")
1598
1599 (define_expand "bgtu"
1600 [(set (pc)
1601 (if_then_else (gtu (match_dup 1) (match_dup 2))
1602 (label_ref (match_operand 0 "" ""))
1603 (pc)))]
1604 ""
1605 "
1606 {
1607 if (hppa_branch_type != CMP_SI)
1608 FAIL;
1609 operands[1] = hppa_compare_op0;
1610 operands[2] = hppa_compare_op1;
1611 }")
1612
1613 (define_expand "bltu"
1614 [(set (pc)
1615 (if_then_else (ltu (match_dup 1) (match_dup 2))
1616 (label_ref (match_operand 0 "" ""))
1617 (pc)))]
1618 ""
1619 "
1620 {
1621 if (hppa_branch_type != CMP_SI)
1622 FAIL;
1623 operands[1] = hppa_compare_op0;
1624 operands[2] = hppa_compare_op1;
1625 }")
1626
1627 (define_expand "bgeu"
1628 [(set (pc)
1629 (if_then_else (geu (match_dup 1) (match_dup 2))
1630 (label_ref (match_operand 0 "" ""))
1631 (pc)))]
1632 ""
1633 "
1634 {
1635 if (hppa_branch_type != CMP_SI)
1636 FAIL;
1637 operands[1] = hppa_compare_op0;
1638 operands[2] = hppa_compare_op1;
1639 }")
1640
1641 (define_expand "bleu"
1642 [(set (pc)
1643 (if_then_else (leu (match_dup 1) (match_dup 2))
1644 (label_ref (match_operand 0 "" ""))
1645 (pc)))]
1646 ""
1647 "
1648 {
1649 if (hppa_branch_type != CMP_SI)
1650 FAIL;
1651 operands[1] = hppa_compare_op0;
1652 operands[2] = hppa_compare_op1;
1653 }")
1654
1655 (define_expand "bltgt"
1656 [(set (pc)
1657 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1658 (label_ref (match_operand 0 "" ""))
1659 (pc)))]
1660 ""
1661 "
1662 {
1663 if (hppa_branch_type == CMP_SI)
1664 FAIL;
1665 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1666 emit_bcond_fp (NE, operands[0]);
1667 DONE; 1306 DONE;
1668 }") 1307 }")
1669 1308
1670 (define_expand "bunle" 1309
1310 (define_expand "cbranchdf4"
1671 [(set (pc) 1311 [(set (pc)
1672 (if_then_else (unle (match_dup 1) (match_dup 2)) 1312 (if_then_else (match_operator 0 "comparison_operator"
1673 (label_ref (match_operand 0 "" "")) 1313 [(match_operand:DF 1 "reg_or_0_operand" "")
1314 (match_operand:DF 2 "reg_or_0_operand" "")])
1315 (label_ref (match_operand 3 "" ""))
1674 (pc)))] 1316 (pc)))]
1675 "" 1317 ""
1676 " 1318 "
1677 { 1319 {
1678 if (hppa_branch_type == CMP_SI) 1320 emit_bcond_fp (operands);
1679 FAIL;
1680 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1681 emit_bcond_fp (NE, operands[0]);
1682 DONE;
1683 }")
1684
1685 (define_expand "bunlt"
1686 [(set (pc)
1687 (if_then_else (unlt (match_dup 1) (match_dup 2))
1688 (label_ref (match_operand 0 "" ""))
1689 (pc)))]
1690 ""
1691 "
1692 {
1693 if (hppa_branch_type == CMP_SI)
1694 FAIL;
1695 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1696 emit_bcond_fp (NE, operands[0]);
1697 DONE;
1698 }")
1699
1700 (define_expand "bunge"
1701 [(set (pc)
1702 (if_then_else (unge (match_dup 1) (match_dup 2))
1703 (label_ref (match_operand 0 "" ""))
1704 (pc)))]
1705 ""
1706 "
1707 {
1708 if (hppa_branch_type == CMP_SI)
1709 FAIL;
1710 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1711 emit_bcond_fp (NE, operands[0]);
1712 DONE;
1713 }")
1714
1715 (define_expand "bungt"
1716 [(set (pc)
1717 (if_then_else (ungt (match_dup 1) (match_dup 2))
1718 (label_ref (match_operand 0 "" ""))
1719 (pc)))]
1720 ""
1721 "
1722 {
1723 if (hppa_branch_type == CMP_SI)
1724 FAIL;
1725 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1726 emit_bcond_fp (NE, operands[0]);
1727 DONE;
1728 }")
1729
1730 (define_expand "buneq"
1731 [(set (pc)
1732 (if_then_else (uneq (match_dup 1) (match_dup 2))
1733 (label_ref (match_operand 0 "" ""))
1734 (pc)))]
1735 ""
1736 "
1737 {
1738 if (hppa_branch_type == CMP_SI)
1739 FAIL;
1740 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1741 emit_bcond_fp (NE, operands[0]);
1742 DONE;
1743 }")
1744
1745 (define_expand "bunordered"
1746 [(set (pc)
1747 (if_then_else (unordered (match_dup 1) (match_dup 2))
1748 (label_ref (match_operand 0 "" ""))
1749 (pc)))]
1750 ""
1751 "
1752 {
1753 if (hppa_branch_type == CMP_SI)
1754 FAIL;
1755 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1756 emit_bcond_fp (NE, operands[0]);
1757 DONE;
1758 }")
1759
1760 (define_expand "bordered"
1761 [(set (pc)
1762 (if_then_else (ordered (match_dup 1) (match_dup 2))
1763 (label_ref (match_operand 0 "" ""))
1764 (pc)))]
1765 ""
1766 "
1767 {
1768 if (hppa_branch_type == CMP_SI)
1769 FAIL;
1770 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1771 emit_bcond_fp (NE, operands[0]);
1772 DONE; 1321 DONE;
1773 }") 1322 }")
1774 1323
1775 ;; Match the branch patterns. 1324 ;; Match the branch patterns.
1776 1325
7582 check if the casesi insn is in a delay branch sequence and output 7131 check if the casesi insn is in a delay branch sequence and output
7583 the delay insn if one is found. If this was done, then it might 7132 the delay insn if one is found. If this was done, then it might
7584 then be worthwhile to split the casesi patterns to improve scheduling. 7133 then be worthwhile to split the casesi patterns to improve scheduling.
7585 However, it's not clear that all this extra complexity is worth 7134 However, it's not clear that all this extra complexity is worth
7586 the effort. */ 7135 the effort. */
7587 emit_insn (gen_cmpsi (operands[0], operands[2])); 7136 {
7588 emit_jump_insn (gen_bgtu (operands[4])); 7137 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
7138 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
7139 }
7589 7140
7590 /* In 64bit mode we must make sure to wipe the upper bits of the register 7141 /* In 64bit mode we must make sure to wipe the upper bits of the register
7591 just in case the addition overflowed or we had random bits in the 7142 just in case the addition overflowed or we had random bits in the
7592 high part of the register. */ 7143 high part of the register. */
7593 if (TARGET_64BIT) 7144 if (TARGET_64BIT)
7645 (const_int 4)) 7196 (const_int 4))
7646 (label_ref (match_operand 1 "" ""))))) 7197 (label_ref (match_operand 1 "" "")))))
7647 (clobber (match_scratch:SI 2 "=&r")) 7198 (clobber (match_scratch:SI 2 "=&r"))
7648 (clobber (match_scratch:SI 3 "=&r"))] 7199 (clobber (match_scratch:SI 3 "=&r"))]
7649 "flag_pic" 7200 "flag_pic"
7650 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\ 7201 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7651 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)" 7202 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7652 [(set_attr "type" "multi") 7203 [(set_attr "type" "multi")
7653 (set (attr "length") 7204 (set (attr "length")
7654 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0)) 7205 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7655 (const_int 20) 7206 (const_int 20)
7662 (const_int 8)) 7213 (const_int 8))
7663 (label_ref (match_operand 1 "" ""))))) 7214 (label_ref (match_operand 1 "" "")))))
7664 (clobber (match_scratch:DI 2 "=&r")) 7215 (clobber (match_scratch:DI 2 "=&r"))
7665 (clobber (match_scratch:DI 3 "=&r"))] 7216 (clobber (match_scratch:DI 3 "=&r"))]
7666 "" 7217 ""
7667 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\ 7218 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7668 add,l %2,%3,%3\;bv,n %%r0(%3)" 7219 add,l %2,%3,%3\;bv,n %%r0(%3)"
7669 [(set_attr "type" "multi") 7220 [(set_attr "type" "multi")
7670 (set_attr "length" "24")]) 7221 (set_attr "length" "24")])
7671 7222
7672 7223