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comparison gcc/config/pdp11/pdp11.md @ 55:77e2b8dfacca gcc-4.4.5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
16 ;; GNU General Public License for more details. 16 ;; GNU General Public License for more details.
17 17
18 ;; You should have received a copy of the GNU General Public License 18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see 19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>. 20 ;; <http://www.gnu.org/licenses/>.
21
22 ;; Match CONST_DOUBLE zero for tstd/tstf.
23 (define_predicate "register_or_const0_operand"
24 (ior (match_operand 0 "register_operand")
25 (match_test "op == CONST0_RTX (GET_MODE (op))")))
21 26
22 27
23 ;; HI is 16 bit 28 ;; HI is 16 bit
24 ;; QI is 8 bit 29 ;; QI is 8 bit
25 30
79 84
80 ;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0) 85 ;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0)
81 ;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0) 86 ;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0)
82 87
83 ;; compare 88 ;; compare
84 (define_insn "cmpdf" 89 (define_insn "*cmpdf"
85 [(set (cc0) 90 [(set (cc0)
86 (compare (match_operand:DF 0 "general_operand" "fR,Q,F") 91 (compare (match_operand:DF 0 "general_operand" "fR,fR,Q,Q,F")
87 (match_operand:DF 1 "register_operand" "a,a,a")))] 92 (match_operand:DF 1 "register_or_const0_operand" "G,a,G,a,a")))]
88 "TARGET_FPU" 93 "TARGET_FPU"
89 "* 94 "*
90 { 95 {
91 cc_status.flags = CC_IN_FPU; 96 cc_status.flags = CC_IN_FPU;
92 return \"{cmpd|cmpf} %0, %1\;cfcc\"; 97 if (which_alternative == 0 || which_alternative == 2)
93 }" 98 return \"{tstd|tstf} %0, %1\;cfcc\";
94 [(set_attr "length" "2,3,6")]) 99 else
95 100 return \"{cmpd|cmpf} %0, %1\;cfcc\";
96 ;; a bit of brain damage, maybe inline later - 101 }"
97 ;; problem is - gcc seems to NEED SImode because 102 [(set_attr "length" "2,2,3,3,6")])
98 ;; of the cmp weirdness - maybe change gcc to handle this? 103
99 104 (define_insn "*cmphi"
100 (define_expand "cmpsi"
101 [(set (reg:SI 0)
102 (match_operand:SI 0 "general_operand" "g"))
103 (set (reg:SI 2)
104 (match_operand:SI 1 "general_operand" "g"))
105 (parallel [(set (cc0)
106 (compare (reg:SI 0)
107 (reg:SI 2)))
108 (clobber (reg:SI 0))])]
109 "0" ;; disable for test
110 "")
111
112 ;; check for next insn for branch code - does this still
113 ;; work in gcc 2.* ?
114
115 (define_insn ""
116 [(set (cc0) 105 [(set (cc0)
117 (compare (reg:SI 0) 106 (compare (match_operand:HI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
118 (reg:SI 2))) 107 (match_operand:HI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
119 (clobber (reg:SI 0))] 108 ""
120 "" 109 "@
121 "* 110 tst %0
122 { 111 cmp %0,%1
123 rtx br_insn = NEXT_INSN (insn); 112 cmp %0,%1
124 RTX_CODE br_code; 113 tst %0
125 114 cmp %0,%1
126 gcc_assert (GET_CODE (br_insn) == JUMP_INSN); 115 cmp %0,%1"
127 br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0)); 116 [(set_attr "length" "1,1,2,2,2,3")])
128 117
129 switch(br_code) 118 (define_insn "*cmpqi"
130 {
131 case GEU:
132 case LTU:
133 case GTU:
134 case LEU:
135
136 return \"jsr pc, ___ucmpsi\;cmp $1,r0\";
137
138 case GE:
139 case LT:
140 case GT:
141 case LE:
142 case EQ:
143 case NE:
144
145 return \"jsr pc, ___cmpsi\;tst r0\";
146
147 default:
148
149 gcc_unreachable ();
150 }
151 }"
152 [(set_attr "length" "4")])
153
154
155 (define_insn "cmphi"
156 [(set (cc0) 119 [(set (cc0)
157 (compare (match_operand:HI 0 "general_operand" "rR,rR,Qi,Qi") 120 (compare (match_operand:QI 0 "general_operand" "rR,rR,rR,Q,Qi,Qi")
158 (match_operand:HI 1 "general_operand" "rR,Qi,rR,Qi")))] 121 (match_operand:QI 1 "general_operand" "N,rR,Qi,N,rR,Qi")))]
159 "" 122 ""
160 "cmp %0,%1" 123 "@
161 [(set_attr "length" "1,2,2,3")]) 124 tstb %0
162 125 cmpb %0,%1
163 (define_insn "cmpqi" 126 cmpb %0,%1
164 [(set (cc0) 127 tstb %0
165 (compare (match_operand:QI 0 "general_operand" "rR,rR,Qi,Qi") 128 cmpb %0,%1
166 (match_operand:QI 1 "general_operand" "rR,Qi,rR,Qi")))] 129 cmpb %0,%1"
167 "" 130 [(set_attr "length" "1,1,2,2,2,3")])
168 "cmpb %0,%1"
169 [(set_attr "length" "1,2,2,3")])
170 131
171
172 ;; We have to have this because cse can optimize the previous pattern
173 ;; into this one.
174
175 (define_insn "tstdf"
176 [(set (cc0)
177 (match_operand:DF 0 "general_operand" "fR,Q"))]
178 "TARGET_FPU"
179 "*
180 {
181 cc_status.flags = CC_IN_FPU;
182 return \"{tstd|tstf} %0\;cfcc\";
183 }"
184 [(set_attr "length" "2,3")])
185
186
187 (define_expand "tstsi"
188 [(set (reg:SI 0)
189 (match_operand:SI 0 "general_operand" "g"))
190 (parallel [(set (cc0)
191 (reg:SI 0))
192 (clobber (reg:SI 0))])]
193 "0" ;; disable for test
194 "")
195
196 (define_insn ""
197 [(set (cc0)
198 (reg:SI 0))
199 (clobber (reg:SI 0))]
200 ""
201 "jsr pc, ___tstsi\;tst r0"
202 [(set_attr "length" "3")])
203
204
205 (define_insn "tsthi"
206 [(set (cc0)
207 (match_operand:HI 0 "general_operand" "rR,Q"))]
208 ""
209 "tst %0"
210 [(set_attr "length" "1,2")])
211
212 (define_insn "tstqi"
213 [(set (cc0)
214 (match_operand:QI 0 "general_operand" "rR,Q"))]
215 ""
216 "tstb %0"
217 [(set_attr "length" "1,2")])
218 132
219 ;; sob instruction - we need an assembler which can make this instruction 133 ;; sob instruction - we need an assembler which can make this instruction
220 ;; valid under _all_ circumstances! 134 ;; valid under _all_ circumstances!
221 135
222 (define_insn "" 136 (define_insn ""
262 (const_int 1)))]) 176 (const_int 1)))])
263 177
264 ;; These control RTL generation for conditional jump insns 178 ;; These control RTL generation for conditional jump insns
265 ;; and match them for register allocation. 179 ;; and match them for register allocation.
266 180
181 (define_expand "cbranchdf4"
182 [(set (cc0)
183 (compare (match_operand:DF 1 "general_operand")
184 (match_operand:DF 2 "general_operand")))
185 (set (pc)
186 (if_then_else (match_operator 0 "ordered_comparison_operator"
187 [(cc0) (const_int 0)])
188 (label_ref (match_operand 3 "" ""))
189 (pc)))]
190 ""
191 "")
192
193 (define_expand "cbranchhi4"
194 [(set (cc0)
195 (compare (match_operand:HI 1 "general_operand")
196 (match_operand:HI 2 "general_operand")))
197 (set (pc)
198 (if_then_else (match_operator 0 "ordered_comparison_operator"
199 [(cc0) (const_int 0)])
200 (label_ref (match_operand 3 "" ""))
201 (pc)))]
202 ""
203 "")
204
205 (define_expand "cbranchqi4"
206 [(set (cc0)
207 (compare (match_operand:QI 1 "general_operand")
208 (match_operand:QI 2 "general_operand")))
209 (set (pc)
210 (if_then_else (match_operator 0 "ordered_comparison_operator"
211 [(cc0) (const_int 0)])
212 (label_ref (match_operand 3 "" ""))
213 (pc)))]
214 ""
215 "")
216
267 ;; problem with too short jump distance! we need an assembler which can 217 ;; problem with too short jump distance! we need an assembler which can
268 ;; make this valid for all jump distances! 218 ;; make this valid for all jump distances!
269 ;; e.g. gas! 219 ;; e.g. gas!
270 220
271 ;; these must be changed to check for CC_IN_FCCR if float is to be 221 ;; these must be changed to check for CC_IN_FCCR if float is to be
272 ;; enabled 222 ;; enabled
273 223
274 (define_insn "beq" 224 (define_insn "*branch"
275 [(set (pc) 225 [(set (pc)
276 (if_then_else (eq (cc0) 226 (if_then_else (match_operator 0 "ordered_comparison_operator"
277 (const_int 0)) 227 [(cc0) (const_int 0)])
278 (label_ref (match_operand 0 "" "")) 228 (label_ref (match_operand 1 "" ""))
279 (pc)))] 229 (pc)))]
280 "" 230 ""
281 "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));" 231 "* return output_jump(GET_CODE (operands[0]), 0, get_attr_length(insn));"
282 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) 232 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
283 (pc)) 233 (pc))
284 (const_int -128)) 234 (const_int -128))
285 (ge (minus (match_dup 0) 235 (ge (minus (match_dup 1)
286 (pc)) 236 (pc))
287 (const_int 128))) 237 (const_int 128)))
288 (const_int 3) 238 (const_int 3)
289 (const_int 1)))]) 239 (const_int 1)))])
290 240
291 241
292 (define_insn "bne" 242 ;; These match inverted jump insns for register allocation.
243
244 (define_insn "*branch_inverted"
293 [(set (pc) 245 [(set (pc)
294 (if_then_else (ne (cc0) 246 (if_then_else (match_operator 0 "ordered_comparison_operator"
295 (const_int 0)) 247 [(cc0) (const_int 0)])
296 (label_ref (match_operand 0 "" "")) 248 (pc)
297 (pc)))] 249 (label_ref (match_operand 1 "" ""))))]
298 "" 250 ""
299 "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));" 251 "* return output_jump(GET_CODE (operands[0]), 1, get_attr_length(insn));"
300 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) 252 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
301 (pc)) 253 (pc))
302 (const_int -128)) 254 (const_int -128))
303 (ge (minus (match_dup 0) 255 (ge (minus (match_dup 1)
304 (pc))
305 (const_int 128)))
306 (const_int 3)
307 (const_int 1)))])
308
309 (define_insn "bgt"
310 [(set (pc)
311 (if_then_else (gt (cc0)
312 (const_int 0))
313 (label_ref (match_operand 0 "" ""))
314 (pc)))]
315 ""
316 "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
317 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
318 (pc))
319 (const_int -128))
320 (ge (minus (match_dup 0)
321 (pc))
322 (const_int 128)))
323 (const_int 3)
324 (const_int 1)))])
325
326 (define_insn "bgtu"
327 [(set (pc)
328 (if_then_else (gtu (cc0)
329 (const_int 0))
330 (label_ref (match_operand 0 "" ""))
331 (pc)))]
332 ""
333 "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
334 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
335 (pc))
336 (const_int -128))
337 (ge (minus (match_dup 0)
338 (pc))
339 (const_int 128)))
340 (const_int 3)
341 (const_int 1)))])
342
343 (define_insn "blt"
344 [(set (pc)
345 (if_then_else (lt (cc0)
346 (const_int 0))
347 (label_ref (match_operand 0 "" ""))
348 (pc)))]
349 ""
350 "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
351 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
352 (pc))
353 (const_int -128))
354 (ge (minus (match_dup 0)
355 (pc))
356 (const_int 128)))
357 (const_int 3)
358 (const_int 1)))])
359
360
361 (define_insn "bltu"
362 [(set (pc)
363 (if_then_else (ltu (cc0)
364 (const_int 0))
365 (label_ref (match_operand 0 "" ""))
366 (pc)))]
367 ""
368 "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
369 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
370 (pc))
371 (const_int -128))
372 (ge (minus (match_dup 0)
373 (pc))
374 (const_int 128)))
375 (const_int 3)
376 (const_int 1)))])
377
378 (define_insn "bge"
379 [(set (pc)
380 (if_then_else (ge (cc0)
381 (const_int 0))
382 (label_ref (match_operand 0 "" ""))
383 (pc)))]
384 ""
385 "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
386 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
387 (pc))
388 (const_int -128))
389 (ge (minus (match_dup 0)
390 (pc))
391 (const_int 128)))
392 (const_int 3)
393 (const_int 1)))])
394
395 (define_insn "bgeu"
396 [(set (pc)
397 (if_then_else (geu (cc0)
398 (const_int 0))
399 (label_ref (match_operand 0 "" ""))
400 (pc)))]
401 ""
402 "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
403 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
404 (pc))
405 (const_int -128))
406 (ge (minus (match_dup 0)
407 (pc))
408 (const_int 128)))
409 (const_int 3)
410 (const_int 1)))])
411
412 (define_insn "ble"
413 [(set (pc)
414 (if_then_else (le (cc0)
415 (const_int 0))
416 (label_ref (match_operand 0 "" ""))
417 (pc)))]
418 ""
419 "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
420 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
421 (pc))
422 (const_int -128))
423 (ge (minus (match_dup 0)
424 (pc))
425 (const_int 128)))
426 (const_int 3)
427 (const_int 1)))])
428
429 (define_insn "bleu"
430 [(set (pc)
431 (if_then_else (leu (cc0)
432 (const_int 0))
433 (label_ref (match_operand 0 "" ""))
434 (pc)))]
435 ""
436 "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
437 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
438 (pc))
439 (const_int -128))
440 (ge (minus (match_dup 0)
441 (pc))
442 (const_int 128)))
443 (const_int 3)
444 (const_int 1)))])
445
446
447 ;; These match inverted jump insns for register allocation.
448
449 (define_insn ""
450 [(set (pc)
451 (if_then_else (eq (cc0)
452 (const_int 0))
453 (pc)
454 (label_ref (match_operand 0 "" ""))))]
455 ""
456 "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));"
457 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
458 (pc))
459 (const_int -128))
460 (ge (minus (match_dup 0)
461 (pc))
462 (const_int 128)))
463 (const_int 3)
464 (const_int 1)))])
465
466 (define_insn ""
467 [(set (pc)
468 (if_then_else (ne (cc0)
469 (const_int 0))
470 (pc)
471 (label_ref (match_operand 0 "" ""))))]
472 ""
473 "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));"
474 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
475 (pc))
476 (const_int -128))
477 (ge (minus (match_dup 0)
478 (pc))
479 (const_int 128)))
480 (const_int 3)
481 (const_int 1)))])
482
483 (define_insn ""
484 [(set (pc)
485 (if_then_else (gt (cc0)
486 (const_int 0))
487 (pc)
488 (label_ref (match_operand 0 "" ""))))]
489 ""
490 "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
491 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
492 (pc))
493 (const_int -128))
494 (ge (minus (match_dup 0)
495 (pc))
496 (const_int 128)))
497 (const_int 3)
498 (const_int 1)))])
499
500 (define_insn ""
501 [(set (pc)
502 (if_then_else (gtu (cc0)
503 (const_int 0))
504 (pc)
505 (label_ref (match_operand 0 "" ""))))]
506 ""
507 "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
508 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
509 (pc))
510 (const_int -128))
511 (ge (minus (match_dup 0)
512 (pc))
513 (const_int 128)))
514 (const_int 3)
515 (const_int 1)))])
516
517 (define_insn ""
518 [(set (pc)
519 (if_then_else (lt (cc0)
520 (const_int 0))
521 (pc)
522 (label_ref (match_operand 0 "" ""))))]
523 ""
524 "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
525 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
526 (pc))
527 (const_int -128))
528 (ge (minus (match_dup 0)
529 (pc))
530 (const_int 128)))
531 (const_int 3)
532 (const_int 1)))])
533
534 (define_insn ""
535 [(set (pc)
536 (if_then_else (ltu (cc0)
537 (const_int 0))
538 (pc)
539 (label_ref (match_operand 0 "" ""))))]
540 ""
541 "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
542 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
543 (pc))
544 (const_int -128))
545 (ge (minus (match_dup 0)
546 (pc))
547 (const_int 128)))
548 (const_int 3)
549 (const_int 1)))])
550
551 (define_insn ""
552 [(set (pc)
553 (if_then_else (ge (cc0)
554 (const_int 0))
555 (pc)
556 (label_ref (match_operand 0 "" ""))))]
557 ""
558 "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
559 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
560 (pc))
561 (const_int -128))
562 (ge (minus (match_dup 0)
563 (pc))
564 (const_int 128)))
565 (const_int 3)
566 (const_int 1)))])
567
568 (define_insn ""
569 [(set (pc)
570 (if_then_else (geu (cc0)
571 (const_int 0))
572 (pc)
573 (label_ref (match_operand 0 "" ""))))]
574 ""
575 "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
576 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
577 (pc))
578 (const_int -128))
579 (ge (minus (match_dup 0)
580 (pc))
581 (const_int 128)))
582 (const_int 3)
583 (const_int 1)))])
584
585 (define_insn ""
586 [(set (pc)
587 (if_then_else (le (cc0)
588 (const_int 0))
589 (pc)
590 (label_ref (match_operand 0 "" ""))))]
591 ""
592 "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
593 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
594 (pc))
595 (const_int -128))
596 (ge (minus (match_dup 0)
597 (pc))
598 (const_int 128)))
599 (const_int 3)
600 (const_int 1)))])
601
602 (define_insn ""
603 [(set (pc)
604 (if_then_else (leu (cc0)
605 (const_int 0))
606 (pc)
607 (label_ref (match_operand 0 "" ""))))]
608 ""
609 "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
610 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
611 (pc))
612 (const_int -128))
613 (ge (minus (match_dup 0)
614 (pc)) 256 (pc))
615 (const_int 128))) 257 (const_int 128)))
616 (const_int 3) 258 (const_int 3)
617 (const_int 1)))]) 259 (const_int 1)))])
618 260