Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/rs6000/cell.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Scheduling description for cell processor. 1 ;; Scheduling description for cell processor.
2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Sony Computer Entertainment, Inc., 4 ;; Contributed by Sony Computer Entertainment, Inc.,
5 5
6 6
7 ;; This file is free software; you can redistribute it and/or modify it under 7 ;; This file is free software; you can redistribute it and/or modify it under
155 "vsu2_cell+lsu_cell+slot01") 155 "vsu2_cell+lsu_cell+slot01")
156 156
157 ;; Integer latency is 2 cycles 157 ;; Integer latency is 2 cycles
158 (define_insn_reservation "cell-integer" 2 158 (define_insn_reservation "cell-integer" 2
159 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ 159 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
160 var_shift_rotate,cntlz,exts") 160 var_shift_rotate,cntlz,exts,isel")
161 (eq_attr "cpu" "cell")) 161 (eq_attr "cpu" "cell"))
162 "slot01,fxu_cell") 162 "slot01,fxu_cell")
163 163
164 ;; Two integer latency is 4 cycles 164 ;; Two integer latency is 4 cycles
165 (define_insn_reservation "cell-two" 4 165 (define_insn_reservation "cell-two" 4