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comparison gcc/config/rs6000/dfp.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
103 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*") 103 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
104 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) 104 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
105 105
106 (define_insn "movsd_store" 106 (define_insn "movsd_store"
107 [(set (match_operand:DD 0 "nonimmediate_operand" "=m") 107 [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
108 (unspec:DD [(match_operand:SD 1 "input_operand" "f")] 108 (unspec:DD [(match_operand:SD 1 "input_operand" "d")]
109 UNSPEC_MOVSD_STORE))] 109 UNSPEC_MOVSD_STORE))]
110 "(gpc_reg_operand (operands[0], DDmode) 110 "(gpc_reg_operand (operands[0], DDmode)
111 || gpc_reg_operand (operands[1], SDmode)) 111 || gpc_reg_operand (operands[1], SDmode))
112 && TARGET_HARD_FLOAT && TARGET_FPRS" 112 && TARGET_HARD_FLOAT && TARGET_FPRS"
113 "stfd%U0%X0 %1,%0" 113 "stfd%U0%X0 %1,%0"
126 (set_attr "length" "4")]) 126 (set_attr "length" "4")])
127 127
128 ;; Hardware support for decimal floating point operations. 128 ;; Hardware support for decimal floating point operations.
129 129
130 (define_insn "extendsddd2" 130 (define_insn "extendsddd2"
131 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 131 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
132 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] 132 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
133 "TARGET_DFP" 133 "TARGET_DFP"
134 "dctdp %0,%1" 134 "dctdp %0,%1"
135 [(set_attr "type" "fp")]) 135 [(set_attr "type" "fp")])
136 136
137 (define_expand "extendsdtd2" 137 (define_expand "extendsdtd2"
138 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 138 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
139 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "f")))] 139 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
140 "TARGET_DFP" 140 "TARGET_DFP"
141 { 141 {
142 rtx tmp = gen_reg_rtx (DDmode); 142 rtx tmp = gen_reg_rtx (DDmode);
143 emit_insn (gen_extendsddd2 (tmp, operands[1])); 143 emit_insn (gen_extendsddd2 (tmp, operands[1]));
144 emit_insn (gen_extendddtd2 (operands[0], tmp)); 144 emit_insn (gen_extendddtd2 (operands[0], tmp));
145 DONE; 145 DONE;
146 }) 146 })
147 147
148 (define_insn "truncddsd2" 148 (define_insn "truncddsd2"
149 [(set (match_operand:SD 0 "gpc_reg_operand" "=f") 149 [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
150 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "f")))] 150 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
151 "TARGET_DFP" 151 "TARGET_DFP"
152 "drsp %0,%1" 152 "drsp %0,%1"
153 [(set_attr "type" "fp")]) 153 [(set_attr "type" "fp")])
154 154
155 (define_expand "negdd2" 155 (define_expand "negdd2"
157 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))] 157 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
158 "TARGET_HARD_FLOAT && TARGET_FPRS" 158 "TARGET_HARD_FLOAT && TARGET_FPRS"
159 "") 159 "")
160 160
161 (define_insn "*negdd2_fpr" 161 (define_insn "*negdd2_fpr"
162 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 162 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
163 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] 163 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
164 "TARGET_HARD_FLOAT && TARGET_FPRS" 164 "TARGET_HARD_FLOAT && TARGET_FPRS"
165 "fneg %0,%1" 165 "fneg %0,%1"
166 [(set_attr "type" "fp")]) 166 [(set_attr "type" "fp")])
167 167
168 (define_expand "absdd2" 168 (define_expand "absdd2"
170 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))] 170 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
171 "TARGET_HARD_FLOAT && TARGET_FPRS" 171 "TARGET_HARD_FLOAT && TARGET_FPRS"
172 "") 172 "")
173 173
174 (define_insn "*absdd2_fpr" 174 (define_insn "*absdd2_fpr"
175 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 175 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
176 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] 176 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
177 "TARGET_HARD_FLOAT && TARGET_FPRS" 177 "TARGET_HARD_FLOAT && TARGET_FPRS"
178 "fabs %0,%1" 178 "fabs %0,%1"
179 [(set_attr "type" "fp")]) 179 [(set_attr "type" "fp")])
180 180
181 (define_insn "*nabsdd2_fpr" 181 (define_insn "*nabsdd2_fpr"
182 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 182 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
183 (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "f"))))] 183 (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
184 "TARGET_HARD_FLOAT && TARGET_FPRS" 184 "TARGET_HARD_FLOAT && TARGET_FPRS"
185 "fnabs %0,%1" 185 "fnabs %0,%1"
186 [(set_attr "type" "fp")]) 186 [(set_attr "type" "fp")])
187 187
188 (define_expand "movdd" 188 (define_expand "movdd"
279 ;; a non-offsettable memref, but also it is less efficient than loading 279 ;; a non-offsettable memref, but also it is less efficient than loading
280 ;; the constant into an FP register, since it will probably be used there. 280 ;; the constant into an FP register, since it will probably be used there.
281 ;; The "??" is a kludge until we can figure out a more reasonable way 281 ;; The "??" is a kludge until we can figure out a more reasonable way
282 ;; of handling these non-offsettable values. 282 ;; of handling these non-offsettable values.
283 (define_insn "*movdd_hardfloat32" 283 (define_insn "*movdd_hardfloat32"
284 [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") 284 [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
285 (match_operand:DD 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] 285 (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
286 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS 286 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
287 && (gpc_reg_operand (operands[0], DDmode) 287 && (gpc_reg_operand (operands[0], DDmode)
288 || gpc_reg_operand (operands[1], DDmode))" 288 || gpc_reg_operand (operands[1], DDmode))"
289 "* 289 "*
290 { 290 {
415 (set_attr "length" "8,8,8,8,12,16")]) 415 (set_attr "length" "8,8,8,8,12,16")])
416 416
417 ; ld/std require word-aligned displacements -> 'Y' constraint. 417 ; ld/std require word-aligned displacements -> 'Y' constraint.
418 ; List Y->r and r->Y before r->r for reload. 418 ; List Y->r and r->Y before r->r for reload.
419 (define_insn "*movdd_hardfloat64_mfpgpr" 419 (define_insn "*movdd_hardfloat64_mfpgpr"
420 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") 420 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
421 (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] 421 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
422 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 422 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
423 && (gpc_reg_operand (operands[0], DDmode) 423 && (gpc_reg_operand (operands[0], DDmode)
424 || gpc_reg_operand (operands[1], DDmode))" 424 || gpc_reg_operand (operands[1], DDmode))"
425 "@ 425 "@
426 std%U0%X0 %1,%0 426 std%U0%X0 %1,%0
441 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) 441 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
442 442
443 ; ld/std require word-aligned displacements -> 'Y' constraint. 443 ; ld/std require word-aligned displacements -> 'Y' constraint.
444 ; List Y->r and r->Y before r->r for reload. 444 ; List Y->r and r->Y before r->r for reload.
445 (define_insn "*movdd_hardfloat64" 445 (define_insn "*movdd_hardfloat64"
446 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") 446 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
447 (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] 447 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
448 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 448 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
449 && (gpc_reg_operand (operands[0], DDmode) 449 && (gpc_reg_operand (operands[0], DDmode)
450 || gpc_reg_operand (operands[1], DDmode))" 450 || gpc_reg_operand (operands[1], DDmode))"
451 "@ 451 "@
452 std%U0%X0 %1,%0 452 std%U0%X0 %1,%0
488 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))] 488 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
489 "TARGET_HARD_FLOAT && TARGET_FPRS" 489 "TARGET_HARD_FLOAT && TARGET_FPRS"
490 "") 490 "")
491 491
492 (define_insn "*negtd2_fpr" 492 (define_insn "*negtd2_fpr"
493 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 493 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
494 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] 494 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
495 "TARGET_HARD_FLOAT && TARGET_FPRS" 495 "TARGET_HARD_FLOAT && TARGET_FPRS"
496 "fneg %0,%1" 496 "fneg %0,%1"
497 [(set_attr "type" "fp")]) 497 [(set_attr "type" "fp")])
498 498
499 (define_expand "abstd2" 499 (define_expand "abstd2"
501 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))] 501 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
502 "TARGET_HARD_FLOAT && TARGET_FPRS" 502 "TARGET_HARD_FLOAT && TARGET_FPRS"
503 "") 503 "")
504 504
505 (define_insn "*abstd2_fpr" 505 (define_insn "*abstd2_fpr"
506 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 506 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
507 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] 507 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
508 "TARGET_HARD_FLOAT && TARGET_FPRS" 508 "TARGET_HARD_FLOAT && TARGET_FPRS"
509 "fabs %0,%1" 509 "fabs %0,%1"
510 [(set_attr "type" "fp")]) 510 [(set_attr "type" "fp")])
511 511
512 (define_insn "*nabstd2_fpr" 512 (define_insn "*nabstd2_fpr"
513 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 513 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
514 (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "f"))))] 514 (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]
515 "TARGET_HARD_FLOAT && TARGET_FPRS" 515 "TARGET_HARD_FLOAT && TARGET_FPRS"
516 "fnabs %0,%1" 516 "fnabs %0,%1"
517 [(set_attr "type" "fp")]) 517 [(set_attr "type" "fp")])
518 518
519 (define_expand "movtd" 519 (define_expand "movtd"
524 524
525 ; It's important to list the o->f and f->o moves before f->f because 525 ; It's important to list the o->f and f->o moves before f->f because
526 ; otherwise reload, given m->f, will try to pick f->f and reload it, 526 ; otherwise reload, given m->f, will try to pick f->f and reload it,
527 ; which doesn't make progress. Likewise r->Y must be before r->r. 527 ; which doesn't make progress. Likewise r->Y must be before r->r.
528 (define_insn_and_split "*movtd_internal" 528 (define_insn_and_split "*movtd_internal"
529 [(set (match_operand:TD 0 "nonimmediate_operand" "=o,f,f,r,Y,r") 529 [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
530 (match_operand:TD 1 "input_operand" "f,o,f,YGHF,r,r"))] 530 (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))]
531 "TARGET_HARD_FLOAT && TARGET_FPRS 531 "TARGET_HARD_FLOAT && TARGET_FPRS
532 && (gpc_reg_operand (operands[0], TDmode) 532 && (gpc_reg_operand (operands[0], TDmode)
533 || gpc_reg_operand (operands[1], TDmode))" 533 || gpc_reg_operand (operands[1], TDmode))"
534 "#" 534 "#"
535 "&& reload_completed" 535 "&& reload_completed"
538 [(set_attr "length" "8,8,8,20,20,16")]) 538 [(set_attr "length" "8,8,8,20,20,16")])
539 539
540 ;; Hardware support for decimal floating point operations. 540 ;; Hardware support for decimal floating point operations.
541 541
542 (define_insn "extendddtd2" 542 (define_insn "extendddtd2"
543 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 543 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
544 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))] 544 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
545 "TARGET_DFP" 545 "TARGET_DFP"
546 "dctqpq %0,%1" 546 "dctqpq %0,%1"
547 [(set_attr "type" "fp")]) 547 [(set_attr "type" "fp")])
548 548
549 ;; The result of drdpq is an even/odd register pair with the converted 549 ;; The result of drdpq is an even/odd register pair with the converted
550 ;; value in the even register and zero in the odd register. 550 ;; value in the even register and zero in the odd register.
551 ;; FIXME: Avoid the register move by using a reload constraint to ensure 551 ;; FIXME: Avoid the register move by using a reload constraint to ensure
552 ;; that the result is the first of the pair receiving the result of drdpq. 552 ;; that the result is the first of the pair receiving the result of drdpq.
553 553
554 (define_insn "trunctddd2" 554 (define_insn "trunctddd2"
555 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 555 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
556 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f"))) 556 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
557 (clobber (match_scratch:TD 2 "=f"))] 557 (clobber (match_scratch:TD 2 "=d"))]
558 "TARGET_DFP" 558 "TARGET_DFP"
559 "drdpq %2,%1\;fmr %0,%2" 559 "drdpq %2,%1\;fmr %0,%2"
560 [(set_attr "type" "fp")]) 560 [(set_attr "type" "fp")])
561 561
562 (define_insn "adddd3" 562 (define_insn "adddd3"
563 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 563 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
564 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f") 564 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
565 (match_operand:DD 2 "gpc_reg_operand" "f")))] 565 (match_operand:DD 2 "gpc_reg_operand" "d")))]
566 "TARGET_DFP" 566 "TARGET_DFP"
567 "dadd %0,%1,%2" 567 "dadd %0,%1,%2"
568 [(set_attr "type" "fp")]) 568 [(set_attr "type" "fp")])
569 569
570 (define_insn "addtd3" 570 (define_insn "addtd3"
571 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 571 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
572 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f") 572 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
573 (match_operand:TD 2 "gpc_reg_operand" "f")))] 573 (match_operand:TD 2 "gpc_reg_operand" "d")))]
574 "TARGET_DFP" 574 "TARGET_DFP"
575 "daddq %0,%1,%2" 575 "daddq %0,%1,%2"
576 [(set_attr "type" "fp")]) 576 [(set_attr "type" "fp")])
577 577
578 (define_insn "subdd3" 578 (define_insn "subdd3"
579 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 579 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
580 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "f") 580 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
581 (match_operand:DD 2 "gpc_reg_operand" "f")))] 581 (match_operand:DD 2 "gpc_reg_operand" "d")))]
582 "TARGET_DFP" 582 "TARGET_DFP"
583 "dsub %0,%1,%2" 583 "dsub %0,%1,%2"
584 [(set_attr "type" "fp")]) 584 [(set_attr "type" "fp")])
585 585
586 (define_insn "subtd3" 586 (define_insn "subtd3"
587 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 587 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
588 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "f") 588 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
589 (match_operand:TD 2 "gpc_reg_operand" "f")))] 589 (match_operand:TD 2 "gpc_reg_operand" "d")))]
590 "TARGET_DFP" 590 "TARGET_DFP"
591 "dsubq %0,%1,%2" 591 "dsubq %0,%1,%2"
592 [(set_attr "type" "fp")]) 592 [(set_attr "type" "fp")])
593 593
594 (define_insn "muldd3" 594 (define_insn "muldd3"
595 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 595 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
596 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f") 596 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
597 (match_operand:DD 2 "gpc_reg_operand" "f")))] 597 (match_operand:DD 2 "gpc_reg_operand" "d")))]
598 "TARGET_DFP" 598 "TARGET_DFP"
599 "dmul %0,%1,%2" 599 "dmul %0,%1,%2"
600 [(set_attr "type" "fp")]) 600 [(set_attr "type" "fp")])
601 601
602 (define_insn "multd3" 602 (define_insn "multd3"
603 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 603 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
604 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f") 604 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
605 (match_operand:TD 2 "gpc_reg_operand" "f")))] 605 (match_operand:TD 2 "gpc_reg_operand" "d")))]
606 "TARGET_DFP" 606 "TARGET_DFP"
607 "dmulq %0,%1,%2" 607 "dmulq %0,%1,%2"
608 [(set_attr "type" "fp")]) 608 [(set_attr "type" "fp")])
609 609
610 (define_insn "divdd3" 610 (define_insn "divdd3"
611 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 611 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
612 (div:DD (match_operand:DD 1 "gpc_reg_operand" "f") 612 (div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
613 (match_operand:DD 2 "gpc_reg_operand" "f")))] 613 (match_operand:DD 2 "gpc_reg_operand" "d")))]
614 "TARGET_DFP" 614 "TARGET_DFP"
615 "ddiv %0,%1,%2" 615 "ddiv %0,%1,%2"
616 [(set_attr "type" "fp")]) 616 [(set_attr "type" "fp")])
617 617
618 (define_insn "divtd3" 618 (define_insn "divtd3"
619 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 619 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
620 (div:TD (match_operand:TD 1 "gpc_reg_operand" "f") 620 (div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
621 (match_operand:TD 2 "gpc_reg_operand" "f")))] 621 (match_operand:TD 2 "gpc_reg_operand" "d")))]
622 "TARGET_DFP" 622 "TARGET_DFP"
623 "ddivq %0,%1,%2" 623 "ddivq %0,%1,%2"
624 [(set_attr "type" "fp")]) 624 [(set_attr "type" "fp")])
625 625
626 (define_insn "*cmpdd_internal1" 626 (define_insn "*cmpdd_internal1"
627 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 627 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
628 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f") 628 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
629 (match_operand:DD 2 "gpc_reg_operand" "f")))] 629 (match_operand:DD 2 "gpc_reg_operand" "d")))]
630 "TARGET_DFP" 630 "TARGET_DFP"
631 "dcmpu %0,%1,%2" 631 "dcmpu %0,%1,%2"
632 [(set_attr "type" "fpcompare")]) 632 [(set_attr "type" "fpcompare")])
633 633
634 (define_insn "*cmptd_internal1" 634 (define_insn "*cmptd_internal1"
635 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 635 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
636 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f") 636 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
637 (match_operand:TD 2 "gpc_reg_operand" "f")))] 637 (match_operand:TD 2 "gpc_reg_operand" "d")))]
638 "TARGET_DFP" 638 "TARGET_DFP"
639 "dcmpuq %0,%1,%2" 639 "dcmpuq %0,%1,%2"
640 [(set_attr "type" "fpcompare")]) 640 [(set_attr "type" "fpcompare")])
641 641
642 (define_insn "floatditd2" 642 (define_insn "floatditd2"
643 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 643 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
644 (float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))] 644 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
645 "TARGET_DFP" 645 "TARGET_DFP"
646 "dcffixq %0,%1" 646 "dcffixq %0,%1"
647 [(set_attr "type" "fp")]) 647 [(set_attr "type" "fp")])
648 648
649 ;; Convert a decimal64 to a decimal64 whose value is an integer. 649 ;; Convert a decimal64 to a decimal64 whose value is an integer.
650 ;; This is the first stage of converting it to an integer type. 650 ;; This is the first stage of converting it to an integer type.
651 651
652 (define_insn "ftruncdd2" 652 (define_insn "ftruncdd2"
653 [(set (match_operand:DD 0 "gpc_reg_operand" "=f") 653 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
654 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] 654 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
655 "TARGET_DFP" 655 "TARGET_DFP"
656 "drintn. 0,%0,%1,1" 656 "drintn. 0,%0,%1,1"
657 [(set_attr "type" "fp")]) 657 [(set_attr "type" "fp")])
658 658
659 ;; Convert a decimal64 whose value is an integer to an actual integer. 659 ;; Convert a decimal64 whose value is an integer to an actual integer.
660 ;; This is the second stage of converting decimal float to integer type. 660 ;; This is the second stage of converting decimal float to integer type.
661 661
662 (define_insn "fixdddi2" 662 (define_insn "fixdddi2"
663 [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 663 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
664 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))] 664 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
665 "TARGET_DFP" 665 "TARGET_DFP"
666 "dctfix %0,%1" 666 "dctfix %0,%1"
667 [(set_attr "type" "fp")]) 667 [(set_attr "type" "fp")])
668 668
669 ;; Convert a decimal128 to a decimal128 whose value is an integer. 669 ;; Convert a decimal128 to a decimal128 whose value is an integer.
670 ;; This is the first stage of converting it to an integer type. 670 ;; This is the first stage of converting it to an integer type.
671 671
672 (define_insn "ftrunctd2" 672 (define_insn "ftrunctd2"
673 [(set (match_operand:TD 0 "gpc_reg_operand" "=f") 673 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
674 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] 674 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
675 "TARGET_DFP" 675 "TARGET_DFP"
676 "drintnq. 0,%0,%1,1" 676 "drintnq. 0,%0,%1,1"
677 [(set_attr "type" "fp")]) 677 [(set_attr "type" "fp")])
678 678
679 ;; Convert a decimal128 whose value is an integer to an actual integer. 679 ;; Convert a decimal128 whose value is an integer to an actual integer.
680 ;; This is the second stage of converting decimal float to integer type. 680 ;; This is the second stage of converting decimal float to integer type.
681 681
682 (define_insn "fixtddi2" 682 (define_insn "fixtddi2"
683 [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 683 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
684 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))] 684 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
685 "TARGET_DFP" 685 "TARGET_DFP"
686 "dctfixq %0,%1" 686 "dctfixq %0,%1"
687 [(set_attr "type" "fp")]) 687 [(set_attr "type" "fp")])