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comparison gcc/config/rs6000/power5.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Scheduling description for IBM POWER5 processor. 1 ;; Scheduling description for IBM POWER5 processor.
2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published 7 ;; under the terms of the GNU General Public License as published
38 |(du2_power5,lsu2_power5)\ 38 |(du2_power5,lsu2_power5)\
39 |(du3_power5,lsu2_power5)\ 39 |(du3_power5,lsu2_power5)\
40 |(du4_power5,lsu1_power5)") 40 |(du4_power5,lsu1_power5)")
41 41
42 (define_reservation "iq_power5" 42 (define_reservation "iq_power5"
43 "(du1_power5,iu1_power5)\ 43 "(du1_power5|du2_power5|du3_power5|du4_power5),\
44 |(du2_power5,iu2_power5)\ 44 (iu1_power5|iu2_power5)")
45 |(du3_power5,iu2_power5)\
46 |(du4_power5,iu1_power5)")
47 45
48 (define_reservation "fpq_power5" 46 (define_reservation "fpq_power5"
49 "(du1_power5,fpu1_power5)\ 47 "(du1_power5|du2_power5|du3_power5|du4_power5),\
50 |(du2_power5,fpu2_power5)\ 48 (fpu1_power5|fpu2_power5)")
51 |(du3_power5,fpu2_power5)\
52 |(du4_power5,fpu1_power5)")
53 49
54 ; Dispatch slots are allocated in order conforming to program order. 50 ; Dispatch slots are allocated in order conforming to program order.
55 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") 51 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
56 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") 52 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
57 (absence_set "du3_power5" "du4_power5,du5_power5") 53 (absence_set "du3_power5" "du4_power5,du5_power5")
103 "du1_power5+du2_power5,lsu1_power5+iu2_power5") 99 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
104 100
105 (define_insn_reservation "power5-store" 12 101 (define_insn_reservation "power5-store" 12
106 (and (eq_attr "type" "store") 102 (and (eq_attr "type" "store")
107 (eq_attr "cpu" "power5")) 103 (eq_attr "cpu" "power5"))
108 "(du1_power5,lsu1_power5,iu1_power5)\ 104 "((du1_power5,lsu1_power5)\
109 |(du2_power5,lsu2_power5,iu2_power5)\ 105 |(du2_power5,lsu2_power5)\
110 |(du3_power5,lsu2_power5,iu2_power5)\ 106 |(du3_power5,lsu2_power5)\
111 |(du4_power5,lsu1_power5,iu1_power5)") 107 |(du4_power5,lsu1_power5)),\
108 (iu1_power5|iu2_power5)")
112 109
113 (define_insn_reservation "power5-store-update" 12 110 (define_insn_reservation "power5-store-update" 12
114 (and (eq_attr "type" "store_u") 111 (and (eq_attr "type" "store_u")
115 (eq_attr "cpu" "power5")) 112 (eq_attr "cpu" "power5"))
116 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") 113 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
122 iu1_power5,lsu2_power5+iu2_power5,iu2_power5") 119 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
123 120
124 (define_insn_reservation "power5-fpstore" 12 121 (define_insn_reservation "power5-fpstore" 12
125 (and (eq_attr "type" "fpstore") 122 (and (eq_attr "type" "fpstore")
126 (eq_attr "cpu" "power5")) 123 (eq_attr "cpu" "power5"))
127 "(du1_power5,lsu1_power5,fpu1_power5)\ 124 "((du1_power5,lsu1_power5)\
128 |(du2_power5,lsu2_power5,fpu2_power5)\ 125 |(du2_power5,lsu2_power5)\
129 |(du3_power5,lsu2_power5,fpu2_power5)\ 126 |(du3_power5,lsu2_power5)\
130 |(du4_power5,lsu1_power5,fpu1_power5)") 127 |(du4_power5,lsu1_power5)),\
128 (fpu1_power5|fpu2_power5)")
131 129
132 (define_insn_reservation "power5-fpstore-update" 12 130 (define_insn_reservation "power5-fpstore-update" 12
133 (and (eq_attr "type" "fpstore_u,fpstore_ux") 131 (and (eq_attr "type" "fpstore_u,fpstore_ux")
134 (eq_attr "cpu" "power5")) 132 (eq_attr "cpu" "power5"))
135 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") 133 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
142 140
143 141
144 ; Integer latency is 2 cycles 142 ; Integer latency is 2 cycles
145 (define_insn_reservation "power5-integer" 2 143 (define_insn_reservation "power5-integer" 2
146 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ 144 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
147 var_shift_rotate,cntlz,exts") 145 var_shift_rotate,cntlz,exts,isel")
148 (eq_attr "cpu" "power5")) 146 (eq_attr "cpu" "power5"))
149 "iq_power5") 147 "iq_power5")
150 148
151 (define_insn_reservation "power5-two" 2 149 (define_insn_reservation "power5-two" 2
152 (and (eq_attr "type" "two") 150 (and (eq_attr "type" "two")
153 (eq_attr "cpu" "power5")) 151 (eq_attr "cpu" "power5"))
154 "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\ 152 "((du1_power5+du2_power5)\
155 |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\ 153 |(du2_power5+du3_power5)\
156 |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\ 154 |(du3_power5+du4_power5)\
157 |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)") 155 |(du4_power5+du1_power5)),\
156 ((iu1_power5,nothing,iu2_power5)\
157 |(iu2_power5,nothing,iu2_power5)\
158 |(iu2_power5,nothing,iu1_power5)\
159 |(iu1_power5,nothing,iu1_power5))")
158 160
159 (define_insn_reservation "power5-three" 2 161 (define_insn_reservation "power5-three" 2
160 (and (eq_attr "type" "three") 162 (and (eq_attr "type" "three")
161 (eq_attr "cpu" "power5")) 163 (eq_attr "cpu" "power5"))
162 "(du1_power5+du2_power5+du3_power5,\ 164 "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
163 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\ 165 |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
164 |(du2_power5+du3_power5+du4_power5,\ 166 ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
165 iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\ 167 |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
166 |(du3_power5+du4_power5+du1_power5,\ 168 |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
167 iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\ 169 |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
168 |(du4_power5+du1_power5+du2_power5,\
169 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
170 170
171 (define_insn_reservation "power5-insert" 4 171 (define_insn_reservation "power5-insert" 4
172 (and (eq_attr "type" "insert_word") 172 (and (eq_attr "type" "insert_word")
173 (eq_attr "cpu" "power5")) 173 (eq_attr "cpu" "power5"))
174 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") 174 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
200 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 200 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
201 201
202 (define_insn_reservation "power5-lmul" 7 202 (define_insn_reservation "power5-lmul" 7
203 (and (eq_attr "type" "lmul") 203 (and (eq_attr "type" "lmul")
204 (eq_attr "cpu" "power5")) 204 (eq_attr "cpu" "power5"))
205 "(du1_power5,iu1_power5*6)\ 205 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
206 |(du2_power5,iu2_power5*6)\
207 |(du3_power5,iu2_power5*6)\
208 |(du4_power5,iu1_power5*6)")
209 206
210 (define_insn_reservation "power5-imul" 5 207 (define_insn_reservation "power5-imul" 5
211 (and (eq_attr "type" "imul") 208 (and (eq_attr "type" "imul")
212 (eq_attr "cpu" "power5")) 209 (eq_attr "cpu" "power5"))
213 "(du1_power5,iu1_power5*4)\ 210 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
214 |(du2_power5,iu2_power5*4)\
215 |(du3_power5,iu2_power5*4)\
216 |(du4_power5,iu1_power5*4)")
217 211
218 (define_insn_reservation "power5-imul3" 4 212 (define_insn_reservation "power5-imul3" 4
219 (and (eq_attr "type" "imul2,imul3") 213 (and (eq_attr "type" "imul2,imul3")
220 (eq_attr "cpu" "power5")) 214 (eq_attr "cpu" "power5"))
221 "(du1_power5,iu1_power5*3)\ 215 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
222 |(du2_power5,iu2_power5*3)\
223 |(du3_power5,iu2_power5*3)\
224 |(du4_power5,iu1_power5*3)")
225 216
226 217
227 ; SPR move only executes in first IU. 218 ; SPR move only executes in first IU.
228 ; Integer division only executes in second IU. 219 ; Integer division only executes in second IU.
229 (define_insn_reservation "power5-idiv" 36 220 (define_insn_reservation "power5-idiv" 36
298 "fpq_power5") 289 "fpq_power5")
299 290
300 (define_insn_reservation "power5-sdiv" 33 291 (define_insn_reservation "power5-sdiv" 33
301 (and (eq_attr "type" "sdiv,ddiv") 292 (and (eq_attr "type" "sdiv,ddiv")
302 (eq_attr "cpu" "power5")) 293 (eq_attr "cpu" "power5"))
303 "(du1_power5,fpu1_power5*28)\ 294 "(du1_power5|du2_power5|du3_power5|du4_power5),\
304 |(du2_power5,fpu2_power5*28)\ 295 (fpu1_power5*28|fpu2_power5*28)")
305 |(du3_power5,fpu2_power5*28)\
306 |(du4_power5,fpu1_power5*28)")
307 296
308 (define_insn_reservation "power5-sqrt" 40 297 (define_insn_reservation "power5-sqrt" 40
309 (and (eq_attr "type" "ssqrt,dsqrt") 298 (and (eq_attr "type" "ssqrt,dsqrt")
310 (eq_attr "cpu" "power5")) 299 (eq_attr "cpu" "power5"))
311 "(du1_power5,fpu1_power5*35)\ 300 "(du1_power5|du2_power5|du3_power5|du4_power5),\
312 |(du2_power5,fpu2_power5*35)\ 301 (fpu1_power5*35|fpu2_power5*35)")
313 |(du3_power5,fpu2_power5*35)\
314 |(du4_power5,fpu2_power5*35)")
315 302
316 (define_insn_reservation "power5-isync" 2 303 (define_insn_reservation "power5-isync" 2
317 (and (eq_attr "type" "isync") 304 (and (eq_attr "type" "isync")
318 (eq_attr "cpu" "power5")) 305 (eq_attr "cpu" "power5"))
319 "du1_power5+du2_power5+du3_power5+du4_power5,\ 306 "du1_power5+du2_power5+du3_power5+du4_power5,\