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comparison gcc/config/rs6000/power7.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
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children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Scheduling description for IBM POWER7 processor.
2 ;; Copyright (C) 2009 Free Software Foundation, Inc.
3 ;;
4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
5
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21
22 (define_automaton "power7iu,power7lsu,power7vsu,power7misc")
23
24 (define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
25 (define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
26 (define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
27 (define_cpu_unit "bpu_power7,cru_power7" "power7misc")
28 (define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
29 "power7misc")
30
31
32 (define_reservation "DU_power7"
33 "du1_power7|du2_power7|du3_power7|du4_power7")
34
35 (define_reservation "DU2F_power7"
36 "du1_power7+du2_power7")
37
38 (define_reservation "DU4_power7"
39 "du1_power7+du2_power7+du3_power7+du4_power7")
40
41 (define_reservation "FXU_power7"
42 "iu1_power7|iu2_power7")
43
44 (define_reservation "VSU_power7"
45 "vsu1_power7|vsu2_power7")
46
47 (define_reservation "LSU_power7"
48 "lsu1_power7|lsu2_power7")
49
50
51 ; Dispatch slots are allocated in order conforming to program order.
52 (absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
53 (absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
54 (absence_set "du3_power7" "du4_power7,du5_power7")
55 (absence_set "du4_power7" "du5_power7")
56
57
58 ; LS Unit
59 (define_insn_reservation "power7-load" 2
60 (and (eq_attr "type" "load")
61 (eq_attr "cpu" "power7"))
62 "DU_power7,LSU_power7")
63
64 (define_insn_reservation "power7-load-ext" 3
65 (and (eq_attr "type" "load_ext")
66 (eq_attr "cpu" "power7"))
67 "DU2F_power7,LSU_power7,FXU_power7")
68
69 (define_insn_reservation "power7-load-update" 2
70 (and (eq_attr "type" "load_u")
71 (eq_attr "cpu" "power7"))
72 "DU2F_power7,LSU_power7+FXU_power7")
73
74 (define_insn_reservation "power7-load-update-indexed" 3
75 (and (eq_attr "type" "load_ux")
76 (eq_attr "cpu" "power7"))
77 "DU4_power7,FXU_power7,LSU_power7+FXU_power7")
78
79 (define_insn_reservation "power7-load-ext-update" 4
80 (and (eq_attr "type" "load_ext_u")
81 (eq_attr "cpu" "power7"))
82 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
83
84 (define_insn_reservation "power7-load-ext-update-indexed" 4
85 (and (eq_attr "type" "load_ext_ux")
86 (eq_attr "cpu" "power7"))
87 "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
88
89 (define_insn_reservation "power7-fpload" 3
90 (and (eq_attr "type" "fpload")
91 (eq_attr "cpu" "power7"))
92 "DU_power7,LSU_power7")
93
94 (define_insn_reservation "power7-fpload-update" 3
95 (and (eq_attr "type" "fpload_u,fpload_ux")
96 (eq_attr "cpu" "power7"))
97 "DU2F_power7,LSU_power7+FXU_power7")
98
99 (define_insn_reservation "power7-store" 6 ; store-forwarding latency
100 (and (eq_attr "type" "store")
101 (eq_attr "cpu" "power7"))
102 "DU_power7,LSU_power7+FXU_power7")
103
104 (define_insn_reservation "power7-store-update" 6
105 (and (eq_attr "type" "store_u")
106 (eq_attr "cpu" "power7"))
107 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
108
109 (define_insn_reservation "power7-store-update-indexed" 6
110 (and (eq_attr "type" "store_ux")
111 (eq_attr "cpu" "power7"))
112 "DU4_power7,LSU_power7+FXU_power7,FXU_power7")
113
114 (define_insn_reservation "power7-fpstore" 6
115 (and (eq_attr "type" "fpstore")
116 (eq_attr "cpu" "power7"))
117 "DU_power7,LSU_power7+VSU_power7")
118
119 (define_insn_reservation "power7-fpstore-update" 6
120 (and (eq_attr "type" "fpstore_u,fpstore_ux")
121 (eq_attr "cpu" "power7"))
122 "DU_power7,LSU_power7+VSU_power7+FXU_power7")
123
124 (define_insn_reservation "power7-larx" 3
125 (and (eq_attr "type" "load_l")
126 (eq_attr "cpu" "power7"))
127 "DU4_power7,LSU_power7")
128
129 (define_insn_reservation "power7-stcx" 10
130 (and (eq_attr "type" "store_c")
131 (eq_attr "cpu" "power7"))
132 "DU4_power7,LSU_power7")
133
134 (define_insn_reservation "power7-vecload" 3
135 (and (eq_attr "type" "vecload")
136 (eq_attr "cpu" "power7"))
137 "DU_power7,LSU_power7")
138
139 (define_insn_reservation "power7-vecstore" 6
140 (and (eq_attr "type" "vecstore")
141 (eq_attr "cpu" "power7"))
142 "DU_power7,LSU_power7+VSU_power7")
143
144 (define_insn_reservation "power7-sync" 11
145 (and (eq_attr "type" "sync")
146 (eq_attr "cpu" "power7"))
147 "DU4_power7,LSU_power7")
148
149
150 ; FX Unit
151 (define_insn_reservation "power7-integer" 1
152 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
153 var_shift_rotate,exts,isel")
154 (eq_attr "cpu" "power7"))
155 "DU_power7,FXU_power7")
156
157 (define_insn_reservation "power7-cntlz" 2
158 (and (eq_attr "type" "cntlz")
159 (eq_attr "cpu" "power7"))
160 "DU_power7,FXU_power7")
161
162 (define_insn_reservation "power7-two" 2
163 (and (eq_attr "type" "two")
164 (eq_attr "cpu" "power7"))
165 "DU_power7+DU_power7,FXU_power7,FXU_power7")
166
167 (define_insn_reservation "power7-three" 3
168 (and (eq_attr "type" "three")
169 (eq_attr "cpu" "power7"))
170 "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
171
172 (define_insn_reservation "power7-cmp" 1
173 (and (eq_attr "type" "cmp,fast_compare")
174 (eq_attr "cpu" "power7"))
175 "DU_power7,FXU_power7")
176
177 (define_insn_reservation "power7-compare" 2
178 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
179 (eq_attr "cpu" "power7"))
180 "DU2F_power7,FXU_power7,FXU_power7")
181
182 (define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
183
184 (define_insn_reservation "power7-mul" 4
185 (and (eq_attr "type" "imul,imul2,imul3,lmul")
186 (eq_attr "cpu" "power7"))
187 "DU_power7,FXU_power7")
188
189 (define_insn_reservation "power7-mul-compare" 5
190 (and (eq_attr "type" "imul_compare,lmul_compare")
191 (eq_attr "cpu" "power7"))
192 "DU2F_power7,FXU_power7,nothing*3,FXU_power7")
193
194 (define_insn_reservation "power7-idiv" 36
195 (and (eq_attr "type" "idiv")
196 (eq_attr "cpu" "power7"))
197 "DU2F_power7,iu1_power7*36|iu2_power7*36")
198
199 (define_insn_reservation "power7-ldiv" 68
200 (and (eq_attr "type" "ldiv")
201 (eq_attr "cpu" "power7"))
202 "DU2F_power7,iu1_power7*68|iu2_power7*68")
203
204 (define_insn_reservation "power7-isync" 1 ;
205 (and (eq_attr "type" "isync")
206 (eq_attr "cpu" "power7"))
207 "DU4_power7,FXU_power7")
208
209
210 ; CR Unit
211 (define_insn_reservation "power7-mtjmpr" 4
212 (and (eq_attr "type" "mtjmpr")
213 (eq_attr "cpu" "power7"))
214 "du1_power7,FXU_power7")
215
216 (define_insn_reservation "power7-mfjmpr" 5
217 (and (eq_attr "type" "mfjmpr")
218 (eq_attr "cpu" "power7"))
219 "du1_power7,cru_power7+FXU_power7")
220
221 (define_insn_reservation "power7-crlogical" 3
222 (and (eq_attr "type" "cr_logical")
223 (eq_attr "cpu" "power7"))
224 "du1_power7,cru_power7")
225
226 (define_insn_reservation "power7-delayedcr" 3
227 (and (eq_attr "type" "delayed_cr")
228 (eq_attr "cpu" "power7"))
229 "du1_power7,cru_power7")
230
231 (define_insn_reservation "power7-mfcr" 6
232 (and (eq_attr "type" "mfcr")
233 (eq_attr "cpu" "power7"))
234 "du1_power7,cru_power7")
235
236 (define_insn_reservation "power7-mfcrf" 3
237 (and (eq_attr "type" "mfcrf")
238 (eq_attr "cpu" "power7"))
239 "du1_power7,cru_power7")
240
241 (define_insn_reservation "power7-mtcr" 3
242 (and (eq_attr "type" "mtcr")
243 (eq_attr "cpu" "power7"))
244 "DU4_power7,cru_power7+FXU_power7")
245
246
247 ; BR Unit
248 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
249 ; grabbing previous dispatch slots once this is assigned.
250 (define_insn_reservation "power7-branch" 3
251 (and (eq_attr "type" "jmpreg,branch")
252 (eq_attr "cpu" "power7"))
253 "(du5_power7\
254 |du4_power7+du5_power7\
255 |du3_power7+du4_power7+du5_power7\
256 |du2_power7+du3_power7+du4_power7+du5_power7\
257 |du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
258
259
260 ; VS Unit (includes FP/VSX/VMX/DFP)
261 (define_insn_reservation "power7-fp" 6
262 (and (eq_attr "type" "fp,dmul")
263 (eq_attr "cpu" "power7"))
264 "DU_power7,VSU_power7")
265
266 (define_bypass 8 "power7-fp" "power7-branch")
267
268 (define_insn_reservation "power7-fpcompare" 4
269 (and (eq_attr "type" "fpcompare")
270 (eq_attr "cpu" "power7"))
271 "DU_power7,VSU_power7")
272
273 (define_insn_reservation "power7-sdiv" 26
274 (and (eq_attr "type" "sdiv")
275 (eq_attr "cpu" "power7"))
276 "DU_power7,VSU_power7")
277
278 (define_insn_reservation "power7-ddiv" 32
279 (and (eq_attr "type" "ddiv")
280 (eq_attr "cpu" "power7"))
281 "DU_power7,VSU_power7")
282
283 (define_insn_reservation "power7-sqrt" 31
284 (and (eq_attr "type" "ssqrt")
285 (eq_attr "cpu" "power7"))
286 "DU_power7,VSU_power7")
287
288 (define_insn_reservation "power7-dsqrt" 43
289 (and (eq_attr "type" "dsqrt")
290 (eq_attr "cpu" "power7"))
291 "DU_power7,VSU_power7")
292
293 (define_insn_reservation "power7-vecsimple" 2
294 (and (eq_attr "type" "vecsimple")
295 (eq_attr "cpu" "power7"))
296 "du1_power7,VSU_power7")
297
298 (define_insn_reservation "power7-veccmp" 7
299 (and (eq_attr "type" "veccmp")
300 (eq_attr "cpu" "power7"))
301 "du1_power7,VSU_power7")
302
303 (define_insn_reservation "power7-vecfloat" 7
304 (and (eq_attr "type" "vecfloat")
305 (eq_attr "cpu" "power7"))
306 "du1_power7,VSU_power7")
307
308 (define_bypass 6 "power7-vecfloat" "power7-vecfloat")
309
310 (define_insn_reservation "power7-veccomplex" 7
311 (and (eq_attr "type" "veccomplex")
312 (eq_attr "cpu" "power7"))
313 "du1_power7,VSU_power7")
314
315 (define_insn_reservation "power7-vecperm" 3
316 (and (eq_attr "type" "vecperm")
317 (eq_attr "cpu" "power7"))
318 "du2_power7,VSU_power7")