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comparison gcc/config/s390/2064.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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52:c156f1bd5cd9 55:77e2b8dfacca
19 ;; along with GCC; see the file COPYING3. If not see 19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>. 20 ;; <http://www.gnu.org/licenses/>.
21 21
22 ;; 22 ;;
23 ;; References: 23 ;; References:
24 ;; The microarchitecture of the IBM eServer z900 processor. 24 ;; The microarchitecture of the IBM eServer z900 processor.
25 ;; E.M. Schwarz et al. 25 ;; E.M. Schwarz et al.
26 ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. 26 ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
27 ;; 27 ;;
28 ;; z900 (cpu 2064) pipeline 28 ;; z900 (cpu 2064) pipeline
29 ;; 29 ;;
30 ;; dec 30 ;; dec
31 ;; --> | <--- 31 ;; --> | <---
32 ;; LA bypass | agen | 32 ;; LA bypass | agen |
33 ;; | | | 33 ;; | | |
34 ;; --- c1 | Load bypass 34 ;; --- c1 | Load bypass
35 ;; | | 35 ;; | |
36 ;; c2---- 36 ;; c2----
37 ;; | 37 ;; |
38 ;; e1 38 ;; e1
39 ;; | 39 ;; |
40 ;; wr 40 ;; wr
41 41
42 ;; This scheduler description is also used for the g5 and g6. 42 ;; This scheduler description is also used for the g5 and g6.
43 43
44 (define_automaton "z_ipu") 44 (define_automaton "z_ipu")
45 (define_cpu_unit "z_e1" "z_ipu") 45 (define_cpu_unit "z_e1" "z_ipu")
46 (define_cpu_unit "z_wr" "z_ipu") 46 (define_cpu_unit "z_wr" "z_ipu")
47 47
48 48
49 (define_insn_reservation "z_la" 1 49 (define_insn_reservation "z_la" 1
50 (and (eq_attr "cpu" "z900,g5,g6") 50 (and (eq_attr "cpu" "z900,g5,g6")
51 (eq_attr "type" "la")) 51 (eq_attr "type" "la"))
52 "z_e1,z_wr") 52 "z_e1,z_wr")
53 53
54 (define_insn_reservation "z_larl" 1 54 (define_insn_reservation "z_larl" 1
55 (and (eq_attr "cpu" "z900,g5,g6") 55 (and (eq_attr "cpu" "z900,g5,g6")
56 (eq_attr "type" "larl")) 56 (eq_attr "type" "larl"))
57 "z_e1,z_wr") 57 "z_e1,z_wr")
58 58
59 (define_insn_reservation "z_load" 1 59 (define_insn_reservation "z_load" 1
99 (and (not (eq_attr "type" "la,larl,load,store,jsr")) 99 (and (not (eq_attr "type" "la,larl,load,store,jsr"))
100 (eq_attr "atype" "agen"))) 100 (eq_attr "atype" "agen")))
101 "z_e1,z_wr") 101 "z_e1,z_wr")
102 102
103 ;; 103 ;;
104 ;; s390_agen_dep_p returns 1, if a register is set in the 104 ;; s390_agen_dep_p returns 1, if a register is set in the
105 ;; first insn and used in the dependent insn to form a address. 105 ;; first insn and used in the dependent insn to form a address.
106 ;; 106 ;;
107 107
108 ;; 108 ;;
109 ;; If an instruction uses a register to address memory, it needs 109 ;; If an instruction uses a register to address memory, it needs
110 ;; to be set 5 cycles in advance. 110 ;; to be set 5 cycles in advance.
111 ;; 111 ;;
112 112
113 (define_bypass 5 "z_int,z_agen" 113 (define_bypass 5 "z_int,z_agen"
114 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 114 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
115 115
116 ;; 116 ;;
117 ;; A load type instruction uses a bypass to feed the result back 117 ;; A load type instruction uses a bypass to feed the result back
118 ;; to the address generation pipeline stage. 118 ;; to the address generation pipeline stage.
119 ;; 119 ;;
120 120
121 (define_bypass 3 "z_load" 121 (define_bypass 3 "z_load"
122 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 122 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
123 123
124 ;; 124 ;;
125 ;; A load address type instruction uses a bypass to feed the 125 ;; A load address type instruction uses a bypass to feed the
126 ;; result back to the address generation pipeline stage. 126 ;; result back to the address generation pipeline stage.
127 ;; 127 ;;
128 128
129 (define_bypass 2 "z_larl,z_la" 129 (define_bypass 2 "z_larl,z_la"
130 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 130 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
131 131
132 132
133 133
134 134