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comparison gcc/config/spu/spu.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents 3bfb6c00c1e0
children f6334be47118
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
369 (define_split 369 (define_split
370 [(set (match_operand 0 "spu_reg_operand") 370 [(set (match_operand 0 "spu_reg_operand")
371 (match_operand 1 "memory_operand"))] 371 (match_operand 1 "memory_operand"))]
372 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16 372 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16
373 && GET_MODE(operands[0]) == GET_MODE(operands[1]) 373 && GET_MODE(operands[0]) == GET_MODE(operands[1])
374 && !reload_in_progress && !reload_completed" 374 && !reload_in_progress && !reload_completed"
375 [(set (match_dup 0) 375 [(set (match_dup 0)
376 (match_dup 1))] 376 (match_dup 1))]
377 { if (spu_split_load(operands)) 377 { if (spu_split_load(operands))
378 DONE; 378 DONE;
379 }) 379 })
381 (define_split 381 (define_split
382 [(set (match_operand 0 "memory_operand") 382 [(set (match_operand 0 "memory_operand")
383 (match_operand 1 "spu_reg_operand"))] 383 (match_operand 1 "spu_reg_operand"))]
384 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16 384 "GET_MODE_SIZE (GET_MODE (operands[0])) < 16
385 && GET_MODE(operands[0]) == GET_MODE(operands[1]) 385 && GET_MODE(operands[0]) == GET_MODE(operands[1])
386 && !reload_in_progress && !reload_completed" 386 && !reload_in_progress && !reload_completed"
387 [(set (match_dup 0) 387 [(set (match_dup 0)
388 (match_dup 1))] 388 (match_dup 1))]
389 { if (spu_split_store(operands)) 389 { if (spu_split_store(operands))
390 DONE; 390 DONE;
391 }) 391 })
2524 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r") 2524 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r")
2525 (match_operand:VHSI 2 "immediate_operand" "W")))] 2525 (match_operand:VHSI 2 "immediate_operand" "W")))]
2526 "" 2526 ""
2527 "rotma<bh>i\t%0,%1,-%<umask>2" 2527 "rotma<bh>i\t%0,%1,-%<umask>2"
2528 [(set_attr "type" "fx3")]) 2528 [(set_attr "type" "fx3")])
2529 2529
2530 2530
2531 (define_insn "rotma_<mode>" 2531 (define_insn "rotma_<mode>"
2532 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r") 2532 [(set (match_operand:VHSI 0 "spu_reg_operand" "=r,r")
2533 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r") 2533 (ashiftrt:VHSI (match_operand:VHSI 1 "spu_reg_operand" "r,r")
2534 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))] 2534 (neg:VHSI (match_operand:VHSI 2 "spu_nonmem_operand" "r,W"))))]
3749 "direct_return ()" 3749 "direct_return ()"
3750 "bi%b1%b0z\t%1,$lr" 3750 "bi%b1%b0z\t%1,$lr"
3751 [(set_attr "type" "br")]) 3751 [(set_attr "type" "br")])
3752 3752
3753 3753
3754 ;; Compare insns are next. Note that the spu has two types of compares,
3755 ;; signed & unsigned, and one type of branch.
3756 ;;
3757 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3758 ;; insns, and branches. We store the operands of compares until we see
3759 ;; how it is used.
3760
3761 (define_expand "cmp<mode>"
3762 [(set (cc0)
3763 (compare (match_operand:VQHSI 0 "spu_reg_operand" "")
3764 (match_operand:VQHSI 1 "spu_nonmem_operand" "")))]
3765 ""
3766 {
3767 spu_compare_op0 = operands[0];
3768 spu_compare_op1 = operands[1];
3769 DONE;
3770 })
3771
3772 (define_expand "cmp<mode>"
3773 [(set (cc0)
3774 (compare (match_operand:DTI 0 "spu_reg_operand" "")
3775 (match_operand:DTI 1 "spu_reg_operand" "")))]
3776 ""
3777 {
3778 spu_compare_op0 = operands[0];
3779 spu_compare_op1 = operands[1];
3780 DONE;
3781 })
3782
3783 (define_expand "cmp<mode>"
3784 [(set (cc0)
3785 (compare (match_operand:VSF 0 "spu_reg_operand" "")
3786 (match_operand:VSF 1 "spu_reg_operand" "")))]
3787 ""
3788 {
3789 spu_compare_op0 = operands[0];
3790 spu_compare_op1 = operands[1];
3791 DONE;
3792 })
3793
3794 (define_expand "cmpdf"
3795 [(set (cc0)
3796 (compare (match_operand:DF 0 "register_operand" "")
3797 (match_operand:DF 1 "register_operand" "")))]
3798 ""
3799 "{
3800 spu_compare_op0 = operands[0];
3801 spu_compare_op1 = operands[1];
3802 DONE;
3803 }")
3804
3805 ;; vector conditional compare patterns 3754 ;; vector conditional compare patterns
3806 (define_expand "vcond<mode>" 3755 (define_expand "vcond<mode>"
3807 [(set (match_operand:VCMP 0 "spu_reg_operand" "=r") 3756 [(set (match_operand:VCMP 0 "spu_reg_operand" "=r")
3808 (if_then_else:VCMP 3757 (if_then_else:VCMP
3809 (match_operator 3 "comparison_operator" 3758 (match_operator 3 "comparison_operator"
3838 }) 3787 })
3839 3788
3840 3789
3841 ;; branch on condition 3790 ;; branch on condition
3842 3791
3843 (define_expand "beq" 3792 (define_expand "cbranch<mode>4"
3844 [(use (match_operand 0 "" ""))] 3793 [(use (match_operator 0 "ordered_comparison_operator"
3845 "" 3794 [(match_operand:VQHSI 1 "spu_reg_operand" "")
3846 { spu_emit_branch_or_set (0, EQ, operands); DONE; }) 3795 (match_operand:VQHSI 2 "spu_nonmem_operand" "")]))
3847 3796 (use (match_operand 3 ""))]
3848 (define_expand "bne" 3797 ""
3849 [(use (match_operand 0 "" ""))] 3798 { spu_emit_branch_or_set (0, operands[0], operands); DONE; })
3850 "" 3799
3851 { spu_emit_branch_or_set (0, NE, operands); DONE; }) 3800 (define_expand "cbranch<mode>4"
3852 3801 [(use (match_operator 0 "ordered_comparison_operator"
3853 (define_expand "bge" 3802 [(match_operand:DTI 1 "spu_reg_operand" "")
3854 [(use (match_operand 0 "" ""))] 3803 (match_operand:DTI 2 "spu_reg_operand" "")]))
3855 "" 3804 (use (match_operand 3 ""))]
3856 { spu_emit_branch_or_set (0, GE, operands); DONE; }) 3805 ""
3857 3806 { spu_emit_branch_or_set (0, operands[0], operands); DONE; })
3858 (define_expand "bgt" 3807
3859 [(use (match_operand 0 "" ""))] 3808 (define_expand "cbranch<mode>4"
3860 "" 3809 [(use (match_operator 0 "ordered_comparison_operator"
3861 { spu_emit_branch_or_set (0, GT, operands); DONE; }) 3810 [(match_operand:VSF 1 "spu_reg_operand" "")
3862 3811 (match_operand:VSF 2 "spu_reg_operand" "")]))
3863 (define_expand "ble" 3812 (use (match_operand 3 ""))]
3864 [(use (match_operand 0 "" ""))] 3813 ""
3865 "" 3814 { spu_emit_branch_or_set (0, operands[0], operands); DONE; })
3866 { spu_emit_branch_or_set (0, LE, operands); DONE; }) 3815
3867 3816 (define_expand "cbranchdf4"
3868 (define_expand "blt" 3817 [(use (match_operator 0 "ordered_comparison_operator"
3869 [(use (match_operand 0 "" ""))] 3818 [(match_operand:DF 1 "spu_reg_operand" "")
3870 "" 3819 (match_operand:DF 2 "spu_reg_operand" "")]))
3871 { spu_emit_branch_or_set (0, LT, operands); DONE; }) 3820 (use (match_operand 3 ""))]
3872 3821 ""
3873 (define_expand "bgeu" 3822 { spu_emit_branch_or_set (0, operands[0], operands); DONE; })
3874 [(use (match_operand 0 "" ""))]
3875 ""
3876 { spu_emit_branch_or_set (0, GEU, operands); DONE; })
3877
3878 (define_expand "bgtu"
3879 [(use (match_operand 0 "" ""))]
3880 ""
3881 { spu_emit_branch_or_set (0, GTU, operands); DONE; })
3882
3883 (define_expand "bleu"
3884 [(use (match_operand 0 "" ""))]
3885 ""
3886 { spu_emit_branch_or_set (0, LEU, operands); DONE; })
3887
3888 (define_expand "bltu"
3889 [(use (match_operand 0 "" ""))]
3890 ""
3891 { spu_emit_branch_or_set (0, LTU, operands); DONE; })
3892 3823
3893 3824
3894 ;; set on condition 3825 ;; set on condition
3895 3826
3896 (define_expand "seq" 3827 (define_expand "cstore<mode>4"
3897 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3828 [(use (match_operator 1 "ordered_comparison_operator"
3898 "" 3829 [(match_operand:VQHSI 2 "spu_reg_operand" "")
3899 { spu_emit_branch_or_set (1, EQ, operands); DONE; }) 3830 (match_operand:VQHSI 3 "spu_nonmem_operand" "")]))
3900 3831 (clobber (match_operand:SI 0 "spu_reg_operand"))]
3901 (define_expand "sne" 3832 ""
3902 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3833 { spu_emit_branch_or_set (1, operands[1], operands); DONE; })
3903 "" 3834
3904 { spu_emit_branch_or_set (1, NE, operands); DONE; }) 3835 (define_expand "cstore<mode>4"
3905 3836 [(use (match_operator 1 "ordered_comparison_operator"
3906 (define_expand "sgt" 3837 [(match_operand:DTI 2 "spu_reg_operand" "")
3907 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3838 (match_operand:DTI 3 "spu_reg_operand" "")]))
3908 "" 3839 (clobber (match_operand:SI 0 "spu_reg_operand"))]
3909 { spu_emit_branch_or_set (1, GT, operands); DONE; }) 3840 ""
3910 3841 { spu_emit_branch_or_set (1, operands[1], operands); DONE; })
3911 (define_expand "slt" 3842
3912 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3843 (define_expand "cstore<mode>4"
3913 "" 3844 [(use (match_operator 1 "ordered_comparison_operator"
3914 { spu_emit_branch_or_set (1, LT, operands); DONE; }) 3845 [(match_operand:VSF 2 "spu_reg_operand" "")
3915 3846 (match_operand:VSF 3 "spu_reg_operand" "")]))
3916 (define_expand "sge" 3847 (clobber (match_operand:SI 0 "spu_reg_operand"))]
3917 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3848 ""
3918 "" 3849 { spu_emit_branch_or_set (1, operands[1], operands); DONE; })
3919 { spu_emit_branch_or_set (1, GE, operands); DONE; }) 3850
3920 3851 (define_expand "cstoredf4"
3921 (define_expand "sle" 3852 [(use (match_operator 1 "ordered_comparison_operator"
3922 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))] 3853 [(match_operand:DF 2 "spu_reg_operand" "")
3923 "" 3854 (match_operand:DF 3 "spu_reg_operand" "")]))
3924 { spu_emit_branch_or_set (1, LE, operands); DONE; }) 3855 (clobber (match_operand:SI 0 "spu_reg_operand"))]
3925 3856 ""
3926 (define_expand "sgtu" 3857 { spu_emit_branch_or_set (1, operands[1], operands); DONE; })
3927 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))]
3928 ""
3929 { spu_emit_branch_or_set (1, GTU, operands); DONE; })
3930
3931 (define_expand "sltu"
3932 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))]
3933 ""
3934 { spu_emit_branch_or_set (1, LTU, operands); DONE; })
3935
3936 (define_expand "sgeu"
3937 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))]
3938 ""
3939 { spu_emit_branch_or_set (1, GEU, operands); DONE; })
3940
3941 (define_expand "sleu"
3942 [(clobber (match_operand:SI 0 "spu_reg_operand" ""))]
3943 ""
3944 { spu_emit_branch_or_set (1, LEU, operands); DONE; })
3945 3858
3946 3859
3947 ;; conditional move 3860 ;; conditional move
3948 3861
3949 ;; Define this first one so HAVE_conditional_move is defined. 3862 ;; Define this first one so HAVE_conditional_move is defined.
3955 "!operands[0]" 3868 "!operands[0]"
3956 "") 3869 "")
3957 3870
3958 (define_expand "mov<mode>cc" 3871 (define_expand "mov<mode>cc"
3959 [(set (match_operand:ALL 0 "spu_reg_operand" "") 3872 [(set (match_operand:ALL 0 "spu_reg_operand" "")
3960 (if_then_else:ALL (match_operand 1 "comparison_operator" "") 3873 (if_then_else:ALL (match_operand 1 "ordered_comparison_operator" "")
3961 (match_operand:ALL 2 "spu_reg_operand" "") 3874 (match_operand:ALL 2 "spu_reg_operand" "")
3962 (match_operand:ALL 3 "spu_reg_operand" "")))] 3875 (match_operand:ALL 3 "spu_reg_operand" "")))]
3963 "" 3876 ""
3964 { 3877 {
3965 spu_emit_branch_or_set(2, GET_CODE(operands[1]), operands); 3878 spu_emit_branch_or_set(2, operands[1], operands);
3966 DONE; 3879 DONE;
3967 }) 3880 })
3968 3881
3969 ;; This pattern is used when the result of a compare is not large 3882 ;; This pattern is used when the result of a compare is not large
3970 ;; enough to use in a selb when expanding conditional moves. 3883 ;; enough to use in a selb when expanding conditional moves.