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comparison gcc/config/v850/v850.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
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52:c156f1bd5cd9 55:77e2b8dfacca
225 ;; ---------------------------------------------------------------------- 225 ;; ----------------------------------------------------------------------
226 ;; TEST INSTRUCTIONS 226 ;; TEST INSTRUCTIONS
227 ;; ---------------------------------------------------------------------- 227 ;; ----------------------------------------------------------------------
228 228
229 (define_insn "*v850_tst1" 229 (define_insn "*v850_tst1"
230 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") 230 [(set (cc0)
231 (const_int 1) 231 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
232 (match_operand:QI 1 "const_int_operand" "n")))] 232 (const_int 1)
233 (match_operand:QI 1 "const_int_operand" "n"))
234 (const_int 0)))]
233 "" 235 ""
234 "tst1 %1,%0" 236 "tst1 %1,%0"
235 [(set_attr "length" "4") 237 [(set_attr "length" "4")
236 (set_attr "cc" "clobber")]) 238 (set_attr "cc" "clobber")])
237 239
238 ;; This replaces ld.b;sar;andi with tst1;setf nz. 240 ;; This replaces ld.b;sar;andi with tst1;setf nz.
239
240 ;; ??? The zero_extract sets the Z bit to the opposite of what one would
241 ;; expect. This perhaps should be wrapped in a (eq: X (const_int 0)).
242 241
243 (define_split 242 (define_split
244 [(set (match_operand:SI 0 "register_operand" "") 243 [(set (match_operand:SI 0 "register_operand" "")
245 (zero_extract:SI (match_operand:QI 1 "memory_operand" "") 244 (compare (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
246 (const_int 1) 245 (const_int 1)
247 (match_operand 2 "const_int_operand" "")))] 246 (match_operand 2 "const_int_operand" ""))
248 "" 247 (const_int 0)))]
249 [(set (cc0) (zero_extract:SI (match_dup 1) 248 ""
250 (const_int 1) 249 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
251 (match_dup 2))) 250 (const_int 1)
251 (match_dup 2))
252 (const_int 0)))
252 (set (match_dup 0) (ne:SI (cc0) (const_int 0)))]) 253 (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
253 254
254 (define_insn "tstsi" 255 (define_expand "cbranchsi4"
255 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
256 ""
257 "cmp %.,%0"
258 [(set_attr "length" "2")
259 (set_attr "cc" "set_znv")])
260
261 (define_insn "cmpsi"
262 [(set (cc0) 256 [(set (cc0)
263 (compare (match_operand:SI 0 "register_operand" "r,r") 257 (compare (match_operand:SI 1 "register_operand" "")
264 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] 258 (match_operand:SI 2 "reg_or_int5_operand" "")))
259 (set (pc)
260 (if_then_else
261 (match_operator 0 "ordered_comparison_operator" [(cc0)
262 (const_int 0)])
263 (label_ref (match_operand 3 "" ""))
264 (pc)))]
265 "")
266
267 (define_expand "cstoresi4"
268 [(set (cc0)
269 (compare (match_operand:SI 2 "register_operand" "")
270 (match_operand:SI 3 "reg_or_int5_operand" "")))
271 (set (match_operand:SI 0 "register_operand")
272 (match_operator:SI 1 "ordered_comparison_operator" [(cc0)
273 (const_int 0)]))]
274 "")
275
276 (define_insn "*cmpsi"
277 [(set (cc0)
278 (compare (match_operand:SI 0 "register_operand" "r,r,r")
279 (match_operand:SI 1 "reg_or_int5_operand" "r,I,J")))]
265 "" 280 ""
266 "@ 281 "@
267 cmp %1,%0 282 cmp %1,%0
283 cmp %.,%0
268 cmp %1,%0" 284 cmp %1,%0"
269 [(set_attr "length" "2,2") 285 [(set_attr "length" "2,2,2")
270 (set_attr "cc" "compare")]) 286 (set_attr "cc" "compare,set_znv,compare")])
287
271 288
272 ;; ---------------------------------------------------------------------- 289 ;; ----------------------------------------------------------------------
273 ;; ADD INSTRUCTIONS 290 ;; ADD INSTRUCTIONS
274 ;; ---------------------------------------------------------------------- 291 ;; ----------------------------------------------------------------------
275 292
686 703
687 ;; ----------------------------------------------------------------- 704 ;; -----------------------------------------------------------------
688 ;; Scc INSTRUCTIONS 705 ;; Scc INSTRUCTIONS
689 ;; ----------------------------------------------------------------- 706 ;; -----------------------------------------------------------------
690 707
691 (define_insn "sle" 708 (define_insn "*setcc"
692 [(set (match_operand:SI 0 "register_operand" "=r") 709 [(set (match_operand:SI 0 "register_operand" "=r")
693 (le:SI (cc0) (const_int 0)))] 710 (match_operator:SI 1 "comparison_operator"
711 [(cc0) (const_int 0)]))]
694 "" 712 ""
695 "* 713 "*
696 { 714 {
697 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 715 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
716 && (GET_CODE (operands[1]) == GT
717 || GET_CODE (operands[1]) == GE
718 || GET_CODE (operands[1]) == LE
719 || GET_CODE (operands[1]) == LT))
698 return 0; 720 return 0;
699 721
700 return \"setf le,%0\"; 722 return \"setf %c1,%0\";
701 }" 723 }"
702 [(set_attr "length" "4")
703 (set_attr "cc" "none_0hit")])
704
705 (define_insn "sleu"
706 [(set (match_operand:SI 0 "register_operand" "=r")
707 (leu:SI (cc0) (const_int 0)))]
708 ""
709 "setf nh,%0"
710 [(set_attr "length" "4")
711 (set_attr "cc" "none_0hit")])
712
713 (define_insn "sge"
714 [(set (match_operand:SI 0 "register_operand" "=r")
715 (ge:SI (cc0) (const_int 0)))]
716 ""
717 "*
718 {
719 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
720 return 0;
721
722 return \"setf ge,%0\";
723 }"
724 [(set_attr "length" "4")
725 (set_attr "cc" "none_0hit")])
726
727 (define_insn "sgeu"
728 [(set (match_operand:SI 0 "register_operand" "=r")
729 (geu:SI (cc0) (const_int 0)))]
730 ""
731 "setf nl,%0"
732 [(set_attr "length" "4")
733 (set_attr "cc" "none_0hit")])
734
735 (define_insn "slt"
736 [(set (match_operand:SI 0 "register_operand" "=r")
737 (lt:SI (cc0) (const_int 0)))]
738 ""
739 "*
740 {
741 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
742 return 0;
743
744 return \"setf lt,%0\";
745 }"
746 [(set_attr "length" "4")
747 (set_attr "cc" "none_0hit")])
748
749 (define_insn "sltu"
750 [(set (match_operand:SI 0 "register_operand" "=r")
751 (ltu:SI (cc0) (const_int 0)))]
752 ""
753 "setf l,%0"
754 [(set_attr "length" "4")
755 (set_attr "cc" "none_0hit")])
756
757 (define_insn "sgt"
758 [(set (match_operand:SI 0 "register_operand" "=r")
759 (gt:SI (cc0) (const_int 0)))]
760 ""
761 "*
762 {
763 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
764 return 0;
765
766 return \"setf gt,%0\";
767 }"
768 [(set_attr "length" "4")
769 (set_attr "cc" "none_0hit")])
770
771 (define_insn "sgtu"
772 [(set (match_operand:SI 0 "register_operand" "=r")
773 (gtu:SI (cc0) (const_int 0)))]
774 ""
775 "setf h,%0"
776 [(set_attr "length" "4")
777 (set_attr "cc" "none_0hit")])
778
779 (define_insn "seq"
780 [(set (match_operand:SI 0 "register_operand" "=r")
781 (eq:SI (cc0) (const_int 0)))]
782 ""
783 "setf z,%0"
784 [(set_attr "length" "4")
785 (set_attr "cc" "none_0hit")])
786
787 (define_insn "sne"
788 [(set (match_operand:SI 0 "register_operand" "=r")
789 (ne:SI (cc0) (const_int 0)))]
790 ""
791 "setf nz,%0"
792 [(set_attr "length" "4") 724 [(set_attr "length" "4")
793 (set_attr "cc" "none_0hit")]) 725 (set_attr "cc" "none_0hit")])
794 726
795 ;; ---------------------------------------------------------------------- 727 ;; ----------------------------------------------------------------------
796 ;; CONDITIONAL MOVE INSTRUCTIONS 728 ;; CONDITIONAL MOVE INSTRUCTIONS
798 730
799 ;; Instructions using cc0 aren't allowed to have input reloads, so we must 731 ;; Instructions using cc0 aren't allowed to have input reloads, so we must
800 ;; hide the fact that this instruction uses cc0. We do so by including the 732 ;; hide the fact that this instruction uses cc0. We do so by including the
801 ;; compare instruction inside it. 733 ;; compare instruction inside it.
802 734
803 ;; ??? This is very ugly. The right way to do this is to modify cmpsi so
804 ;; that it doesn't emit RTL, and then modify the bcc/scc patterns so that
805 ;; they emit RTL for the compare instruction. Unfortunately, this requires
806 ;; lots of changes that will be hard to sanitize. So for now, cmpsi still
807 ;; emits RTL, and I get the compare operands here from the previous insn.
808
809 (define_expand "movsicc" 735 (define_expand "movsicc"
810 [(set (match_operand:SI 0 "register_operand" "=r") 736 [(set (match_operand:SI 0 "register_operand" "=r")
811 (if_then_else:SI 737 (if_then_else:SI
812 (match_operator 1 "comparison_operator" 738 (match_operand 1 "comparison_operator")
813 [(match_dup 4) (match_dup 5)])
814 (match_operand:SI 2 "reg_or_const_operand" "rJ") 739 (match_operand:SI 2 "reg_or_const_operand" "rJ")
815 (match_operand:SI 3 "reg_or_const_operand" "rI")))] 740 (match_operand:SI 3 "reg_or_const_operand" "rI")))]
816 "TARGET_V850E" 741 "TARGET_V850E"
817 " 742 "
818 { 743 {
819 rtx insn = get_last_insn_anywhere ();
820 rtx src;
821
822 if ( (GET_CODE (operands[2]) == CONST_INT 744 if ( (GET_CODE (operands[2]) == CONST_INT
823 && GET_CODE (operands[3]) == CONST_INT)) 745 && GET_CODE (operands[3]) == CONST_INT))
824 { 746 {
825 int o2 = INTVAL (operands[2]); 747 int o2 = INTVAL (operands[2]);
826 int o3 = INTVAL (operands[3]); 748 int o3 = INTVAL (operands[3]);
843 if (GET_CODE (operands[2]) != REG) 765 if (GET_CODE (operands[2]) != REG)
844 operands[2] = copy_to_mode_reg (SImode,operands[2]); 766 operands[2] = copy_to_mode_reg (SImode,operands[2]);
845 if (GET_CODE (operands[3]) != REG) 767 if (GET_CODE (operands[3]) != REG)
846 operands[3] = copy_to_mode_reg (SImode, operands[3]); 768 operands[3] = copy_to_mode_reg (SImode, operands[3]);
847 } 769 }
848 gcc_assert (GET_CODE (insn) == INSN
849 && GET_CODE (PATTERN (insn)) == SET
850 && SET_DEST (PATTERN (insn)) == cc0_rtx);
851
852 src = SET_SRC (PATTERN (insn));
853
854 switch (GET_CODE (src))
855 {
856 case COMPARE:
857 operands[4] = XEXP (src, 0);
858 operands[5] = XEXP (src, 1);
859 break;
860
861 case REG:
862 case SUBREG:
863 operands[4] = src;
864 operands[5] = const0_rtx;
865 break;
866
867 default:
868 gcc_unreachable ();
869 }
870 }") 770 }")
871 771
872 ;; ??? Clobbering the condition codes is overkill. 772 ;; ??? Clobbering the condition codes is overkill.
873 773
874 ;; ??? We sometimes emit an unnecessary compare instruction because the 774 ;; ??? We sometimes emit an unnecessary compare instruction because the
1035 ;; JUMP INSTRUCTIONS 935 ;; JUMP INSTRUCTIONS
1036 ;; ---------------------------------------------------------------------- 936 ;; ----------------------------------------------------------------------
1037 937
1038 ;; Conditional jump instructions 938 ;; Conditional jump instructions
1039 939
1040 (define_expand "ble"
1041 [(set (pc)
1042 (if_then_else (le (cc0)
1043 (const_int 0))
1044 (label_ref (match_operand 0 "" ""))
1045 (pc)))]
1046 ""
1047 "")
1048
1049 (define_expand "bleu"
1050 [(set (pc)
1051 (if_then_else (leu (cc0)
1052 (const_int 0))
1053 (label_ref (match_operand 0 "" ""))
1054 (pc)))]
1055 ""
1056 "")
1057
1058 (define_expand "bge"
1059 [(set (pc)
1060 (if_then_else (ge (cc0)
1061 (const_int 0))
1062 (label_ref (match_operand 0 "" ""))
1063 (pc)))]
1064 ""
1065 "")
1066
1067 (define_expand "bgeu"
1068 [(set (pc)
1069 (if_then_else (geu (cc0)
1070 (const_int 0))
1071 (label_ref (match_operand 0 "" ""))
1072 (pc)))]
1073 ""
1074 "")
1075
1076 (define_expand "blt"
1077 [(set (pc)
1078 (if_then_else (lt (cc0)
1079 (const_int 0))
1080 (label_ref (match_operand 0 "" ""))
1081 (pc)))]
1082 ""
1083 "")
1084
1085 (define_expand "bltu"
1086 [(set (pc)
1087 (if_then_else (ltu (cc0)
1088 (const_int 0))
1089 (label_ref (match_operand 0 "" ""))
1090 (pc)))]
1091 ""
1092 "")
1093
1094 (define_expand "bgt"
1095 [(set (pc)
1096 (if_then_else (gt (cc0)
1097 (const_int 0))
1098 (label_ref (match_operand 0 "" ""))
1099 (pc)))]
1100 ""
1101 "")
1102
1103 (define_expand "bgtu"
1104 [(set (pc)
1105 (if_then_else (gtu (cc0)
1106 (const_int 0))
1107 (label_ref (match_operand 0 "" ""))
1108 (pc)))]
1109 ""
1110 "")
1111
1112 (define_expand "beq"
1113 [(set (pc)
1114 (if_then_else (eq (cc0)
1115 (const_int 0))
1116 (label_ref (match_operand 0 "" ""))
1117 (pc)))]
1118 ""
1119 "")
1120
1121 (define_expand "bne"
1122 [(set (pc)
1123 (if_then_else (ne (cc0)
1124 (const_int 0))
1125 (label_ref (match_operand 0 "" ""))
1126 (pc)))]
1127 ""
1128 "")
1129
1130 (define_insn "*branch_normal" 940 (define_insn "*branch_normal"
1131 [(set (pc) 941 [(set (pc)
1132 (if_then_else (match_operator 1 "comparison_operator" 942 (if_then_else (match_operator 1 "comparison_operator"
1133 [(cc0) (const_int 0)]) 943 [(cc0) (const_int 0)])
1134 (label_ref (match_operand 0 "" "")) 944 (label_ref (match_operand 0 "" ""))
1239 "" 1049 ""
1240 " 1050 "
1241 { 1051 {
1242 rtx reg = gen_reg_rtx (SImode); 1052 rtx reg = gen_reg_rtx (SImode);
1243 rtx tableaddress = gen_reg_rtx (SImode); 1053 rtx tableaddress = gen_reg_rtx (SImode);
1054 rtx test;
1244 rtx mem; 1055 rtx mem;
1245 1056
1246 /* Subtract the lower bound from the index. */ 1057 /* Subtract the lower bound from the index. */
1247 emit_insn (gen_subsi3 (reg, operands[0], operands[1])); 1058 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
1248 /* Compare the result against the number of table entries. */ 1059
1249 emit_insn (gen_cmpsi (reg, operands[2])); 1060 /* Compare the result against the number of table entries;
1250 /* Branch to the default label if out of range of the table. */ 1061 branch to the default label if out of range of the table. */
1251 emit_jump_insn (gen_bgtu (operands[4])); 1062 test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
1063 emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
1252 1064
1253 /* Shift index for the table array access. */ 1065 /* Shift index for the table array access. */
1254 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1))); 1066 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
1255 /* Load the table address into a pseudo. */ 1067 /* Load the table address into a pseudo. */
1256 emit_insn (gen_movsi (tableaddress, 1068 emit_insn (gen_movsi (tableaddress,
1550 (define_expand "epilogue" 1362 (define_expand "epilogue"
1551 [(return)] 1363 [(return)]
1552 "" 1364 ""
1553 " 1365 "
1554 { 1366 {
1555 /* Try to use the trivial return first. Else use the 1367 expand_epilogue ();
1556 full epilogue. */
1557 if (0)
1558 emit_jump_insn (gen_return ());
1559 else
1560 expand_epilogue ();
1561 DONE; 1368 DONE;
1562 }") 1369 }")
1563 1370
1564 (define_insn "return" 1371 (define_insn "return_simple"
1565 [(return)] 1372 [(return)]
1566 "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0" 1373 "reload_completed"
1567 "jmp [r31]" 1374 "jmp [r31]"
1568 [(set_attr "length" "2") 1375 [(set_attr "length" "2")
1569 (set_attr "cc" "none")]) 1376 (set_attr "cc" "none")])
1570 1377
1571 (define_insn "return_internal" 1378 (define_insn "return_internal"