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comparison gcc/config/vax/vax.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; Machine description for GNU compiler, VAX Version 1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005, 2007 Free Software Foundation, Inc. 3 ;; 2002, 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by 8 ;; it under the terms of the GNU General Public License as published by
41 ) 41 )
42 42
43 ;; Integer modes supported on VAX, with a mapping from machine mode 43 ;; Integer modes supported on VAX, with a mapping from machine mode
44 ;; to mnemonic suffix. DImode is always a special case. 44 ;; to mnemonic suffix. DImode is always a special case.
45 (define_mode_iterator VAXint [QI HI SI]) 45 (define_mode_iterator VAXint [QI HI SI])
46 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l")]) 46 (define_mode_iterator VAXintQH [QI HI])
47 (define_mode_iterator VAXintQHSD [QI HI SI DI])
48 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
47 49
48 ;; Similar for float modes supported on VAX. 50 ;; Similar for float modes supported on VAX.
49 (define_mode_iterator VAXfp [SF DF]) 51 (define_mode_iterator VAXfp [SF DF])
50 (define_mode_attr fsfx [(SF "f") (DF "%#")]) 52 (define_mode_attr fsfx [(SF "f") (DF "%#")])
51 53
52 ;; Some output patterns want integer immediates with a prefix... 54 ;; Some output patterns want integer immediates with a prefix...
53 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")]) 55 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
54 56
55 ;; We don't want to allow a constant operand for test insns because 57 ;;
56 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 58 (include "constraints.md")
57 ;; be folded while optimizing anyway. 59 (include "predicates.md")
58 60
59 (define_insn "tst<mode>" 61 (define_insn "*cmp<mode>"
60 [(set (cc0) 62 [(set (cc0)
61 (match_operand:VAXint 0 "nonimmediate_operand" "g"))] 63 (compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT,nrmT")
62 "" 64 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
63 "tst<VAXint:isfx> %0") 65 ""
64 66 "@
65 (define_insn "tst<mode>" 67 tst<VAXint:isfx> %0
66 [(set (cc0) 68 cmp<VAXint:isfx> %0,%1")
67 (match_operand:VAXfp 0 "general_operand" "gF"))] 69
68 "" 70 (define_insn "*cmp<mode>"
69 "tst<VAXfp:fsfx> %0")
70
71 (define_insn "cmp<mode>"
72 [(set (cc0)
73 (compare (match_operand:VAXint 0 "nonimmediate_operand" "g")
74 (match_operand:VAXint 1 "general_operand" "g")))]
75 ""
76 "cmp<VAXint:isfx> %0,%1")
77
78 (define_insn "cmp<mode>"
79 [(set (cc0) 71 [(set (cc0)
80 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF") 72 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
81 (match_operand:VAXfp 1 "general_operand" "G,gF")))] 73 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
82 "" 74 ""
83 "@ 75 "@
84 tst<VAXfp:fsfx> %0 76 tst<VAXfp:fsfx> %0
85 cmp<VAXfp:fsfx> %0,%1") 77 cmp<VAXfp:fsfx> %0,%1")
86 78
87 (define_insn "*bit<mode>" 79 (define_insn "*bit<mode>"
88 [(set (cc0) 80 [(set (cc0)
89 (and:VAXint (match_operand:VAXint 0 "general_operand" "g") 81 (compare (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
90 (match_operand:VAXint 1 "general_operand" "g")))] 82 (match_operand:VAXint 1 "general_operand" "nrmT"))
83 (const_int 0)))]
91 "" 84 ""
92 "bit<VAXint:isfx> %0,%1") 85 "bit<VAXint:isfx> %0,%1")
93 86
94 ;; The VAX has no sCOND insns. It does have add/subtract with carry 87 ;; The VAX has no sCOND insns. It does have add/subtract with carry
95 ;; which could be used to implement the sltu and sgeu patterns. However, 88 ;; which could be used to implement the sltu and sgeu patterns. However,
113 ;; (match_operand:TI 1 "general_operand" "g"))] 106 ;; (match_operand:TI 1 "general_operand" "g"))]
114 ;; "" 107 ;; ""
115 ;; "movh %1,%0") 108 ;; "movh %1,%0")
116 109
117 (define_insn "movdi" 110 (define_insn "movdi"
118 [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g") 111 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
119 (match_operand:DI 1 "general_operand" "I,g"))] 112 (match_operand:DI 1 "general_operand" "g"))]
120 "" 113 ""
121 "@ 114 "* return vax_output_int_move (insn, operands, DImode);")
122 clrq %0
123 movq %D1,%0")
124 115
125 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX 116 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
126 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl 117 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
127 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles 118 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
128 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword 119 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
137 ;; operand take 1 cycle). 128 ;; operand take 1 cycle).
138 129
139 ;; Loads of constants between 64 and 128 used to be done with 130 ;; Loads of constants between 64 and 128 used to be done with
140 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space. 131 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
141 132
133 (define_expand "movsi"
134 [(set (match_operand:SI 0 "nonimmediate_operand" "")
135 (match_operand:SI 1 "general_operand" ""))]
136 ""
137 "
138 {
139 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
140 if (flag_pic
141 && GET_CODE (operands[1]) == CONST
142 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
143 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
144 {
145 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
146 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
147 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
148 emit_move_insn (temp, symbol_ref);
149 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
150 DONE;
151 }
152 #endif
153 }")
154
155 (define_insn "movsi_2"
156 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
157 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
158 ""
159 "* return vax_output_int_move (insn, operands, SImode);")
160
142 (define_insn "mov<mode>" 161 (define_insn "mov<mode>"
143 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 162 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
144 (match_operand:VAXint 1 "general_operand" "g"))] 163 (match_operand:VAXintQH 1 "general_operand" "g"))]
145 "" 164 ""
146 "* return vax_output_int_move (insn, operands, <MODE>mode);") 165 "* return vax_output_int_move (insn, operands, <MODE>mode);")
147 166
148 (define_insn "movstricthi" 167 (define_insn "movstricthi"
149 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g")) 168 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
190 (match_operand:BLK 1 "general_operand" "g")) 209 (match_operand:BLK 1 "general_operand" "g"))
191 (use (match_operand:HI 2 "general_operand" "g")) 210 (use (match_operand:HI 2 "general_operand" "g"))
192 (match_operand 3 "" "")] 211 (match_operand 3 "" "")]
193 "" 212 ""
194 " 213 "
214 {
195 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 215 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
196 DONE; 216 DONE;
197 ") 217 }")
198 218
199 ;; The definition of this insn does not really explain what it does, 219 ;; The definition of this insn does not really explain what it does,
200 ;; but it should suffice 220 ;; but it should suffice
201 ;; that anything generated as this insn will be recognized as one 221 ;; that anything generated as this insn will be recognized as one
202 ;; and that it won't successfully combine with anything. 222 ;; and that it won't successfully combine with anything.
223
203 (define_insn "movmemhi1" 224 (define_insn "movmemhi1"
204 [(set (match_operand:BLK 0 "memory_operand" "=m") 225 [(set (match_operand:BLK 0 "memory_operand" "=o")
205 (match_operand:BLK 1 "memory_operand" "m")) 226 (match_operand:BLK 1 "memory_operand" "o"))
206 (use (match_operand:HI 2 "general_operand" "g")) 227 (use (match_operand:HI 2 "general_operand" "g"))
207 (clobber (reg:SI 0)) 228 (clobber (reg:SI 0))
208 (clobber (reg:SI 1)) 229 (clobber (reg:SI 1))
209 (clobber (reg:SI 2)) 230 (clobber (reg:SI 2))
210 (clobber (reg:SI 3)) 231 (clobber (reg:SI 3))
215 236
216 ;; Extension and truncation insns. 237 ;; Extension and truncation insns.
217 238
218 (define_insn "truncsiqi2" 239 (define_insn "truncsiqi2"
219 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 240 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
220 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))] 241 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
221 "" 242 ""
222 "cvtlb %1,%0") 243 "cvtlb %1,%0")
223 244
224 (define_insn "truncsihi2" 245 (define_insn "truncsihi2"
225 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 246 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
226 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))] 247 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
227 "" 248 ""
228 "cvtlw %1,%0") 249 "cvtlw %1,%0")
229 250
230 (define_insn "trunchiqi2" 251 (define_insn "trunchiqi2"
231 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 252 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
307 "@ 328 "@
308 add<VAXfp:fsfx>2 %2,%0 329 add<VAXfp:fsfx>2 %2,%0
309 add<VAXfp:fsfx>2 %1,%0 330 add<VAXfp:fsfx>2 %1,%0
310 add<VAXfp:fsfx>3 %1,%2,%0") 331 add<VAXfp:fsfx>3 %1,%2,%0")
311 332
333 (define_insn "pushlclsymreg"
334 [(set (match_operand:SI 0 "push_operand" "=g")
335 (plus:SI (match_operand:SI 1 "register_operand" "%r")
336 (match_operand:SI 2 "local_symbolic_operand" "i")))]
337 "flag_pic"
338 "pushab %a2[%1]")
339
340 (define_insn "pushextsymreg"
341 [(set (match_operand:SI 0 "push_operand" "=g")
342 (plus:SI (match_operand:SI 1 "register_operand" "%r")
343 (match_operand:SI 2 "external_symbolic_operand" "i")))]
344 "flag_pic"
345 "pushab %a2[%1]")
346
347 (define_insn "movlclsymreg"
348 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
349 (plus:SI (match_operand:SI 1 "register_operand" "%r")
350 (match_operand:SI 2 "local_symbolic_operand" "i")))]
351 "flag_pic"
352 "movab %a2[%1],%0")
353
354 (define_insn "movextsymreg"
355 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
356 (plus:SI (match_operand:SI 1 "register_operand" "%r")
357 (match_operand:SI 2 "external_symbolic_operand" "i")))]
358 "flag_pic"
359 "movab %a2[%1],%0")
360
312 (define_insn "add<mode>3" 361 (define_insn "add<mode>3"
313 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 362 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
314 (plus:VAXint (match_operand:VAXint 1 "general_operand" "g") 363 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
315 (match_operand:VAXint 2 "general_operand" "g")))] 364 (match_operand:VAXint 2 "general_operand" "nrmT")))]
316 "" 365 ""
317 "* return vax_output_int_add (insn, operands, <MODE>mode);") 366 "* return vax_output_int_add (insn, operands, <MODE>mode);")
318 367
368 (define_expand "adddi3"
369 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
370 (plus:DI (match_operand:DI 1 "general_operand" "g")
371 (match_operand:DI 2 "general_operand" "g")))]
372 "!reload_in_progress"
373 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
374
375 (define_insn "adcdi3"
376 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
377 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
378 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
379 "TARGET_QMATH"
380 "* return vax_output_int_add (insn, operands, DImode);")
381
319 ;; The add-with-carry (adwc) instruction only accepts two operands. 382 ;; The add-with-carry (adwc) instruction only accepts two operands.
320 (define_insn "adddi3" 383 (define_insn "adddi3_old"
321 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 384 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
322 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 385 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
323 (match_operand:DI 2 "general_operand" "Fro,F")))] 386 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
324 "" 387 "!TARGET_QMATH"
325 "* 388 "* return vax_output_int_add (insn, operands, DImode);")
326 {
327 rtx low[3];
328 const char *pattern;
329 int carry = 1;
330
331 split_quadword_operands (operands, low, 3);
332 /* Add low parts. */
333 if (rtx_equal_p (operands[0], operands[1]))
334 {
335 if (low[2] == const0_rtx)
336 /* Should examine operand, punt if not POST_INC. */
337 pattern = \"tstl %0\", carry = 0;
338 else if (low[2] == const1_rtx)
339 pattern = \"incl %0\";
340 else
341 pattern = \"addl2 %2,%0\";
342 }
343 else
344 {
345 if (low[2] == const0_rtx)
346 pattern = \"movl %1,%0\", carry = 0;
347 else
348 pattern = \"addl3 %2,%1,%0\";
349 }
350 if (pattern)
351 output_asm_insn (pattern, low);
352 if (!carry)
353 /* If CARRY is 0, we don't have any carry value to worry about. */
354 return get_insn_template (CODE_FOR_addsi3, insn);
355 /* %0 = C + %1 + %2 */
356 if (!rtx_equal_p (operands[0], operands[1]))
357 output_asm_insn ((operands[1] == const0_rtx
358 ? \"clrl %0\"
359 : \"movl %1,%0\"), operands);
360 return \"adwc %2,%0\";
361 }")
362 389
363 ;;- All kinds of subtract instructions. 390 ;;- All kinds of subtract instructions.
364 391
365 (define_insn "sub<mode>3" 392 (define_insn "sub<mode>3"
366 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 393 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
371 sub<VAXfp:fsfx>2 %2,%0 398 sub<VAXfp:fsfx>2 %2,%0
372 sub<VAXfp:fsfx>3 %2,%1,%0") 399 sub<VAXfp:fsfx>3 %2,%1,%0")
373 400
374 (define_insn "sub<mode>3" 401 (define_insn "sub<mode>3"
375 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 402 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
376 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,g") 403 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
377 (match_operand:VAXint 2 "general_operand" "g,g")))] 404 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
378 "" 405 ""
379 "@ 406 "@
380 sub<VAXint:isfx>2 %2,%0 407 sub<VAXint:isfx>2 %2,%0
381 sub<VAXint:isfx>3 %2,%1,%0") 408 sub<VAXint:isfx>3 %2,%1,%0")
382 409
410 (define_expand "subdi3"
411 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
412 (minus:DI (match_operand:DI 1 "general_operand" "g")
413 (match_operand:DI 2 "general_operand" "g")))]
414 "!reload_in_progress"
415 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
416
417 (define_insn "sbcdi3"
418 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
419 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
420 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
421 "TARGET_QMATH"
422 "* return vax_output_int_subtract (insn, operands, DImode);")
423
383 ;; The subtract-with-carry (sbwc) instruction only takes two operands. 424 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
384 (define_insn "subdi3" 425 (define_insn "subdi3_old"
385 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 426 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
386 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 427 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
387 (match_operand:DI 2 "general_operand" "For,F")))] 428 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
388 "" 429 "!TARGET_QMATH"
389 "* 430 "* return vax_output_int_subtract (insn, operands, DImode);")
390 {
391 rtx low[3];
392 const char *pattern;
393 int carry = 1;
394
395 split_quadword_operands (operands, low, 3);
396 /* Subtract low parts. */
397 if (rtx_equal_p (operands[0], operands[1]))
398 {
399 if (low[2] == const0_rtx)
400 pattern = 0, carry = 0;
401 else if (low[2] == constm1_rtx)
402 pattern = \"decl %0\";
403 else
404 pattern = \"subl2 %2,%0\";
405 }
406 else
407 {
408 if (low[2] == constm1_rtx)
409 pattern = \"decl %0\";
410 else if (low[2] == const0_rtx)
411 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
412 else
413 pattern = \"subl3 %2,%1,%0\";
414 }
415 if (pattern)
416 output_asm_insn (pattern, low);
417 if (carry)
418 {
419 if (!rtx_equal_p (operands[0], operands[1]))
420 return \"movl %1,%0\;sbwc %2,%0\";
421 return \"sbwc %2,%0\";
422 /* %0 = %2 - %1 - C */
423 }
424 return get_insn_template (CODE_FOR_subsi3, insn);
425 }")
426 431
427 ;;- Multiply instructions. 432 ;;- Multiply instructions.
428 433
429 (define_insn "mul<mode>3" 434 (define_insn "mul<mode>3"
430 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 435 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
436 mul<VAXfp:fsfx>2 %1,%0 441 mul<VAXfp:fsfx>2 %1,%0
437 mul<VAXfp:fsfx>3 %1,%2,%0") 442 mul<VAXfp:fsfx>3 %1,%2,%0")
438 443
439 (define_insn "mul<mode>3" 444 (define_insn "mul<mode>3"
440 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 445 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
441 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g") 446 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
442 (match_operand:VAXint 2 "general_operand" "g,0,g")))] 447 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
443 "" 448 ""
444 "@ 449 "@
445 mul<VAXint:isfx>2 %2,%0 450 mul<VAXint:isfx>2 %2,%0
446 mul<VAXint:isfx>2 %1,%0 451 mul<VAXint:isfx>2 %1,%0
447 mul<VAXint:isfx>3 %1,%2,%0") 452 mul<VAXint:isfx>3 %1,%2,%0")
448 453
449 (define_insn "mulsidi3" 454 (define_insn "mulsidi3"
450 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 455 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
451 (mult:DI (sign_extend:DI 456 (mult:DI (sign_extend:DI
452 (match_operand:SI 1 "nonimmediate_operand" "g")) 457 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
453 (sign_extend:DI 458 (sign_extend:DI
454 (match_operand:SI 2 "nonimmediate_operand" "g"))))] 459 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))]
455 "" 460 ""
456 "emul %1,%2,$0,%0") 461 "emul %1,%2,$0,%0")
457 462
458 (define_insn "" 463 (define_insn ""
459 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 464 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
460 (plus:DI 465 (plus:DI
461 (mult:DI (sign_extend:DI 466 (mult:DI (sign_extend:DI
462 (match_operand:SI 1 "nonimmediate_operand" "g")) 467 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
463 (sign_extend:DI 468 (sign_extend:DI
464 (match_operand:SI 2 "nonimmediate_operand" "g"))) 469 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
465 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))] 470 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
466 "" 471 ""
467 "emul %1,%2,%3,%0") 472 "emul %1,%2,%3,%0")
468 473
469 ;; 'F' constraint means type CONST_DOUBLE 474 ;; 'F' constraint means type CONST_DOUBLE
470 (define_insn "" 475 (define_insn ""
471 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 476 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
472 (plus:DI 477 (plus:DI
473 (mult:DI (sign_extend:DI 478 (mult:DI (sign_extend:DI
474 (match_operand:SI 1 "nonimmediate_operand" "g")) 479 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
475 (sign_extend:DI 480 (sign_extend:DI
476 (match_operand:SI 2 "nonimmediate_operand" "g"))) 481 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
477 (match_operand:DI 3 "immediate_operand" "F")))] 482 (match_operand:DI 3 "immediate_operand" "F")))]
478 "GET_CODE (operands[3]) == CONST_DOUBLE 483 "GET_CODE (operands[3]) == CONST_DOUBLE
479 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)" 484 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
480 "* 485 "*
481 { 486 {
495 div<VAXfp:fsfx>2 %2,%0 500 div<VAXfp:fsfx>2 %2,%0
496 div<VAXfp:fsfx>3 %2,%1,%0") 501 div<VAXfp:fsfx>3 %2,%1,%0")
497 502
498 (define_insn "div<mode>3" 503 (define_insn "div<mode>3"
499 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 504 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
500 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,g") 505 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
501 (match_operand:VAXint 2 "general_operand" "g,g")))] 506 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
502 "" 507 ""
503 "@ 508 "@
504 div<VAXint:isfx>2 %2,%0 509 div<VAXint:isfx>2 %2,%0
505 div<VAXint:isfx>3 %2,%1,%0") 510 div<VAXint:isfx>3 %2,%1,%0")
506 511
525 " 530 "
526 { 531 {
527 rtx op1 = operands[1]; 532 rtx op1 = operands[1];
528 533
529 /* If there is a constant argument, complement that one. */ 534 /* If there is a constant argument, complement that one. */
530 if (CONST_INT_P (operands[2]) && !CONST_INT_P (op1)) 535 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
531 { 536 {
532 operands[1] = operands[2]; 537 operands[1] = operands[2];
533 operands[2] = op1; 538 operands[2] = op1;
534 op1 = operands[1]; 539 op1 = operands[1];
535 } 540 }
540 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); 545 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
541 }") 546 }")
542 547
543 (define_insn "*and<mode>" 548 (define_insn "*and<mode>"
544 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 549 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
545 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "g,g")) 550 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
546 (match_operand:VAXint 2 "general_operand" "0,g")))] 551 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
547 "" 552 ""
548 "@ 553 "@
549 bic<VAXint:isfx>2 %1,%0 554 bic<VAXint:isfx>2 %1,%0
550 bic<VAXint:isfx>3 %1,%2,%0") 555 bic<VAXint:isfx>3 %1,%2,%0")
551 556
554 ;; longer a problem. However, having these patterns allows optimization 559 ;; longer a problem. However, having these patterns allows optimization
555 ;; opportunities in combine.c. 560 ;; opportunities in combine.c.
556 561
557 (define_insn "*and<mode>_const_int" 562 (define_insn "*and<mode>_const_int"
558 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 563 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
559 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,g") 564 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
560 (match_operand:VAXint 2 "const_int_operand" "n,n")))] 565 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
561 "" 566 ""
562 "@ 567 "@
563 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0 568 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
564 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0") 569 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
566 571
567 ;;- Bit set instructions. 572 ;;- Bit set instructions.
568 573
569 (define_insn "ior<mode>3" 574 (define_insn "ior<mode>3"
570 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 575 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
571 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g") 576 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
572 (match_operand:VAXint 2 "general_operand" "g,0,g")))] 577 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
573 "" 578 ""
574 "@ 579 "@
575 bis<VAXint:isfx>2 %2,%0 580 bis<VAXint:isfx>2 %2,%0
576 bis<VAXint:isfx>2 %1,%0 581 bis<VAXint:isfx>2 %1,%0
577 bis<VAXint:isfx>3 %2,%1,%0") 582 bis<VAXint:isfx>3 %2,%1,%0")
578 583
579 ;;- xor instructions. 584 ;;- xor instructions.
580 585
581 (define_insn "xor<mode>3" 586 (define_insn "xor<mode>3"
582 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 587 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
583 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g") 588 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
584 (match_operand:VAXint 2 "general_operand" "g,0,g")))] 589 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
585 "" 590 ""
586 "@ 591 "@
587 xor<VAXint:isfx>2 %2,%0 592 xor<VAXint:isfx>2 %2,%0
588 xor<VAXint:isfx>2 %1,%0 593 xor<VAXint:isfx>2 %1,%0
589 xor<VAXint:isfx>3 %2,%1,%0") 594 xor<VAXint:isfx>3 %2,%1,%0")
595 "" 600 ""
596 "mneg<VAXfp:fsfx> %1,%0") 601 "mneg<VAXfp:fsfx> %1,%0")
597 602
598 (define_insn "neg<mode>2" 603 (define_insn "neg<mode>2"
599 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 604 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
600 (neg:VAXint (match_operand:VAXint 1 "general_operand" "g")))] 605 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
601 "" 606 ""
602 "mneg<VAXint:isfx> %1,%0") 607 "mneg<VAXint:isfx> %1,%0")
603 608
604 (define_insn "one_cmpl<mode>2" 609 (define_insn "one_cmpl<mode>2"
605 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 610 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
606 (not:VAXint (match_operand:VAXint 1 "general_operand" "g")))] 611 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
607 "" 612 ""
608 "mcom<VAXint:isfx> %1,%0") 613 "mcom<VAXint:isfx> %1,%0")
609 614
610 615
611 ;; Arithmetic right shift on the VAX works by negating the shift count, 616 ;; Arithmetic right shift on the VAX works by negating the shift count,
618 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 623 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
619 (match_operand:QI 2 "general_operand" "g")))] 624 (match_operand:QI 2 "general_operand" "g")))]
620 "" 625 ""
621 " 626 "
622 { 627 {
623 if (!CONST_INT_P (operands[2])) 628 if (! CONST_INT_P(operands[2]))
624 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 629 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
625 }") 630 }")
626 631
627 (define_insn "" 632 (define_insn ""
628 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 633 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
629 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 634 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
630 (match_operand:QI 2 "const_int_operand" "n")))] 635 (match_operand:QI 2 "const_int_operand" "n")))]
631 "" 636 ""
632 "ashl $%n2,%1,%0") 637 "ashl $%n2,%1,%0")
633 638
634 (define_insn "" 639 (define_insn ""
635 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 640 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
636 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 641 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
637 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 642 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
638 "" 643 ""
639 "ashl %2,%1,%0") 644 "ashl %2,%1,%0")
640 645
641 (define_insn "ashlsi3" 646 (define_insn "ashlsi3"
642 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 647 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
643 (ashift:SI (match_operand:SI 1 "general_operand" "g") 648 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
644 (match_operand:QI 2 "general_operand" "g")))] 649 (match_operand:QI 2 "general_operand" "g")))]
645 "" 650 ""
646 "* 651 "*
647 { 652 {
648 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 653 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
649 return \"addl2 %0,%0\"; 654 return \"addl2 %0,%0\";
650 if (REG_P (operands[1]) 655 if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
651 && CONST_INT_P (operands[2]))
652 { 656 {
653 int i = INTVAL (operands[2]); 657 int i = INTVAL (operands[2]);
654 if (i == 1) 658 if (i == 1)
655 return \"addl3 %1,%1,%0\"; 659 return \"addl3 %1,%1,%0\";
656 if (i == 2) 660 if (i == 2 && !optimize_size)
657 return \"moval 0[%1],%0\"; 661 {
658 if (i == 3) 662 if (push_operand (operands[0], SImode))
659 return \"movad 0[%1],%0\"; 663 return \"pushal 0[%1]\";
664 return \"moval 0[%1],%0\";
665 }
666 if (i == 3 && !optimize_size)
667 {
668 if (push_operand (operands[0], SImode))
669 return \"pushaq 0[%1]\";
670 return \"movaq 0[%1],%0\";
671 }
660 } 672 }
661 return \"ashl %2,%1,%0\"; 673 return \"ashl %2,%1,%0\";
662 }") 674 }")
663 675
664 ;; Arithmetic right shift on the VAX works by negating the shift count. 676 ;; Arithmetic right shift on the VAX works by negating the shift count.
693 705
694 (define_expand "lshrsi3" 706 (define_expand "lshrsi3"
695 [(set (match_dup 3) 707 [(set (match_dup 3)
696 (minus:QI (const_int 32) 708 (minus:QI (const_int 32)
697 (match_dup 4))) 709 (match_dup 4)))
698 (set (match_operand:SI 0 "general_operand" "=g") 710 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
699 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 711 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
700 (match_dup 3) 712 (match_dup 3)
701 (match_operand:SI 2 "register_operand" "g")))] 713 (match_operand:SI 2 "register_operand" "g")))]
702 "" 714 ""
703 " 715 "
712 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 724 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
713 (match_operand:QI 2 "general_operand" "g")))] 725 (match_operand:QI 2 "general_operand" "g")))]
714 "" 726 ""
715 " 727 "
716 { 728 {
717 if (!CONST_INT_P (operands[2])) 729 if (! CONST_INT_P (operands[2]))
718 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 730 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
719 }") 731 }")
720 732
721 (define_insn "rotlsi3" 733 (define_insn "rotlsi3"
722 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 734 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
723 (rotate:SI (match_operand:SI 1 "general_operand" "g") 735 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
724 (match_operand:QI 2 "general_operand" "g")))] 736 (match_operand:QI 2 "general_operand" "g")))]
725 "" 737 ""
726 "rotl %2,%1,%0") 738 "rotl %2,%1,%0")
727 739
728 (define_insn "" 740 (define_insn ""
729 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 741 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
730 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 742 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
731 (match_operand:QI 2 "const_int_operand" "n")))] 743 (match_operand:QI 2 "const_int_operand" "n")))]
732 "" 744 ""
733 "rotl %R2,%1,%0") 745 "rotl %R2,%1,%0")
734 746
735 (define_insn "" 747 (define_insn ""
736 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 748 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
737 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 749 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
738 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 750 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
739 "" 751 ""
740 "rotl %2,%1,%0") 752 "rotl %2,%1,%0")
741 753
742 ;This insn is probably slower than a multiply and an add. 754 ;This insn is probably slower than a multiply and an add.
759 (match_operand:SI 2 "const_int_operand" "n")) 771 (match_operand:SI 2 "const_int_operand" "n"))
760 (match_operand:SI 3 "general_operand" "g"))] 772 (match_operand:SI 3 "general_operand" "g"))]
761 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 773 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
762 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 774 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
763 && (REG_P (operands[0]) 775 && (REG_P (operands[0])
764 || !mode_dependent_address_p (XEXP (operands[0], 0)))" 776 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
765 "* 777 "*
766 { 778 {
767 if (REG_P (operands[0])) 779 if (REG_P (operands[0]))
768 { 780 {
769 if (INTVAL (operands[2]) != 0) 781 if (INTVAL (operands[2]) != 0)
787 (match_operand:QI 2 "const_int_operand" "n") 799 (match_operand:QI 2 "const_int_operand" "n")
788 (match_operand:SI 3 "const_int_operand" "n")))] 800 (match_operand:SI 3 "const_int_operand" "n")))]
789 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 801 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
790 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 802 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
791 && (REG_P (operands[1]) 803 && (REG_P (operands[1])
792 || !mode_dependent_address_p (XEXP (operands[1], 0)))" 804 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
793 "* 805 "*
794 { 806 {
795 if (REG_P (operands[1])) 807 if (REG_P (operands[1]))
796 { 808 {
797 if (INTVAL (operands[3]) != 0) 809 if (INTVAL (operands[3]) != 0)
814 (match_operand:QI 2 "const_int_operand" "n") 826 (match_operand:QI 2 "const_int_operand" "n")
815 (match_operand:SI 3 "const_int_operand" "n")))] 827 (match_operand:SI 3 "const_int_operand" "n")))]
816 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 828 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
817 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 829 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
818 && (REG_P (operands[1]) 830 && (REG_P (operands[1])
819 || !mode_dependent_address_p (XEXP (operands[1], 0)))" 831 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
820 "* 832 "*
821 { 833 {
822 if (REG_P (operands[1])) 834 if (REG_P (operands[1]))
823 { 835 {
824 if (INTVAL (operands[3]) != 0) 836 if (INTVAL (operands[3]) != 0)
840 (define_insn "" 852 (define_insn ""
841 [(set (cc0) 853 [(set (cc0)
842 (compare 854 (compare
843 (sign_extract:SI (match_operand:SI 0 "register_operand" "r") 855 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
844 (match_operand:QI 1 "general_operand" "g") 856 (match_operand:QI 1 "general_operand" "g")
845 (match_operand:SI 2 "general_operand" "g")) 857 (match_operand:SI 2 "general_operand" "nrmT"))
846 (match_operand:SI 3 "general_operand" "g")))] 858 (match_operand:SI 3 "general_operand" "nrmT")))]
847 "" 859 ""
848 "cmpv %2,%1,%0,%3") 860 "cmpv %2,%1,%0,%3")
849 861
850 (define_insn "" 862 (define_insn ""
851 [(set (cc0) 863 [(set (cc0)
852 (compare 864 (compare
853 (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 865 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
854 (match_operand:QI 1 "general_operand" "g") 866 (match_operand:QI 1 "general_operand" "g")
855 (match_operand:SI 2 "general_operand" "g")) 867 (match_operand:SI 2 "general_operand" "nrmT"))
856 (match_operand:SI 3 "general_operand" "g")))] 868 (match_operand:SI 3 "general_operand" "nrmT")))]
857 "" 869 ""
858 "cmpzv %2,%1,%0,%3") 870 "cmpzv %2,%1,%0,%3")
859 871
860 ;; When the field position and size are constant and the destination 872 ;; When the field position and size are constant and the destination
861 ;; is a register, extv and extzv are much slower than a rotate followed 873 ;; is a register, extv and extzv are much slower than a rotate followed
864 876
865 (define_insn "" 877 (define_insn ""
866 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 878 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
867 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro") 879 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
868 (match_operand:QI 2 "general_operand" "g") 880 (match_operand:QI 2 "general_operand" "g")
869 (match_operand:SI 3 "general_operand" "g")))] 881 (match_operand:SI 3 "general_operand" "nrmT")))]
870 "" 882 ""
871 "* 883 "*
872 { 884 {
873 if (!CONST_INT_P (operands[3]) 885 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
874 || !CONST_INT_P (operands[2]) 886 || ! REG_P (operands[0])
875 || !REG_P (operands[0])
876 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)) 887 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
877 return \"extv %3,%2,%1,%0\"; 888 return \"extv %3,%2,%1,%0\";
878 if (INTVAL (operands[2]) == 8) 889 if (INTVAL (operands[2]) == 8)
879 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 890 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
880 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 891 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
882 893
883 (define_insn "" 894 (define_insn ""
884 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 895 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
885 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro") 896 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
886 (match_operand:QI 2 "general_operand" "g") 897 (match_operand:QI 2 "general_operand" "g")
887 (match_operand:SI 3 "general_operand" "g")))] 898 (match_operand:SI 3 "general_operand" "nrmT")))]
888 "" 899 ""
889 "* 900 "*
890 { 901 {
891 if (!CONST_INT_P (operands[3]) 902 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
892 || !CONST_INT_P (operands[2]) 903 || ! REG_P (operands[0]))
893 || !REG_P (operands[0]))
894 return \"extzv %3,%2,%1,%0\"; 904 return \"extzv %3,%2,%1,%0\";
895 if (INTVAL (operands[2]) == 8) 905 if (INTVAL (operands[2]) == 8)
896 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 906 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
897 if (INTVAL (operands[2]) == 16) 907 if (INTVAL (operands[2]) == 16)
898 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 908 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
910 (define_insn "" 920 (define_insn ""
911 [(set (cc0) 921 [(set (cc0)
912 (compare 922 (compare
913 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m") 923 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
914 (match_operand:QI 1 "general_operand" "g") 924 (match_operand:QI 1 "general_operand" "g")
915 (match_operand:SI 2 "general_operand" "g")) 925 (match_operand:SI 2 "general_operand" "nrmT"))
916 (match_operand:SI 3 "general_operand" "g")))] 926 (match_operand:SI 3 "general_operand" "nrmT")))]
917 "" 927 ""
918 "cmpv %2,%1,%0,%3") 928 "cmpv %2,%1,%0,%3")
919 929
920 (define_insn "" 930 (define_insn ""
921 [(set (cc0) 931 [(set (cc0)
922 (compare 932 (compare
923 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") 933 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
924 (match_operand:QI 1 "general_operand" "g") 934 (match_operand:QI 1 "general_operand" "g")
925 (match_operand:SI 2 "general_operand" "g")) 935 (match_operand:SI 2 "general_operand" "nrmT"))
926 (match_operand:SI 3 "general_operand" "g")))] 936 (match_operand:SI 3 "general_operand" "nrmT")))]
927 "" 937 ""
928 "cmpzv %2,%1,%0,%3") 938 "cmpzv %2,%1,%0,%3")
929 939
930 (define_insn "extv" 940 (define_insn "extv"
931 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 941 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
932 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 942 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
933 (match_operand:QI 2 "general_operand" "g") 943 (match_operand:QI 2 "general_operand" "g")
934 (match_operand:SI 3 "general_operand" "g")))] 944 (match_operand:SI 3 "general_operand" "nrmT")))]
935 "" 945 ""
936 "* 946 "*
937 { 947 {
938 if (!REG_P (operands[0]) 948 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
939 || !CONST_INT_P (operands[2])
940 || !CONST_INT_P (operands[3]) 949 || !CONST_INT_P (operands[3])
941 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16) 950 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
942 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 951 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
943 || side_effects_p (operands[1]) 952 || side_effects_p (operands[1])
944 || (MEM_P (operands[1]) 953 || (MEM_P (operands[1])
959 968
960 (define_insn "" 969 (define_insn ""
961 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 970 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
962 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 971 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
963 (match_operand:QI 2 "general_operand" "g") 972 (match_operand:QI 2 "general_operand" "g")
964 (match_operand:SI 3 "general_operand" "g")))] 973 (match_operand:SI 3 "general_operand" "nrmT")))]
965 "" 974 ""
966 "* 975 "*
967 { 976 {
968 if (!REG_P (operands[0]) 977 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
969 || !CONST_INT_P (operands[2])
970 || !CONST_INT_P (operands[3]) 978 || !CONST_INT_P (operands[3])
971 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 979 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
972 || side_effects_p (operands[1]) 980 || side_effects_p (operands[1])
973 || (MEM_P (operands[1]) 981 || (MEM_P (operands[1])
974 && mode_dependent_address_p (XEXP (operands[1], 0)))) 982 && mode_dependent_address_p (XEXP (operands[1], 0))))
975 return \"extzv %3,%2,%1,%0\"; 983 return \"extzv %3,%2,%1,%0\";
976 if (INTVAL (operands[2]) == 8) 984 if (INTVAL (operands[2]) == 8)
977 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 985 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
978 if (INTVAL (operands[2]) == 16) 986 if (INTVAL (operands[2]) == 16)
979 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 987 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
988 if (MEM_P (operands[1])
989 && GET_CODE (XEXP (operands[1], 0)) == PLUS
990 && REG_P (XEXP (XEXP (operands[1], 0), 0))
991 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
992 && CONST_INT_P (operands[2])
993 && CONST_INT_P (operands[3]))
994 {
995 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
996 HOST_WIDE_INT l = INTVAL (operands[2]);
997 HOST_WIDE_INT v = INTVAL (operands[3]);
998 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
999 {
1000 rtx tmp;
1001 tmp = XEXP (XEXP (operands[1], 0), 0);
1002 if (o & ~3)
1003 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1004 operands[1] = gen_rtx_MEM (QImode, tmp);
1005 operands[3] = GEN_INT (v + (o & 3) * 8);
1006 }
1007 if (optimize_size)
1008 return \"extzv %3,%2,%1,%0\";
1009 }
980 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 1010 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
981 }") 1011 }")
982 1012
983 (define_expand "insv" 1013 (define_expand "insv"
984 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 1014 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
989 "") 1019 "")
990 1020
991 (define_insn "" 1021 (define_insn ""
992 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g") 1022 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
993 (match_operand:QI 1 "general_operand" "g") 1023 (match_operand:QI 1 "general_operand" "g")
994 (match_operand:SI 2 "general_operand" "g")) 1024 (match_operand:SI 2 "general_operand" "nrmT"))
995 (match_operand:SI 3 "general_operand" "g"))] 1025 (match_operand:SI 3 "general_operand" "nrmT"))]
996 "" 1026 ""
997 "insv %3,%2,%1,%0") 1027 "*
1028 {
1029 if (MEM_P (operands[0])
1030 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1031 && REG_P (XEXP (XEXP (operands[0], 0), 0))
1032 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
1033 && CONST_INT_P (operands[1])
1034 && CONST_INT_P (operands[2]))
1035 {
1036 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1037 HOST_WIDE_INT v = INTVAL (operands[2]);
1038 HOST_WIDE_INT l = INTVAL (operands[1]);
1039 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1040 {
1041 rtx tmp;
1042 tmp = XEXP (XEXP (operands[0], 0), 0);
1043 if (o & ~3)
1044 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1045 operands[0] = gen_rtx_MEM (QImode, tmp);
1046 operands[2] = GEN_INT (v + (o & 3) * 8);
1047 }
1048 }
1049 return \"insv %3,%2,%1,%0\";
1050 }")
998 1051
999 (define_insn "" 1052 (define_insn ""
1000 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1053 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1001 (match_operand:QI 1 "general_operand" "g") 1054 (match_operand:QI 1 "general_operand" "g")
1002 (match_operand:SI 2 "general_operand" "g")) 1055 (match_operand:SI 2 "general_operand" "nrmT"))
1003 (match_operand:SI 3 "general_operand" "g"))] 1056 (match_operand:SI 3 "general_operand" "nrmT"))]
1004 "" 1057 ""
1005 "insv %3,%2,%1,%0") 1058 "insv %3,%2,%1,%0")
1006 1059
1007 ;; Unconditional jump 1060 ;; Unconditional jump
1008 (define_insn "jump" 1061 (define_insn "jump"
1010 (label_ref (match_operand 0 "" "")))] 1063 (label_ref (match_operand 0 "" "")))]
1011 "" 1064 ""
1012 "jbr %l0") 1065 "jbr %l0")
1013 1066
1014 ;; Conditional jumps 1067 ;; Conditional jumps
1015 (define_code_iterator any_cond [eq ne gt lt gtu ltu ge le geu leu]) 1068
1016 1069 (define_expand "cbranch<mode>4"
1017 (define_insn "b<code>" 1070 [(set (cc0)
1071 (compare (match_operand:VAXint 1 "nonimmediate_operand" "")
1072 (match_operand:VAXint 2 "general_operand" "")))
1073 (set (pc)
1074 (if_then_else
1075 (match_operator 0 "ordered_comparison_operator" [(cc0)
1076 (const_int 0)])
1077 (label_ref (match_operand 3 "" ""))
1078 (pc)))]
1079 "")
1080
1081 (define_expand "cbranch<mode>4"
1082 [(set (cc0)
1083 (compare (match_operand:VAXfp 1 "general_operand" "")
1084 (match_operand:VAXfp 2 "general_operand" "")))
1085 (set (pc)
1086 (if_then_else
1087 (match_operator 0 "ordered_comparison_operator" [(cc0)
1088 (const_int 0)])
1089 (label_ref (match_operand 3 "" ""))
1090 (pc)))]
1091 "")
1092
1093 (define_insn "*branch"
1018 [(set (pc) 1094 [(set (pc)
1019 (if_then_else (any_cond (cc0) 1095 (if_then_else (match_operator 0 "ordered_comparison_operator"
1020 (const_int 0)) 1096 [(cc0)
1021 (label_ref (match_operand 0 "" "")) 1097 (const_int 0)])
1098 (label_ref (match_operand 1 "" ""))
1022 (pc)))] 1099 (pc)))]
1023 "" 1100 ""
1024 "* return vax_output_conditional_branch (<CODE>);") 1101 "j%c0 %l1")
1025 1102
1026 ;; Recognize reversed jumps. 1103 ;; Recognize reversed jumps.
1027 (define_insn "" 1104 (define_insn "*branch_reversed"
1028 [(set (pc) 1105 [(set (pc)
1029 (if_then_else (match_operator 0 "comparison_operator" 1106 (if_then_else (match_operator 0 "ordered_comparison_operator"
1030 [(cc0) 1107 [(cc0)
1031 (const_int 0)]) 1108 (const_int 0)])
1032 (pc) 1109 (pc)
1033 (label_ref (match_operand 1 "" ""))))] 1110 (label_ref (match_operand 1 "" ""))))]
1034 "" 1111 ""
1042 (define_insn "" 1119 (define_insn ""
1043 [(set (pc) 1120 [(set (pc)
1044 (if_then_else 1121 (if_then_else
1045 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 1122 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1046 (const_int 1) 1123 (const_int 1)
1047 (match_operand:SI 1 "general_operand" "I,g")) 1124 (match_operand:SI 1 "general_operand" "I,nrmT"))
1048 (const_int 0)) 1125 (const_int 0))
1049 (label_ref (match_operand 2 "" "")) 1126 (label_ref (match_operand 2 "" ""))
1050 (pc)))] 1127 (pc)))]
1051 "" 1128 ""
1052 "@ 1129 "@
1056 (define_insn "" 1133 (define_insn ""
1057 [(set (pc) 1134 [(set (pc)
1058 (if_then_else 1135 (if_then_else
1059 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 1136 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1060 (const_int 1) 1137 (const_int 1)
1061 (match_operand:SI 1 "general_operand" "I,g")) 1138 (match_operand:SI 1 "general_operand" "I,nrmT"))
1062 (const_int 0)) 1139 (const_int 0))
1063 (label_ref (match_operand 2 "" "")) 1140 (label_ref (match_operand 2 "" ""))
1064 (pc)))] 1141 (pc)))]
1065 "" 1142 ""
1066 "@ 1143 "@
1070 (define_insn "" 1147 (define_insn ""
1071 [(set (pc) 1148 [(set (pc)
1072 (if_then_else 1149 (if_then_else
1073 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1150 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1074 (const_int 1) 1151 (const_int 1)
1075 (match_operand:SI 1 "general_operand" "I,g")) 1152 (match_operand:SI 1 "general_operand" "I,nrmT"))
1076 (const_int 0)) 1153 (const_int 0))
1077 (label_ref (match_operand 2 "" "")) 1154 (label_ref (match_operand 2 "" ""))
1078 (pc)))] 1155 (pc)))]
1079 "" 1156 ""
1080 "@ 1157 "@
1084 (define_insn "" 1161 (define_insn ""
1085 [(set (pc) 1162 [(set (pc)
1086 (if_then_else 1163 (if_then_else
1087 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1164 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1088 (const_int 1) 1165 (const_int 1)
1089 (match_operand:SI 1 "general_operand" "I,g")) 1166 (match_operand:SI 1 "general_operand" "I,nrmT"))
1090 (const_int 0)) 1167 (const_int 0))
1091 (label_ref (match_operand 2 "" "")) 1168 (label_ref (match_operand 2 "" ""))
1092 (pc)))] 1169 (pc)))]
1093 "" 1170 ""
1094 "@ 1171 "@
1133 (define_insn "" 1210 (define_insn ""
1134 [(set (pc) 1211 [(set (pc)
1135 (if_then_else 1212 (if_then_else
1136 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1213 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1137 (const_int 1)) 1214 (const_int 1))
1138 (match_operand:SI 1 "general_operand" "g")) 1215 (match_operand:SI 1 "general_operand" "nrmT"))
1139 (label_ref (match_operand 2 "" "")) 1216 (label_ref (match_operand 2 "" ""))
1140 (pc))) 1217 (pc)))
1141 (set (match_dup 0) 1218 (set (match_dup 0)
1142 (plus:SI (match_dup 0) 1219 (plus:SI (match_dup 0)
1143 (const_int 1)))] 1220 (const_int 1)))]
1146 1223
1147 (define_insn "" 1224 (define_insn ""
1148 [(set (pc) 1225 [(set (pc)
1149 (if_then_else 1226 (if_then_else
1150 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 1227 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1151 (match_operand:SI 1 "general_operand" "g")) 1228 (match_operand:SI 1 "general_operand" "nrmT"))
1152 (label_ref (match_operand 2 "" "")) 1229 (label_ref (match_operand 2 "" ""))
1153 (pc))) 1230 (pc)))
1154 (set (match_dup 0) 1231 (set (match_dup 0)
1155 (plus:SI (match_dup 0) 1232 (plus:SI (match_dup 0)
1156 (const_int 1)))] 1233 (const_int 1)))]
1160 (define_insn "" 1237 (define_insn ""
1161 [(set (pc) 1238 [(set (pc)
1162 (if_then_else 1239 (if_then_else
1163 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1240 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1164 (const_int 1)) 1241 (const_int 1))
1165 (match_operand:SI 1 "general_operand" "g")) 1242 (match_operand:SI 1 "general_operand" "nrmT"))
1166 (label_ref (match_operand 2 "" "")) 1243 (label_ref (match_operand 2 "" ""))
1167 (pc))) 1244 (pc)))
1168 (set (match_dup 0) 1245 (set (match_dup 0)
1169 (plus:SI (match_dup 0) 1246 (plus:SI (match_dup 0)
1170 (const_int 1)))] 1247 (const_int 1)))]
1173 1250
1174 (define_insn "" 1251 (define_insn ""
1175 [(set (pc) 1252 [(set (pc)
1176 (if_then_else 1253 (if_then_else
1177 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 1254 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1178 (match_operand:SI 1 "general_operand" "g")) 1255 (match_operand:SI 1 "general_operand" "nrmT"))
1179 (label_ref (match_operand 2 "" "")) 1256 (label_ref (match_operand 2 "" ""))
1180 (pc))) 1257 (pc)))
1181 (set (match_dup 0) 1258 (set (match_dup 0)
1182 (plus:SI (match_dup 0) 1259 (plus:SI (match_dup 0)
1183 (const_int 1)))] 1260 (const_int 1)))]
1276 "calls $0,%0") 1353 "calls $0,%0")
1277 1354
1278 (define_expand "call_value" 1355 (define_expand "call_value"
1279 [(set (match_operand 0 "" "") 1356 [(set (match_operand 0 "" "")
1280 (call (match_operand:QI 1 "memory_operand" "") 1357 (call (match_operand:QI 1 "memory_operand" "")
1281 (match_operand:SI 2 "const_int_operand" "")))] 1358 (match_operand:SI 2 "const_int_operand" "")))]
1282 "" 1359 ""
1283 " 1360 "
1284 { 1361 {
1285 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 1362 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1286 during EH unwinding. We must include the argument count pushed by 1363 during EH unwinding. We must include the argument count pushed by
1297 1374
1298 ;; Call subroutine returning any type. 1375 ;; Call subroutine returning any type.
1299 1376
1300 (define_expand "untyped_call" 1377 (define_expand "untyped_call"
1301 [(parallel [(call (match_operand 0 "" "") 1378 [(parallel [(call (match_operand 0 "" "")
1302 (const_int 0)) 1379 (const_int 0))
1303 (match_operand 1 "" "") 1380 (match_operand 1 "" "")
1304 (match_operand 2 "" "")])] 1381 (match_operand 2 "" "")])]
1305 "" 1382 ""
1306 " 1383 "
1307 { 1384 {
1308 int i; 1385 int i;
1309 1386
1384 (match_operand:SI 2 "general_operand" "") 1461 (match_operand:SI 2 "general_operand" "")
1385 (match_operand 3 "" "") 1462 (match_operand 3 "" "")
1386 (match_operand 4 "" "")] 1463 (match_operand 4 "" "")]
1387 "" 1464 ""
1388 { 1465 {
1466 rtx test;
1467
1389 /* i = index - minimum_bound; 1468 /* i = index - minimum_bound;
1390 But only if the lower bound is not already zero. */ 1469 But only if the lower bound is not already zero. */
1391 if (operands[1] != const0_rtx) 1470 if (operands[1] != const0_rtx)
1392 { 1471 {
1393 rtx index = gen_reg_rtx (SImode); 1472 rtx index = gen_reg_rtx (SImode);
1395 operands[0], 1474 operands[0],
1396 GEN_INT (-INTVAL (operands[1])))); 1475 GEN_INT (-INTVAL (operands[1]))));
1397 operands[0] = index; 1476 operands[0] = index;
1398 } 1477 }
1399 1478
1400 /* if (i > (maximum_bound - minimum_bound + 1) goto default; */ 1479 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */
1401 emit_insn (gen_cmpsi (operands[0], operands[2])); 1480 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
1402 emit_jump_insn (gen_bgtu (operands[4])); 1481 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
1403 1482
1404 /* casesi (i, 0, table); */ 1483 /* casesi (i, 0, table); */
1405 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3])); 1484 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1406 DONE; 1485 DONE;
1407 }) 1486 })
1411 ;; before this, see the define_expand above. 1490 ;; before this, see the define_expand above.
1412 (define_insn "casesi1" 1491 (define_insn "casesi1"
1413 [(match_operand:SI 1 "const_int_operand" "n") 1492 [(match_operand:SI 1 "const_int_operand" "n")
1414 (set (pc) 1493 (set (pc)
1415 (plus:SI (sign_extend:SI 1494 (plus:SI (sign_extend:SI
1416 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "g") 1495 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT")
1417 (const_int 2)) 1496 (const_int 2))
1418 (pc)))) 1497 (pc))))
1419 (label_ref:SI (match_operand 2 "" ""))))] 1498 (label_ref:SI (match_operand 2 "" ""))))]
1420 "" 1499 ""
1421 "casel %0,$0,%1") 1500 "casel %0,$0,%1")
1501
1502 (define_insn "pushextsym"
1503 [(set (match_operand:SI 0 "push_operand" "=g")
1504 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1505 ""
1506 "pushab %a1")
1507
1508 (define_insn "movextsym"
1509 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1510 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1511 ""
1512 "movab %a1,%0")
1513
1514 (define_insn "pushlclsym"
1515 [(set (match_operand:SI 0 "push_operand" "=g")
1516 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1517 ""
1518 "pushab %a1")
1519
1520 (define_insn "movlclsym"
1521 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1522 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1523 ""
1524 "movab %a1,%0")
1422 1525
1423 ;;- load or push effective address 1526 ;;- load or push effective address
1424 ;; These come after the move and add/sub patterns 1527 ;; These come after the move and add/sub patterns
1425 ;; because we don't want pushl $1 turned into pushad 1. 1528 ;; because we don't want pushl $1 turned into pushad 1.
1426 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. 1529 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1427 1530
1428 ;; It does not work to use constraints to distinguish pushes from moves, 1531 ;; It does not work to use constraints to distinguish pushes from moves,
1429 ;; because < matches any autodecrement, not just a push. 1532 ;; because < matches any autodecrement, not just a push.
1430 1533
1431 (define_insn "" 1534 (define_insn "pushaddr<mode>"
1432 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1535 [(set (match_operand:SI 0 "push_operand" "=g")
1433 (match_operand:QI 1 "address_operand" "p"))] 1536 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1434 "" 1537 ""
1435 "* 1538 "pusha<VAXintQHSD:isfx> %a1")
1436 { 1539
1437 if (push_operand (operands[0], SImode)) 1540 (define_insn "movaddr<mode>"
1438 return \"pushab %a1\"; 1541 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1439 else 1542 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1440 return \"movab %a1,%0\"; 1543 ""
1441 }") 1544 "mova<VAXintQHSD:isfx> %a1,%0")
1442 1545
1443 (define_insn "" 1546 (define_insn "pushaddr<mode>"
1444 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1547 [(set (match_operand:SI 0 "push_operand" "=g")
1445 (match_operand:HI 1 "address_operand" "p"))] 1548 (match_operand:VAXfp 1 "address_operand" "p"))]
1446 "" 1549 ""
1447 "* 1550 "pusha<VAXfp:fsfx> %a1")
1448 { 1551
1449 if (push_operand (operands[0], SImode)) 1552 (define_insn "movaddr<mode>"
1450 return \"pushaw %a1\"; 1553 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1451 else 1554 (match_operand:VAXfp 1 "address_operand" "p"))]
1452 return \"movaw %a1,%0\"; 1555 ""
1453 }") 1556 "mova<VAXfp:fsfx> %a1,%0")
1454
1455 (define_insn ""
1456 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1457 (match_operand:SI 1 "address_operand" "p"))]
1458 ""
1459 "*
1460 {
1461 if (push_operand (operands[0], SImode))
1462 return \"pushal %a1\";
1463 else
1464 return \"moval %a1,%0\";
1465 }")
1466
1467 (define_insn ""
1468 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1469 (match_operand:DI 1 "address_operand" "p"))]
1470 ""
1471 "*
1472 {
1473 if (push_operand (operands[0], SImode))
1474 return \"pushaq %a1\";
1475 else
1476 return \"movaq %a1,%0\";
1477 }")
1478
1479 (define_insn ""
1480 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1481 (match_operand:SF 1 "address_operand" "p"))]
1482 ""
1483 "*
1484 {
1485 if (push_operand (operands[0], SImode))
1486 return \"pushaf %a1\";
1487 else
1488 return \"movaf %a1,%0\";
1489 }")
1490
1491 (define_insn ""
1492 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1493 (match_operand:DF 1 "address_operand" "p"))]
1494 ""
1495 "*
1496 {
1497 if (push_operand (operands[0], SImode))
1498 return \"pushad %a1\";
1499 else
1500 return \"movad %a1,%0\";
1501 }")
1502 1557
1503 ;; These used to be peepholes, but it is more straightforward to do them 1558 ;; These used to be peepholes, but it is more straightforward to do them
1504 ;; as single insns. However, we must force the output to be a register 1559 ;; as single insns. However, we must force the output to be a register
1505 ;; if it is not an offsettable address so that we know that we can assign 1560 ;; if it is not an offsettable address so that we know that we can assign
1506 ;; to it twice. 1561 ;; to it twice.
1513 ;; with other operands constant. This is what the combiner converts the 1568 ;; with other operands constant. This is what the combiner converts the
1514 ;; above sequences to before attempting to recognize the new insn. 1569 ;; above sequences to before attempting to recognize the new insn.
1515 1570
1516 (define_insn "" 1571 (define_insn ""
1517 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 1572 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1518 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1573 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1519 (match_operand:QI 2 "const_int_operand" "n")) 1574 (match_operand:QI 2 "const_int_operand" "n"))
1520 (match_operand:SI 3 "const_int_operand" "n")))] 1575 (match_operand:SI 3 "const_int_operand" "n")))]
1521 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0" 1576 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1522 "* 1577 "*
1523 { 1578 {
1535 ;; bits that the ashl would anyways, in which case it should have been 1590 ;; bits that the ashl would anyways, in which case it should have been
1536 ;; optimized away. 1591 ;; optimized away.
1537 1592
1538 (define_insn "" 1593 (define_insn ""
1539 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 1594 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1540 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g") 1595 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1541 (match_operand:QI 2 "const_int_operand" "n")) 1596 (match_operand:QI 2 "const_int_operand" "n"))
1542 (match_operand:SI 3 "const_int_operand" "n")))] 1597 (match_operand:SI 3 "const_int_operand" "n")))]
1543 "" 1598 ""
1544 "* 1599 "*
1545 { 1600 {
1551 ;; Instruction sequence to sync the VAX instruction stream. 1606 ;; Instruction sequence to sync the VAX instruction stream.
1552 (define_insn "sync_istream" 1607 (define_insn "sync_istream"
1553 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)] 1608 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1554 "" 1609 ""
1555 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei") 1610 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
1611
1612 (define_expand "nonlocal_goto"
1613 [(use (match_operand 0 "general_operand" ""))
1614 (use (match_operand 1 "general_operand" ""))
1615 (use (match_operand 2 "general_operand" ""))
1616 (use (match_operand 3 "general_operand" ""))]
1617 ""
1618 {
1619 rtx lab = operands[1];
1620 rtx stack = operands[2];
1621 rtx fp = operands[3];
1622
1623 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
1624 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
1625
1626 emit_move_insn (hard_frame_pointer_rtx, fp);
1627 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
1628
1629 emit_use (hard_frame_pointer_rtx);
1630 emit_use (stack_pointer_rtx);
1631
1632 /* We'll convert this to direct jump via a peephole optimization. */
1633 emit_indirect_jump (copy_to_reg (lab));
1634 emit_barrier ();
1635 DONE;
1636 })