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comparison gcc/config/xtensa/xtensa.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
61 (define_code_iterator any_minmax [smin umin smax umax]) 61 (define_code_iterator any_minmax [smin umin smax umax])
62 62
63 ;; <minmax> expands to the opcode name for any_minmax operations. 63 ;; <minmax> expands to the opcode name for any_minmax operations.
64 (define_code_attr minmax [(smin "min") (umin "minu") 64 (define_code_attr minmax [(smin "min") (umin "minu")
65 (smax "max") (umax "maxu")]) 65 (smax "max") (umax "maxu")])
66
67 ;; This code iterator allows all branch instructions to be generated from
68 ;; a single define_expand template.
69 (define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu
70 uneq ltgt ungt unge unlt unle
71 unordered ordered])
72
73 ;; This code iterator is for setting a register from a comparison.
74 (define_code_iterator any_scc [eq ne gt ge lt le])
75 66
76 ;; This code iterator is for floating-point comparisons. 67 ;; This code iterator is for floating-point comparisons.
77 (define_code_iterator any_scc_sf [eq lt le uneq unlt unle unordered]) 68 (define_code_iterator any_scc_sf [eq lt le uneq unlt unle unordered])
78 (define_code_attr scc_sf [(eq "oeq") (lt "olt") (le "ole") 69 (define_code_attr scc_sf [(eq "oeq") (lt "olt") (le "ole")
79 (uneq "ueq") (unlt "ult") (unle "ule") 70 (uneq "ueq") (unlt "ult") (unle "ule")
1129 (set_attr "length" "6,6")]) 1120 (set_attr "length" "6,6")])
1130 1121
1131 1122
1132 ;; Comparisons. 1123 ;; Comparisons.
1133 1124
1134 ;; Handle comparisons by stashing away the operands and then using that 1125 ;; Conditional branches.
1135 ;; information in the subsequent conditional branch. 1126
1136 1127 (define_expand "cbranchsi4"
1137 (define_expand "cmpsi" 1128 [(match_operator 0 "comparison_operator"
1138 [(set (cc0) 1129 [(match_operand:SI 1 "register_operand")
1139 (compare:CC (match_operand:SI 0 "register_operand" "") 1130 (match_operand:SI 2 "nonmemory_operand")])
1140 (match_operand:SI 1 "nonmemory_operand" "")))] 1131 (match_operand 3 "")]
1141 "" 1132 ""
1142 { 1133 {
1143 branch_cmp[0] = operands[0]; 1134 xtensa_expand_conditional_branch (operands, SImode);
1144 branch_cmp[1] = operands[1]; 1135 DONE;
1145 branch_type = CMP_SI; 1136 })
1146 DONE; 1137
1147 }) 1138 (define_expand "cbranchsf4"
1148 1139 [(match_operator 0 "comparison_operator"
1149 (define_expand "cmpsf" 1140 [(match_operand:SF 1 "register_operand")
1150 [(set (cc0) 1141 (match_operand:SF 2 "register_operand")])
1151 (compare:CC (match_operand:SF 0 "register_operand" "") 1142 (match_operand 3 "")]
1152 (match_operand:SF 1 "register_operand" "")))]
1153 "TARGET_HARD_FLOAT" 1143 "TARGET_HARD_FLOAT"
1154 { 1144 {
1155 branch_cmp[0] = operands[0]; 1145 xtensa_expand_conditional_branch (operands, SFmode);
1156 branch_cmp[1] = operands[1];
1157 branch_type = CMP_SF;
1158 DONE;
1159 })
1160
1161
1162 ;; Conditional branches.
1163
1164 (define_expand "b<code>"
1165 [(set (pc)
1166 (if_then_else (any_cond (cc0) (const_int 0))
1167 (label_ref (match_operand 0 "" ""))
1168 (pc)))]
1169 ""
1170 {
1171 xtensa_expand_conditional_branch (operands, <CODE>);
1172 DONE; 1146 DONE;
1173 }) 1147 })
1174 1148
1175 ;; Branch patterns for standard integer comparisons 1149 ;; Branch patterns for standard integer comparisons
1176 1150
1351 (set_attr "length" "0")]) 1325 (set_attr "length" "0")])
1352 1326
1353 1327
1354 ;; Setting a register from a comparison. 1328 ;; Setting a register from a comparison.
1355 1329
1356 (define_expand "s<code>" 1330 (define_expand "cstoresi4"
1357 [(set (match_operand:SI 0 "register_operand" "") 1331 [(match_operand:SI 0 "register_operand")
1358 (any_scc:SI (match_dup 1) 1332 (match_operator 1 "xtensa_cstoresi_operator"
1359 (match_dup 2)))] 1333 [(match_operand:SI 2 "register_operand")
1360 "" 1334 (match_operand:SI 3 "nonmemory_operand")])]
1361 { 1335 ""
1362 operands[1] = gen_rtx_<CODE> (SImode, branch_cmp[0], branch_cmp[1]); 1336 {
1363 if (!xtensa_expand_scc (operands)) 1337 if (!xtensa_expand_scc (operands, SImode))
1364 FAIL; 1338 FAIL;
1365 DONE; 1339 DONE;
1366 }) 1340 })
1341
1342 (define_expand "cstoresf4"
1343 [(match_operand:SI 0 "register_operand")
1344 (match_operator:SI 1 "comparison_operator"
1345 [(match_operand:SF 2 "register_operand")
1346 (match_operand:SF 3 "register_operand")])]
1347 "TARGET_HARD_FLOAT"
1348 {
1349 if (!xtensa_expand_scc (operands, SFmode))
1350 FAIL;
1351 DONE;
1352 })
1353
1367 1354
1368 1355
1369 ;; Conditional moves. 1356 ;; Conditional moves.
1370 1357
1371 (define_expand "movsicc" 1358 (define_expand "movsicc"