comparison gcc/postreload.c @ 55:77e2b8dfacca gcc-4.4.5

update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
1 /* Perform simple optimizations to clean up the result of reload. 1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc. 4 Free Software Foundation, Inc.
5 5
6 This file is part of GCC. 6 This file is part of GCC.
7 7
8 GCC is free software; you can redistribute it and/or modify it under 8 GCC is free software; you can redistribute it and/or modify it under
282 { 282 {
283 HOST_WIDE_INT this_val; 283 HOST_WIDE_INT this_val;
284 284
285 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other 285 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
286 constants, such as SYMBOL_REF, cannot be extended. */ 286 constants, such as SYMBOL_REF, cannot be extended. */
287 if (GET_CODE (this_rtx) != CONST_INT) 287 if (!CONST_INT_P (this_rtx))
288 continue; 288 continue;
289 289
290 this_val = INTVAL (this_rtx); 290 this_val = INTVAL (this_rtx);
291 switch (extend_op) 291 switch (extend_op)
292 { 292 {
405 for (i = 0; i < recog_data.n_operands; i++) 405 for (i = 0; i < recog_data.n_operands; i++)
406 { 406 {
407 cselib_val *v; 407 cselib_val *v;
408 struct elt_loc_list *l; 408 struct elt_loc_list *l;
409 rtx op; 409 rtx op;
410 enum machine_mode mode;
411 410
412 CLEAR_HARD_REG_SET (equiv_regs[i]); 411 CLEAR_HARD_REG_SET (equiv_regs[i]);
413 412
414 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem 413 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
415 right, so avoid the problem here. Likewise if we have a constant 414 right, so avoid the problem here. Likewise if we have a constant
418 || (CONSTANT_P (recog_data.operand[i]) 417 || (CONSTANT_P (recog_data.operand[i])
419 && recog_data.operand_mode[i] == VOIDmode)) 418 && recog_data.operand_mode[i] == VOIDmode))
420 continue; 419 continue;
421 420
422 op = recog_data.operand[i]; 421 op = recog_data.operand[i];
423 mode = GET_MODE (op);
424 #ifdef LOAD_EXTEND_OP 422 #ifdef LOAD_EXTEND_OP
425 if (MEM_P (op) 423 if (MEM_P (op)
426 && GET_MODE_BITSIZE (mode) < BITS_PER_WORD 424 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
427 && LOAD_EXTEND_OP (mode) != UNKNOWN) 425 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
428 { 426 {
429 rtx set = single_set (insn); 427 rtx set = single_set (insn);
430 428
431 /* We might have multiple sets, some of which do implicit 429 /* We might have multiple sets, some of which do implicit
432 extension. Punt on this for now. */ 430 extension. Punt on this for now. */
455 && recog_data.n_operands == 2 453 && recog_data.n_operands == 2
456 && SET_SRC (set) == op 454 && SET_SRC (set) == op
457 && SET_DEST (set) == recog_data.operand[1-i]) 455 && SET_DEST (set) == recog_data.operand[1-i])
458 { 456 {
459 validate_change (insn, recog_data.operand_loc[i], 457 validate_change (insn, recog_data.operand_loc[i],
460 gen_rtx_fmt_e (LOAD_EXTEND_OP (mode), 458 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
461 word_mode, op), 459 word_mode, op),
462 1); 460 1);
463 validate_change (insn, recog_data.operand_loc[1-i], 461 validate_change (insn, recog_data.operand_loc[1-i],
464 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), 462 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
465 1); 463 1);
517 || constraints[i][0] == '+') 515 || constraints[i][0] == '+')
518 continue; 516 continue;
519 517
520 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 518 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
521 { 519 {
522 int rclass = (int) NO_REGS; 520 enum reg_class rclass = NO_REGS;
523 521
524 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) 522 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
525 continue; 523 continue;
526 524
527 SET_REGNO (testreg, regno); 525 SET_REGNO (testreg, regno);
568 replacement register if we don't have one for this 566 replacement register if we don't have one for this
569 alternative yet and the operand being replaced is not 567 alternative yet and the operand being replaced is not
570 a cheap CONST_INT. */ 568 a cheap CONST_INT. */
571 if (op_alt_regno[i][j] == -1 569 if (op_alt_regno[i][j] == -1
572 && reg_fits_class_p (testreg, rclass, 0, mode) 570 && reg_fits_class_p (testreg, rclass, 0, mode)
573 && (GET_CODE (recog_data.operand[i]) != CONST_INT 571 && (!CONST_INT_P (recog_data.operand[i])
574 || (rtx_cost (recog_data.operand[i], SET, 572 || (rtx_cost (recog_data.operand[i], SET,
575 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))) 573 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
576 > rtx_cost (testreg, SET, 574 > rtx_cost (testreg, SET,
577 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))))) 575 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))))))
578 { 576 {
579 alternative_nregs[j]++; 577 alternative_nregs[j]++;
580 op_alt_regno[i][j] = regno; 578 op_alt_regno[i][j] = regno;
581 } 579 }
582 j++; 580 j++;
583 rclass = (int) NO_REGS; 581 rclass = NO_REGS;
584 break; 582 break;
585 } 583 }
586 p += CONSTRAINT_LEN (c, p); 584 p += CONSTRAINT_LEN (c, p);
587 585
588 if (c == '\0') 586 if (c == '\0')
792 (set (REGZ) (CONST_INT)) 790 (set (REGZ) (CONST_INT))
793 ... 791 ...
794 ... (MEM (PLUS (REGZ) (REGY)))... . 792 ... (MEM (PLUS (REGZ) (REGY)))... .
795 793
796 First, check that we have (set (REGX) (PLUS (REGX) (REGY))) 794 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
797 and that we know all uses of REGX before it dies. 795 and that we know all uses of REGX before it dies.
798 Also, explicitly check that REGX != REGY; our life information 796 Also, explicitly check that REGX != REGY; our life information
799 does not yet show whether REGY changes in this insn. */ 797 does not yet show whether REGY changes in this insn. */
800 set = single_set (insn); 798 set = single_set (insn);
801 if (set != NULL_RTX 799 if (set != NULL_RTX
802 && REG_P (SET_DEST (set)) 800 && REG_P (SET_DEST (set))
813 rtx plus = SET_SRC (set); 811 rtx plus = SET_SRC (set);
814 rtx base = XEXP (plus, 1); 812 rtx base = XEXP (plus, 1);
815 rtx prev = prev_nonnote_insn (insn); 813 rtx prev = prev_nonnote_insn (insn);
816 rtx prev_set = prev ? single_set (prev) : NULL_RTX; 814 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
817 unsigned int regno = REGNO (reg); 815 unsigned int regno = REGNO (reg);
818 rtx const_reg = NULL_RTX; 816 rtx index_reg = NULL_RTX;
819 rtx reg_sum = NULL_RTX; 817 rtx reg_sum = NULL_RTX;
820 818
821 /* Now, we need an index register. 819 /* Now we need to set INDEX_REG to an index register (denoted as
822 We'll set index_reg to this index register, const_reg to the 820 REGZ in the illustration above) and REG_SUM to the expression
823 register that is to be loaded with the constant 821 register+register that we want to use to substitute uses of REG
824 (denoted as REGZ in the substitution illustration above), 822 (typically in MEMs) with. First check REG and BASE for being
825 and reg_sum to the register-register that we want to use to 823 index registers; we can use them even if they are not dead. */
826 substitute uses of REG (typically in MEMs) with.
827 First check REG and BASE for being index registers;
828 we can use them even if they are not dead. */
829 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) 824 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
830 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], 825 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
831 REGNO (base))) 826 REGNO (base)))
832 { 827 {
833 const_reg = reg; 828 index_reg = reg;
834 reg_sum = plus; 829 reg_sum = plus;
835 } 830 }
836 else 831 else
837 { 832 {
838 /* Otherwise, look for a free index register. Since we have 833 /* Otherwise, look for a free index register. Since we have
845 i) 840 i)
846 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES 841 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
847 && reg_state[i].store_ruid <= reg_state[regno].use_ruid 842 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
848 && hard_regno_nregs[i][GET_MODE (reg)] == 1) 843 && hard_regno_nregs[i][GET_MODE (reg)] == 1)
849 { 844 {
850 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); 845 index_reg = gen_rtx_REG (GET_MODE (reg), i);
851
852 const_reg = index_reg;
853 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); 846 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
854 break; 847 break;
855 } 848 }
856 } 849 }
857 } 850 }
858 851
859 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that 852 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
860 (REGY), i.e. BASE, is not clobbered before the last use we'll 853 (REGY), i.e. BASE, is not clobbered before the last use we'll
861 create. */ 854 create. */
862 if (prev_set != 0 855 if (reg_sum
863 && GET_CODE (SET_SRC (prev_set)) == CONST_INT 856 && prev_set
857 && CONST_INT_P (SET_SRC (prev_set))
864 && rtx_equal_p (SET_DEST (prev_set), reg) 858 && rtx_equal_p (SET_DEST (prev_set), reg)
865 && reg_state[regno].use_index >= 0 859 && reg_state[regno].use_index >= 0
866 && (reg_state[REGNO (base)].store_ruid 860 && (reg_state[REGNO (base)].store_ruid
867 <= reg_state[regno].use_ruid) 861 <= reg_state[regno].use_ruid))
868 && reg_sum != 0)
869 { 862 {
870 int i; 863 int i;
871 864
872 /* Change destination register and, if necessary, the 865 /* Change destination register and, if necessary, the constant
873 constant value in PREV, the constant loading instruction. */ 866 value in PREV, the constant loading instruction. */
874 validate_change (prev, &SET_DEST (prev_set), const_reg, 1); 867 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
875 if (reg_state[regno].offset != const0_rtx) 868 if (reg_state[regno].offset != const0_rtx)
876 validate_change (prev, 869 validate_change (prev,
877 &SET_SRC (prev_set), 870 &SET_SRC (prev_set),
878 GEN_INT (INTVAL (SET_SRC (prev_set)) 871 GEN_INT (INTVAL (SET_SRC (prev_set))
879 + INTVAL (reg_state[regno].offset)), 872 + INTVAL (reg_state[regno].offset)),
889 replacement. */ 882 replacement. */
890 reg_sum, 1); 883 reg_sum, 1);
891 884
892 if (apply_change_group ()) 885 if (apply_change_group ())
893 { 886 {
887 /* For every new use of REG_SUM, we have to record the use
888 of BASE therein, i.e. operand 1. */
889 for (i = reg_state[regno].use_index;
890 i < RELOAD_COMBINE_MAX_USES; i++)
891 reload_combine_note_use
892 (&XEXP (*reg_state[regno].reg_use[i].usep, 1),
893 reg_state[regno].reg_use[i].insn);
894
895 if (reg_state[REGNO (base)].use_ruid
896 > reg_state[regno].use_ruid)
897 reg_state[REGNO (base)].use_ruid
898 = reg_state[regno].use_ruid;
899
894 /* Delete the reg-reg addition. */ 900 /* Delete the reg-reg addition. */
895 delete_insn (insn); 901 delete_insn (insn);
896 902
897 if (reg_state[regno].offset != const0_rtx) 903 if (reg_state[regno].offset != const0_rtx)
898 /* Previous REG_EQUIV / REG_EQUAL notes for PREV 904 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
899 are now invalid. */ 905 are now invalid. */
900 remove_reg_equal_equiv_notes (prev); 906 remove_reg_equal_equiv_notes (prev);
901 907
902 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; 908 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
903 reg_state[REGNO (const_reg)].store_ruid 909 reg_state[REGNO (index_reg)].store_ruid
904 = reload_combine_ruid; 910 = reload_combine_ruid;
905 continue; 911 continue;
906 } 912 }
907 } 913 }
908 } 914 }
1072 break; 1078 break;
1073 1079
1074 case PLUS: 1080 case PLUS:
1075 /* We are interested in (plus (reg) (const_int)) . */ 1081 /* We are interested in (plus (reg) (const_int)) . */
1076 if (!REG_P (XEXP (x, 0)) 1082 if (!REG_P (XEXP (x, 0))
1077 || GET_CODE (XEXP (x, 1)) != CONST_INT) 1083 || !CONST_INT_P (XEXP (x, 1)))
1078 break; 1084 break;
1079 offset = XEXP (x, 1); 1085 offset = XEXP (x, 1);
1080 x = XEXP (x, 0); 1086 x = XEXP (x, 0);
1081 /* Fall through. */ 1087 /* Fall through. */
1082 case REG: 1088 case REG:
1237 (set (REGX) (CONST_INT A)) 1243 (set (REGX) (CONST_INT A))
1238 ... 1244 ...
1239 (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) 1245 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1240 */ 1246 */
1241 1247
1242 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) 1248 if (CONST_INT_P (src) && reg_base_reg[regno] < 0)
1243 { 1249 {
1244 rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], 1250 rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno],
1245 GET_MODE (reg)); 1251 GET_MODE (reg));
1246 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 1252 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1247 1253
1323 set = single_set (next); 1329 set = single_set (next);
1324 if (set 1330 if (set
1325 && SET_DEST (set) == reg 1331 && SET_DEST (set) == reg
1326 && GET_CODE (SET_SRC (set)) == PLUS 1332 && GET_CODE (SET_SRC (set)) == PLUS
1327 && XEXP (SET_SRC (set), 0) == reg 1333 && XEXP (SET_SRC (set), 0) == reg
1328 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) 1334 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1329 { 1335 {
1330 rtx src3 = XEXP (SET_SRC (set), 1); 1336 rtx src3 = XEXP (SET_SRC (set), 1);
1331 HOST_WIDE_INT added_offset = INTVAL (src3); 1337 HOST_WIDE_INT added_offset = INTVAL (src3);
1332 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; 1338 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1333 HOST_WIDE_INT regno_offset = reg_offset[regno]; 1339 HOST_WIDE_INT regno_offset = reg_offset[regno];
1396 move2add_note_store, are intended to reduce the 1402 move2add_note_store, are intended to reduce the
1397 number of calls to gen_rtx_SET to avoid memory 1403 number of calls to gen_rtx_SET to avoid memory
1398 allocation if possible. */ 1404 allocation if possible. */
1399 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) 1405 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
1400 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1 1406 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
1401 && GET_CODE (XEXP (cnd, 1)) == CONST_INT) 1407 && CONST_INT_P (XEXP (cnd, 1)))
1402 { 1408 {
1403 rtx implicit_set = 1409 rtx implicit_set =
1404 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); 1410 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
1405 move2add_note_store (SET_DEST (implicit_set), implicit_set, 0); 1411 move2add_note_store (SET_DEST (implicit_set), implicit_set, 0);
1406 } 1412 }
1477 case PLUS: 1483 case PLUS:
1478 if (REG_P (XEXP (src, 0))) 1484 if (REG_P (XEXP (src, 0)))
1479 { 1485 {
1480 base_reg = XEXP (src, 0); 1486 base_reg = XEXP (src, 0);
1481 1487
1482 if (GET_CODE (XEXP (src, 1)) == CONST_INT) 1488 if (CONST_INT_P (XEXP (src, 1)))
1483 offset = INTVAL (XEXP (src, 1)); 1489 offset = INTVAL (XEXP (src, 1));
1484 else if (REG_P (XEXP (src, 1)) 1490 else if (REG_P (XEXP (src, 1))
1485 && (reg_set_luid[REGNO (XEXP (src, 1))] 1491 && (reg_set_luid[REGNO (XEXP (src, 1))]
1486 > move2add_last_label_luid) 1492 > move2add_last_label_luid)
1487 && (MODES_OK_FOR_MOVE2ADD 1493 && (MODES_OK_FOR_MOVE2ADD
1608 0, /* todo_flags_start */ 1614 0, /* todo_flags_start */
1609 TODO_df_finish | TODO_verify_rtl_sharing | 1615 TODO_df_finish | TODO_verify_rtl_sharing |
1610 TODO_dump_func /* todo_flags_finish */ 1616 TODO_dump_func /* todo_flags_finish */
1611 } 1617 }
1612 }; 1618 };
1613