Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/aarch64/predicates.md @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
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date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
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111:04ced10e8804 | 131:84e7813d76e9 |
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1 ;; Machine description for AArch64 architecture. | 1 ;; Machine description for AArch64 architecture. |
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc. |
3 ;; Contributed by ARM Ltd. | 3 ;; Contributed by ARM Ltd. |
4 ;; | 4 ;; |
5 ;; This file is part of GCC. | 5 ;; This file is part of GCC. |
6 ;; | 6 ;; |
7 ;; GCC is free software; you can redistribute it and/or modify it | 7 ;; GCC is free software; you can redistribute it and/or modify it |
60 (define_predicate "aarch64_reg_or_fp_zero" | 60 (define_predicate "aarch64_reg_or_fp_zero" |
61 (ior (match_operand 0 "register_operand") | 61 (ior (match_operand 0 "register_operand") |
62 (and (match_code "const_double") | 62 (and (match_code "const_double") |
63 (match_test "aarch64_float_const_zero_rtx_p (op)")))) | 63 (match_test "aarch64_float_const_zero_rtx_p (op)")))) |
64 | 64 |
65 (define_predicate "aarch64_reg_zero_or_fp_zero" | |
66 (ior (match_operand 0 "aarch64_reg_or_fp_zero") | |
67 (match_operand 0 "aarch64_reg_or_zero"))) | |
68 | |
65 (define_predicate "aarch64_reg_zero_or_m1_or_1" | 69 (define_predicate "aarch64_reg_zero_or_m1_or_1" |
66 (and (match_code "reg,subreg,const_int") | 70 (and (match_code "reg,subreg,const_int") |
67 (ior (match_operand 0 "register_operand") | 71 (ior (match_operand 0 "register_operand") |
68 (ior (match_test "op == const0_rtx") | 72 (ior (match_test "op == const0_rtx") |
69 (ior (match_test "op == constm1_rtx") | 73 (ior (match_test "op == constm1_rtx") |
70 (match_test "op == const1_rtx")))))) | 74 (match_test "op == const1_rtx")))))) |
71 | 75 |
72 (define_predicate "aarch64_reg_or_orr_imm" | 76 (define_predicate "aarch64_reg_or_orr_imm" |
73 (ior (match_operand 0 "register_operand") | 77 (ior (match_operand 0 "register_operand") |
74 (and (match_code "const_vector") | 78 (and (match_code "const_vector") |
75 (match_test "aarch64_simd_valid_immediate (op, mode, false, | 79 (match_test "aarch64_simd_valid_immediate (op, NULL, |
76 NULL, AARCH64_CHECK_ORR)")))) | 80 AARCH64_CHECK_ORR)")))) |
77 | 81 |
78 (define_predicate "aarch64_reg_or_bic_imm" | 82 (define_predicate "aarch64_reg_or_bic_imm" |
79 (ior (match_operand 0 "register_operand") | 83 (ior (match_operand 0 "register_operand") |
80 (and (match_code "const_vector") | 84 (and (match_code "const_vector") |
81 (match_test "aarch64_simd_valid_immediate (op, mode, false, | 85 (match_test "aarch64_simd_valid_immediate (op, NULL, |
82 NULL, AARCH64_CHECK_BIC)")))) | 86 AARCH64_CHECK_BIC)")))) |
83 | 87 |
84 (define_predicate "aarch64_fp_compare_operand" | 88 (define_predicate "aarch64_fp_compare_operand" |
85 (ior (match_operand 0 "register_operand") | 89 (ior (match_operand 0 "register_operand") |
86 (and (match_code "const_double") | 90 (and (match_code "const_double") |
87 (match_test "aarch64_float_const_zero_rtx_p (op)")))) | 91 (match_test "aarch64_float_const_zero_rtx_p (op)")))) |
91 (match_test "aarch64_fpconst_pow_of_2 (op) > 0"))) | 95 (match_test "aarch64_fpconst_pow_of_2 (op) > 0"))) |
92 | 96 |
93 (define_predicate "aarch64_fp_vec_pow2" | 97 (define_predicate "aarch64_fp_vec_pow2" |
94 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0")) | 98 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0")) |
95 | 99 |
100 (define_predicate "aarch64_sve_cnt_immediate" | |
101 (and (match_code "const_poly_int") | |
102 (match_test "aarch64_sve_cnt_immediate_p (op)"))) | |
103 | |
96 (define_predicate "aarch64_sub_immediate" | 104 (define_predicate "aarch64_sub_immediate" |
97 (and (match_code "const_int") | 105 (and (match_code "const_int") |
98 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))) | 106 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))) |
99 | 107 |
100 (define_predicate "aarch64_plus_immediate" | 108 (define_predicate "aarch64_plus_immediate" |
112 | 120 |
113 (define_predicate "aarch64_pluslong_strict_immedate" | 121 (define_predicate "aarch64_pluslong_strict_immedate" |
114 (and (match_operand 0 "aarch64_pluslong_immediate") | 122 (and (match_operand 0 "aarch64_pluslong_immediate") |
115 (not (match_operand 0 "aarch64_plus_immediate")))) | 123 (not (match_operand 0 "aarch64_plus_immediate")))) |
116 | 124 |
125 (define_predicate "aarch64_sve_addvl_addpl_immediate" | |
126 (and (match_code "const_poly_int") | |
127 (match_test "aarch64_sve_addvl_addpl_immediate_p (op)"))) | |
128 | |
129 (define_predicate "aarch64_split_add_offset_immediate" | |
130 (and (match_code "const_poly_int") | |
131 (match_test "aarch64_add_offset_temporaries (op) == 1"))) | |
132 | |
117 (define_predicate "aarch64_pluslong_operand" | 133 (define_predicate "aarch64_pluslong_operand" |
118 (ior (match_operand 0 "register_operand") | 134 (ior (match_operand 0 "register_operand") |
119 (match_operand 0 "aarch64_pluslong_immediate"))) | 135 (match_operand 0 "aarch64_pluslong_immediate") |
136 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))) | |
137 | |
138 (define_predicate "aarch64_pluslong_or_poly_operand" | |
139 (ior (match_operand 0 "aarch64_pluslong_operand") | |
140 (match_operand 0 "aarch64_split_add_offset_immediate"))) | |
120 | 141 |
121 (define_predicate "aarch64_logical_immediate" | 142 (define_predicate "aarch64_logical_immediate" |
122 (and (match_code "const_int") | 143 (and (match_code "const_int") |
123 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)"))) | 144 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)"))) |
124 | 145 |
158 ;; range 0..4. | 179 ;; range 0..4. |
159 (define_predicate "aarch64_imm3" | 180 (define_predicate "aarch64_imm3" |
160 (and (match_code "const_int") | 181 (and (match_code "const_int") |
161 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4"))) | 182 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4"))) |
162 | 183 |
184 ;; The imm2 field is a 2-bit field that only accepts immediates in the | |
185 ;; range 0..3. | |
186 (define_predicate "aarch64_imm2" | |
187 (and (match_code "const_int") | |
188 (match_test "UINTVAL (op) <= 3"))) | |
189 | |
190 ;; The imm3 field is a 3-bit field that only accepts immediates in the | |
191 ;; range 0..7. | |
192 (define_predicate "aarch64_lane_imm3" | |
193 (and (match_code "const_int") | |
194 (match_test "UINTVAL (op) <= 7"))) | |
195 | |
163 ;; An immediate that fits into 24 bits. | 196 ;; An immediate that fits into 24 bits. |
164 (define_predicate "aarch64_imm24" | 197 (define_predicate "aarch64_imm24" |
165 (and (match_code "const_int") | 198 (and (match_code "const_int") |
166 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)"))) | 199 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)"))) |
167 | 200 |
184 (and (match_code "const_int") | 217 (and (match_code "const_int") |
185 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))"))) | 218 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))"))) |
186 | 219 |
187 (define_predicate "aarch64_mem_pair_operand" | 220 (define_predicate "aarch64_mem_pair_operand" |
188 (and (match_code "mem") | 221 (and (match_code "mem") |
189 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL, | 222 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false, |
190 0)"))) | 223 ADDR_QUERY_LDP_STP)"))) |
224 | |
225 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP | |
226 ;; as a 128-bit vec_concat. | |
227 (define_predicate "aarch64_mem_pair_lanes_operand" | |
228 (and (match_code "mem") | |
229 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), | |
230 false, | |
231 ADDR_QUERY_LDP_STP_N)"))) | |
191 | 232 |
192 (define_predicate "aarch64_prefetch_operand" | 233 (define_predicate "aarch64_prefetch_operand" |
193 (match_test "aarch64_address_valid_for_prefetch_p (op, false)")) | 234 (match_test "aarch64_address_valid_for_prefetch_p (op, false)")) |
194 | 235 |
195 (define_predicate "aarch64_valid_symref" | 236 (define_predicate "aarch64_valid_symref" |
242 gcc_unreachable (); | 283 gcc_unreachable (); |
243 } | 284 } |
244 }) | 285 }) |
245 | 286 |
246 (define_predicate "aarch64_mov_operand" | 287 (define_predicate "aarch64_mov_operand" |
247 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high") | 288 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high, |
289 const_poly_int,const_vector") | |
248 (ior (match_operand 0 "register_operand") | 290 (ior (match_operand 0 "register_operand") |
249 (ior (match_operand 0 "memory_operand") | 291 (ior (match_operand 0 "memory_operand") |
250 (match_test "aarch64_mov_operand_p (op, mode)"))))) | 292 (match_test "aarch64_mov_operand_p (op, mode)"))))) |
251 | 293 |
294 (define_predicate "aarch64_nonmemory_operand" | |
295 (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high, | |
296 const_poly_int,const_vector") | |
297 (ior (match_operand 0 "register_operand") | |
298 (match_test "aarch64_mov_operand_p (op, mode)")))) | |
299 | |
252 (define_predicate "aarch64_movti_operand" | 300 (define_predicate "aarch64_movti_operand" |
253 (and (match_code "reg,subreg,mem,const_int") | 301 (ior (match_operand 0 "register_operand") |
254 (ior (match_operand 0 "register_operand") | 302 (match_operand 0 "memory_operand") |
255 (ior (match_operand 0 "memory_operand") | 303 (and (match_operand 0 "const_scalar_int_operand") |
256 (match_operand 0 "const_int_operand"))))) | 304 (match_test "aarch64_mov128_immediate (op)")))) |
257 | 305 |
258 (define_predicate "aarch64_reg_or_imm" | 306 (define_predicate "aarch64_reg_or_imm" |
259 (and (match_code "reg,subreg,const_int") | 307 (ior (match_operand 0 "register_operand") |
260 (ior (match_operand 0 "register_operand") | 308 (match_operand 0 "const_scalar_int_operand"))) |
261 (match_operand 0 "const_int_operand")))) | |
262 | 309 |
263 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ. | 310 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ. |
264 (define_special_predicate "aarch64_comparison_operator" | 311 (define_special_predicate "aarch64_comparison_operator" |
265 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered, | 312 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered, |
266 ordered,unlt,unle,unge,ungt")) | 313 ordered,unlt,unle,unge,ungt")) |
282 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) | 329 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) |
283 return false; | 330 return false; |
284 return aarch64_get_condition_code (op) >= 0; | 331 return aarch64_get_condition_code (op) >= 0; |
285 }) | 332 }) |
286 | 333 |
334 (define_special_predicate "aarch64_equality_operator" | |
335 (match_code "eq,ne")) | |
336 | |
287 (define_special_predicate "aarch64_carry_operation" | 337 (define_special_predicate "aarch64_carry_operation" |
288 (match_code "ne,geu") | 338 (match_code "ne,geu") |
289 { | 339 { |
290 if (XEXP (op, 1) != const0_rtx) | 340 if (XEXP (op, 1) != const0_rtx) |
291 return false; | 341 return false; |
307 ;; True if the operand is memory reference suitable for a load/store exclusive. | 357 ;; True if the operand is memory reference suitable for a load/store exclusive. |
308 (define_predicate "aarch64_sync_memory_operand" | 358 (define_predicate "aarch64_sync_memory_operand" |
309 (and (match_operand 0 "memory_operand") | 359 (and (match_operand 0 "memory_operand") |
310 (match_code "reg" "0"))) | 360 (match_code "reg" "0"))) |
311 | 361 |
362 (define_predicate "aarch64_9bit_offset_memory_operand" | |
363 (and (match_operand 0 "memory_operand") | |
364 (ior (match_code "reg" "0") | |
365 (and (match_code "plus" "0") | |
366 (match_code "reg" "00") | |
367 (match_code "const_int" "01")))) | |
368 { | |
369 rtx mem_op = XEXP (op, 0); | |
370 | |
371 if (REG_P (mem_op)) | |
372 return GET_MODE (mem_op) == DImode; | |
373 | |
374 rtx plus_op0 = XEXP (mem_op, 0); | |
375 rtx plus_op1 = XEXP (mem_op, 1); | |
376 | |
377 if (GET_MODE (plus_op0) != DImode) | |
378 return false; | |
379 | |
380 poly_int64 offset; | |
381 if (!poly_int_rtx_p (plus_op1, &offset)) | |
382 gcc_unreachable (); | |
383 | |
384 return aarch64_offset_9bit_signed_unscaled_p (mode, offset); | |
385 }) | |
386 | |
387 (define_predicate "aarch64_rcpc_memory_operand" | |
388 (if_then_else (match_test "AARCH64_ISA_RCPC8_4") | |
389 (match_operand 0 "aarch64_9bit_offset_memory_operand") | |
390 (match_operand 0 "aarch64_sync_memory_operand"))) | |
391 | |
312 ;; Predicates for parallel expanders based on mode. | 392 ;; Predicates for parallel expanders based on mode. |
313 (define_special_predicate "vect_par_cnst_hi_half" | 393 (define_special_predicate "vect_par_cnst_hi_half" |
314 (match_code "parallel") | 394 (match_code "parallel") |
315 { | 395 { |
316 return aarch64_simd_check_vect_par_cnst_half (op, mode, true); | 396 return aarch64_simd_check_vect_par_cnst_half (op, mode, true); |
321 { | 401 { |
322 return aarch64_simd_check_vect_par_cnst_half (op, mode, false); | 402 return aarch64_simd_check_vect_par_cnst_half (op, mode, false); |
323 }) | 403 }) |
324 | 404 |
325 (define_special_predicate "aarch64_simd_lshift_imm" | 405 (define_special_predicate "aarch64_simd_lshift_imm" |
326 (match_code "const_vector") | 406 (match_code "const,const_vector") |
327 { | 407 { |
328 return aarch64_simd_shift_imm_p (op, mode, true); | 408 return aarch64_simd_shift_imm_p (op, mode, true); |
329 }) | 409 }) |
330 | 410 |
331 (define_special_predicate "aarch64_simd_rshift_imm" | 411 (define_special_predicate "aarch64_simd_rshift_imm" |
332 (match_code "const_vector") | 412 (match_code "const,const_vector") |
333 { | 413 { |
334 return aarch64_simd_shift_imm_p (op, mode, false); | 414 return aarch64_simd_shift_imm_p (op, mode, false); |
335 }) | 415 }) |
336 | 416 |
417 (define_predicate "aarch64_simd_imm_zero" | |
418 (and (match_code "const,const_vector") | |
419 (match_test "op == CONST0_RTX (GET_MODE (op))"))) | |
420 | |
421 (define_predicate "aarch64_simd_or_scalar_imm_zero" | |
422 (and (match_code "const_int,const_double,const,const_vector") | |
423 (match_test "op == CONST0_RTX (GET_MODE (op))"))) | |
424 | |
425 (define_predicate "aarch64_simd_imm_minus_one" | |
426 (and (match_code "const,const_vector") | |
427 (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) | |
428 | |
337 (define_predicate "aarch64_simd_reg_or_zero" | 429 (define_predicate "aarch64_simd_reg_or_zero" |
338 (and (match_code "reg,subreg,const_int,const_double,const_vector") | 430 (and (match_code "reg,subreg,const_int,const_double,const,const_vector") |
339 (ior (match_operand 0 "register_operand") | 431 (ior (match_operand 0 "register_operand") |
340 (ior (match_test "op == const0_rtx") | 432 (match_test "op == const0_rtx") |
341 (match_test "aarch64_simd_imm_zero_p (op, mode)"))))) | 433 (match_operand 0 "aarch64_simd_or_scalar_imm_zero")))) |
342 | 434 |
343 (define_predicate "aarch64_simd_struct_operand" | 435 (define_predicate "aarch64_simd_struct_operand" |
344 (and (match_code "mem") | 436 (and (match_code "mem") |
345 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)"))) | 437 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)"))) |
346 | 438 |
356 (and (match_operand 0 "nonimmediate_operand") | 448 (and (match_operand 0 "nonimmediate_operand") |
357 (match_test "!MEM_P (op) | 449 (match_test "!MEM_P (op) |
358 || GET_CODE (XEXP (op, 0)) == POST_INC | 450 || GET_CODE (XEXP (op, 0)) == POST_INC |
359 || GET_CODE (XEXP (op, 0)) == REG"))) | 451 || GET_CODE (XEXP (op, 0)) == REG"))) |
360 | 452 |
361 (define_special_predicate "aarch64_simd_imm_zero" | |
362 (match_code "const_vector") | |
363 { | |
364 return aarch64_simd_imm_zero_p (op, mode); | |
365 }) | |
366 | |
367 (define_special_predicate "aarch64_simd_imm_minus_one" | |
368 (match_code "const_vector") | |
369 { | |
370 return aarch64_const_vec_all_same_int_p (op, -1); | |
371 }) | |
372 | |
373 ;; Predicates used by the various SIMD shift operations. These | 453 ;; Predicates used by the various SIMD shift operations. These |
374 ;; fall in to 3 categories. | 454 ;; fall in to 3 categories. |
375 ;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) | 455 ;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) |
376 ;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) | 456 ;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) |
377 ;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) | 457 ;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) |
424 (match_test "IN_RANGE (INTVAL (op), 0, 64)"))) | 504 (match_test "IN_RANGE (INTVAL (op), 0, 64)"))) |
425 | 505 |
426 (define_predicate "aarch64_constant_pool_symref" | 506 (define_predicate "aarch64_constant_pool_symref" |
427 (and (match_code "symbol_ref") | 507 (and (match_code "symbol_ref") |
428 (match_test "CONSTANT_POOL_ADDRESS_P (op)"))) | 508 (match_test "CONSTANT_POOL_ADDRESS_P (op)"))) |
509 | |
510 (define_predicate "aarch64_constant_vector_operand" | |
511 (match_code "const,const_vector")) | |
512 | |
513 (define_predicate "aarch64_sve_ld1r_operand" | |
514 (and (match_operand 0 "memory_operand") | |
515 (match_test "aarch64_sve_ld1r_operand_p (op)"))) | |
516 | |
517 ;; Like memory_operand, but restricted to addresses that are valid for | |
518 ;; SVE LDR and STR instructions. | |
519 (define_predicate "aarch64_sve_ldr_operand" | |
520 (and (match_code "mem") | |
521 (match_test "aarch64_sve_ldr_operand_p (op)"))) | |
522 | |
523 (define_predicate "aarch64_sve_nonimmediate_operand" | |
524 (ior (match_operand 0 "register_operand") | |
525 (match_operand 0 "aarch64_sve_ldr_operand"))) | |
526 | |
527 (define_predicate "aarch64_sve_general_operand" | |
528 (and (match_code "reg,subreg,mem,const,const_vector") | |
529 (ior (match_operand 0 "register_operand") | |
530 (match_operand 0 "aarch64_sve_ldr_operand") | |
531 (match_test "aarch64_mov_operand_p (op, mode)")))) | |
532 | |
533 (define_predicate "aarch64_sve_struct_memory_operand" | |
534 (and (match_code "mem") | |
535 (match_test "aarch64_sve_struct_memory_operand_p (op)"))) | |
536 | |
537 (define_predicate "aarch64_sve_struct_nonimmediate_operand" | |
538 (ior (match_operand 0 "register_operand") | |
539 (match_operand 0 "aarch64_sve_struct_memory_operand"))) | |
540 | |
541 ;; Doesn't include immediates, since those are handled by the move | |
542 ;; patterns instead. | |
543 (define_predicate "aarch64_sve_dup_operand" | |
544 (ior (match_operand 0 "register_operand") | |
545 (match_operand 0 "aarch64_sve_ld1r_operand"))) | |
546 | |
547 (define_predicate "aarch64_sve_arith_immediate" | |
548 (and (match_code "const,const_vector") | |
549 (match_test "aarch64_sve_arith_immediate_p (op, false)"))) | |
550 | |
551 (define_predicate "aarch64_sve_sub_arith_immediate" | |
552 (and (match_code "const,const_vector") | |
553 (match_test "aarch64_sve_arith_immediate_p (op, true)"))) | |
554 | |
555 (define_predicate "aarch64_sve_inc_dec_immediate" | |
556 (and (match_code "const,const_vector") | |
557 (match_test "aarch64_sve_inc_dec_immediate_p (op)"))) | |
558 | |
559 (define_predicate "aarch64_sve_logical_immediate" | |
560 (and (match_code "const,const_vector") | |
561 (match_test "aarch64_sve_bitmask_immediate_p (op)"))) | |
562 | |
563 (define_predicate "aarch64_sve_mul_immediate" | |
564 (and (match_code "const,const_vector") | |
565 (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)"))) | |
566 | |
567 (define_predicate "aarch64_sve_dup_immediate" | |
568 (and (match_code "const,const_vector") | |
569 (match_test "aarch64_sve_dup_immediate_p (op)"))) | |
570 | |
571 (define_predicate "aarch64_sve_cmp_vsc_immediate" | |
572 (and (match_code "const,const_vector") | |
573 (match_test "aarch64_sve_cmp_immediate_p (op, true)"))) | |
574 | |
575 (define_predicate "aarch64_sve_cmp_vsd_immediate" | |
576 (and (match_code "const,const_vector") | |
577 (match_test "aarch64_sve_cmp_immediate_p (op, false)"))) | |
578 | |
579 (define_predicate "aarch64_sve_index_immediate" | |
580 (and (match_code "const_int") | |
581 (match_test "aarch64_sve_index_immediate_p (op)"))) | |
582 | |
583 (define_predicate "aarch64_sve_float_arith_immediate" | |
584 (and (match_code "const,const_vector") | |
585 (match_test "aarch64_sve_float_arith_immediate_p (op, false)"))) | |
586 | |
587 (define_predicate "aarch64_sve_float_arith_with_sub_immediate" | |
588 (and (match_code "const,const_vector") | |
589 (match_test "aarch64_sve_float_arith_immediate_p (op, true)"))) | |
590 | |
591 (define_predicate "aarch64_sve_float_mul_immediate" | |
592 (and (match_code "const,const_vector") | |
593 (match_test "aarch64_sve_float_mul_immediate_p (op)"))) | |
594 | |
595 (define_predicate "aarch64_sve_arith_operand" | |
596 (ior (match_operand 0 "register_operand") | |
597 (match_operand 0 "aarch64_sve_arith_immediate"))) | |
598 | |
599 (define_predicate "aarch64_sve_add_operand" | |
600 (ior (match_operand 0 "aarch64_sve_arith_operand") | |
601 (match_operand 0 "aarch64_sve_sub_arith_immediate") | |
602 (match_operand 0 "aarch64_sve_inc_dec_immediate"))) | |
603 | |
604 (define_predicate "aarch64_sve_logical_operand" | |
605 (ior (match_operand 0 "register_operand") | |
606 (match_operand 0 "aarch64_sve_logical_immediate"))) | |
607 | |
608 (define_predicate "aarch64_sve_lshift_operand" | |
609 (ior (match_operand 0 "register_operand") | |
610 (match_operand 0 "aarch64_simd_lshift_imm"))) | |
611 | |
612 (define_predicate "aarch64_sve_rshift_operand" | |
613 (ior (match_operand 0 "register_operand") | |
614 (match_operand 0 "aarch64_simd_rshift_imm"))) | |
615 | |
616 (define_predicate "aarch64_sve_mul_operand" | |
617 (ior (match_operand 0 "register_operand") | |
618 (match_operand 0 "aarch64_sve_mul_immediate"))) | |
619 | |
620 (define_predicate "aarch64_sve_cmp_vsc_operand" | |
621 (ior (match_operand 0 "register_operand") | |
622 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))) | |
623 | |
624 (define_predicate "aarch64_sve_cmp_vsd_operand" | |
625 (ior (match_operand 0 "register_operand") | |
626 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))) | |
627 | |
628 (define_predicate "aarch64_sve_index_operand" | |
629 (ior (match_operand 0 "register_operand") | |
630 (match_operand 0 "aarch64_sve_index_immediate"))) | |
631 | |
632 (define_predicate "aarch64_sve_float_arith_operand" | |
633 (ior (match_operand 0 "register_operand") | |
634 (match_operand 0 "aarch64_sve_float_arith_immediate"))) | |
635 | |
636 (define_predicate "aarch64_sve_float_arith_with_sub_operand" | |
637 (ior (match_operand 0 "aarch64_sve_float_arith_operand") | |
638 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate"))) | |
639 | |
640 (define_predicate "aarch64_sve_float_mul_operand" | |
641 (ior (match_operand 0 "register_operand") | |
642 (match_operand 0 "aarch64_sve_float_mul_immediate"))) | |
643 | |
644 (define_predicate "aarch64_sve_vec_perm_operand" | |
645 (ior (match_operand 0 "register_operand") | |
646 (match_operand 0 "aarch64_constant_vector_operand"))) | |
647 | |
648 (define_predicate "aarch64_gather_scale_operand_w" | |
649 (and (match_code "const_int") | |
650 (match_test "INTVAL (op) == 1 || INTVAL (op) == 4"))) | |
651 | |
652 (define_predicate "aarch64_gather_scale_operand_d" | |
653 (and (match_code "const_int") | |
654 (match_test "INTVAL (op) == 1 || INTVAL (op) == 8"))) | |
655 | |
656 ;; A special predicate that doesn't match a particular mode. | |
657 (define_special_predicate "aarch64_any_register_operand" | |
658 (match_code "reg")) | |
659 | |
660 (define_predicate "aarch64_sve_any_binary_operator" | |
661 (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor")) |