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comparison gcc/config/aarch64/thunderx2t99.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
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111:04ced10e8804 131:84e7813d76e9
1 ;; Cavium ThunderX 2 CN99xx pipeline description 1 ;; Cavium ThunderX 2 CN99xx pipeline description
2 ;; Copyright (C) 2016-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2016-2018 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; Contributed by Cavium, Broadcom and Mentor Embedded. 4 ;; Contributed by Cavium, Broadcom and Mentor Embedded.
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
51 (define_cpu_unit "thunderx2t99_f1" "thunderx2t99_advsimd") 51 (define_cpu_unit "thunderx2t99_f1" "thunderx2t99_advsimd")
52 52
53 (define_reservation "thunderx2t99_i012" "thunderx2t99_i0|thunderx2t99_i1|thunderx2t99_i2") 53 (define_reservation "thunderx2t99_i012" "thunderx2t99_i0|thunderx2t99_i1|thunderx2t99_i2")
54 (define_reservation "thunderx2t99_ls01" "thunderx2t99_ls0|thunderx2t99_ls1") 54 (define_reservation "thunderx2t99_ls01" "thunderx2t99_ls0|thunderx2t99_ls1")
55 (define_reservation "thunderx2t99_f01" "thunderx2t99_f0|thunderx2t99_f1") 55 (define_reservation "thunderx2t99_f01" "thunderx2t99_f0|thunderx2t99_f1")
56
57 (define_reservation "thunderx2t99_ls_both" "thunderx2t99_ls0+thunderx2t99_ls1")
58 56
59 ; A load with delay in the ls0/ls1 pipes. 57 ; A load with delay in the ls0/ls1 pipes.
60 (define_reservation "thunderx2t99_l0delay" "thunderx2t99_ls0,\ 58 (define_reservation "thunderx2t99_l0delay" "thunderx2t99_ls0,\
61 thunderx2t99_ls0d1,thunderx2t99_ls0d2,\ 59 thunderx2t99_ls0d1,thunderx2t99_ls0d2,\
62 thunderx2t99_ls0d3") 60 thunderx2t99_ls0d3")
67 65
68 ;; Branch and call instructions. 66 ;; Branch and call instructions.
69 67
70 (define_insn_reservation "thunderx2t99_branch" 1 68 (define_insn_reservation "thunderx2t99_branch" 1
71 (and (eq_attr "tune" "thunderx2t99") 69 (and (eq_attr "tune" "thunderx2t99")
72 (eq_attr "type" "call,branch")) 70 (eq_attr "type" "call,branch,trap"))
73 "thunderx2t99_i2") 71 "thunderx2t99_i2")
72
73 ;; Misc instructions.
74
75 (define_insn_reservation "thunderx2t99_nothing" 0
76 (and (eq_attr "tune" "thunderx2t99")
77 (eq_attr "type" "no_insn,block"))
78 "nothing")
79
80 (define_insn_reservation "thunderx2t99_mrs" 0
81 (and (eq_attr "tune" "thunderx2t99")
82 (eq_attr "type" "mrs"))
83 "thunderx2t99_i2")
84
85 (define_insn_reservation "thunderx2t99_multiple" 1
86 (and (eq_attr "tune" "thunderx2t99")
87 (eq_attr "type" "multiple,untyped"))
88 "thunderx2t99_i0+thunderx2t99_i1+thunderx2t99_i2+thunderx2t99_ls0+\
89 thunderx2t99_ls1+thunderx2t99_sd+thunderx2t99_i1m1+thunderx2t99_i1m2+\
90 thunderx2t99_i1m3+thunderx2t99_f0+thunderx2t99_f1")
74 91
75 ;; Integer arithmetic/logic instructions. 92 ;; Integer arithmetic/logic instructions.
76 93
77 ; Plain register moves are handled by renaming, and don't create any uops. 94 ; Plain register moves are handled by renaming, and don't create any uops.
78 95
85 (and (eq_attr "tune" "thunderx2t99") 102 (and (eq_attr "tune" "thunderx2t99")
86 (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,\ 103 (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,\
87 adc_reg,adc_imm,adcs_reg,adcs_imm,\ 104 adc_reg,adc_imm,adcs_reg,adcs_imm,\
88 logic_reg,logic_imm,logics_reg,logics_imm,\ 105 logic_reg,logic_imm,logics_reg,logics_imm,\
89 csel,adr,mov_imm,shift_reg,shift_imm,bfm,\ 106 csel,adr,mov_imm,shift_reg,shift_imm,bfm,\
90 rbit,rev,extend,rotate_imm")) 107 bfx,rbit,rev,extend,rotate_imm"))
91 "thunderx2t99_i012") 108 "thunderx2t99_i012")
92 109
93 (define_insn_reservation "thunderx2t99_alu_shift" 2 110 (define_insn_reservation "thunderx2t99_alu_shift" 2
94 (and (eq_attr "tune" "thunderx2t99") 111 (and (eq_attr "tune" "thunderx2t99")
95 (eq_attr "type" "alu_shift_imm,alu_ext,alu_shift_reg,\ 112 (eq_attr "type" "alu_shift_imm,alu_ext,\
96 alus_shift_imm,alus_ext,alus_shift_reg,\ 113 alus_shift_imm,alus_ext,\
97 logic_shift_imm,logics_shift_reg")) 114 logic_shift_imm,logics_shift_imm"))
98 "thunderx2t99_i012,thunderx2t99_i012") 115 "thunderx2t99_i012,thunderx2t99_i012")
99 116
100 (define_insn_reservation "thunderx2t99_div" 13 117 (define_insn_reservation "thunderx2t99_div" 13
101 (and (eq_attr "tune" "thunderx2t99") 118 (and (eq_attr "tune" "thunderx2t99")
102 (eq_attr "type" "sdiv,udiv")) 119 (eq_attr "type" "sdiv,udiv"))
153 (eq_attr "type" "fadds,faddd")) 170 (eq_attr "type" "fadds,faddd"))
154 "thunderx2t99_f01") 171 "thunderx2t99_f01")
155 172
156 (define_insn_reservation "thunderx2t99_fp_cmp" 5 173 (define_insn_reservation "thunderx2t99_fp_cmp" 5
157 (and (eq_attr "tune" "thunderx2t99") 174 (and (eq_attr "tune" "thunderx2t99")
158 (eq_attr "type" "fcmps,fcmpd")) 175 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
159 "thunderx2t99_f01") 176 "thunderx2t99_f01")
160 177
161 (define_insn_reservation "thunderx2t99_fp_divsqrt_s" 16 178 (define_insn_reservation "thunderx2t99_fp_divsqrt_s" 16
162 (and (eq_attr "tune" "thunderx2t99") 179 (and (eq_attr "tune" "thunderx2t99")
163 (eq_attr "type" "fdivs,fsqrts")) 180 (eq_attr "type" "fdivs,fsqrts"))
205 (define_insn_reservation "thunderx2t99_fp_load_basic" 4 222 (define_insn_reservation "thunderx2t99_fp_load_basic" 4
206 (and (eq_attr "tune" "thunderx2t99") 223 (and (eq_attr "tune" "thunderx2t99")
207 (eq_attr "type" "f_loads,f_loadd")) 224 (eq_attr "type" "f_loads,f_loadd"))
208 "thunderx2t99_ls01") 225 "thunderx2t99_ls01")
209 226
210 (define_insn_reservation "thunderx2t99_fp_loadpair_basic" 4
211 (and (eq_attr "tune" "thunderx2t99")
212 (eq_attr "type" "neon_load1_2reg"))
213 "thunderx2t99_ls01*2")
214
215 (define_insn_reservation "thunderx2t99_fp_store_basic" 1 227 (define_insn_reservation "thunderx2t99_fp_store_basic" 1
216 (and (eq_attr "tune" "thunderx2t99") 228 (and (eq_attr "tune" "thunderx2t99")
217 (eq_attr "type" "f_stores,f_stored")) 229 (eq_attr "type" "f_stores,f_stored"))
218 "thunderx2t99_ls01,thunderx2t99_sd") 230 "thunderx2t99_ls01,thunderx2t99_sd")
219
220 (define_insn_reservation "thunderx2t99_fp_storepair_basic" 1
221 (and (eq_attr "tune" "thunderx2t99")
222 (eq_attr "type" "neon_store1_2reg"))
223 "thunderx2t99_ls01,(thunderx2t99_ls01+thunderx2t99_sd),thunderx2t99_sd")
224 231
225 ;; ASIMD integer instructions. 232 ;; ASIMD integer instructions.
226 233
227 (define_insn_reservation "thunderx2t99_asimd_int" 7 234 (define_insn_reservation "thunderx2t99_asimd_int" 7
228 (and (eq_attr "tune" "thunderx2t99") 235 (and (eq_attr "tune" "thunderx2t99")
229 (eq_attr "type" "neon_abd,neon_abd_q,\ 236 (eq_attr "type" "neon_abd,neon_abd_q,\
230 neon_arith_acc,neon_arith_acc_q,\ 237 neon_arith_acc,neon_arith_acc_q,\
231 neon_abs,neon_abs_q,\ 238 neon_abs,neon_abs_q,\
232 neon_add,neon_add_q,\ 239 neon_add,neon_add_q,\
240 neon_sub,neon_sub_q,\
233 neon_neg,neon_neg_q,\ 241 neon_neg,neon_neg_q,\
234 neon_add_long,neon_add_widen,\ 242 neon_add_long,neon_add_widen,\
235 neon_add_halve,neon_add_halve_q,\ 243 neon_add_halve,neon_add_halve_q,\
236 neon_sub_long,neon_sub_widen,\ 244 neon_sub_long,neon_sub_widen,\
237 neon_sub_halve,neon_sub_halve_q,\ 245 neon_sub_halve,neon_sub_halve_q,\
278 (define_insn_reservation "thunderx2t99_asimd_logic" 5 286 (define_insn_reservation "thunderx2t99_asimd_logic" 5
279 (and (eq_attr "tune" "thunderx2t99") 287 (and (eq_attr "tune" "thunderx2t99")
280 (eq_attr "type" "neon_logic,neon_logic_q")) 288 (eq_attr "type" "neon_logic,neon_logic_q"))
281 "thunderx2t99_f01") 289 "thunderx2t99_f01")
282 290
283 (define_insn_reservation "thunderx2t99_asimd_polynomial" 5
284 (and (eq_attr "tune" "thunderx2t99")
285 (eq_attr "type" "neon_mul_d_long"))
286 "thunderx2t99_f01")
287
288 ;; ASIMD floating-point instructions. 291 ;; ASIMD floating-point instructions.
289 292
290 (define_insn_reservation "thunderx2t99_asimd_fp_simple" 5 293 (define_insn_reservation "thunderx2t99_asimd_fp_simple" 5
291 (and (eq_attr "tune" "thunderx2t99") 294 (and (eq_attr "tune" "thunderx2t99")
292 (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_d,\ 295 (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_d,\
309 neon_fp_addsub_s_q,neon_fp_addsub_d_q,\ 312 neon_fp_addsub_s_q,neon_fp_addsub_d_q,\
310 neon_fp_reduc_add_s,neon_fp_reduc_add_d,\ 313 neon_fp_reduc_add_s,neon_fp_reduc_add_d,\
311 neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q,\ 314 neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q,\
312 neon_fp_mul_s,neon_fp_mul_d,\ 315 neon_fp_mul_s,neon_fp_mul_d,\
313 neon_fp_mul_s_q,neon_fp_mul_d_q,\ 316 neon_fp_mul_s_q,neon_fp_mul_d_q,\
317 neon_fp_mul_s_scalar_q,neon_fp_mul_d_scalar_q,\
314 neon_fp_mla_s,neon_fp_mla_d,\ 318 neon_fp_mla_s,neon_fp_mla_d,\
315 neon_fp_mla_s_q,neon_fp_mla_d_q")) 319 neon_fp_mla_s_q,neon_fp_mla_d_q"))
316 "thunderx2t99_f01") 320 "thunderx2t99_f01")
317 321
318 (define_insn_reservation "thunderx2t99_asimd_fp_conv" 7 322 (define_insn_reservation "thunderx2t99_asimd_fp_conv" 7
319 (and (eq_attr "tune" "thunderx2t99") 323 (and (eq_attr "tune" "thunderx2t99")
320 (eq_attr "type" "neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q,\ 324 (eq_attr "type" "neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q,\
321 neon_fp_to_int_s,neon_fp_to_int_d,\ 325 neon_fp_to_int_s,neon_fp_to_int_d,\
322 neon_fp_to_int_s_q,neon_fp_to_int_d_q,\ 326 neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
327 neon_int_to_fp_s,neon_int_to_fp_d,\
328 neon_int_to_fp_s_q,neon_int_to_fp_d_q,\
323 neon_fp_round_s,neon_fp_round_d,\ 329 neon_fp_round_s,neon_fp_round_d,\
324 neon_fp_round_s_q,neon_fp_round_d_q")) 330 neon_fp_round_s_q,neon_fp_round_d_q"))
325 "thunderx2t99_f01") 331 "thunderx2t99_f01")
326 332
327 (define_insn_reservation "thunderx2t99_asimd_fp_div_s" 16 333 (define_insn_reservation "thunderx2t99_asimd_fp_div_s" 16
350 neon_fp_recpe_s,neon_fp_recpe_d,\ 356 neon_fp_recpe_s,neon_fp_recpe_d,\
351 neon_fp_recpe_s_q,neon_fp_recpe_d_q,\ 357 neon_fp_recpe_s_q,neon_fp_recpe_d_q,\
352 neon_fp_recpx_s,neon_fp_recpx_d,\ 358 neon_fp_recpx_s,neon_fp_recpx_d,\
353 neon_fp_recpx_s_q,neon_fp_recpx_d_q,\ 359 neon_fp_recpx_s_q,neon_fp_recpx_d_q,\
354 neon_rev,neon_rev_q,\ 360 neon_rev,neon_rev_q,\
355 neon_dup,neon_dup_q,\
356 neon_permute,neon_permute_q")) 361 neon_permute,neon_permute_q"))
357 "thunderx2t99_f01") 362 "thunderx2t99_f01")
358 363
359 (define_insn_reservation "thunderx2t99_asimd_recip_step" 6 364 (define_insn_reservation "thunderx2t99_asimd_recip_step" 6
360 (and (eq_attr "tune" "thunderx2t99") 365 (and (eq_attr "tune" "thunderx2t99")
361 (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\ 366 (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\
362 neon_fp_recps_d,neon_fp_recps_d_q,\ 367 neon_fp_recps_d,neon_fp_recps_d_q,\
368 neon_fp_sqrt_s,neon_fp_sqrt_s_q,\
369 neon_fp_sqrt_d,neon_fp_sqrt_d_q,\
370 neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\
371 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q,\
363 neon_fp_rsqrts_s, neon_fp_rsqrts_s_q,\ 372 neon_fp_rsqrts_s, neon_fp_rsqrts_s_q,\
364 neon_fp_rsqrts_d, neon_fp_rsqrts_d_q")) 373 neon_fp_rsqrts_d, neon_fp_rsqrts_d_q"))
365 "thunderx2t99_f01") 374 "thunderx2t99_f01")
366 375
367 (define_insn_reservation "thunderx2t99_asimd_lut" 8 376 (define_insn_reservation "thunderx2t99_asimd_lut" 8
368 (and (eq_attr "tune" "thunderx2t99") 377 (and (eq_attr "tune" "thunderx2t99")
369 (eq_attr "type" "neon_tbl1,neon_tbl1_q,neon_tbl2_q")) 378 (eq_attr "type" "neon_tbl1,neon_tbl1_q,neon_tbl2,neon_tbl2_q,\
379 neon_tbl3,neon_tbl3_q,neon_tbl4,neon_tbl4_q"))
370 "thunderx2t99_f01") 380 "thunderx2t99_f01")
371 381
372 (define_insn_reservation "thunderx2t99_asimd_elt_to_gr" 6 382 (define_insn_reservation "thunderx2t99_asimd_elt_to_gr" 6
373 (and (eq_attr "tune" "thunderx2t99") 383 (and (eq_attr "tune" "thunderx2t99")
374 (eq_attr "type" "neon_to_gp,neon_to_gp_q")) 384 (eq_attr "type" "neon_to_gp,neon_to_gp_q"))
375 "thunderx2t99_f01")
376
377 (define_insn_reservation "thunderx2t99_asimd_ext" 7
378 (and (eq_attr "tune" "thunderx2t99")
379 (eq_attr "type" "neon_shift_imm_narrow_q,neon_sat_shift_imm_narrow_q"))
380 "thunderx2t99_f01") 385 "thunderx2t99_f01")
381 386
382 ;; ASIMD load instructions. 387 ;; ASIMD load instructions.
383 388
384 ; NOTE: These reservations attempt to model latency and throughput correctly, 389 ; NOTE: These reservations attempt to model latency and throughput correctly,
385 ; but the cycle timing of unit allocation is not necessarily accurate (because 390 ; but the cycle timing of unit allocation is not necessarily accurate (because
386 ; insns are split into uops, and those may be issued out-of-order). 391 ; insns are split into uops, and those may be issued out-of-order).
387 392
388 (define_insn_reservation "thunderx2t99_asimd_load1_1_mult" 4 393 (define_insn_reservation "thunderx2t99_asimd_load1_ldp" 5
389 (and (eq_attr "tune" "thunderx2t99") 394 (and (eq_attr "tune" "thunderx2t99")
390 (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q")) 395 (eq_attr "type" "neon_ldp,neon_ldp_q"))
396 "thunderx2t99_i012,thunderx2t99_ls01")
397
398 (define_insn_reservation "thunderx2t99_asimd_load1" 4
399 (and (eq_attr "tune" "thunderx2t99")
400 (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,\
401 neon_load1_2reg,neon_load1_2reg_q,\
402 neon_load1_3reg,neon_load1_3reg_q,\
403 neon_load1_4reg,neon_load1_4reg_q"))
391 "thunderx2t99_ls01") 404 "thunderx2t99_ls01")
392
393 (define_insn_reservation "thunderx2t99_asimd_load1_2_mult" 4
394 (and (eq_attr "tune" "thunderx2t99")
395 (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q"))
396 "thunderx2t99_ls_both")
397 405
398 (define_insn_reservation "thunderx2t99_asimd_load1_onelane" 5 406 (define_insn_reservation "thunderx2t99_asimd_load1_onelane" 5
399 (and (eq_attr "tune" "thunderx2t99") 407 (and (eq_attr "tune" "thunderx2t99")
400 (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q")) 408 (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q"))
401 "thunderx2t99_l01delay,thunderx2t99_f01") 409 "thunderx2t99_l01delay,thunderx2t99_f01")
408 (define_insn_reservation "thunderx2t99_asimd_load2" 5 416 (define_insn_reservation "thunderx2t99_asimd_load2" 5
409 (and (eq_attr "tune" "thunderx2t99") 417 (and (eq_attr "tune" "thunderx2t99")
410 (eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\ 418 (eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\
411 neon_load2_one_lane,neon_load2_one_lane_q,\ 419 neon_load2_one_lane,neon_load2_one_lane_q,\
412 neon_load2_all_lanes,neon_load2_all_lanes_q")) 420 neon_load2_all_lanes,neon_load2_all_lanes_q"))
413 "(thunderx2t99_l0delay,thunderx2t99_f01)|(thunderx2t99_l1delay,\ 421 "thunderx2t99_l01delay,thunderx2t99_f01")
414 thunderx2t99_f01)") 422
423 (define_insn_reservation "thunderx2t99_asimd_load3" 7
424 (and (eq_attr "tune" "thunderx2t99")
425 (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\
426 neon_load3_one_lane,neon_load3_one_lane_q,\
427 neon_load3_all_lanes,neon_load3_all_lanes_q"))
428 "thunderx2t99_l01delay,thunderx2t99_f01")
429
430 (define_insn_reservation "thunderx2t99_asimd_load4" 8
431 (and (eq_attr "tune" "thunderx2t99")
432 (eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q,\
433 neon_load4_one_lane,neon_load4_one_lane_q,\
434 neon_load4_all_lanes,neon_load4_all_lanes_q"))
435 "thunderx2t99_l01delay,thunderx2t99_f01")
415 436
416 ;; ASIMD store instructions. 437 ;; ASIMD store instructions.
417 438
418 ; Same note applies as for ASIMD load instructions. 439 ; Same note applies as for ASIMD load instructions.
419 440
420 (define_insn_reservation "thunderx2t99_asimd_store1_1_mult" 1 441 (define_insn_reservation "thunderx2t99_asimd_store_stp" 1
421 (and (eq_attr "tune" "thunderx2t99") 442 (and (eq_attr "tune" "thunderx2t99")
422 (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q")) 443 (eq_attr "type" "neon_stp,neon_stp_q"))
444 "thunderx2t99_ls01,thunderx2t99_sd")
445
446 (define_insn_reservation "thunderx2t99_asimd_store1" 1
447 (and (eq_attr "tune" "thunderx2t99")
448 (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
449 neon_store1_2reg,neon_store1_2reg_q,\
450 neon_store1_3reg,neon_store1_4reg"))
423 "thunderx2t99_ls01") 451 "thunderx2t99_ls01")
424
425 (define_insn_reservation "thunderx2t99_asimd_store1_2_mult" 1
426 (and (eq_attr "tune" "thunderx2t99")
427 (eq_attr "type" "neon_store1_2reg,neon_store1_2reg_q"))
428 "thunderx2t99_ls_both")
429 452
430 (define_insn_reservation "thunderx2t99_asimd_store1_onelane" 1 453 (define_insn_reservation "thunderx2t99_asimd_store1_onelane" 1
431 (and (eq_attr "tune" "thunderx2t99") 454 (and (eq_attr "tune" "thunderx2t99")
432 (eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q")) 455 (eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q"))
433 "thunderx2t99_ls01,thunderx2t99_f01") 456 "thunderx2t99_ls01,thunderx2t99_f01")
434 457
435 (define_insn_reservation "thunderx2t99_asimd_store2_mult" 1 458 (define_insn_reservation "thunderx2t99_asimd_store2" 1
436 (and (eq_attr "tune" "thunderx2t99") 459 (and (eq_attr "tune" "thunderx2t99")
437 (eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q")) 460 (eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q,\
438 "thunderx2t99_ls_both,thunderx2t99_f01") 461 neon_store2_one_lane,neon_store2_one_lane_q"))
439 462 "thunderx2t99_ls01,thunderx2t99_f01")
440 (define_insn_reservation "thunderx2t99_asimd_store2_onelane" 1 463
441 (and (eq_attr "tune" "thunderx2t99") 464 (define_insn_reservation "thunderx2t99_asimd_store3" 1
442 (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q")) 465 (and (eq_attr "tune" "thunderx2t99")
466 (eq_attr "type" "neon_store3_3reg,neon_store3_3reg_q,\
467 neon_store3_one_lane,neon_store3_one_lane_q"))
468 "thunderx2t99_ls01,thunderx2t99_f01")
469
470 (define_insn_reservation "thunderx2t99_asimd_store4" 1
471 (and (eq_attr "tune" "thunderx2t99")
472 (eq_attr "type" "neon_store4_4reg,neon_store4_4reg_q,\
473 neon_store4_one_lane,neon_store4_one_lane_q"))
443 "thunderx2t99_ls01,thunderx2t99_f01") 474 "thunderx2t99_ls01,thunderx2t99_f01")
444 475
445 ;; Crypto extensions. 476 ;; Crypto extensions.
446 477
447 (define_insn_reservation "thunderx2t99_aes" 5 478 (define_insn_reservation "thunderx2t99_aes" 5