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comparison gcc/config/arm/vfp.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
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111:04ced10e8804 131:84e7813d76e9
1 ;; ARM VFP instruction patterns 1 ;; ARM VFP instruction patterns
2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery. 3 ;; Written by CodeSourcery.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
302 302
303 303
304 ;; DImode moves 304 ;; DImode moves
305 305
306 (define_insn "*movdi_vfp" 306 (define_insn "*movdi_vfp"
307 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv") 307 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,!r,w,w, Uv")
308 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))] 308 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
309 "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune != TARGET_CPU_cortexa8 309 "TARGET_32BIT && TARGET_HARD_FLOAT
310 && ( register_operand (operands[0], DImode) 310 && ( register_operand (operands[0], DImode)
311 || register_operand (operands[1], DImode)) 311 || register_operand (operands[1], DImode))
312 && !(TARGET_NEON && CONST_INT_P (operands[1]) 312 && !(TARGET_NEON && CONST_INT_P (operands[1])
313 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))" 313 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
314 "* 314 "*
337 default: 337 default:
338 gcc_unreachable (); 338 gcc_unreachable ();
339 } 339 }
340 " 340 "
341 [(set_attr "type" "multiple,multiple,multiple,multiple,load_8,load_8,store_8,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") 341 [(set_attr "type" "multiple,multiple,multiple,multiple,load_8,load_8,store_8,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
342 (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8) 342 (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
343 (eq_attr "alternative" "2") (const_int 12) 343 (eq_attr "alternative" "2") (const_int 12)
344 (eq_attr "alternative" "3") (const_int 16) 344 (eq_attr "alternative" "3") (const_int 16)
345 (eq_attr "alternative" "4,5,6")
346 (symbol_ref "arm_count_output_move_double_insns (operands) * 4")
345 (eq_attr "alternative" "9") 347 (eq_attr "alternative" "9")
346 (if_then_else 348 (if_then_else
347 (match_test "TARGET_VFP_SINGLE") 349 (match_test "TARGET_VFP_SINGLE")
348 (const_int 8) 350 (const_int 8)
349 (const_int 4))] 351 (const_int 4))]
350 (const_int 4))) 352 (const_int 4)))
353 (set_attr "predicable" "yes")
351 (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") 354 (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*")
352 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") 355 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
353 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") 356 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
357 (set (attr "ce_count") (symbol_ref "get_attr_length (insn) / 4"))
354 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] 358 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
355 ) 359 )
356
357 (define_insn "*movdi_vfp_cortexa8"
358 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,!r,w,w, Uv")
359 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
360 "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == TARGET_CPU_cortexa8
361 && ( register_operand (operands[0], DImode)
362 || register_operand (operands[1], DImode))
363 && !(TARGET_NEON && CONST_INT_P (operands[1])
364 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
365 "*
366 switch (which_alternative)
367 {
368 case 0:
369 case 1:
370 case 2:
371 case 3:
372 return \"#\";
373 case 4:
374 case 5:
375 case 6:
376 return output_move_double (operands, true, NULL);
377 case 7:
378 return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
379 case 8:
380 return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
381 case 9:
382 return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
383 case 10: case 11:
384 return output_move_vfp (operands);
385 default:
386 gcc_unreachable ();
387 }
388 "
389 [(set_attr "type" "multiple,multiple,multiple,multiple,load_8,load_8,store_8,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
390 (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
391 (eq_attr "alternative" "2") (const_int 12)
392 (eq_attr "alternative" "3") (const_int 16)
393 (eq_attr "alternative" "4,5,6")
394 (symbol_ref
395 "arm_count_output_move_double_insns (operands) \
396 * 4")]
397 (const_int 4)))
398 (set_attr "predicable" "yes")
399 (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
400 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
401 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
402 (set (attr "ce_count")
403 (symbol_ref "get_attr_length (insn) / 4"))
404 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
405 )
406 360
407 ;; HFmode moves 361 ;; HFmode moves
408 362
409 (define_insn "*movhf_vfp_fp16" 363 (define_insn "*movhf_vfp_fp16"
410 [(set (match_operand:HF 0 "nonimmediate_operand" 364 [(set (match_operand:HF 0 "nonimmediate_operand"
454 } 408 }
455 default: 409 default:
456 gcc_unreachable (); 410 gcc_unreachable ();
457 } 411 }
458 } 412 }
459 [(set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no") 413 [(set_attr "conds" "*, *, unconditional, *, unconditional, unconditional,\
414 unconditional, unconditional, unconditional,\
415 unconditional")
416 (set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no")
460 (set_attr "predicable_short_it" "no, no, no, yes,\ 417 (set_attr "predicable_short_it" "no, no, no, yes,\
461 no, no, no, no,\ 418 no, no, no, no,\
462 no, no") 419 no, no")
463 (set_attr_alternative "type" 420 (set_attr_alternative "type"
464 [(const_string "load_4") (const_string "store_4") 421 [(const_string "load_4") (const_string "store_4")
656 default: 613 default:
657 gcc_unreachable (); 614 gcc_unreachable ();
658 } 615 }
659 " 616 "
660 [(set_attr "predicable" "yes") 617 [(set_attr "predicable" "yes")
661 (set_attr "predicable_short_it" "no")
662 (set_attr "type" 618 (set_attr "type"
663 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg") 619 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg")
664 (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") 620 (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
665 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] 621 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
666 ) 622 )
868 [(set (match_operand:SF 0 "s_register_operand" "=t") 824 [(set (match_operand:SF 0 "s_register_operand" "=t")
869 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))] 825 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
870 "TARGET_32BIT && TARGET_HARD_FLOAT" 826 "TARGET_32BIT && TARGET_HARD_FLOAT"
871 "vabs%?.f32\\t%0, %1" 827 "vabs%?.f32\\t%0, %1"
872 [(set_attr "predicable" "yes") 828 [(set_attr "predicable" "yes")
873 (set_attr "predicable_short_it" "no")
874 (set_attr "type" "ffariths")] 829 (set_attr "type" "ffariths")]
875 ) 830 )
876 831
877 (define_insn "*absdf2_vfp" 832 (define_insn "*absdf2_vfp"
878 [(set (match_operand:DF 0 "s_register_operand" "=w") 833 [(set (match_operand:DF 0 "s_register_operand" "=w")
879 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] 834 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
880 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 835 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
881 "vabs%?.f64\\t%P0, %P1" 836 "vabs%?.f64\\t%P0, %P1"
882 [(set_attr "predicable" "yes") 837 [(set_attr "predicable" "yes")
883 (set_attr "predicable_short_it" "no")
884 (set_attr "type" "ffarithd")] 838 (set_attr "type" "ffarithd")]
885 ) 839 )
886 840
887 (define_insn "*negsf2_vfp" 841 (define_insn "*negsf2_vfp"
888 [(set (match_operand:SF 0 "s_register_operand" "=t,?r") 842 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
890 "TARGET_32BIT && TARGET_HARD_FLOAT" 844 "TARGET_32BIT && TARGET_HARD_FLOAT"
891 "@ 845 "@
892 vneg%?.f32\\t%0, %1 846 vneg%?.f32\\t%0, %1
893 eor%?\\t%0, %1, #-2147483648" 847 eor%?\\t%0, %1, #-2147483648"
894 [(set_attr "predicable" "yes") 848 [(set_attr "predicable" "yes")
895 (set_attr "predicable_short_it" "no")
896 (set_attr "type" "ffariths")] 849 (set_attr "type" "ffariths")]
897 ) 850 )
898 851
899 (define_insn_and_split "*negdf2_vfp" 852 (define_insn_and_split "*negdf2_vfp"
900 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r") 853 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
936 operands[1] = in_lo; 889 operands[1] = in_lo;
937 } 890 }
938 } 891 }
939 " 892 "
940 [(set_attr "predicable" "yes") 893 [(set_attr "predicable" "yes")
941 (set_attr "predicable_short_it" "no")
942 (set_attr "length" "4,4,8") 894 (set_attr "length" "4,4,8")
943 (set_attr "type" "ffarithd")] 895 (set_attr "type" "ffarithd")]
944 ) 896 )
945 897
946 ;; ABS and NEG for FP16. 898 ;; ABS and NEG for FP16.
1005 (plus:SF (match_operand:SF 1 "s_register_operand" "t") 957 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
1006 (match_operand:SF 2 "s_register_operand" "t")))] 958 (match_operand:SF 2 "s_register_operand" "t")))]
1007 "TARGET_32BIT && TARGET_HARD_FLOAT" 959 "TARGET_32BIT && TARGET_HARD_FLOAT"
1008 "vadd%?.f32\\t%0, %1, %2" 960 "vadd%?.f32\\t%0, %1, %2"
1009 [(set_attr "predicable" "yes") 961 [(set_attr "predicable" "yes")
1010 (set_attr "predicable_short_it" "no")
1011 (set_attr "type" "fadds")] 962 (set_attr "type" "fadds")]
1012 ) 963 )
1013 964
1014 (define_insn "*adddf3_vfp" 965 (define_insn "*adddf3_vfp"
1015 [(set (match_operand:DF 0 "s_register_operand" "=w") 966 [(set (match_operand:DF 0 "s_register_operand" "=w")
1016 (plus:DF (match_operand:DF 1 "s_register_operand" "w") 967 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
1017 (match_operand:DF 2 "s_register_operand" "w")))] 968 (match_operand:DF 2 "s_register_operand" "w")))]
1018 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 969 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1019 "vadd%?.f64\\t%P0, %P1, %P2" 970 "vadd%?.f64\\t%P0, %P1, %P2"
1020 [(set_attr "predicable" "yes") 971 [(set_attr "predicable" "yes")
1021 (set_attr "predicable_short_it" "no")
1022 (set_attr "type" "faddd")] 972 (set_attr "type" "faddd")]
1023 ) 973 )
1024 974
1025 (define_insn "subhf3" 975 (define_insn "subhf3"
1026 [(set 976 [(set
1039 (minus:SF (match_operand:SF 1 "s_register_operand" "t") 989 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
1040 (match_operand:SF 2 "s_register_operand" "t")))] 990 (match_operand:SF 2 "s_register_operand" "t")))]
1041 "TARGET_32BIT && TARGET_HARD_FLOAT" 991 "TARGET_32BIT && TARGET_HARD_FLOAT"
1042 "vsub%?.f32\\t%0, %1, %2" 992 "vsub%?.f32\\t%0, %1, %2"
1043 [(set_attr "predicable" "yes") 993 [(set_attr "predicable" "yes")
1044 (set_attr "predicable_short_it" "no")
1045 (set_attr "type" "fadds")] 994 (set_attr "type" "fadds")]
1046 ) 995 )
1047 996
1048 (define_insn "*subdf3_vfp" 997 (define_insn "*subdf3_vfp"
1049 [(set (match_operand:DF 0 "s_register_operand" "=w") 998 [(set (match_operand:DF 0 "s_register_operand" "=w")
1050 (minus:DF (match_operand:DF 1 "s_register_operand" "w") 999 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
1051 (match_operand:DF 2 "s_register_operand" "w")))] 1000 (match_operand:DF 2 "s_register_operand" "w")))]
1052 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1001 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1053 "vsub%?.f64\\t%P0, %P1, %P2" 1002 "vsub%?.f64\\t%P0, %P1, %P2"
1054 [(set_attr "predicable" "yes") 1003 [(set_attr "predicable" "yes")
1055 (set_attr "predicable_short_it" "no")
1056 (set_attr "type" "faddd")] 1004 (set_attr "type" "faddd")]
1057 ) 1005 )
1058 1006
1059 1007
1060 ;; Division insns 1008 ;; Division insns
1080 (div:SF (match_operand:SF 1 "s_register_operand" "t,t") 1028 (div:SF (match_operand:SF 1 "s_register_operand" "t,t")
1081 (match_operand:SF 2 "s_register_operand" "t,t")))] 1029 (match_operand:SF 2 "s_register_operand" "t,t")))]
1082 "TARGET_32BIT && TARGET_HARD_FLOAT" 1030 "TARGET_32BIT && TARGET_HARD_FLOAT"
1083 "vdiv%?.f32\\t%0, %1, %2" 1031 "vdiv%?.f32\\t%0, %1, %2"
1084 [(set_attr "predicable" "yes") 1032 [(set_attr "predicable" "yes")
1085 (set_attr "predicable_short_it" "no")
1086 (set_attr "arch" "*,armv6_or_vfpv3") 1033 (set_attr "arch" "*,armv6_or_vfpv3")
1087 (set_attr "type" "fdivs")] 1034 (set_attr "type" "fdivs")]
1088 ) 1035 )
1089 1036
1090 (define_insn "*divdf3_vfp" 1037 (define_insn "*divdf3_vfp"
1092 (div:DF (match_operand:DF 1 "s_register_operand" "w,w") 1039 (div:DF (match_operand:DF 1 "s_register_operand" "w,w")
1093 (match_operand:DF 2 "s_register_operand" "w,w")))] 1040 (match_operand:DF 2 "s_register_operand" "w,w")))]
1094 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1041 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1095 "vdiv%?.f64\\t%P0, %P1, %P2" 1042 "vdiv%?.f64\\t%P0, %P1, %P2"
1096 [(set_attr "predicable" "yes") 1043 [(set_attr "predicable" "yes")
1097 (set_attr "predicable_short_it" "no")
1098 (set_attr "arch" "*,armv6_or_vfpv3") 1044 (set_attr "arch" "*,armv6_or_vfpv3")
1099 (set_attr "type" "fdivd")] 1045 (set_attr "type" "fdivd")]
1100 ) 1046 )
1101 1047
1102 1048
1118 (mult:SF (match_operand:SF 1 "s_register_operand" "t") 1064 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
1119 (match_operand:SF 2 "s_register_operand" "t")))] 1065 (match_operand:SF 2 "s_register_operand" "t")))]
1120 "TARGET_32BIT && TARGET_HARD_FLOAT" 1066 "TARGET_32BIT && TARGET_HARD_FLOAT"
1121 "vmul%?.f32\\t%0, %1, %2" 1067 "vmul%?.f32\\t%0, %1, %2"
1122 [(set_attr "predicable" "yes") 1068 [(set_attr "predicable" "yes")
1123 (set_attr "predicable_short_it" "no")
1124 (set_attr "type" "fmuls")] 1069 (set_attr "type" "fmuls")]
1125 ) 1070 )
1126 1071
1127 (define_insn "*muldf3_vfp" 1072 (define_insn "*muldf3_vfp"
1128 [(set (match_operand:DF 0 "s_register_operand" "=w") 1073 [(set (match_operand:DF 0 "s_register_operand" "=w")
1129 (mult:DF (match_operand:DF 1 "s_register_operand" "w") 1074 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
1130 (match_operand:DF 2 "s_register_operand" "w")))] 1075 (match_operand:DF 2 "s_register_operand" "w")))]
1131 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1076 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1132 "vmul%?.f64\\t%P0, %P1, %P2" 1077 "vmul%?.f64\\t%P0, %P1, %P2"
1133 [(set_attr "predicable" "yes") 1078 [(set_attr "predicable" "yes")
1134 (set_attr "predicable_short_it" "no")
1135 (set_attr "type" "fmuld")] 1079 (set_attr "type" "fmuld")]
1136 ) 1080 )
1137 1081
1138 (define_insn "*mulsf3neghf_vfp" 1082 (define_insn "*mulsf3neghf_vfp"
1139 [(set (match_operand:HF 0 "s_register_operand" "=t") 1083 [(set (match_operand:HF 0 "s_register_operand" "=t")
1160 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) 1104 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
1161 (match_operand:SF 2 "s_register_operand" "t")))] 1105 (match_operand:SF 2 "s_register_operand" "t")))]
1162 "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math" 1106 "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
1163 "vnmul%?.f32\\t%0, %1, %2" 1107 "vnmul%?.f32\\t%0, %1, %2"
1164 [(set_attr "predicable" "yes") 1108 [(set_attr "predicable" "yes")
1165 (set_attr "predicable_short_it" "no")
1166 (set_attr "type" "fmuls")] 1109 (set_attr "type" "fmuls")]
1167 ) 1110 )
1168 1111
1169 (define_insn "*negmulsf3_vfp" 1112 (define_insn "*negmulsf3_vfp"
1170 [(set (match_operand:SF 0 "s_register_operand" "=t") 1113 [(set (match_operand:SF 0 "s_register_operand" "=t")
1171 (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t") 1114 (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
1172 (match_operand:SF 2 "s_register_operand" "t"))))] 1115 (match_operand:SF 2 "s_register_operand" "t"))))]
1173 "TARGET_32BIT && TARGET_HARD_FLOAT" 1116 "TARGET_32BIT && TARGET_HARD_FLOAT"
1174 "vnmul%?.f32\\t%0, %1, %2" 1117 "vnmul%?.f32\\t%0, %1, %2"
1175 [(set_attr "predicable" "yes") 1118 [(set_attr "predicable" "yes")
1176 (set_attr "predicable_short_it" "no")
1177 (set_attr "type" "fmuls")] 1119 (set_attr "type" "fmuls")]
1178 ) 1120 )
1179 1121
1180 (define_insn "*muldf3negdf_vfp" 1122 (define_insn "*muldf3negdf_vfp"
1181 [(set (match_operand:DF 0 "s_register_operand" "=w") 1123 [(set (match_operand:DF 0 "s_register_operand" "=w")
1183 (match_operand:DF 2 "s_register_operand" "w")))] 1125 (match_operand:DF 2 "s_register_operand" "w")))]
1184 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE 1126 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
1185 && !flag_rounding_math" 1127 && !flag_rounding_math"
1186 "vnmul%?.f64\\t%P0, %P1, %P2" 1128 "vnmul%?.f64\\t%P0, %P1, %P2"
1187 [(set_attr "predicable" "yes") 1129 [(set_attr "predicable" "yes")
1188 (set_attr "predicable_short_it" "no")
1189 (set_attr "type" "fmuld")] 1130 (set_attr "type" "fmuld")]
1190 ) 1131 )
1191 1132
1192 (define_insn "*negmuldf3_vfp" 1133 (define_insn "*negmuldf3_vfp"
1193 [(set (match_operand:DF 0 "s_register_operand" "=w") 1134 [(set (match_operand:DF 0 "s_register_operand" "=w")
1194 (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w") 1135 (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w")
1195 (match_operand:DF 2 "s_register_operand" "w"))))] 1136 (match_operand:DF 2 "s_register_operand" "w"))))]
1196 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1137 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1197 "vnmul%?.f64\\t%P0, %P1, %P2" 1138 "vnmul%?.f64\\t%P0, %P1, %P2"
1198 [(set_attr "predicable" "yes") 1139 [(set_attr "predicable" "yes")
1199 (set_attr "predicable_short_it" "no")
1200 (set_attr "type" "fmuld")] 1140 (set_attr "type" "fmuld")]
1201 ) 1141 )
1202 1142
1203 1143
1204 ;; Multiply-accumulate insns 1144 ;; Multiply-accumulate insns
1222 (match_operand:SF 3 "s_register_operand" "t")) 1162 (match_operand:SF 3 "s_register_operand" "t"))
1223 (match_operand:SF 1 "s_register_operand" "0")))] 1163 (match_operand:SF 1 "s_register_operand" "0")))]
1224 "TARGET_32BIT && TARGET_HARD_FLOAT" 1164 "TARGET_32BIT && TARGET_HARD_FLOAT"
1225 "vmla%?.f32\\t%0, %2, %3" 1165 "vmla%?.f32\\t%0, %2, %3"
1226 [(set_attr "predicable" "yes") 1166 [(set_attr "predicable" "yes")
1227 (set_attr "predicable_short_it" "no")
1228 (set_attr "type" "fmacs")] 1167 (set_attr "type" "fmacs")]
1229 ) 1168 )
1230 1169
1231 (define_insn "*muldf3adddf_vfp" 1170 (define_insn "*muldf3adddf_vfp"
1232 [(set (match_operand:DF 0 "s_register_operand" "=w") 1171 [(set (match_operand:DF 0 "s_register_operand" "=w")
1234 (match_operand:DF 3 "s_register_operand" "w")) 1173 (match_operand:DF 3 "s_register_operand" "w"))
1235 (match_operand:DF 1 "s_register_operand" "0")))] 1174 (match_operand:DF 1 "s_register_operand" "0")))]
1236 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1175 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1237 "vmla%?.f64\\t%P0, %P2, %P3" 1176 "vmla%?.f64\\t%P0, %P2, %P3"
1238 [(set_attr "predicable" "yes") 1177 [(set_attr "predicable" "yes")
1239 (set_attr "predicable_short_it" "no")
1240 (set_attr "type" "fmacd")] 1178 (set_attr "type" "fmacd")]
1241 ) 1179 )
1242 1180
1243 ;; 0 = 1 * 2 - 0 1181 ;; 0 = 1 * 2 - 0
1244 (define_insn "*mulhf3subhf_vfp" 1182 (define_insn "*mulhf3subhf_vfp"
1258 (match_operand:SF 3 "s_register_operand" "t")) 1196 (match_operand:SF 3 "s_register_operand" "t"))
1259 (match_operand:SF 1 "s_register_operand" "0")))] 1197 (match_operand:SF 1 "s_register_operand" "0")))]
1260 "TARGET_32BIT && TARGET_HARD_FLOAT" 1198 "TARGET_32BIT && TARGET_HARD_FLOAT"
1261 "vnmls%?.f32\\t%0, %2, %3" 1199 "vnmls%?.f32\\t%0, %2, %3"
1262 [(set_attr "predicable" "yes") 1200 [(set_attr "predicable" "yes")
1263 (set_attr "predicable_short_it" "no")
1264 (set_attr "type" "fmacs")] 1201 (set_attr "type" "fmacs")]
1265 ) 1202 )
1266 1203
1267 (define_insn "*muldf3subdf_vfp" 1204 (define_insn "*muldf3subdf_vfp"
1268 [(set (match_operand:DF 0 "s_register_operand" "=w") 1205 [(set (match_operand:DF 0 "s_register_operand" "=w")
1270 (match_operand:DF 3 "s_register_operand" "w")) 1207 (match_operand:DF 3 "s_register_operand" "w"))
1271 (match_operand:DF 1 "s_register_operand" "0")))] 1208 (match_operand:DF 1 "s_register_operand" "0")))]
1272 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1209 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1273 "vnmls%?.f64\\t%P0, %P2, %P3" 1210 "vnmls%?.f64\\t%P0, %P2, %P3"
1274 [(set_attr "predicable" "yes") 1211 [(set_attr "predicable" "yes")
1275 (set_attr "predicable_short_it" "no")
1276 (set_attr "type" "fmacd")] 1212 (set_attr "type" "fmacd")]
1277 ) 1213 )
1278 1214
1279 ;; 0 = -(1 * 2) + 0 1215 ;; 0 = -(1 * 2) + 0
1280 (define_insn "*mulhf3neghfaddhf_vfp" 1216 (define_insn "*mulhf3neghfaddhf_vfp"
1294 (mult:SF (match_operand:SF 2 "s_register_operand" "t") 1230 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
1295 (match_operand:SF 3 "s_register_operand" "t"))))] 1231 (match_operand:SF 3 "s_register_operand" "t"))))]
1296 "TARGET_32BIT && TARGET_HARD_FLOAT" 1232 "TARGET_32BIT && TARGET_HARD_FLOAT"
1297 "vmls%?.f32\\t%0, %2, %3" 1233 "vmls%?.f32\\t%0, %2, %3"
1298 [(set_attr "predicable" "yes") 1234 [(set_attr "predicable" "yes")
1299 (set_attr "predicable_short_it" "no")
1300 (set_attr "type" "fmacs")] 1235 (set_attr "type" "fmacs")]
1301 ) 1236 )
1302 1237
1303 (define_insn "*fmuldf3negdfadddf_vfp" 1238 (define_insn "*fmuldf3negdfadddf_vfp"
1304 [(set (match_operand:DF 0 "s_register_operand" "=w") 1239 [(set (match_operand:DF 0 "s_register_operand" "=w")
1306 (mult:DF (match_operand:DF 2 "s_register_operand" "w") 1241 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
1307 (match_operand:DF 3 "s_register_operand" "w"))))] 1242 (match_operand:DF 3 "s_register_operand" "w"))))]
1308 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1243 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1309 "vmls%?.f64\\t%P0, %P2, %P3" 1244 "vmls%?.f64\\t%P0, %P2, %P3"
1310 [(set_attr "predicable" "yes") 1245 [(set_attr "predicable" "yes")
1311 (set_attr "predicable_short_it" "no")
1312 (set_attr "type" "fmacd")] 1246 (set_attr "type" "fmacd")]
1313 ) 1247 )
1314 1248
1315 1249
1316 ;; 0 = -(1 * 2) - 0 1250 ;; 0 = -(1 * 2) - 0
1333 (match_operand:SF 3 "s_register_operand" "t")) 1267 (match_operand:SF 3 "s_register_operand" "t"))
1334 (match_operand:SF 1 "s_register_operand" "0")))] 1268 (match_operand:SF 1 "s_register_operand" "0")))]
1335 "TARGET_32BIT && TARGET_HARD_FLOAT" 1269 "TARGET_32BIT && TARGET_HARD_FLOAT"
1336 "vnmla%?.f32\\t%0, %2, %3" 1270 "vnmla%?.f32\\t%0, %2, %3"
1337 [(set_attr "predicable" "yes") 1271 [(set_attr "predicable" "yes")
1338 (set_attr "predicable_short_it" "no")
1339 (set_attr "type" "fmacs")] 1272 (set_attr "type" "fmacs")]
1340 ) 1273 )
1341 1274
1342 (define_insn "*muldf3negdfsubdf_vfp" 1275 (define_insn "*muldf3negdfsubdf_vfp"
1343 [(set (match_operand:DF 0 "s_register_operand" "=w") 1276 [(set (match_operand:DF 0 "s_register_operand" "=w")
1346 (match_operand:DF 3 "s_register_operand" "w")) 1279 (match_operand:DF 3 "s_register_operand" "w"))
1347 (match_operand:DF 1 "s_register_operand" "0")))] 1280 (match_operand:DF 1 "s_register_operand" "0")))]
1348 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1281 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1349 "vnmla%?.f64\\t%P0, %P2, %P3" 1282 "vnmla%?.f64\\t%P0, %P2, %P3"
1350 [(set_attr "predicable" "yes") 1283 [(set_attr "predicable" "yes")
1351 (set_attr "predicable_short_it" "no")
1352 (set_attr "type" "fmacd")] 1284 (set_attr "type" "fmacd")]
1353 ) 1285 )
1354 1286
1355 ;; Fused-multiply-accumulate 1287 ;; Fused-multiply-accumulate
1356 1288
1384 (match_operand:SDF 2 "register_operand" "<F_constraint>") 1316 (match_operand:SDF 2 "register_operand" "<F_constraint>")
1385 (match_operand:SDF 3 "register_operand" "0")))] 1317 (match_operand:SDF 3 "register_operand" "0")))]
1386 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" 1318 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
1387 "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" 1319 "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1388 [(set_attr "predicable" "yes") 1320 [(set_attr "predicable" "yes")
1389 (set_attr "predicable_short_it" "no")
1390 (set_attr "type" "ffma<vfp_type>")] 1321 (set_attr "type" "ffma<vfp_type>")]
1391 ) 1322 )
1392 1323
1393 (define_insn "fmsubhf4_fp16" 1324 (define_insn "fmsubhf4_fp16"
1394 [(set (match_operand:HF 0 "register_operand" "=w") 1325 [(set (match_operand:HF 0 "register_operand" "=w")
1421 (match_operand:SDF 2 "register_operand" "<F_constraint>") 1352 (match_operand:SDF 2 "register_operand" "<F_constraint>")
1422 (match_operand:SDF 3 "register_operand" "0")))] 1353 (match_operand:SDF 3 "register_operand" "0")))]
1423 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" 1354 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
1424 "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" 1355 "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1425 [(set_attr "predicable" "yes") 1356 [(set_attr "predicable" "yes")
1426 (set_attr "predicable_short_it" "no")
1427 (set_attr "type" "ffma<vfp_type>")] 1357 (set_attr "type" "ffma<vfp_type>")]
1428 ) 1358 )
1429 1359
1430 (define_insn "*fnmsubhf4" 1360 (define_insn "*fnmsubhf4"
1431 [(set (match_operand:HF 0 "register_operand" "=w") 1361 [(set (match_operand:HF 0 "register_operand" "=w")
1444 (match_operand:SDF 2 "register_operand" "<F_constraint>") 1374 (match_operand:SDF 2 "register_operand" "<F_constraint>")
1445 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] 1375 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
1446 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" 1376 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
1447 "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" 1377 "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1448 [(set_attr "predicable" "yes") 1378 [(set_attr "predicable" "yes")
1449 (set_attr "predicable_short_it" "no")
1450 (set_attr "type" "ffma<vfp_type>")] 1379 (set_attr "type" "ffma<vfp_type>")]
1451 ) 1380 )
1452 1381
1453 (define_insn "*fnmaddhf4" 1382 (define_insn "*fnmaddhf4"
1454 [(set (match_operand:HF 0 "register_operand" "=w") 1383 [(set (match_operand:HF 0 "register_operand" "=w")
1468 (match_operand:SDF 2 "register_operand" "<F_constraint>") 1397 (match_operand:SDF 2 "register_operand" "<F_constraint>")
1469 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] 1398 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
1470 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" 1399 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
1471 "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" 1400 "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1472 [(set_attr "predicable" "yes") 1401 [(set_attr "predicable" "yes")
1473 (set_attr "predicable_short_it" "no")
1474 (set_attr "type" "ffma<vfp_type>")] 1402 (set_attr "type" "ffma<vfp_type>")]
1475 ) 1403 )
1476 1404
1477 1405
1478 ;; Conversion routines 1406 ;; Conversion routines
1481 [(set (match_operand:DF 0 "s_register_operand" "=w") 1409 [(set (match_operand:DF 0 "s_register_operand" "=w")
1482 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))] 1410 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
1483 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1411 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1484 "vcvt%?.f64.f32\\t%P0, %1" 1412 "vcvt%?.f64.f32\\t%P0, %1"
1485 [(set_attr "predicable" "yes") 1413 [(set_attr "predicable" "yes")
1486 (set_attr "predicable_short_it" "no")
1487 (set_attr "type" "f_cvt")] 1414 (set_attr "type" "f_cvt")]
1488 ) 1415 )
1489 1416
1490 (define_insn "*truncdfsf2_vfp" 1417 (define_insn "*truncdfsf2_vfp"
1491 [(set (match_operand:SF 0 "s_register_operand" "=t") 1418 [(set (match_operand:SF 0 "s_register_operand" "=t")
1492 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] 1419 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
1493 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1420 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1494 "vcvt%?.f32.f64\\t%0, %P1" 1421 "vcvt%?.f32.f64\\t%0, %P1"
1495 [(set_attr "predicable" "yes") 1422 [(set_attr "predicable" "yes")
1496 (set_attr "predicable_short_it" "no")
1497 (set_attr "type" "f_cvt")] 1423 (set_attr "type" "f_cvt")]
1498 ) 1424 )
1499 1425
1500 (define_insn "extendhfsf2" 1426 (define_insn "extendhfsf2"
1501 [(set (match_operand:SF 0 "s_register_operand" "=t") 1427 [(set (match_operand:SF 0 "s_register_operand" "=t")
1502 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))] 1428 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
1503 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" 1429 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
1504 "vcvtb%?.f32.f16\\t%0, %1" 1430 "vcvtb%?.f32.f16\\t%0, %1"
1505 [(set_attr "predicable" "yes") 1431 [(set_attr "predicable" "yes")
1506 (set_attr "predicable_short_it" "no")
1507 (set_attr "type" "f_cvt")] 1432 (set_attr "type" "f_cvt")]
1508 ) 1433 )
1509 1434
1510 (define_insn "*truncdfhf2" 1435 (define_insn "*truncdfhf2"
1511 [(set (match_operand:HF 0 "s_register_operand" "=t") 1436 [(set (match_operand:HF 0 "s_register_operand" "=t")
1512 (float_truncate:HF (match_operand:DF 1 "s_register_operand" "w")))] 1437 (float_truncate:HF (match_operand:DF 1 "s_register_operand" "w")))]
1513 "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" 1438 "TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
1514 "vcvtb%?.f16.f64\\t%0, %P1" 1439 "vcvtb%?.f16.f64\\t%0, %P1"
1515 [(set_attr "predicable" "yes") 1440 [(set_attr "predicable" "yes")
1516 (set_attr "predicable_short_it" "no")
1517 (set_attr "type" "f_cvt")] 1441 (set_attr "type" "f_cvt")]
1518 ) 1442 )
1519 1443
1520 (define_insn "*extendhfdf2" 1444 (define_insn "*extendhfdf2"
1521 [(set (match_operand:DF 0 "s_register_operand" "=w") 1445 [(set (match_operand:DF 0 "s_register_operand" "=w")
1522 (float_extend:DF (match_operand:HF 1 "s_register_operand" "t")))] 1446 (float_extend:DF (match_operand:HF 1 "s_register_operand" "t")))]
1523 "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" 1447 "TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
1524 "vcvtb%?.f64.f16\\t%P0, %1" 1448 "vcvtb%?.f64.f16\\t%P0, %1"
1525 [(set_attr "predicable" "yes") 1449 [(set_attr "predicable" "yes")
1526 (set_attr "predicable_short_it" "no")
1527 (set_attr "type" "f_cvt")] 1450 (set_attr "type" "f_cvt")]
1528 ) 1451 )
1529 1452
1530 (define_insn "truncsfhf2" 1453 (define_insn "truncsfhf2"
1531 [(set (match_operand:HF 0 "s_register_operand" "=t") 1454 [(set (match_operand:HF 0 "s_register_operand" "=t")
1532 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))] 1455 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
1533 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" 1456 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
1534 "vcvtb%?.f16.f32\\t%0, %1" 1457 "vcvtb%?.f16.f32\\t%0, %1"
1535 [(set_attr "predicable" "yes") 1458 [(set_attr "predicable" "yes")
1536 (set_attr "predicable_short_it" "no")
1537 (set_attr "type" "f_cvt")] 1459 (set_attr "type" "f_cvt")]
1538 ) 1460 )
1539 1461
1540 (define_insn "*truncsisf2_vfp" 1462 (define_insn "*truncsisf2_vfp"
1541 [(set (match_operand:SI 0 "s_register_operand" "=t") 1463 [(set (match_operand:SI 0 "s_register_operand" "=t")
1542 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] 1464 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1543 "TARGET_32BIT && TARGET_HARD_FLOAT" 1465 "TARGET_32BIT && TARGET_HARD_FLOAT"
1544 "vcvt%?.s32.f32\\t%0, %1" 1466 "vcvt%?.s32.f32\\t%0, %1"
1545 [(set_attr "predicable" "yes") 1467 [(set_attr "predicable" "yes")
1546 (set_attr "predicable_short_it" "no")
1547 (set_attr "type" "f_cvtf2i")] 1468 (set_attr "type" "f_cvtf2i")]
1548 ) 1469 )
1549 1470
1550 (define_insn "*truncsidf2_vfp" 1471 (define_insn "*truncsidf2_vfp"
1551 [(set (match_operand:SI 0 "s_register_operand" "=t") 1472 [(set (match_operand:SI 0 "s_register_operand" "=t")
1552 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] 1473 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
1553 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1474 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1554 "vcvt%?.s32.f64\\t%0, %P1" 1475 "vcvt%?.s32.f64\\t%0, %P1"
1555 [(set_attr "predicable" "yes") 1476 [(set_attr "predicable" "yes")
1556 (set_attr "predicable_short_it" "no")
1557 (set_attr "type" "f_cvtf2i")] 1477 (set_attr "type" "f_cvtf2i")]
1558 ) 1478 )
1559 1479
1560 1480
1561 (define_insn "fixuns_truncsfsi2" 1481 (define_insn "fixuns_truncsfsi2"
1562 [(set (match_operand:SI 0 "s_register_operand" "=t") 1482 [(set (match_operand:SI 0 "s_register_operand" "=t")
1563 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] 1483 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1564 "TARGET_32BIT && TARGET_HARD_FLOAT" 1484 "TARGET_32BIT && TARGET_HARD_FLOAT"
1565 "vcvt%?.u32.f32\\t%0, %1" 1485 "vcvt%?.u32.f32\\t%0, %1"
1566 [(set_attr "predicable" "yes") 1486 [(set_attr "predicable" "yes")
1567 (set_attr "predicable_short_it" "no")
1568 (set_attr "type" "f_cvtf2i")] 1487 (set_attr "type" "f_cvtf2i")]
1569 ) 1488 )
1570 1489
1571 (define_insn "fixuns_truncdfsi2" 1490 (define_insn "fixuns_truncdfsi2"
1572 [(set (match_operand:SI 0 "s_register_operand" "=t") 1491 [(set (match_operand:SI 0 "s_register_operand" "=t")
1573 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))] 1492 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1574 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1493 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1575 "vcvt%?.u32.f64\\t%0, %P1" 1494 "vcvt%?.u32.f64\\t%0, %P1"
1576 [(set_attr "predicable" "yes") 1495 [(set_attr "predicable" "yes")
1577 (set_attr "predicable_short_it" "no")
1578 (set_attr "type" "f_cvtf2i")] 1496 (set_attr "type" "f_cvtf2i")]
1579 ) 1497 )
1580 1498
1581 1499
1582 (define_insn "*floatsisf2_vfp" 1500 (define_insn "*floatsisf2_vfp"
1583 [(set (match_operand:SF 0 "s_register_operand" "=t") 1501 [(set (match_operand:SF 0 "s_register_operand" "=t")
1584 (float:SF (match_operand:SI 1 "s_register_operand" "t")))] 1502 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1585 "TARGET_32BIT && TARGET_HARD_FLOAT" 1503 "TARGET_32BIT && TARGET_HARD_FLOAT"
1586 "vcvt%?.f32.s32\\t%0, %1" 1504 "vcvt%?.f32.s32\\t%0, %1"
1587 [(set_attr "predicable" "yes") 1505 [(set_attr "predicable" "yes")
1588 (set_attr "predicable_short_it" "no")
1589 (set_attr "type" "f_cvti2f")] 1506 (set_attr "type" "f_cvti2f")]
1590 ) 1507 )
1591 1508
1592 (define_insn "*floatsidf2_vfp" 1509 (define_insn "*floatsidf2_vfp"
1593 [(set (match_operand:DF 0 "s_register_operand" "=w") 1510 [(set (match_operand:DF 0 "s_register_operand" "=w")
1594 (float:DF (match_operand:SI 1 "s_register_operand" "t")))] 1511 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1595 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1512 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1596 "vcvt%?.f64.s32\\t%P0, %1" 1513 "vcvt%?.f64.s32\\t%P0, %1"
1597 [(set_attr "predicable" "yes") 1514 [(set_attr "predicable" "yes")
1598 (set_attr "predicable_short_it" "no")
1599 (set_attr "type" "f_cvti2f")] 1515 (set_attr "type" "f_cvti2f")]
1600 ) 1516 )
1601 1517
1602 1518
1603 (define_insn "floatunssisf2" 1519 (define_insn "floatunssisf2"
1604 [(set (match_operand:SF 0 "s_register_operand" "=t") 1520 [(set (match_operand:SF 0 "s_register_operand" "=t")
1605 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))] 1521 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1606 "TARGET_32BIT && TARGET_HARD_FLOAT" 1522 "TARGET_32BIT && TARGET_HARD_FLOAT"
1607 "vcvt%?.f32.u32\\t%0, %1" 1523 "vcvt%?.f32.u32\\t%0, %1"
1608 [(set_attr "predicable" "yes") 1524 [(set_attr "predicable" "yes")
1609 (set_attr "predicable_short_it" "no")
1610 (set_attr "type" "f_cvti2f")] 1525 (set_attr "type" "f_cvti2f")]
1611 ) 1526 )
1612 1527
1613 (define_insn "floatunssidf2" 1528 (define_insn "floatunssidf2"
1614 [(set (match_operand:DF 0 "s_register_operand" "=w") 1529 [(set (match_operand:DF 0 "s_register_operand" "=w")
1615 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))] 1530 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1616 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1531 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1617 "vcvt%?.f64.u32\\t%P0, %1" 1532 "vcvt%?.f64.u32\\t%P0, %1"
1618 [(set_attr "predicable" "yes") 1533 [(set_attr "predicable" "yes")
1619 (set_attr "predicable_short_it" "no")
1620 (set_attr "type" "f_cvti2f")] 1534 (set_attr "type" "f_cvti2f")]
1621 ) 1535 )
1622 1536
1623 1537
1624 ;; Sqrt insns. 1538 ;; Sqrt insns.
1651 [(set (match_operand:SF 0 "s_register_operand" "=&t,t") 1565 [(set (match_operand:SF 0 "s_register_operand" "=&t,t")
1652 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))] 1566 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
1653 "TARGET_32BIT && TARGET_HARD_FLOAT" 1567 "TARGET_32BIT && TARGET_HARD_FLOAT"
1654 "vsqrt%?.f32\\t%0, %1" 1568 "vsqrt%?.f32\\t%0, %1"
1655 [(set_attr "predicable" "yes") 1569 [(set_attr "predicable" "yes")
1656 (set_attr "predicable_short_it" "no")
1657 (set_attr "arch" "*,armv6_or_vfpv3") 1570 (set_attr "arch" "*,armv6_or_vfpv3")
1658 (set_attr "type" "fsqrts")] 1571 (set_attr "type" "fsqrts")]
1659 ) 1572 )
1660 1573
1661 (define_insn "*sqrtdf2_vfp" 1574 (define_insn "*sqrtdf2_vfp"
1662 [(set (match_operand:DF 0 "s_register_operand" "=&w,w") 1575 [(set (match_operand:DF 0 "s_register_operand" "=&w,w")
1663 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))] 1576 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))]
1664 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1577 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1665 "vsqrt%?.f64\\t%P0, %P1" 1578 "vsqrt%?.f64\\t%P0, %P1"
1666 [(set_attr "predicable" "yes") 1579 [(set_attr "predicable" "yes")
1667 (set_attr "predicable_short_it" "no")
1668 (set_attr "arch" "*,armv6_or_vfpv3") 1580 (set_attr "arch" "*,armv6_or_vfpv3")
1669 (set_attr "type" "fsqrtd")] 1581 (set_attr "type" "fsqrtd")]
1670 ) 1582 )
1671 1583
1672 1584
1754 "TARGET_32BIT && TARGET_HARD_FLOAT" 1666 "TARGET_32BIT && TARGET_HARD_FLOAT"
1755 "@ 1667 "@
1756 vcmp%?.f32\\t%0, %1 1668 vcmp%?.f32\\t%0, %1
1757 vcmp%?.f32\\t%0, #0" 1669 vcmp%?.f32\\t%0, #0"
1758 [(set_attr "predicable" "yes") 1670 [(set_attr "predicable" "yes")
1759 (set_attr "predicable_short_it" "no")
1760 (set_attr "type" "fcmps")] 1671 (set_attr "type" "fcmps")]
1761 ) 1672 )
1762 1673
1763 (define_insn "*cmpsf_trap_vfp" 1674 (define_insn "*cmpsf_trap_vfp"
1764 [(set (reg:CCFPE VFPCC_REGNUM) 1675 [(set (reg:CCFPE VFPCC_REGNUM)
1767 "TARGET_32BIT && TARGET_HARD_FLOAT" 1678 "TARGET_32BIT && TARGET_HARD_FLOAT"
1768 "@ 1679 "@
1769 vcmpe%?.f32\\t%0, %1 1680 vcmpe%?.f32\\t%0, %1
1770 vcmpe%?.f32\\t%0, #0" 1681 vcmpe%?.f32\\t%0, #0"
1771 [(set_attr "predicable" "yes") 1682 [(set_attr "predicable" "yes")
1772 (set_attr "predicable_short_it" "no")
1773 (set_attr "type" "fcmps")] 1683 (set_attr "type" "fcmps")]
1774 ) 1684 )
1775 1685
1776 (define_insn "*cmpdf_vfp" 1686 (define_insn "*cmpdf_vfp"
1777 [(set (reg:CCFP VFPCC_REGNUM) 1687 [(set (reg:CCFP VFPCC_REGNUM)
1780 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1690 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1781 "@ 1691 "@
1782 vcmp%?.f64\\t%P0, %P1 1692 vcmp%?.f64\\t%P0, %P1
1783 vcmp%?.f64\\t%P0, #0" 1693 vcmp%?.f64\\t%P0, #0"
1784 [(set_attr "predicable" "yes") 1694 [(set_attr "predicable" "yes")
1785 (set_attr "predicable_short_it" "no")
1786 (set_attr "type" "fcmpd")] 1695 (set_attr "type" "fcmpd")]
1787 ) 1696 )
1788 1697
1789 (define_insn "*cmpdf_trap_vfp" 1698 (define_insn "*cmpdf_trap_vfp"
1790 [(set (reg:CCFPE VFPCC_REGNUM) 1699 [(set (reg:CCFPE VFPCC_REGNUM)
1793 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" 1702 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1794 "@ 1703 "@
1795 vcmpe%?.f64\\t%P0, %P1 1704 vcmpe%?.f64\\t%P0, %P1
1796 vcmpe%?.f64\\t%P0, #0" 1705 vcmpe%?.f64\\t%P0, #0"
1797 [(set_attr "predicable" "yes") 1706 [(set_attr "predicable" "yes")
1798 (set_attr "predicable_short_it" "no")
1799 (set_attr "type" "fcmpd")] 1707 (set_attr "type" "fcmpd")]
1800 ) 1708 )
1801 1709
1802 ;; Fixed point to floating point conversions. 1710 ;; Fixed point to floating point conversions.
1803 (define_insn "*combine_vcvt_f32_<FCVTI32typename>" 1711 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1806 (match_operand 2 1714 (match_operand 2
1807 "const_double_vcvt_power_of_two_reciprocal" "Dt")))] 1715 "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1808 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" 1716 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1809 "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2" 1717 "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
1810 [(set_attr "predicable" "yes") 1718 [(set_attr "predicable" "yes")
1811 (set_attr "predicable_short_it" "no")
1812 (set_attr "type" "f_cvti2f")] 1719 (set_attr "type" "f_cvti2f")]
1813 ) 1720 )
1814 1721
1815 ;; Not the ideal way of implementing this. Ideally we would be able to split 1722 ;; Not the ideal way of implementing this. Ideally we would be able to split
1816 ;; this into a move to a DP register and then a vcvt.f64.i32 1723 ;; this into a move to a DP register and then a vcvt.f64.i32
1825 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 1732 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1826 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 1733 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1827 vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2" 1734 vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1828 [(set_attr "predicable" "yes") 1735 [(set_attr "predicable" "yes")
1829 (set_attr "ce_count" "2") 1736 (set_attr "ce_count" "2")
1830 (set_attr "predicable_short_it" "no")
1831 (set_attr "type" "f_cvti2f") 1737 (set_attr "type" "f_cvti2f")
1832 (set_attr "length" "8")] 1738 (set_attr "length" "8")]
1833 ) 1739 )
1834 1740
1835 (define_insn "*combine_vcvtf2i" 1741 (define_insn "*combine_vcvtf2i"
1838 (match_operand 2 1744 (match_operand 2
1839 "const_double_vcvt_power_of_two" "Dp")))))] 1745 "const_double_vcvt_power_of_two" "Dp")))))]
1840 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" 1746 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1841 "vcvt%?.s32.f32\\t%0, %1, %v2" 1747 "vcvt%?.s32.f32\\t%0, %1, %v2"
1842 [(set_attr "predicable" "yes") 1748 [(set_attr "predicable" "yes")
1843 (set_attr "predicable_short_it" "no")
1844 (set_attr "type" "f_cvtf2i")] 1749 (set_attr "type" "f_cvtf2i")]
1845 ) 1750 )
1846 1751
1847 ;; FP16 conversions. 1752 ;; FP16 conversions.
1848 (define_insn "neon_vcvth<sup>hf" 1753 (define_insn "neon_vcvth<sup>hf"
1984 "register_operand" "<F_constraint>")] 1889 "register_operand" "<F_constraint>")]
1985 VRINT))] 1890 VRINT))]
1986 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" 1891 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
1987 "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1" 1892 "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1988 [(set_attr "predicable" "<vrint_predicable>") 1893 [(set_attr "predicable" "<vrint_predicable>")
1989 (set_attr "predicable_short_it" "no")
1990 (set_attr "type" "f_rint<vfp_type>") 1894 (set_attr "type" "f_rint<vfp_type>")
1991 (set_attr "conds" "<vrint_conds>")] 1895 (set_attr "conds" "<vrint_conds>")]
1992 ) 1896 )
1993 1897
1994 ;; Implements the lround, lfloor and lceil optabs. 1898 ;; Implements the lround, lfloor and lceil optabs.
1997 (FIXUORS:SI (unspec:SDF 1901 (FIXUORS:SI (unspec:SDF
1998 [(match_operand:SDF 1 1902 [(match_operand:SDF 1
1999 "register_operand" "<F_constraint>")] VCVT)))] 1903 "register_operand" "<F_constraint>")] VCVT)))]
2000 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" 1904 "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
2001 "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" 1905 "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
2002 [(set_attr "predicable" "no") 1906 [(set_attr "conds" "unconditional")
2003 (set_attr "conds" "unconditional")
2004 (set_attr "type" "f_cvtf2i")] 1907 (set_attr "type" "f_cvtf2i")]
2005 ) 1908 )
2006 1909
2007 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL. 1910 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
2008 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which 1911 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which