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comparison gcc/config/cr16/cr16.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 ;; GCC machine description for CR16. 1 ;; GCC machine description for CR16.
2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 ;; Contributed by KPIT Cummins Infosystems Limited. 3 ;; Contributed by KPIT Cummins Infosystems Limited.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
653 "register_operand (operands[0], DImode) 653 "register_operand (operands[0], DImode)
654 || register_operand (operands[0], DFmode) 654 || register_operand (operands[0], DFmode)
655 || register_operand (operands[1], DImode) 655 || register_operand (operands[1], DImode)
656 || register_operand (operands[1], DFmode)" 656 || register_operand (operands[1], DFmode)"
657 { 657 {
658 if (0 == which_alternative) { 658 if (which_alternative == 0) {
659 rtx xoperands[2] ; 659 rtx xoperands[2];
660 int reg0 = REGNO (operands[0]); 660 int reg0 = REGNO (operands[0]);
661 int reg1 = REGNO (operands[1]); 661 int reg1 = REGNO (operands[1]);
662 662
663 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2); 663 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
664 xoperands[1] = gen_rtx_REG (SImode, reg1 + 2); 664 xoperands[1] = gen_rtx_REG (SImode, reg1 + 2);
671 { 671 {
672 output_asm_insn ("movd\t%1, %0", xoperands); 672 output_asm_insn ("movd\t%1, %0", xoperands);
673 output_asm_insn ("movd\t%1, %0", operands); 673 output_asm_insn ("movd\t%1, %0", operands);
674 }} 674 }}
675 675
676 else if (1 == which_alternative) { 676 else if (which_alternative == 1) {
677 rtx lo_operands[2] ; 677 rtx lo_operands[2];
678 rtx hi_operands[2] ; 678 rtx hi_operands[2];
679 679
680 lo_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 680 lo_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
681 hi_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); 681 hi_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
682 lo_operands[1] = simplify_gen_subreg (SImode, operands[1], 682 lo_operands[1] = simplify_gen_subreg (SImode, operands[1],
683 VOIDmode == GET_MODE (operands[1]) 683 VOIDmode == GET_MODE (operands[1])
686 VOIDmode == GET_MODE (operands[1]) 686 VOIDmode == GET_MODE (operands[1])
687 ? DImode : GET_MODE (operands[1]), 4); 687 ? DImode : GET_MODE (operands[1]), 4);
688 output_asm_insn ("movd\t%1, %0", lo_operands); 688 output_asm_insn ("movd\t%1, %0", lo_operands);
689 output_asm_insn ("movd\t%1, %0", hi_operands);} 689 output_asm_insn ("movd\t%1, %0", hi_operands);}
690 690
691 else if (2 == which_alternative) { 691 else if (which_alternative == 2) {
692 rtx xoperands[2] ; 692 rtx xoperands[2];
693 int reg0 = REGNO (operands[0]), reg1 = -2 ; 693 int reg0 = REGNO (operands[0]), reg1 = -2;
694 rtx addr ; 694 rtx addr;
695 695
696 if (MEM_P (operands[1])) 696 if (MEM_P (operands[1]))
697 addr = XEXP (operands[1], 0); 697 addr = XEXP (operands[1], 0);
698 else 698 else
699 addr = NULL_RTX ; 699 addr = NULL_RTX;
700 switch (GET_CODE (addr)) 700 switch (GET_CODE (addr))
701 { 701 {
702 case REG: 702 case REG:
703 case SUBREG: 703 case SUBREG:
704 reg1 = REGNO (addr); 704 reg1 = REGNO (addr);
705 break ; 705 break;
706 case PLUS: 706 case PLUS:
707 switch (GET_CODE (XEXP (addr, 0))) { 707 switch (GET_CODE (XEXP (addr, 0))) {
708 case REG: 708 case REG:
709 case SUBREG: 709 case SUBREG:
710 reg1 = REGNO (XEXP (addr, 0)); 710 reg1 = REGNO (XEXP (addr, 0));
711 break ; 711 break;
712 case PLUS: 712 case PLUS:
713 reg1 = REGNO (XEXP (XEXP (addr, 0), 0)); 713 reg1 = REGNO (XEXP (XEXP (addr, 0), 0));
714 break ; 714 break;
715 default: 715 default:
716 inform (DECL_SOURCE_LOCATION (cfun->decl), "unexpected expression; addr:"); 716 inform (DECL_SOURCE_LOCATION (cfun->decl), "unexpected expression; addr:");
717 debug_rtx (addr); 717 debug_rtx (addr);
718 inform (DECL_SOURCE_LOCATION (cfun->decl), "operands[1]:"); 718 inform (DECL_SOURCE_LOCATION (cfun->decl), "operands[1]:");
719 debug_rtx (operands[1]); 719 debug_rtx (operands[1]);
720 inform (DECL_SOURCE_LOCATION (cfun->decl), "generated code might now work\n"); 720 inform (DECL_SOURCE_LOCATION (cfun->decl), "generated code might now work\n");
721 break ;} 721 break;}
722 break ; 722 break;
723 default: 723 default:
724 break ; 724 break;
725 } 725 }
726 726
727 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2); 727 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
728 xoperands[1] = offset_address (operands[1], GEN_INT (4), 2); 728 xoperands[1] = offset_address (operands[1], GEN_INT (4), 2);
729 gcc_assert ((reg0 + 1) != reg1); 729 gcc_assert ((reg0 + 1) != reg1);
737 output_asm_insn ("loadd\t%1, %0", xoperands); 737 output_asm_insn ("loadd\t%1, %0", xoperands);
738 output_asm_insn ("loadd\t%1, %0", operands); 738 output_asm_insn ("loadd\t%1, %0", operands);
739 }} 739 }}
740 else 740 else
741 { 741 {
742 rtx xoperands[2] ; 742 rtx xoperands[2];
743 xoperands[0] = offset_address (operands[0], GEN_INT (4), 2); 743 xoperands[0] = offset_address (operands[0], GEN_INT (4), 2);
744 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 744 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
745 output_asm_insn ("stord\t%1, %0", operands); 745 output_asm_insn ("stord\t%1, %0", operands);
746 output_asm_insn ("stord\t%1, %0", xoperands); 746 output_asm_insn ("stord\t%1, %0", xoperands);
747 } 747 }
748 return "" ; 748 return "";
749 } 749 }
750 [(set_attr "length" "4, <lImmArithD>, <lImmArithD>, <lImmArithD>")] 750 [(set_attr "length" "4, <lImmArithD>, <lImmArithD>, <lImmArithD>")]
751 ) 751 )
752 752
753 ; All long (SI, SF) register move, load and store operations 753 ; All long (SI, SF) register move, load and store operations