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comparison gcc/config/i386/constraints.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 ;; Constraint definitions for IA-32 and x86-64. 1 ;; Constraint definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
76 76
77 (define_register_constraint "u" 77 (define_register_constraint "u"
78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" 78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
79 "Second from top of 80387 floating-point stack (@code{%st(1)}).") 79 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
80 80
81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" 81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.") 82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
83 83
84 (define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS" 84 (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
85 "@internal Any mask register.") 85 "@internal Any mask register.")
86 86
87 ;; Vector registers (also used for plain floating point nowadays). 87 ;; Vector registers (also used for plain floating point nowadays).
88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" 88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
89 "Any MMX register.") 89 "Any MMX register.")
92 "Any SSE register.") 92 "Any SSE register.")
93 93
94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" 94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
95 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") 95 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
96 96
97 (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
98 "@internal Any bound register.")
99
100 ;; We use the Y prefix to denote any number of conditional register sets: 97 ;; We use the Y prefix to denote any number of conditional register sets:
101 ;; z First SSE register. 98 ;; z First SSE register.
102 ;; c SSE inter-unit conversions enabled 99 ;; d any EVEX encodable SSE register for AVX512BW target or
103 ;; i SSE2 inter-unit moves to SSE register enabled 100 ;; any SSE register for SSE4_1 target.
104 ;; j SSE2 inter-unit moves from SSE register enabled
105 ;; d any EVEX encodable SSE register for AVX512BW target or any SSE register
106 ;; for SSE4_1 target, when inter-unit moves to SSE register are enabled
107 ;; e any EVEX encodable SSE register for AVX512BW target or any SSE register
108 ;; for SSE4_1 target, when inter-unit moves from SSE register are enabled
109 ;; m MMX inter-unit moves to MMX register enabled
110 ;; n MMX inter-unit moves from MMX register enabled
111 ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled 101 ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
112 ;; a Integer register when zero extensions with AND are disabled 102 ;; a Integer register when zero extensions with AND are disabled
113 ;; b Any register that can be used as the GOT base when calling 103 ;; b Any register that can be used as the GOT base when calling
114 ;; ___tls_get_addr: that is, any general register except EAX 104 ;; ___tls_get_addr: that is, any general register except EAX
115 ;; and ESP, for -fno-plt if linker supports it. Otherwise, 105 ;; and ESP, for -fno-plt if linker supports it. Otherwise,
122 ;; h EVEX encodable SSE register with number factor of four 112 ;; h EVEX encodable SSE register with number factor of four
123 113
124 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" 114 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
125 "First SSE register (@code{%xmm0}).") 115 "First SSE register (@code{%xmm0}).")
126 116
127 (define_register_constraint "Yc"
128 "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
129 "@internal Any SSE register, when SSE and inter-unit conversions are enabled.")
130
131 (define_register_constraint "Yi"
132 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
133 "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
134
135 (define_register_constraint "Yj"
136 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
137 "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
138
139 (define_register_constraint "Yd" 117 (define_register_constraint "Yd"
140 "TARGET_INTER_UNIT_MOVES_TO_VEC 118 "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
141 ? (TARGET_AVX512DQ 119 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
142 ? ALL_SSE_REGS
143 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
144 : NO_REGS"
145 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.")
146
147 (define_register_constraint "Ye"
148 "TARGET_INTER_UNIT_MOVES_FROM_VEC
149 ? (TARGET_AVX512DQ
150 ? ALL_SSE_REGS
151 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
152 : NO_REGS"
153 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.")
154
155 (define_register_constraint "Ym"
156 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS"
157 "@internal Any MMX register, when inter-unit moves to vector registers are enabled.")
158
159 (define_register_constraint "Yn"
160 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS"
161 "@internal Any MMX register, when inter-unit moves from vector registers are enabled.")
162 120
163 (define_register_constraint "Yp" 121 (define_register_constraint "Yp"
164 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" 122 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
165 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") 123 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
166 124
185 "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") 143 "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
186 144
187 (define_register_constraint "Yv" 145 (define_register_constraint "Yv"
188 "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" 146 "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
189 "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") 147 "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
190
191 (define_register_constraint "Yh" "TARGET_AVX512F ? MOD4_SSE_REGS : NO_REGS"
192 "@internal Any EVEX encodable SSE register, which has number factor of four.")
193 148
194 ;; We use the B prefix to denote any number of internal operands: 149 ;; We use the B prefix to denote any number of internal operands:
195 ;; f FLAGS_REG 150 ;; f FLAGS_REG
196 ;; g GOT memory operand. 151 ;; g GOT memory operand.
197 ;; m Vector memory operand 152 ;; m Vector memory operand
223 "@internal Memory operand without REX prefix." 178 "@internal Memory operand without REX prefix."
224 (match_operand 0 "norex_memory_operand")) 179 (match_operand 0 "norex_memory_operand"))
225 180
226 (define_constraint "Bs" 181 (define_constraint "Bs"
227 "@internal Sibcall memory operand." 182 "@internal Sibcall memory operand."
228 (ior (and (not (match_test "TARGET_X32")) 183 (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
184 (not (match_test "TARGET_X32"))
229 (match_operand 0 "sibcall_memory_operand")) 185 (match_operand 0 "sibcall_memory_operand"))
230 (and (match_test "TARGET_X32 && Pmode == DImode") 186 (and (match_test "TARGET_X32 && Pmode == DImode")
231 (match_operand 0 "GOT_memory_operand")))) 187 (match_operand 0 "GOT_memory_operand"))))
232 188
233 (define_constraint "Bw" 189 (define_constraint "Bw"
234 "@internal Call memory operand." 190 "@internal Call memory operand."
235 (ior (and (not (match_test "TARGET_X32")) 191 (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
192 (not (match_test "TARGET_X32"))
236 (match_operand 0 "memory_operand")) 193 (match_operand 0 "memory_operand"))
237 (and (match_test "TARGET_X32 && Pmode == DImode") 194 (and (match_test "TARGET_X32 && Pmode == DImode")
238 (match_operand 0 "GOT_memory_operand")))) 195 (match_operand 0 "GOT_memory_operand"))))
239 196
240 (define_constraint "Bz" 197 (define_constraint "Bz"
295 (and (match_code "const_double") 252 (and (match_code "const_double")
296 (match_test "standard_80387_constant_p (op) > 0"))) 253 (match_test "standard_80387_constant_p (op) > 0")))
297 254
298 ;; This can theoretically be any mode's CONST0_RTX. 255 ;; This can theoretically be any mode's CONST0_RTX.
299 (define_constraint "C" 256 (define_constraint "C"
300 "SSE constant zero operand." 257 "Constant zero operand."
301 (and (match_test "TARGET_SSE") 258 (ior (match_test "op == const0_rtx")
302 (ior (match_test "op == const0_rtx") 259 (match_operand 0 "const0_operand")))
303 (match_operand 0 "const0_operand"))))
304 260
305 ;; Constant-or-symbol-reference constraints. 261 ;; Constant-or-symbol-reference constraints.
306 262
307 (define_constraint "e" 263 (define_constraint "e"
308 "32-bit signed integer constant, or a symbolic reference known 264 "32-bit signed integer constant, or a symbolic reference known
354 (match_operand 0 "vsib_address_operand")) 310 (match_operand 0 "vsib_address_operand"))
355 311
356 (define_address_constraint "Ts" 312 (define_address_constraint "Ts"
357 "Address operand without segment register" 313 "Address operand without segment register"
358 (match_operand 0 "address_no_seg_operand")) 314 (match_operand 0 "address_no_seg_operand"))
359
360 (define_address_constraint "Ti"
361 "MPX address operand without index"
362 (match_operand 0 "address_mpx_no_index_operand"))
363
364 (define_address_constraint "Tb"
365 "MPX address operand without base"
366 (match_operand 0 "address_mpx_no_base_operand"))