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comparison gcc/config/i386/haswell.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;; Scheduling for Haswell and derived processors. 1 ;; Scheduling for Haswell and derived processors.
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2004-2018 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
72 (define_reservation "hsw_p237" "hsw_p2|hsw_p3|hsw_p7") 72 (define_reservation "hsw_p237" "hsw_p2|hsw_p3|hsw_p7")
73 (define_reservation "hsw_p015" "hsw_p0|hsw_p1|hsw_p5") 73 (define_reservation "hsw_p015" "hsw_p0|hsw_p1|hsw_p5")
74 (define_reservation "hsw_p01" "hsw_p0|hsw_p1") 74 (define_reservation "hsw_p01" "hsw_p0|hsw_p1")
75 75
76 (define_insn_reservation "hsw_complex_insn" 6 76 (define_insn_reservation "hsw_complex_insn" 6
77 (and (eq_attr "cpu" "haswell") 77 (and (eq_attr "cpu" "generic,haswell")
78 (eq_attr "type" "other,multi,str")) 78 (eq_attr "type" "other,multi,str"))
79 "hsw_decoder0") 79 "hsw_decoder0")
80 80
81 (define_insn_reservation "hsw_call" 1 81 (define_insn_reservation "hsw_call" 1
82 (and (eq_attr "cpu" "haswell") 82 (and (eq_attr "cpu" "generic,haswell")
83 (eq_attr "type" "call,callv")) 83 (eq_attr "type" "call,callv"))
84 "hsw_decoder0") 84 "hsw_decoder0")
85 85
86 ;; imov with memory operands does not use the integer units. 86 ;; imov with memory operands does not use the integer units.
87 ;; imovx always decodes to one uop, and also doesn't use the integer 87 ;; imovx always decodes to one uop, and also doesn't use the integer
88 ;; units if it has memory operands. 88 ;; units if it has memory operands.
89 (define_insn_reservation "hsw_imov" 1 89 (define_insn_reservation "hsw_imov" 1
90 (and (eq_attr "cpu" "haswell") 90 (and (eq_attr "cpu" "generic,haswell")
91 (and (eq_attr "memory" "none") 91 (and (eq_attr "memory" "none")
92 (eq_attr "type" "imov,imovx"))) 92 (eq_attr "type" "imov,imovx")))
93 "hsw_decodern,hsw_p0156") 93 "hsw_decodern,hsw_p0156")
94 94
95 (define_insn_reservation "hsw_imov_load" 2 95 (define_insn_reservation "hsw_imov_load" 2
96 (and (eq_attr "cpu" "haswell") 96 (and (eq_attr "cpu" "generic,haswell")
97 (and (eq_attr "memory" "load") 97 (and (eq_attr "memory" "load")
98 (eq_attr "type" "imov,imovx"))) 98 (eq_attr "type" "imov,imovx")))
99 "hsw_decodern,hsw_p23") 99 "hsw_decodern,hsw_p23")
100 100
101 (define_insn_reservation "hsw_imov_store" 3 101 (define_insn_reservation "hsw_imov_store" 3
102 (and (eq_attr "cpu" "haswell") 102 (and (eq_attr "cpu" "generic,haswell")
103 (and (eq_attr "memory" "store") 103 (and (eq_attr "memory" "store")
104 (eq_attr "type" "imov"))) 104 (eq_attr "type" "imov")))
105 "hsw_decodern,hsw_p4+(hsw_p2|hsw_p3|hsw_p7)") 105 "hsw_decodern,hsw_p4+(hsw_p2|hsw_p3|hsw_p7)")
106 106
107 (define_insn_reservation "hsw_icmov" 2 107 (define_insn_reservation "hsw_icmov" 2
108 (and (eq_attr "cpu" "haswell") 108 (and (eq_attr "cpu" "generic,haswell")
109 (and (eq_attr "memory" "none") 109 (and (eq_attr "memory" "none")
110 (eq_attr "type" "icmov"))) 110 (eq_attr "type" "icmov")))
111 "hsw_decodern,hsw_p0156,hsw_p0156") 111 "hsw_decodern,hsw_p0156,hsw_p0156")
112 112
113 (define_insn_reservation "hsw_icmov_load" 2 113 (define_insn_reservation "hsw_icmov_load" 2
114 (and (eq_attr "cpu" "haswell") 114 (and (eq_attr "cpu" "generic,haswell")
115 (and (eq_attr "memory" "load") 115 (and (eq_attr "memory" "load")
116 (eq_attr "type" "icmov"))) 116 (eq_attr "type" "icmov")))
117 "hsw_decodern,hsw_p23+hsw_p0156,hsw_p0156") 117 "hsw_decodern,hsw_p23+hsw_p0156,hsw_p0156")
118 118
119 (define_insn_reservation "hsw_push_reg" 3 119 (define_insn_reservation "hsw_push_reg" 3
120 (and (eq_attr "cpu" "haswell") 120 (and (eq_attr "cpu" "generic,haswell")
121 (and (eq_attr "memory" "store") 121 (and (eq_attr "memory" "store")
122 (eq_attr "type" "push"))) 122 (eq_attr "type" "push")))
123 "hsw_decodern,hsw_p4+hsw_p237") 123 "hsw_decodern,hsw_p4+hsw_p237")
124 124
125 (define_insn_reservation "hsw_push_mem" 3 125 (define_insn_reservation "hsw_push_mem" 3
126 (and (eq_attr "cpu" "haswell") 126 (and (eq_attr "cpu" "generic,haswell")
127 (and (eq_attr "memory" "both") 127 (and (eq_attr "memory" "both")
128 (eq_attr "type" "push"))) 128 (eq_attr "type" "push")))
129 "hsw_decodern,hsw_p4+hsw_p237,hsw_p237") 129 "hsw_decodern,hsw_p4+hsw_p237,hsw_p237")
130 130
131 ;; Consider lea latency as having 2 components. 131 ;; Consider lea latency as having 2 components.
132 (define_insn_reservation "hsw_lea" 1 132 (define_insn_reservation "hsw_lea" 1
133 (and (eq_attr "cpu" "haswell") 133 (and (eq_attr "cpu" "generic,haswell")
134 (and (eq_attr "memory" "none") 134 (and (eq_attr "memory" "none")
135 (eq_attr "type" "lea"))) 135 (eq_attr "type" "lea")))
136 "hsw_decodern,hsw_p1|hsw_p5") 136 "hsw_decodern,hsw_p1|hsw_p5")
137 137
138 (define_insn_reservation "hsw_shift_rotate" 1 138 (define_insn_reservation "hsw_shift_rotate" 1
139 (and (eq_attr "cpu" "haswell") 139 (and (eq_attr "cpu" "generic,haswell")
140 (and (eq_attr "memory" "none") 140 (and (eq_attr "memory" "none")
141 (eq_attr "type" "ishift,ishift1,rotate,rotate1"))) 141 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
142 "hsw_decodern,hsw_p0|hsw_p6") 142 "hsw_decodern,hsw_p0|hsw_p6")
143 143
144 (define_insn_reservation "hsw_shift_rotate_mem" 1 144 (define_insn_reservation "hsw_shift_rotate_mem" 1
145 (and (eq_attr "cpu" "haswell") 145 (and (eq_attr "cpu" "generic,haswell")
146 (and (eq_attr "memory" "!none") 146 (and (eq_attr "memory" "!none")
147 (eq_attr "type" "ishift,ishift1,rotate,rotate1"))) 147 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
148 "hsw_decodern,(hsw_p0|hsw_p6)+hsw_p237+hsw_p4") 148 "hsw_decodern,(hsw_p0|hsw_p6)+hsw_p237+hsw_p4")
149 149
150 (define_insn_reservation "hsw_branch" 1 150 (define_insn_reservation "hsw_branch" 1
151 (and (eq_attr "cpu" "haswell") 151 (and (eq_attr "cpu" "generic,haswell")
152 (and (eq_attr "memory" "none") 152 (and (eq_attr "memory" "none")
153 (eq_attr "type" "ibr"))) 153 (eq_attr "type" "ibr")))
154 "hsw_decodern,hsw_p6") 154 "hsw_decodern,hsw_p6")
155 155
156 (define_insn_reservation "hsw_indirect_branch" 2 156 (define_insn_reservation "hsw_indirect_branch" 2
157 (and (eq_attr "cpu" "haswell") 157 (and (eq_attr "cpu" "generic,haswell")
158 (and (eq_attr "memory" "!none") 158 (and (eq_attr "memory" "!none")
159 (eq_attr "type" "ibr"))) 159 (eq_attr "type" "ibr")))
160 "hsw_decoder0,hsw_p23+hsw_p6") 160 "hsw_decoder0,hsw_p23+hsw_p6")
161 161
162 (define_insn_reservation "hsw_leave" 4 162 (define_insn_reservation "hsw_leave" 4
163 (and (eq_attr "cpu" "haswell") 163 (and (eq_attr "cpu" "generic,haswell")
164 (eq_attr "type" "leave")) 164 (eq_attr "type" "leave"))
165 "hsw_decoder0,hsw_p23+hsw_p0156,hsw_p0156") 165 "hsw_decoder0,hsw_p23+hsw_p0156,hsw_p0156")
166 166
167 ;; imul and imulx with two/three operands only execute on port 1. 167 ;; imul and imulx with two/three operands only execute on port 1.
168 (define_insn_reservation "hsw_imul" 3 168 (define_insn_reservation "hsw_imul" 3
169 (and (eq_attr "cpu" "haswell") 169 (and (eq_attr "cpu" "generic,haswell")
170 (and (eq_attr "memory" "none") 170 (and (eq_attr "memory" "none")
171 (eq_attr "type" "imul"))) 171 (eq_attr "type" "imul")))
172 "hsw_decodern,hsw_p1") 172 "hsw_decodern,hsw_p1")
173 173
174 (define_insn_reservation "hsw_imul_mem" 3 174 (define_insn_reservation "hsw_imul_mem" 3
175 (and (eq_attr "cpu" "haswell") 175 (and (eq_attr "cpu" "generic,haswell")
176 (and (eq_attr "memory" "!none") 176 (and (eq_attr "memory" "!none")
177 (eq_attr "type" "imul"))) 177 (eq_attr "type" "imul")))
178 "hsw_decodern,hsw_p23+hsw_p1") 178 "hsw_decodern,hsw_p23+hsw_p1")
179 179
180 (define_insn_reservation "hsw_imulx" 4 180 (define_insn_reservation "hsw_imulx" 4
181 (and (eq_attr "cpu" "haswell") 181 (and (eq_attr "cpu" "generic,haswell")
182 (and (eq_attr "memory" "none") 182 (and (eq_attr "memory" "none")
183 (eq_attr "type" "imulx"))) 183 (eq_attr "type" "imulx")))
184 "hsw_decodern,hsw_p0156,hsw_p0156") 184 "hsw_decodern,hsw_p0156,hsw_p0156")
185 185
186 (define_insn_reservation "hsw_imulx_mem" 4 186 (define_insn_reservation "hsw_imulx_mem" 4
187 (and (eq_attr "cpu" "haswell") 187 (and (eq_attr "cpu" "generic,haswell")
188 (and (eq_attr "memory" "!none") 188 (and (eq_attr "memory" "!none")
189 (eq_attr "type" "imulx"))) 189 (eq_attr "type" "imulx")))
190 "hsw_decodern,hsw_p23+hsw_p0156,(hsw_p0|hsw_p6|hsw_p6)") 190 "hsw_decodern,hsw_p23+hsw_p0156,(hsw_p0|hsw_p6|hsw_p6)")
191 191
192 192
193 ;; div and idiv are very similar, so we model them the same. 193 ;; div and idiv are very similar, so we model them the same.
194 ;; Use the same latency for all QI,HI and SI modes. 194 ;; Use the same latency for all QI,HI and SI modes.
195 (define_insn_reservation "hsw_idiv" 23 195 (define_insn_reservation "hsw_idiv" 23
196 (and (eq_attr "cpu" "haswell") 196 (and (eq_attr "cpu" "generic,haswell")
197 (and (eq_attr "memory" "none") 197 (and (eq_attr "memory" "none")
198 (eq_attr "type" "idiv"))) 198 (eq_attr "type" "idiv")))
199 "hsw_decoder0,(hsw_p0p1p5p6+hsw_idiv)*9") 199 "hsw_decoder0,(hsw_p0p1p5p6+hsw_idiv)*9")
200 200
201 (define_insn_reservation "hsw_idiv_load" 23 201 (define_insn_reservation "hsw_idiv_load" 23
202 (and (eq_attr "cpu" "haswell") 202 (and (eq_attr "cpu" "generic,haswell")
203 (and (eq_attr "memory" "load") 203 (and (eq_attr "memory" "load")
204 (eq_attr "type" "idiv"))) 204 (eq_attr "type" "idiv")))
205 "hsw_decoder0,hsw_p23+hsw_p0+hsw_idiv,(hsw_p0p1p5p6+hsw_idiv)*9") 205 "hsw_decoder0,hsw_p23+hsw_p0+hsw_idiv,(hsw_p0p1p5p6+hsw_idiv)*9")
206 206
207 ;; x87 floating point operations. 207 ;; x87 floating point operations.
208 208
209 (define_insn_reservation "hsw_fxch" 0 209 (define_insn_reservation "hsw_fxch" 0
210 (and (eq_attr "cpu" "haswell") 210 (and (eq_attr "cpu" "generic,haswell")
211 (eq_attr "type" "fxch")) 211 (eq_attr "type" "fxch"))
212 "hsw_decodern") 212 "hsw_decodern")
213 213
214 (define_insn_reservation "hsw_fop" 3 214 (define_insn_reservation "hsw_fop" 3
215 (and (eq_attr "cpu" "haswell") 215 (and (eq_attr "cpu" "generic,haswell")
216 (and (eq_attr "memory" "none,unknown") 216 (and (eq_attr "memory" "none,unknown")
217 (eq_attr "type" "fop"))) 217 (eq_attr "type" "fop")))
218 "hsw_decodern,hsw_p1") 218 "hsw_decodern,hsw_p1")
219 219
220 (define_insn_reservation "hsw_fop_load" 5 220 (define_insn_reservation "hsw_fop_load" 5
221 (and (eq_attr "cpu" "haswell") 221 (and (eq_attr "cpu" "generic,haswell")
222 (and (eq_attr "memory" "load") 222 (and (eq_attr "memory" "load")
223 (eq_attr "type" "fop"))) 223 (eq_attr "type" "fop")))
224 "hsw_decodern,hsw_p23+hsw_p1,hsw_p1") 224 "hsw_decodern,hsw_p23+hsw_p1,hsw_p1")
225 225
226 (define_insn_reservation "hsw_fop_store" 3 226 (define_insn_reservation "hsw_fop_store" 3
227 (and (eq_attr "cpu" "haswell") 227 (and (eq_attr "cpu" "generic,haswell")
228 (and (eq_attr "memory" "store") 228 (and (eq_attr "memory" "store")
229 (eq_attr "type" "fop"))) 229 (eq_attr "type" "fop")))
230 "hsw_decodern,hsw_p0,hsw_p0,hsw_p0+hsw_p4+hsw_p3") 230 "hsw_decodern,hsw_p0,hsw_p0,hsw_p0+hsw_p4+hsw_p3")
231 231
232 (define_insn_reservation "hsw_fop_both" 5 232 (define_insn_reservation "hsw_fop_both" 5
233 (and (eq_attr "cpu" "haswell") 233 (and (eq_attr "cpu" "generic,haswell")
234 (and (eq_attr "memory" "both") 234 (and (eq_attr "memory" "both")
235 (eq_attr "type" "fop"))) 235 (eq_attr "type" "fop")))
236 "hsw_decodern,hsw_p2+hsw_p0,hsw_p0+hsw_p4+hsw_p3") 236 "hsw_decodern,hsw_p2+hsw_p0,hsw_p0+hsw_p4+hsw_p3")
237 237
238 (define_insn_reservation "hsw_fsgn" 1 238 (define_insn_reservation "hsw_fsgn" 1
239 (and (eq_attr "cpu" "haswell") 239 (and (eq_attr "cpu" "generic,haswell")
240 (eq_attr "type" "fsgn")) 240 (eq_attr "type" "fsgn"))
241 "hsw_decodern,hsw_p0") 241 "hsw_decodern,hsw_p0")
242 242
243 (define_insn_reservation "hsw_fistp" 7 243 (define_insn_reservation "hsw_fistp" 7
244 (and (eq_attr "cpu" "haswell") 244 (and (eq_attr "cpu" "generic,haswell")
245 (eq_attr "type" "fistp")) 245 (eq_attr "type" "fistp"))
246 "hsw_decoder0,hsw_p1+hsw_p4+hsw_p23") 246 "hsw_decoder0,hsw_p1+hsw_p4+hsw_p23")
247 247
248 (define_insn_reservation "hsw_fcmov" 2 248 (define_insn_reservation "hsw_fcmov" 2
249 (and (eq_attr "cpu" "haswell") 249 (and (eq_attr "cpu" "generic,haswell")
250 (eq_attr "type" "fcmov")) 250 (eq_attr "type" "fcmov"))
251 "hsw_decoder0,hsw_p0+hsw_p5,hsw_p0") 251 "hsw_decoder0,hsw_p0+hsw_p5,hsw_p0")
252 252
253 (define_insn_reservation "hsw_fcmp" 1 253 (define_insn_reservation "hsw_fcmp" 1
254 (and (eq_attr "cpu" "haswell") 254 (and (eq_attr "cpu" "generic,haswell")
255 (and (eq_attr "memory" "none") 255 (and (eq_attr "memory" "none")
256 (eq_attr "type" "fcmp"))) 256 (eq_attr "type" "fcmp")))
257 "hsw_decodern,hsw_p1") 257 "hsw_decodern,hsw_p1")
258 258
259 (define_insn_reservation "hsw_fcmp_load" 1 259 (define_insn_reservation "hsw_fcmp_load" 1
260 (and (eq_attr "cpu" "haswell") 260 (and (eq_attr "cpu" "generic,haswell")
261 (and (eq_attr "memory" "load") 261 (and (eq_attr "memory" "load")
262 (eq_attr "type" "fcmp"))) 262 (eq_attr "type" "fcmp")))
263 "hsw_decodern,hsw_p23+hsw_p1") 263 "hsw_decodern,hsw_p23+hsw_p1")
264 264
265 (define_insn_reservation "hsw_fmov" 1 265 (define_insn_reservation "hsw_fmov" 1
266 (and (eq_attr "cpu" "haswell") 266 (and (eq_attr "cpu" "generic,haswell")
267 (and (eq_attr "memory" "none") 267 (and (eq_attr "memory" "none")
268 (eq_attr "type" "fmov"))) 268 (eq_attr "type" "fmov")))
269 "hsw_decodern,hsw_p01") 269 "hsw_decodern,hsw_p01")
270 270
271 (define_insn_reservation "hsw_fmov_load" 3 271 (define_insn_reservation "hsw_fmov_load" 3
272 (and (eq_attr "cpu" "haswell") 272 (and (eq_attr "cpu" "generic,haswell")
273 (and (eq_attr "memory" "load") 273 (and (eq_attr "memory" "load")
274 (and (eq_attr "mode" "!XF") 274 (and (eq_attr "mode" "!XF")
275 (eq_attr "type" "fmov")))) 275 (eq_attr "type" "fmov"))))
276 "hsw_decodern,hsw_p23") 276 "hsw_decodern,hsw_p23")
277 277
278 (define_insn_reservation "hsw_fmov_XF_load" 3 278 (define_insn_reservation "hsw_fmov_XF_load" 3
279 (and (eq_attr "cpu" "haswell") 279 (and (eq_attr "cpu" "generic,haswell")
280 (and (eq_attr "memory" "load") 280 (and (eq_attr "memory" "load")
281 (and (eq_attr "mode" "XF") 281 (and (eq_attr "mode" "XF")
282 (eq_attr "type" "fmov")))) 282 (eq_attr "type" "fmov"))))
283 "hsw_decodern,(hsw_p23+hsw_p0)*2") 283 "hsw_decodern,(hsw_p23+hsw_p0)*2")
284 284
285 (define_insn_reservation "hsw_fmov_store" 1 285 (define_insn_reservation "hsw_fmov_store" 1
286 (and (eq_attr "cpu" "haswell") 286 (and (eq_attr "cpu" "generic,haswell")
287 (and (eq_attr "memory" "store") 287 (and (eq_attr "memory" "store")
288 (and (eq_attr "mode" "!XF") 288 (and (eq_attr "mode" "!XF")
289 (eq_attr "type" "fmov")))) 289 (eq_attr "type" "fmov"))))
290 "hsw_decodern,hsw_p4p7") 290 "hsw_decodern,hsw_p4p7")
291 291
292 (define_insn_reservation "hsw_fmov_XF_store" 3 292 (define_insn_reservation "hsw_fmov_XF_store" 3
293 (and (eq_attr "cpu" "haswell") 293 (and (eq_attr "cpu" "generic,haswell")
294 (and (eq_attr "memory" "store") 294 (and (eq_attr "memory" "store")
295 (and (eq_attr "mode" "XF") 295 (and (eq_attr "mode" "XF")
296 (eq_attr "type" "fmov")))) 296 (eq_attr "type" "fmov"))))
297 "hsw_decodern,hsw_p4p7,hsw_p4p7") 297 "hsw_decodern,hsw_p4p7,hsw_p4p7")
298 298
299 (define_insn_reservation "hsw_fmul" 4 299 (define_insn_reservation "hsw_fmul" 4
300 (and (eq_attr "cpu" "haswell") 300 (and (eq_attr "cpu" "generic,haswell")
301 (and (eq_attr "memory" "none") 301 (and (eq_attr "memory" "none")
302 (eq_attr "type" "fmul"))) 302 (eq_attr "type" "fmul")))
303 "hsw_decodern,hsw_p01") 303 "hsw_decodern,hsw_p01")
304 304
305 (define_insn_reservation "hsw_fmul_load" 4 305 (define_insn_reservation "hsw_fmul_load" 4
306 (and (eq_attr "cpu" "haswell") 306 (and (eq_attr "cpu" "generic,haswell")
307 (and (eq_attr "memory" "load") 307 (and (eq_attr "memory" "load")
308 (eq_attr "type" "fmul"))) 308 (eq_attr "type" "fmul")))
309 "hsw_decodern,hsw_p23+hsw_p01") 309 "hsw_decodern,hsw_p23+hsw_p01")
310 310
311 ;; fdiv latencies depend on the mode of the operands. XFmode gives 311 ;; fdiv latencies depend on the mode of the operands. XFmode gives
312 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 312 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18.
313 ;; Division by a power of 2 takes only 9 cycles, but we cannot model 313 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
314 ;; that. Throughput is equal to latency - 1, which we model using the 314 ;; that. Throughput is equal to latency - 1, which we model using the
315 ;; hsw_div automaton. 315 ;; hsw_div automaton.
316 (define_insn_reservation "hsw_fdiv_SF" 18 316 (define_insn_reservation "hsw_fdiv_SF" 18
317 (and (eq_attr "cpu" "haswell") 317 (and (eq_attr "cpu" "generic,haswell")
318 (and (eq_attr "memory" "none") 318 (and (eq_attr "memory" "none")
319 (and (eq_attr "mode" "SF") 319 (and (eq_attr "mode" "SF")
320 (eq_attr "type" "fdiv,fpspc")))) 320 (eq_attr "type" "fdiv,fpspc"))))
321 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*16") 321 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*16")
322 322
323 (define_insn_reservation "hsw_fdiv_SF_load" 19 323 (define_insn_reservation "hsw_fdiv_SF_load" 19
324 (and (eq_attr "cpu" "haswell") 324 (and (eq_attr "cpu" "generic,haswell")
325 (and (eq_attr "memory" "load") 325 (and (eq_attr "memory" "load")
326 (and (eq_attr "mode" "SF") 326 (and (eq_attr "mode" "SF")
327 (eq_attr "type" "fdiv,fpspc")))) 327 (eq_attr "type" "fdiv,fpspc"))))
328 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*16") 328 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*16")
329 329
330 (define_insn_reservation "hsw_fdiv_DF" 32 330 (define_insn_reservation "hsw_fdiv_DF" 32
331 (and (eq_attr "cpu" "haswell") 331 (and (eq_attr "cpu" "generic,haswell")
332 (and (eq_attr "memory" "none") 332 (and (eq_attr "memory" "none")
333 (and (eq_attr "mode" "DF") 333 (and (eq_attr "mode" "DF")
334 (eq_attr "type" "fdiv,fpspc")))) 334 (eq_attr "type" "fdiv,fpspc"))))
335 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*30") 335 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*30")
336 336
337 (define_insn_reservation "hsw_fdiv_DF_load" 33 337 (define_insn_reservation "hsw_fdiv_DF_load" 33
338 (and (eq_attr "cpu" "haswell") 338 (and (eq_attr "cpu" "generic,haswell")
339 (and (eq_attr "memory" "load") 339 (and (eq_attr "memory" "load")
340 (and (eq_attr "mode" "DF") 340 (and (eq_attr "mode" "DF")
341 (eq_attr "type" "fdiv,fpspc")))) 341 (eq_attr "type" "fdiv,fpspc"))))
342 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*30") 342 "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*30")
343 343
344 (define_insn_reservation "hsw_fdiv_XF" 38 344 (define_insn_reservation "hsw_fdiv_XF" 38
345 (and (eq_attr "cpu" "haswell") 345 (and (eq_attr "cpu" "generic,haswell")
346 (and (eq_attr "memory" "none") 346 (and (eq_attr "memory" "none")
347 (and (eq_attr "mode" "XF") 347 (and (eq_attr "mode" "XF")
348 (eq_attr "type" "fdiv,fpspc")))) 348 (eq_attr "type" "fdiv,fpspc"))))
349 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*36") 349 "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*36")
350 350
351 (define_insn_reservation "hsw_fdiv_XF_load" 39 351 (define_insn_reservation "hsw_fdiv_XF_load" 39
352 (and (eq_attr "cpu" "haswell") 352 (and (eq_attr "cpu" "generic,haswell")
353 (and (eq_attr "memory" "load") 353 (and (eq_attr "memory" "load")
354 (and (eq_attr "mode" "XF") 354 (and (eq_attr "mode" "XF")
355 (eq_attr "type" "fdiv,fpspc")))) 355 (eq_attr "type" "fdiv,fpspc"))))
356 "hsw_decodern,hsw_p2+hsw_p0+hsw_fdiv,hsw_fdiv*36") 356 "hsw_decodern,hsw_p2+hsw_p0+hsw_fdiv,hsw_fdiv*36")
357 357
358 ;; MMX instructions. 358 ;; MMX instructions.
359 359
360 (define_insn_reservation "hsw_mmx_add" 1 360 (define_insn_reservation "hsw_mmx_add" 1
361 (and (eq_attr "cpu" "haswell") 361 (and (eq_attr "cpu" "generic,haswell")
362 (and (eq_attr "memory" "none") 362 (and (eq_attr "memory" "none")
363 (eq_attr "type" "mmxadd,sseiadd"))) 363 (eq_attr "type" "mmxadd,sseiadd")))
364 "hsw_decodern,hsw_p1|hsw_p5") 364 "hsw_decodern,hsw_p1|hsw_p5")
365 365
366 (define_insn_reservation "hsw_mmx_add_load" 2 366 (define_insn_reservation "hsw_mmx_add_load" 2
367 (and (eq_attr "cpu" "haswell") 367 (and (eq_attr "cpu" "generic,haswell")
368 (and (eq_attr "memory" "load") 368 (and (eq_attr "memory" "load")
369 (eq_attr "type" "mmxadd,sseiadd"))) 369 (eq_attr "type" "mmxadd,sseiadd")))
370 "hsw_decodern,hsw_p23+(hsw_p1|hsw_p5)") 370 "hsw_decodern,hsw_p23+(hsw_p1|hsw_p5)")
371 371
372 (define_insn_reservation "hsw_mmx_shft" 1 372 (define_insn_reservation "hsw_mmx_shft" 1
373 (and (eq_attr "cpu" "haswell") 373 (and (eq_attr "cpu" "generic,haswell")
374 (and (eq_attr "memory" "none") 374 (and (eq_attr "memory" "none")
375 (eq_attr "type" "mmxshft"))) 375 (eq_attr "type" "mmxshft")))
376 "hsw_decodern,hsw_p0") 376 "hsw_decodern,hsw_p0")
377 377
378 (define_insn_reservation "hsw_mmx_shft_load" 2 378 (define_insn_reservation "hsw_mmx_shft_load" 2
379 (and (eq_attr "cpu" "haswell") 379 (and (eq_attr "cpu" "generic,haswell")
380 (and (eq_attr "memory" "load") 380 (and (eq_attr "memory" "load")
381 (eq_attr "type" "mmxshft"))) 381 (eq_attr "type" "mmxshft")))
382 "hsw_decodern,hsw_p23+hsw_p0") 382 "hsw_decodern,hsw_p23+hsw_p0")
383 383
384 (define_insn_reservation "hsw_mmx_sse_shft" 1 384 (define_insn_reservation "hsw_mmx_sse_shft" 1
385 (and (eq_attr "cpu" "haswell") 385 (and (eq_attr "cpu" "generic,haswell")
386 (and (eq_attr "memory" "none") 386 (and (eq_attr "memory" "none")
387 (and (eq_attr "type" "sseishft") 387 (and (eq_attr "type" "sseishft")
388 (eq_attr "length_immediate" "!0")))) 388 (eq_attr "length_immediate" "!0"))))
389 "hsw_decodern,hsw_p01") 389 "hsw_decodern,hsw_p01")
390 390
391 (define_insn_reservation "hsw_mmx_sse_shft_load" 2 391 (define_insn_reservation "hsw_mmx_sse_shft_load" 2
392 (and (eq_attr "cpu" "haswell") 392 (and (eq_attr "cpu" "generic,haswell")
393 (and (eq_attr "memory" "load") 393 (and (eq_attr "memory" "load")
394 (and (eq_attr "type" "sseishft") 394 (and (eq_attr "type" "sseishft")
395 (eq_attr "length_immediate" "!0")))) 395 (eq_attr "length_immediate" "!0"))))
396 "hsw_decodern,hsw_p01+hsw_p23") 396 "hsw_decodern,hsw_p01+hsw_p23")
397 397
398 (define_insn_reservation "hsw_mmx_sse_shft1" 2 398 (define_insn_reservation "hsw_mmx_sse_shft1" 2
399 (and (eq_attr "cpu" "haswell") 399 (and (eq_attr "cpu" "generic,haswell")
400 (and (eq_attr "memory" "none") 400 (and (eq_attr "memory" "none")
401 (and (eq_attr "type" "sseishft") 401 (and (eq_attr "type" "sseishft")
402 (eq_attr "length_immediate" "0")))) 402 (eq_attr "length_immediate" "0"))))
403 "hsw_decodern,hsw_p01") 403 "hsw_decodern,hsw_p01")
404 404
405 (define_insn_reservation "hsw_mmx_sse_shft1_load" 3 405 (define_insn_reservation "hsw_mmx_sse_shft1_load" 3
406 (and (eq_attr "cpu" "haswell") 406 (and (eq_attr "cpu" "generic,haswell")
407 (and (eq_attr "memory" "load") 407 (and (eq_attr "memory" "load")
408 (and (eq_attr "type" "sseishft") 408 (and (eq_attr "type" "sseishft")
409 (eq_attr "length_immediate" "0")))) 409 (eq_attr "length_immediate" "0"))))
410 "hsw_decodern,hsw_p01+hsw_p23") 410 "hsw_decodern,hsw_p01+hsw_p23")
411 411
412 (define_insn_reservation "hsw_mmx_mul" 5 412 (define_insn_reservation "hsw_mmx_mul" 5
413 (and (eq_attr "cpu" "haswell") 413 (and (eq_attr "cpu" "generic,haswell")
414 (and (eq_attr "memory" "none") 414 (and (eq_attr "memory" "none")
415 (eq_attr "type" "mmxmul,sseimul"))) 415 (eq_attr "type" "mmxmul,sseimul")))
416 "hsw_decodern,hsw_p01") 416 "hsw_decodern,hsw_p01")
417 417
418 (define_insn_reservation "hsw_mmx_mul_load" 5 418 (define_insn_reservation "hsw_mmx_mul_load" 5
419 (and (eq_attr "cpu" "haswell") 419 (and (eq_attr "cpu" "generic,haswell")
420 (and (eq_attr "memory" "none") 420 (and (eq_attr "memory" "none")
421 (eq_attr "type" "mmxmul,sseimul"))) 421 (eq_attr "type" "mmxmul,sseimul")))
422 "hsw_decodern,hsw_p23+hsw_p01") 422 "hsw_decodern,hsw_p23+hsw_p01")
423 423
424 (define_insn_reservation "hsw_sse_mmxcvt" 4 424 (define_insn_reservation "hsw_sse_mmxcvt" 4
425 (and (eq_attr "cpu" "haswell") 425 (and (eq_attr "cpu" "generic,haswell")
426 (and (eq_attr "mode" "DI") 426 (and (eq_attr "mode" "DI")
427 (eq_attr "type" "mmxcvt"))) 427 (eq_attr "type" "mmxcvt")))
428 "hsw_decodern,hsw_p1") 428 "hsw_decodern,hsw_p1")
429 429
430 ;; (define_insn_reservation "hsw_sse_mmxshft" 2 430 ;; (define_insn_reservation "hsw_sse_mmxshft" 2
431 ;; (and (eq_attr "cpu" "haswell") 431 ;; (and (eq_attr "cpu" "generic,haswell")
432 ;; (and (eq_attr "mode" "TI") 432 ;; (and (eq_attr "mode" "TI")
433 ;; (eq_attr "type" "mmxshft"))) 433 ;; (eq_attr "type" "mmxshft")))
434 ;; "hsw_decodern,hsw_p01") 434 ;; "hsw_decodern,hsw_p01")
435 435
436 ;; The sfence instruction. 436 ;; The sfence instruction.
437 (define_insn_reservation "hsw_sse_sfence" 2 437 (define_insn_reservation "hsw_sse_sfence" 2
438 (and (eq_attr "cpu" "haswell") 438 (and (eq_attr "cpu" "generic,haswell")
439 (and (eq_attr "memory" "unknown") 439 (and (eq_attr "memory" "unknown")
440 (eq_attr "type" "sse"))) 440 (eq_attr "type" "sse")))
441 "hsw_decoder0,hsw_p23+hsw_p4") 441 "hsw_decoder0,hsw_p23+hsw_p4")
442 442
443 (define_insn_reservation "hsw_sse_SFDF" 3 443 (define_insn_reservation "hsw_sse_SFDF" 3
444 (and (eq_attr "cpu" "haswell") 444 (and (eq_attr "cpu" "generic,haswell")
445 (and (eq_attr "mode" "SF,DF") 445 (and (eq_attr "mode" "SF,DF")
446 (eq_attr "type" "sse"))) 446 (eq_attr "type" "sse")))
447 "hsw_decodern,hsw_p01") 447 "hsw_decodern,hsw_p01")
448 448
449 (define_insn_reservation "hsw_sse_V4SF" 4 449 (define_insn_reservation "hsw_sse_V4SF" 4
450 (and (eq_attr "cpu" "haswell") 450 (and (eq_attr "cpu" "generic,haswell")
451 (and (eq_attr "mode" "V4SF") 451 (and (eq_attr "mode" "V4SF")
452 (eq_attr "type" "sse"))) 452 (eq_attr "type" "sse")))
453 "hsw_decodern,hsw_p01") 453 "hsw_decodern,hsw_p01")
454 454
455 (define_insn_reservation "hsw_sse_V8SF" 4 455 (define_insn_reservation "hsw_sse_V8SF" 4
456 (and (eq_attr "cpu" "haswell") 456 (and (eq_attr "cpu" "generic,haswell")
457 (and (eq_attr "mode" "V8SF,V4DF") 457 (and (eq_attr "mode" "V8SF,V4DF")
458 (eq_attr "type" "sse"))) 458 (eq_attr "type" "sse")))
459 "hsw_decodern,hsw_p01") 459 "hsw_decodern,hsw_p01")
460 460
461 (define_insn_reservation "hsw_sse_addcmp" 3 461 (define_insn_reservation "hsw_sse_addcmp" 3
462 (and (eq_attr "cpu" "haswell") 462 (and (eq_attr "cpu" "generic,haswell")
463 (and (eq_attr "memory" "none") 463 (and (eq_attr "memory" "none")
464 (eq_attr "type" "sseadd1,ssecmp,ssecomi"))) 464 (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
465 "hsw_decodern,hsw_p01") 465 "hsw_decodern,hsw_p01")
466 466
467 (define_insn_reservation "hsw_sse_addcmp_load" 3 467 (define_insn_reservation "hsw_sse_addcmp_load" 3
468 (and (eq_attr "cpu" "haswell") 468 (and (eq_attr "cpu" "generic,haswell")
469 (and (eq_attr "memory" "load") 469 (and (eq_attr "memory" "load")
470 (eq_attr "type" "sseadd1,ssecmp,ssecomi"))) 470 (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
471 "hsw_decodern,hsw_p23+hsw_p01") 471 "hsw_decodern,hsw_p23+hsw_p01")
472 472
473 (define_insn_reservation "hsw_sse_logic" 1 473 (define_insn_reservation "hsw_sse_logic" 1
474 (and (eq_attr "cpu" "haswell") 474 (and (eq_attr "cpu" "generic,haswell")
475 (and (eq_attr "memory" "none") 475 (and (eq_attr "memory" "none")
476 (eq_attr "type" "sselog,sselog1"))) 476 (eq_attr "type" "sselog,sselog1")))
477 "hsw_decodern,hsw_p015") 477 "hsw_decodern,hsw_p015")
478 478
479 (define_insn_reservation "hsw_sse_logic_load" 2 479 (define_insn_reservation "hsw_sse_logic_load" 2
480 (and (eq_attr "cpu" "haswell") 480 (and (eq_attr "cpu" "generic,haswell")
481 (and (eq_attr "memory" "load") 481 (and (eq_attr "memory" "load")
482 (eq_attr "type" "sselog,sselog1"))) 482 (eq_attr "type" "sselog,sselog1")))
483 "hsw_decodern,hsw_p015+hsw_p23") 483 "hsw_decodern,hsw_p015+hsw_p23")
484 484
485 (define_insn_reservation "hsw_sse_add" 3 485 (define_insn_reservation "hsw_sse_add" 3
486 (and (eq_attr "cpu" "haswell") 486 (and (eq_attr "cpu" "generic,haswell")
487 (and (eq_attr "memory" "none") 487 (and (eq_attr "memory" "none")
488 (eq_attr "type" "sseadd"))) 488 (eq_attr "type" "sseadd")))
489 "hsw_decodern,hsw_p1|hsw_p5") 489 "hsw_decodern,hsw_p1|hsw_p5")
490 490
491 (define_insn_reservation "hsw_sse_add_load" 3 491 (define_insn_reservation "hsw_sse_add_load" 3
492 (and (eq_attr "cpu" "haswell") 492 (and (eq_attr "cpu" "generic,haswell")
493 (and (eq_attr "memory" "load") 493 (and (eq_attr "memory" "load")
494 (eq_attr "type" "sseadd"))) 494 (eq_attr "type" "sseadd")))
495 "hsw_decodern,(hsw_p1|hsw_p5)+hsw_p23") 495 "hsw_decodern,(hsw_p1|hsw_p5)+hsw_p23")
496 496
497 (define_insn_reservation "hsw_sse_mul" 5 497 (define_insn_reservation "hsw_sse_mul" 5
498 (and (eq_attr "cpu" "haswell") 498 (and (eq_attr "cpu" "generic,haswell")
499 (and (eq_attr "memory" "none") 499 (and (eq_attr "memory" "none")
500 (eq_attr "type" "ssemul"))) 500 (eq_attr "type" "ssemul")))
501 "hsw_decodern,hsw_p0") 501 "hsw_decodern,hsw_p0")
502 502
503 (define_insn_reservation "hsw_sse_mul_load" 5 503 (define_insn_reservation "hsw_sse_mul_load" 5
504 (and (eq_attr "cpu" "haswell") 504 (and (eq_attr "cpu" "generic,haswell")
505 (and (eq_attr "memory" "load") 505 (and (eq_attr "memory" "load")
506 (eq_attr "type" "ssemul"))) 506 (eq_attr "type" "ssemul")))
507 "hsw_decodern,hsw_p0+hsw_p23") 507 "hsw_decodern,hsw_p0+hsw_p23")
508 ;; Use skylake pipeline. 508 ;; Use skylake pipeline.
509 (define_insn_reservation "hsw_sse_muladd" 5 509 (define_insn_reservation "hsw_sse_muladd" 5
510 (and (eq_attr "cpu" "haswell") 510 (and (eq_attr "cpu" "generic,haswell")
511 (and (eq_attr "memory" "none") 511 (and (eq_attr "memory" "none")
512 (eq_attr "type" "ssemuladd"))) 512 (eq_attr "type" "ssemuladd")))
513 "hsw_decodern,hsw_p01") 513 "hsw_decodern,hsw_p01")
514 514
515 (define_insn_reservation "hsw_sse_muladd_load" 5 515 (define_insn_reservation "hsw_sse_muladd_load" 5
516 (and (eq_attr "cpu" "haswell") 516 (and (eq_attr "cpu" "generic,haswell")
517 (and (eq_attr "memory" "load") 517 (and (eq_attr "memory" "load")
518 (eq_attr "type" "ssemuladd"))) 518 (eq_attr "type" "ssemuladd")))
519 "hsw_decodern,hsw_p01+hsw_p23") 519 "hsw_decodern,hsw_p01+hsw_p23")
520 520
521 (define_insn_reservation "hsw_sse_div_SF" 18 521 (define_insn_reservation "hsw_sse_div_SF" 18
522 (and (eq_attr "cpu" "haswell") 522 (and (eq_attr "cpu" "generic,haswell")
523 (and (eq_attr "memory" "none") 523 (and (eq_attr "memory" "none")
524 (and (eq_attr "mode" "SF,V4SF,V8SF") 524 (and (eq_attr "mode" "SF,V4SF,V8SF")
525 (eq_attr "type" "ssediv")))) 525 (eq_attr "type" "ssediv"))))
526 "hsw_decodern,hsw_p0,hsw_ssediv*14") 526 "hsw_decodern,hsw_p0,hsw_ssediv*14")
527 527
528 (define_insn_reservation "hsw_sse_div_SF_load" 18 528 (define_insn_reservation "hsw_sse_div_SF_load" 18
529 (and (eq_attr "cpu" "haswell") 529 (and (eq_attr "cpu" "generic,haswell")
530 (and (eq_attr "memory" "none") 530 (and (eq_attr "memory" "none")
531 (and (eq_attr "mode" "SF,V4SF,V8SF") 531 (and (eq_attr "mode" "SF,V4SF,V8SF")
532 (eq_attr "type" "ssediv")))) 532 (eq_attr "type" "ssediv"))))
533 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*14") 533 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*14")
534 534
535 (define_insn_reservation "hsw_sse_div_DF" 28 535 (define_insn_reservation "hsw_sse_div_DF" 28
536 (and (eq_attr "cpu" "haswell") 536 (and (eq_attr "cpu" "generic,haswell")
537 (and (eq_attr "memory" "none") 537 (and (eq_attr "memory" "none")
538 (and (eq_attr "mode" "DF,V2DF,V4DF") 538 (and (eq_attr "mode" "DF,V2DF,V4DF")
539 (eq_attr "type" "ssediv")))) 539 (eq_attr "type" "ssediv"))))
540 "hsw_decodern,hsw_p0,hsw_ssediv*20") 540 "hsw_decodern,hsw_p0,hsw_ssediv*20")
541 541
542 (define_insn_reservation "hsw_sse_div_DF_load" 28 542 (define_insn_reservation "hsw_sse_div_DF_load" 28
543 (and (eq_attr "cpu" "haswell") 543 (and (eq_attr "cpu" "generic,haswell")
544 (and (eq_attr "memory" "none") 544 (and (eq_attr "memory" "none")
545 (and (eq_attr "mode" "DF,V2DF,V4DF") 545 (and (eq_attr "mode" "DF,V2DF,V4DF")
546 (eq_attr "type" "ssediv")))) 546 (eq_attr "type" "ssediv"))))
547 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*20") 547 "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*20")
548 548
549 (define_insn_reservation "hsw_sse_icvt" 4 549 (define_insn_reservation "hsw_sse_icvt" 4
550 (and (eq_attr "cpu" "haswell") 550 (and (eq_attr "cpu" "generic,haswell")
551 (and (eq_attr "memory" "none") 551 (and (eq_attr "memory" "none")
552 (eq_attr "type" "sseicvt"))) 552 (eq_attr "type" "sseicvt")))
553 "hsw_decodern,hsw_p1") 553 "hsw_decodern,hsw_p1")
554 554
555 (define_insn_reservation "hsw_sse_icvt_load" 4 555 (define_insn_reservation "hsw_sse_icvt_load" 4
556 (and (eq_attr "cpu" "haswell") 556 (and (eq_attr "cpu" "generic,haswell")
557 (and (eq_attr "memory" "!none") 557 (and (eq_attr "memory" "!none")
558 (eq_attr "type" "sseicvt"))) 558 (eq_attr "type" "sseicvt")))
559 "hsw_decodern,hsw_p23+hsw_p1") 559 "hsw_decodern,hsw_p23+hsw_p1")
560 560
561 561
562 (define_insn_reservation "hsw_sse_icvt_SI" 3 562 (define_insn_reservation "hsw_sse_icvt_SI" 3
563 (and (eq_attr "cpu" "haswell") 563 (and (eq_attr "cpu" "generic,haswell")
564 (and (eq_attr "memory" "none") 564 (and (eq_attr "memory" "none")
565 (and (eq_attr "mode" "SI") 565 (and (eq_attr "mode" "SI")
566 (eq_attr "type" "sseicvt")))) 566 (eq_attr "type" "sseicvt"))))
567 "hsw_decodern,hsw_p1") 567 "hsw_decodern,hsw_p1")
568 568
569 (define_insn_reservation "hsw_sse_icvt_SI_load" 3 569 (define_insn_reservation "hsw_sse_icvt_SI_load" 3
570 (and (eq_attr "cpu" "haswell") 570 (and (eq_attr "cpu" "generic,haswell")
571 (and (eq_attr "memory" "!none") 571 (and (eq_attr "memory" "!none")
572 (and (eq_attr "mode" "SI") 572 (and (eq_attr "mode" "SI")
573 (eq_attr "type" "sseicvt")))) 573 (eq_attr "type" "sseicvt"))))
574 "hsw_decodern,hsw_p23+hsw_p1") 574 "hsw_decodern,hsw_p23+hsw_p1")
575 575
576 (define_insn_reservation "hsw_sse_mov" 1 576 (define_insn_reservation "hsw_sse_mov" 1
577 (and (eq_attr "cpu" "haswell") 577 (and (eq_attr "cpu" "generic,haswell")
578 (and (eq_attr "memory" "none") 578 (and (eq_attr "memory" "none")
579 (eq_attr "type" "ssemov"))) 579 (eq_attr "type" "ssemov")))
580 "hsw_decodern,hsw_p015") 580 "hsw_decodern,hsw_p015")
581 581
582 (define_insn_reservation "hsw_sse_mov_load" 2 582 (define_insn_reservation "hsw_sse_mov_load" 2
583 (and (eq_attr "cpu" "haswell") 583 (and (eq_attr "cpu" "generic,haswell")
584 (and (eq_attr "memory" "load") 584 (and (eq_attr "memory" "load")
585 (eq_attr "type" "ssemov"))) 585 (eq_attr "type" "ssemov")))
586 "hsw_decodern,hsw_p23") 586 "hsw_decodern,hsw_p23")
587 587
588 (define_insn_reservation "hsw_sse_mov_store" 1 588 (define_insn_reservation "hsw_sse_mov_store" 1
589 (and (eq_attr "cpu" "haswell") 589 (and (eq_attr "cpu" "generic,haswell")
590 (and (eq_attr "memory" "store") 590 (and (eq_attr "memory" "store")
591 (eq_attr "type" "ssemov"))) 591 (eq_attr "type" "ssemov")))
592 "hsw_decodern,hsw_p4p7") 592 "hsw_decodern,hsw_p4p7")
593 593
594 (define_insn_reservation "hsw_insn" 1 594 (define_insn_reservation "hsw_insn" 1
595 (and (eq_attr "cpu" "haswell") 595 (and (eq_attr "cpu" "generic,haswell")
596 (and (eq_attr "memory" "none,unknown") 596 (and (eq_attr "memory" "none,unknown")
597 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp"))) 597 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
598 "hsw_decodern,hsw_p0156") 598 "hsw_decodern,hsw_p0156")
599 599
600 (define_insn_reservation "hsw_insn_load" 1 600 (define_insn_reservation "hsw_insn_load" 1
601 (and (eq_attr "cpu" "haswell") 601 (and (eq_attr "cpu" "generic,haswell")
602 (and (eq_attr "memory" "load") 602 (and (eq_attr "memory" "load")
603 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp"))) 603 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
604 "hsw_decodern,hsw_p23+hsw_p0156") 604 "hsw_decodern,hsw_p23+hsw_p0156")
605 605
606 (define_insn_reservation "hsw_insn_store" 1 606 (define_insn_reservation "hsw_insn_store" 1
607 (and (eq_attr "cpu" "haswell") 607 (and (eq_attr "cpu" "generic,haswell")
608 (and (eq_attr "memory" "store") 608 (and (eq_attr "memory" "store")
609 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp"))) 609 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
610 "hsw_decodern,hsw_p0156+hsw_p4p7") 610 "hsw_decodern,hsw_p0156+hsw_p4p7")
611 611
612 ;; read-modify-store instructions produce 4 uops so they have to be 612 ;; read-modify-store instructions produce 4 uops so they have to be
613 ;; decoded on hsw_decoder0 as well. 613 ;; decoded on hsw_decoder0 as well.
614 (define_insn_reservation "hsw_insn_both" 4 614 (define_insn_reservation "hsw_insn_both" 4
615 (and (eq_attr "cpu" "haswell") 615 (and (eq_attr "cpu" "generic,haswell")
616 (and (eq_attr "memory" "both") 616 (and (eq_attr "memory" "both")
617 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp"))) 617 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
618 "hsw_decodern,hsw_p23+hsw_p0156+hsw_p4p7") 618 "hsw_decodern,hsw_p23+hsw_p0156+hsw_p4p7")