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comparison gcc/config/i386/i386.h @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 /* Definitions of target machine for GCC for IA-32. 1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc. 2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
3 3
4 This file is part of GCC. 4 This file is part of GCC.
5 5
6 GCC is free software; you can redistribute it and/or modify 6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
83 #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 83 #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x)
84 #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS 84 #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS
85 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) 85 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x)
86 #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW 86 #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW
87 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) 87 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x)
88 #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2
89 #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x)
88 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ 90 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ
89 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) 91 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x)
92 #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI
93 #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x)
94 #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG
95 #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x)
90 #define TARGET_FMA TARGET_ISA_FMA 96 #define TARGET_FMA TARGET_ISA_FMA
91 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 97 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
92 #define TARGET_SSE4A TARGET_ISA_SSE4A 98 #define TARGET_SSE4A TARGET_ISA_SSE4A
93 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 99 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x)
94 #define TARGET_FMA4 TARGET_ISA_FMA4 100 #define TARGET_FMA4 TARGET_ISA_FMA4
97 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 103 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x)
98 #define TARGET_LWP TARGET_ISA_LWP 104 #define TARGET_LWP TARGET_ISA_LWP
99 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 105 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x)
100 #define TARGET_ABM TARGET_ISA_ABM 106 #define TARGET_ABM TARGET_ISA_ABM
101 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 107 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
108 #define TARGET_PCONFIG TARGET_ISA_PCONFIG
109 #define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x)
110 #define TARGET_WBNOINVD TARGET_ISA_WBNOINVD
111 #define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x)
102 #define TARGET_SGX TARGET_ISA_SGX 112 #define TARGET_SGX TARGET_ISA_SGX
103 #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) 113 #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x)
104 #define TARGET_RDPID TARGET_ISA_RDPID 114 #define TARGET_RDPID TARGET_ISA_RDPID
105 #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) 115 #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x)
106 #define TARGET_GFNI TARGET_ISA_GFNI 116 #define TARGET_GFNI TARGET_ISA_GFNI
107 #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) 117 #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x)
118 #define TARGET_VAES TARGET_ISA_VAES
119 #define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x)
120 #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ
121 #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x)
108 #define TARGET_BMI TARGET_ISA_BMI 122 #define TARGET_BMI TARGET_ISA_BMI
109 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 123 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
110 #define TARGET_BMI2 TARGET_ISA_BMI2 124 #define TARGET_BMI2 TARGET_ISA_BMI2
111 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 125 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x)
112 #define TARGET_LZCNT TARGET_ISA_LZCNT 126 #define TARGET_LZCNT TARGET_ISA_LZCNT
159 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 173 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
160 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 174 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
161 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 175 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
162 #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 176 #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1
163 #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 177 #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x)
164 #define TARGET_MPX TARGET_ISA_MPX
165 #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x)
166 #define TARGET_CLWB TARGET_ISA_CLWB 178 #define TARGET_CLWB TARGET_ISA_CLWB
167 #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 179 #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x)
168 #define TARGET_MWAITX TARGET_ISA_MWAITX 180 #define TARGET_MWAITX TARGET_ISA_MWAITX
169 #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) 181 #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x)
170 #define TARGET_PKU TARGET_ISA_PKU 182 #define TARGET_PKU TARGET_ISA_PKU
171 #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) 183 #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x)
172 #define TARGET_IBT TARGET_ISA_IBT
173 #define TARGET_IBT_P(x) TARGET_ISA_IBT_P(x)
174 #define TARGET_SHSTK TARGET_ISA_SHSTK 184 #define TARGET_SHSTK TARGET_ISA_SHSTK
175 #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) 185 #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x)
186 #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI
187 #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x)
188 #define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B
189 #define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x)
190 #define TARGET_WAITPKG TARGET_ISA_WAITPKG
191 #define TARGET_WAITPKG_P(x) TARGET_ISA_WAITPKG_P(x)
192 #define TARGET_CLDEMOTE TARGET_ISA_CLDEMOTE
193 #define TARGET_CLDEMOTE_P(x) TARGET_ISA_CLDEMOTE_P(x)
176 194
177 #define TARGET_LP64 TARGET_ABI_64 195 #define TARGET_LP64 TARGET_ABI_64
178 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 196 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
179 #define TARGET_X32 TARGET_ABI_X32 197 #define TARGET_X32 TARGET_ABI_X32
180 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 198 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
291 struct stringop_algs *memcpy, *memset; 309 struct stringop_algs *memcpy, *memset;
292 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 310 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
293 cost model. */ 311 cost model. */
294 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 312 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
295 vectorizer cost model. */ 313 vectorizer cost model. */
314
315 /* The "0:0:8" label alignment specified for some processors generates
316 secondary 8-byte alignment only for those label/jump/loop targets
317 which have primary alignment. */
318 const char *const align_loop; /* Loop alignment. */
319 const char *const align_jump; /* Jump alignment. */
320 const char *const align_label; /* Label alignment. */
321 const char *const align_func; /* Function alignment. */
296 }; 322 };
297 323
298 extern const struct processor_costs *ix86_cost; 324 extern const struct processor_costs *ix86_cost;
299 extern const struct processor_costs ix86_size_cost; 325 extern const struct processor_costs ix86_size_cost;
300 326
367 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 393 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
368 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 394 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
369 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 395 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
370 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 396 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
371 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 397 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
398 #define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT)
399 #define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS)
400 #define TARGET_TREMONT (ix86_tune == PROCESSOR_TREMONT)
372 #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 401 #define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
373 #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) 402 #define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
403 #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE)
374 #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) 404 #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
405 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
406 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
407 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
375 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 408 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
376 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 409 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
377 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 410 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
378 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 411 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
379 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 412 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
485 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 518 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
486 #define TARGET_SLOW_PSHUFB \ 519 #define TARGET_SLOW_PSHUFB \
487 ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 520 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
488 #define TARGET_AVOID_4BYTE_PREFIXES \ 521 #define TARGET_AVOID_4BYTE_PREFIXES \
489 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 522 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
523 #define TARGET_USE_GATHER \
524 ix86_tune_features[X86_TUNE_USE_GATHER]
490 #define TARGET_FUSE_CMP_AND_BRANCH_32 \ 525 #define TARGET_FUSE_CMP_AND_BRANCH_32 \
491 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 526 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
492 #define TARGET_FUSE_CMP_AND_BRANCH_64 \ 527 #define TARGET_FUSE_CMP_AND_BRANCH_64 \
493 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 528 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
494 #define TARGET_FUSE_CMP_AND_BRANCH \ 529 #define TARGET_FUSE_CMP_AND_BRANCH \
515 ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 550 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
516 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 551 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \
517 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 552 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
518 #define TARGET_ONE_IF_CONV_INSN \ 553 #define TARGET_ONE_IF_CONV_INSN \
519 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] 554 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
555 #define TARGET_EMIT_VZEROUPPER \
556 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
520 557
521 /* Feature tests against the various architecture variations. */ 558 /* Feature tests against the various architecture variations. */
522 enum ix86_arch_indices { 559 enum ix86_arch_indices {
523 X86_ARCH_CMOV, 560 X86_ARCH_CMOV,
524 X86_ARCH_CMPXCHG, 561 X86_ARCH_CMPXCHG,
987 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1024 TARGET_CONDITIONAL_REGISTER_USAGE. */
988 1025
989 #define FIXED_REGISTERS \ 1026 #define FIXED_REGISTERS \
990 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1027 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
991 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 1028 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
992 /*arg,flags,fpsr,fpcr,frame*/ \ 1029 /*arg,flags,fpsr,frame*/ \
993 1, 1, 1, 1, 1, \ 1030 1, 1, 1, 1, \
994 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1031 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
995 0, 0, 0, 0, 0, 0, 0, 0, \ 1032 0, 0, 0, 0, 0, 0, 0, 0, \
996 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1033 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
997 0, 0, 0, 0, 0, 0, 0, 0, \ 1034 0, 0, 0, 0, 0, 0, 0, 0, \
998 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1035 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1002 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1039 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1003 0, 0, 0, 0, 0, 0, 0, 0, \ 1040 0, 0, 0, 0, 0, 0, 0, 0, \
1004 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1041 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1005 0, 0, 0, 0, 0, 0, 0, 0, \ 1042 0, 0, 0, 0, 0, 0, 0, 0, \
1006 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1043 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1007 0, 0, 0, 0, 0, 0, 0, 0, \ 1044 0, 0, 0, 0, 0, 0, 0, 0 }
1008 /* b0, b1, b2, b3*/ \
1009 0, 0, 0, 0 }
1010 1045
1011 /* 1 for registers not available across function calls. 1046 /* 1 for registers not available across function calls.
1012 These must include the FIXED_REGISTERS and also any 1047 These must include the FIXED_REGISTERS and also any
1013 registers that can be used without being saved. 1048 registers that can be used without being saved.
1014 The latter must include the registers where values are returned 1049 The latter must include the registers where values are returned
1026 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) 1061 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
1027 1062
1028 #define CALL_USED_REGISTERS \ 1063 #define CALL_USED_REGISTERS \
1029 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1064 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1030 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1065 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1031 /*arg,flags,fpsr,fpcr,frame*/ \ 1066 /*arg,flags,fpsr,frame*/ \
1032 1, 1, 1, 1, 1, \ 1067 1, 1, 1, 1, \
1033 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1068 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1034 1, 1, 1, 1, 1, 1, 6, 6, \ 1069 1, 1, 1, 1, 1, 1, 6, 6, \
1035 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1070 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1036 1, 1, 1, 1, 1, 1, 1, 1, \ 1071 1, 1, 1, 1, 1, 1, 1, 1, \
1037 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1072 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1041 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1076 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1042 6, 6, 6, 6, 6, 6, 6, 6, \ 1077 6, 6, 6, 6, 6, 6, 6, 6, \
1043 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1078 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1044 6, 6, 6, 6, 6, 6, 6, 6, \ 1079 6, 6, 6, 6, 6, 6, 6, 6, \
1045 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1080 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1046 1, 1, 1, 1, 1, 1, 1, 1, \ 1081 1, 1, 1, 1, 1, 1, 1, 1 }
1047 /* b0, b1, b2, b3*/ \
1048 1, 1, 1, 1 }
1049 1082
1050 /* Order in which to allocate registers. Each register must be 1083 /* Order in which to allocate registers. Each register must be
1051 listed once, even those in FIXED_REGISTERS. List frame pointer 1084 listed once, even those in FIXED_REGISTERS. List frame pointer
1052 late and fixed registers last. Note that, in general, we prefer 1085 late and fixed registers last. Note that, in general, we prefer
1053 registers listed in CALL_USED_REGISTERS, keeping the others 1086 registers listed in CALL_USED_REGISTERS, keeping the others
1054 available for storage of persistent values. 1087 available for storage of persistent values.
1055 1088
1056 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 1089 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1057 so this is just empty initializer for array. */ 1090 so this is just empty initializer for array. */
1058 1091
1059 #define REG_ALLOC_ORDER \ 1092 #define REG_ALLOC_ORDER \
1060 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 1093 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1061 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1094 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1062 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1095 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1063 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 1096 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1064 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 1097 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
1065 78, 79, 80 }
1066 1098
1067 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 1099 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1068 to be rearranged based on a particular function. When using sse math, 1100 to be rearranged based on a particular function. When using sse math,
1069 we want to allocate SSE before x87 registers and vice versa. */ 1101 we want to allocate SSE before x87 registers and vice versa. */
1070 1102
1095 #define VALID_AVX512F_REG_MODE(MODE) \ 1127 #define VALID_AVX512F_REG_MODE(MODE) \
1096 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 1128 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1097 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 1129 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1098 || (MODE) == V4TImode) 1130 || (MODE) == V4TImode)
1099 1131
1132 #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1133 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1134
1100 #define VALID_AVX512VL_128_REG_MODE(MODE) \ 1135 #define VALID_AVX512VL_128_REG_MODE(MODE) \
1101 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 1136 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1102 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ 1137 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1103 || (MODE) == TFmode || (MODE) == V1TImode) 1138 || (MODE) == TFmode || (MODE) == V1TImode)
1104 1139
1120 || (MODE) == V4HImode || (MODE) == V8QImode) 1155 || (MODE) == V4HImode || (MODE) == V8QImode)
1121 1156
1122 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 1157 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1123 1158
1124 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 1159 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1125
1126 #define VALID_BND_REG_MODE(MODE) \
1127 (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)
1128 1160
1129 #define VALID_DFP_MODE_P(MODE) \ 1161 #define VALID_DFP_MODE_P(MODE) \
1130 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1162 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1131 1163
1132 #define VALID_FP_MODE_P(MODE) \ 1164 #define VALID_FP_MODE_P(MODE) \
1225 #define LAST_EXT_REX_SSE_REG XMM31_REG 1257 #define LAST_EXT_REX_SSE_REG XMM31_REG
1226 1258
1227 #define FIRST_MASK_REG MASK0_REG 1259 #define FIRST_MASK_REG MASK0_REG
1228 #define LAST_MASK_REG MASK7_REG 1260 #define LAST_MASK_REG MASK7_REG
1229 1261
1230 #define FIRST_BND_REG BND0_REG
1231 #define LAST_BND_REG BND3_REG
1232
1233 /* Override this in other tm.h files to cope with various OS lossage 1262 /* Override this in other tm.h files to cope with various OS lossage
1234 requiring a frame pointer. */ 1263 requiring a frame pointer. */
1235 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1264 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1236 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1265 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1237 #endif 1266 #endif
1284 registers than just %eax, %ecx, %edx. 1313 registers than just %eax, %ecx, %edx.
1285 1314
1286 For any two classes, it is very desirable that there be another 1315 For any two classes, it is very desirable that there be another
1287 class that represents their union. 1316 class that represents their union.
1288 1317
1289 It might seem that class BREG is unnecessary, since no useful 386 1318 The flags and fpsr registers are in no class. */
1290 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1291 and the "b" register constraint is useful in asms for syscalls.
1292
1293 The flags, fpsr and fpcr registers are in no class. */
1294 1319
1295 enum reg_class 1320 enum reg_class
1296 { 1321 {
1297 NO_REGS, 1322 NO_REGS,
1298 AREG, DREG, CREG, BREG, SIREG, DIREG, 1323 AREG, DREG, CREG, BREG, SIREG, DIREG,
1308 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1333 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1309 FLOAT_REGS, 1334 FLOAT_REGS,
1310 SSE_FIRST_REG, 1335 SSE_FIRST_REG,
1311 NO_REX_SSE_REGS, 1336 NO_REX_SSE_REGS,
1312 SSE_REGS, 1337 SSE_REGS,
1313 EVEX_SSE_REGS,
1314 BND_REGS,
1315 ALL_SSE_REGS, 1338 ALL_SSE_REGS,
1316 MMX_REGS, 1339 MMX_REGS,
1317 FP_TOP_SSE_REGS,
1318 FP_SECOND_SSE_REGS,
1319 FLOAT_SSE_REGS, 1340 FLOAT_SSE_REGS,
1320 FLOAT_INT_REGS, 1341 FLOAT_INT_REGS,
1321 INT_SSE_REGS, 1342 INT_SSE_REGS,
1322 FLOAT_INT_SSE_REGS, 1343 FLOAT_INT_SSE_REGS,
1323 MASK_EVEX_REGS,
1324 MASK_REGS, 1344 MASK_REGS,
1325 MOD4_SSE_REGS, 1345 ALL_MASK_REGS,
1326 ALL_REGS, LIM_REG_CLASSES 1346 ALL_REGS,
1347 LIM_REG_CLASSES
1327 }; 1348 };
1328 1349
1329 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1350 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1330 1351
1331 #define INTEGER_CLASS_P(CLASS) \ 1352 #define INTEGER_CLASS_P(CLASS) \
1335 #define SSE_CLASS_P(CLASS) \ 1356 #define SSE_CLASS_P(CLASS) \
1336 reg_class_subset_p ((CLASS), ALL_SSE_REGS) 1357 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1337 #define MMX_CLASS_P(CLASS) \ 1358 #define MMX_CLASS_P(CLASS) \
1338 ((CLASS) == MMX_REGS) 1359 ((CLASS) == MMX_REGS)
1339 #define MASK_CLASS_P(CLASS) \ 1360 #define MASK_CLASS_P(CLASS) \
1340 reg_class_subset_p ((CLASS), MASK_REGS) 1361 reg_class_subset_p ((CLASS), ALL_MASK_REGS)
1341 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1362 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1342 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1363 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1343 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1364 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1344 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1365 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1345 #define MAYBE_SSE_CLASS_P(CLASS) \ 1366 #define MAYBE_SSE_CLASS_P(CLASS) \
1346 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 1367 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1347 #define MAYBE_MMX_CLASS_P(CLASS) \ 1368 #define MAYBE_MMX_CLASS_P(CLASS) \
1348 reg_classes_intersect_p ((CLASS), MMX_REGS) 1369 reg_classes_intersect_p ((CLASS), MMX_REGS)
1349 #define MAYBE_MASK_CLASS_P(CLASS) \ 1370 #define MAYBE_MASK_CLASS_P(CLASS) \
1350 reg_classes_intersect_p ((CLASS), MASK_REGS) 1371 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
1351 1372
1352 #define Q_CLASS_P(CLASS) \ 1373 #define Q_CLASS_P(CLASS) \
1353 reg_class_subset_p ((CLASS), Q_REGS) 1374 reg_class_subset_p ((CLASS), Q_REGS)
1354 1375
1355 #define MAYBE_NON_Q_CLASS_P(CLASS) \ 1376 #define MAYBE_NON_Q_CLASS_P(CLASS) \
1371 "FP_TOP_REG", "FP_SECOND_REG", \ 1392 "FP_TOP_REG", "FP_SECOND_REG", \
1372 "FLOAT_REGS", \ 1393 "FLOAT_REGS", \
1373 "SSE_FIRST_REG", \ 1394 "SSE_FIRST_REG", \
1374 "NO_REX_SSE_REGS", \ 1395 "NO_REX_SSE_REGS", \
1375 "SSE_REGS", \ 1396 "SSE_REGS", \
1376 "EVEX_SSE_REGS", \
1377 "BND_REGS", \
1378 "ALL_SSE_REGS", \ 1397 "ALL_SSE_REGS", \
1379 "MMX_REGS", \ 1398 "MMX_REGS", \
1380 "FP_TOP_SSE_REGS", \
1381 "FP_SECOND_SSE_REGS", \
1382 "FLOAT_SSE_REGS", \ 1399 "FLOAT_SSE_REGS", \
1383 "FLOAT_INT_REGS", \ 1400 "FLOAT_INT_REGS", \
1384 "INT_SSE_REGS", \ 1401 "INT_SSE_REGS", \
1385 "FLOAT_INT_SSE_REGS", \ 1402 "FLOAT_INT_SSE_REGS", \
1386 "MASK_EVEX_REGS", \
1387 "MASK_REGS", \ 1403 "MASK_REGS", \
1388 "MOD4_SSE_REGS", \ 1404 "ALL_MASK_REGS", \
1389 "ALL_REGS" } 1405 "ALL_REGS" }
1390 1406
1391 /* Define which registers fit in which classes. This is an initializer 1407 /* Define which registers fit in which classes. This is an initializer
1392 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1408 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1393 1409
1394 Note that CLOBBERED_REGS are calculated by 1410 Note that CLOBBERED_REGS are calculated by
1395 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1411 TARGET_CONDITIONAL_REGISTER_USAGE. */
1396 1412
1397 #define REG_CLASS_CONTENTS \ 1413 #define REG_CLASS_CONTENTS \
1398 { { 0x00, 0x0, 0x0 }, \ 1414 { { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
1399 { 0x01, 0x0, 0x0 }, /* AREG */ \ 1415 { 0x01, 0x0, 0x0 }, /* AREG */ \
1400 { 0x02, 0x0, 0x0 }, /* DREG */ \ 1416 { 0x02, 0x0, 0x0 }, /* DREG */ \
1401 { 0x04, 0x0, 0x0 }, /* CREG */ \ 1417 { 0x04, 0x0, 0x0 }, /* CREG */ \
1402 { 0x08, 0x0, 0x0 }, /* BREG */ \ 1418 { 0x08, 0x0, 0x0 }, /* BREG */ \
1403 { 0x10, 0x0, 0x0 }, /* SIREG */ \ 1419 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1404 { 0x20, 0x0, 0x0 }, /* DIREG */ \ 1420 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1405 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 1421 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1406 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 1422 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1407 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 1423 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1408 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ 1424 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
1409 { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \ 1425 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1410 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ 1426 { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
1411 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 1427 { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1412 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ 1428 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \
1413 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 1429 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1414 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 1430 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1415 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 1431 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1416 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 1432 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1417 { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ 1433 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
1418 { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ 1434 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
1419 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ 1435 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
1420 { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ 1436 { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
1421 { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ 1437 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
1422 { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ 1438 { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \
1423 { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ 1439 { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \
1424 { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ 1440 { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \
1425 { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ 1441 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
1426 { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ 1442 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
1427 { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ 1443 { 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \
1428 { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
1429 { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
1430 { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
1431 { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \
1432 { 0xffffffff,0xffffffff,0x1ffff } \
1433 } 1444 }
1434 1445
1435 /* The same information, inverted: 1446 /* The same information, inverted:
1436 Return the class number of the smallest class containing 1447 Return the class number of the smallest class containing
1437 reg number REGNO. This could be a conditional expression 1448 reg number REGNO. This could be a conditional expression
1488 1499
1489 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1500 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1490 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1501 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1491 1502
1492 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1503 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1493 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1504 #define CC_REGNO_P(X) ((X) == FLAGS_REG)
1494
1495 #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X)))
1496 #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG)
1497 1505
1498 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) 1506 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1499 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ 1507 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1500 || (N) == XMM4_REG \ 1508 || (N) == XMM4_REG \
1501 || (N) == XMM8_REG \ 1509 || (N) == XMM8_REG \
1507 1515
1508 /* First floating point reg */ 1516 /* First floating point reg */
1509 #define FIRST_FLOAT_REG FIRST_STACK_REG 1517 #define FIRST_FLOAT_REG FIRST_STACK_REG
1510 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) 1518 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1511 1519
1512 #define SSE_REGNO(N) \ 1520 #define GET_SSE_REGNO(N) \
1513 ((N) < 8 ? FIRST_SSE_REG + (N) \ 1521 ((N) < 8 ? FIRST_SSE_REG + (N) \
1514 : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ 1522 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \
1515 : (FIRST_EXT_REX_SSE_REG + (N) - 16)) 1523 : FIRST_EXT_REX_SSE_REG + (N) - 16)
1516 1524
1517 /* The class value for index registers, and the one for base regs. */ 1525 /* The class value for index registers, and the one for base regs. */
1518 1526
1519 #define INDEX_REG_CLASS INDEX_REGS 1527 #define INDEX_REG_CLASS INDEX_REGS
1520 #define BASE_REG_CLASS GENERAL_REGS 1528 #define BASE_REG_CLASS GENERAL_REGS
1529 is at the high-address end of the local variables; 1537 is at the high-address end of the local variables;
1530 that is, each additional local variable allocated 1538 that is, each additional local variable allocated
1531 goes at a more negative offset in the frame. */ 1539 goes at a more negative offset in the frame. */
1532 #define FRAME_GROWS_DOWNWARD 1 1540 #define FRAME_GROWS_DOWNWARD 1
1533 1541
1534 /* If we generate an insn to push BYTES bytes, this says how many the stack 1542 #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES)
1535 pointer really advances by. On 386, we have pushw instruction that
1536 decrements by exactly 2 no matter what the position was, there is no pushb.
1537
1538 But as CIE data alignment factor on this arch is -4 for 32bit targets
1539 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1540 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1541
1542 #define PUSH_ROUNDING(BYTES) ROUND_UP ((BYTES), UNITS_PER_WORD)
1543 1543
1544 /* If defined, the maximum amount of space required for outgoing arguments 1544 /* If defined, the maximum amount of space required for outgoing arguments
1545 will be computed and placed into the variable `crtl->outgoing_args_size'. 1545 will be computed and placed into the variable `crtl->outgoing_args_size'.
1546 No space will be pushed onto the stack for each call; instead, the 1546 No space will be pushed onto the stack for each call; instead, the
1547 function prologue should increase the stack frame size by this amount. 1547 function prologue should increase the stack frame size by this amount.
1631 int warn_avx512f; /* True when we want to warn 1631 int warn_avx512f; /* True when we want to warn
1632 about AVX512F ABI. */ 1632 about AVX512F ABI. */
1633 int warn_avx; /* True when we want to warn about AVX ABI. */ 1633 int warn_avx; /* True when we want to warn about AVX ABI. */
1634 int warn_sse; /* True when we want to warn about SSE ABI. */ 1634 int warn_sse; /* True when we want to warn about SSE ABI. */
1635 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1635 int warn_mmx; /* True when we want to warn about MMX ABI. */
1636 int warn_empty; /* True when we want to warn about empty classes
1637 passing ABI change. */
1636 int sse_regno; /* next available sse register number */ 1638 int sse_regno; /* next available sse register number */
1637 int mmx_words; /* # mmx words passed so far */ 1639 int mmx_words; /* # mmx words passed so far */
1638 int mmx_nregs; /* # mmx registers available for passing */ 1640 int mmx_nregs; /* # mmx registers available for passing */
1639 int mmx_regno; /* next available mmx register number */ 1641 int mmx_regno; /* next available mmx register number */
1640 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1642 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1641 int caller; /* true if it is caller. */ 1643 int caller; /* true if it is caller. */
1642 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1644 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1643 SFmode/DFmode arguments should be passed 1645 SFmode/DFmode arguments should be passed
1644 in SSE registers. Otherwise 0. */ 1646 in SSE registers. Otherwise 0. */
1645 int bnd_regno; /* next available bnd register number */
1646 int bnds_in_bt; /* number of bounds expected in BT. */
1647 int force_bnd_pass; /* number of bounds expected for stdarg arg. */
1648 int stdarg; /* Set to 1 if function is stdarg. */ 1647 int stdarg; /* Set to 1 if function is stdarg. */
1649 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1648 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1650 MS_ABI for ms abi. */ 1649 MS_ABI for ms abi. */
1651 tree decl; /* Callee decl. */ 1650 tree decl; /* Callee decl. */
1652 } CUMULATIVE_ARGS; 1651 } CUMULATIVE_ARGS;
1696 is the address of FUNCTION relative to the instruction following the 1695 is the address of FUNCTION relative to the instruction following the
1697 JMP (which is 5 bytes long). */ 1696 JMP (which is 5 bytes long). */
1698 1697
1699 /* Length in units of the trampoline for entering a nested function. */ 1698 /* Length in units of the trampoline for entering a nested function. */
1700 1699
1701 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1700 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14)
1702 1701
1703 /* Definitions for register eliminations. 1702 /* Definitions for register eliminations.
1704 1703
1705 This is an array of structures. Each structure initializes one pair 1704 This is an array of structures. Each structure initializes one pair
1706 of eliminable registers. The "from" register number is given first, 1705 of eliminable registers. The "from" register number is given first,
1923 /* Specify the machine mode that pointers have. 1922 /* Specify the machine mode that pointers have.
1924 After generation of rtl, the compiler makes no further distinction 1923 After generation of rtl, the compiler makes no further distinction
1925 between pointers and any other objects of this machine mode. */ 1924 between pointers and any other objects of this machine mode. */
1926 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1925 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1927 1926
1928 /* Specify the machine mode that bounds have. */ 1927 /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save.
1929 #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) 1928 NONLOCAL needs space to save both shadow stack and stack pointers.
1929
1930 FIXME: We only need to save and restore stack pointer in ptr_mode.
1931 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode
1932 to save and restore stack pointer. See
1933 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150
1934 */
1935 #define STACK_SAVEAREA_MODE(LEVEL) \
1936 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
1930 1937
1931 /* A C expression whose value is zero if pointers that need to be extended 1938 /* A C expression whose value is zero if pointers that need to be extended
1932 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1939 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1933 greater then zero if they are zero-extended and less then zero if the 1940 greater then zero if they are zero-extended and less then zero if the
1934 ptr_extend instruction should be used. */ 1941 ptr_extend instruction should be used. */
2013 "y" code. */ 2020 "y" code. */
2014 2021
2015 #define HI_REGISTER_NAMES \ 2022 #define HI_REGISTER_NAMES \
2016 {"ax","dx","cx","bx","si","di","bp","sp", \ 2023 {"ax","dx","cx","bx","si","di","bp","sp", \
2017 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2024 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2018 "argp", "flags", "fpsr", "fpcr", "frame", \ 2025 "argp", "flags", "fpsr", "frame", \
2019 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2026 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2020 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2027 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2021 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2028 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2022 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 2029 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
2023 "xmm16", "xmm17", "xmm18", "xmm19", \ 2030 "xmm16", "xmm17", "xmm18", "xmm19", \
2024 "xmm20", "xmm21", "xmm22", "xmm23", \ 2031 "xmm20", "xmm21", "xmm22", "xmm23", \
2025 "xmm24", "xmm25", "xmm26", "xmm27", \ 2032 "xmm24", "xmm25", "xmm26", "xmm27", \
2026 "xmm28", "xmm29", "xmm30", "xmm31", \ 2033 "xmm28", "xmm29", "xmm30", "xmm31", \
2027 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ 2034 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }
2028 "bnd0", "bnd1", "bnd2", "bnd3" }
2029 2035
2030 #define REGISTER_NAMES HI_REGISTER_NAMES 2036 #define REGISTER_NAMES HI_REGISTER_NAMES
2031 2037
2032 /* Table of additional register names to use in user input. */ 2038 /* Table of additional register names to use in user input. */
2033 2039
2034 #define ADDITIONAL_REGISTER_NAMES \ 2040 #define ADDITIONAL_REGISTER_NAMES \
2035 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2041 { \
2036 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2042 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
2037 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2043 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
2038 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2044 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
2039 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2045 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
2040 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2046 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
2041 { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ 2047 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
2042 { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ 2048 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
2043 { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ 2049 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
2044 { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ 2050 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
2045 { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ 2051 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
2046 { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ 2052 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
2047 { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ 2053 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
2048 { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ 2054 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
2049 { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ 2055 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
2050 { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ 2056 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
2051 { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ 2057 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
2052 { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ 2058 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
2053 { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ 2059 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
2054 { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ 2060 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
2055 { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ 2061 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
2056 { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } 2062 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
2063 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
2064 }
2057 2065
2058 /* Note we are omitting these since currently I don't know how 2066 /* Note we are omitting these since currently I don't know how
2059 to get gcc to use these, since they want the same but different 2067 to get gcc to use these, since they want the same but different
2060 number as al, and ax. 2068 number as al, and ax.
2061 */ 2069 */
2095 /* Before the prologue, there are return address and error code for 2103 /* Before the prologue, there are return address and error code for
2096 exception handler on the top of the frame. */ 2104 exception handler on the top of the frame. */
2097 #define INCOMING_FRAME_SP_OFFSET \ 2105 #define INCOMING_FRAME_SP_OFFSET \
2098 (cfun->machine->func_type == TYPE_EXCEPTION \ 2106 (cfun->machine->func_type == TYPE_EXCEPTION \
2099 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) 2107 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2108
2109 /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in
2110 .cfi_startproc. */
2111 #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2100 2112
2101 /* Describe how we implement __builtin_eh_return. */ 2113 /* Describe how we implement __builtin_eh_return. */
2102 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 2114 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2103 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 2115 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2104 2116
2176 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2188 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2177 #undef ASM_OUTPUT_MAX_SKIP_PAD 2189 #undef ASM_OUTPUT_MAX_SKIP_PAD
2178 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2190 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2179 if ((LOG) != 0) \ 2191 if ((LOG) != 0) \
2180 { \ 2192 { \
2181 if ((MAX_SKIP) == 0) \ 2193 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \
2182 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2194 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2183 else \ 2195 else \
2184 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2196 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2185 } 2197 }
2186 #endif 2198 #endif
2212 TEXT_SECTION_ASM_OP); 2224 TEXT_SECTION_ASM_OP);
2213 2225
2214 /* Default threshold for putting data in large sections 2226 /* Default threshold for putting data in large sections
2215 with x86-64 medium memory model */ 2227 with x86-64 medium memory model */
2216 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2228 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2217
2218 /* Adjust the length of the insn with the length of BND prefix. */
2219
2220 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2221 do { \
2222 if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \
2223 && get_attr_maybe_prefix_bnd (INSN)) \
2224 LENGTH += ix86_bnd_prefixed_insn_p (INSN); \
2225 } while (0)
2226 2229
2227 /* Which processor to tune code generation for. These must be in sync 2230 /* Which processor to tune code generation for. These must be in sync
2228 with processor_target_table in i386.c. */ 2231 with processor_target_table in i386.c. */
2229 2232
2230 enum processor_type 2233 enum processor_type
2241 PROCESSOR_NEHALEM, 2244 PROCESSOR_NEHALEM,
2242 PROCESSOR_SANDYBRIDGE, 2245 PROCESSOR_SANDYBRIDGE,
2243 PROCESSOR_HASWELL, 2246 PROCESSOR_HASWELL,
2244 PROCESSOR_BONNELL, 2247 PROCESSOR_BONNELL,
2245 PROCESSOR_SILVERMONT, 2248 PROCESSOR_SILVERMONT,
2249 PROCESSOR_GOLDMONT,
2250 PROCESSOR_GOLDMONT_PLUS,
2251 PROCESSOR_TREMONT,
2246 PROCESSOR_KNL, 2252 PROCESSOR_KNL,
2247 PROCESSOR_KNM, 2253 PROCESSOR_KNM,
2254 PROCESSOR_SKYLAKE,
2248 PROCESSOR_SKYLAKE_AVX512, 2255 PROCESSOR_SKYLAKE_AVX512,
2256 PROCESSOR_CANNONLAKE,
2257 PROCESSOR_ICELAKE_CLIENT,
2258 PROCESSOR_ICELAKE_SERVER,
2249 PROCESSOR_INTEL, 2259 PROCESSOR_INTEL,
2250 PROCESSOR_GEODE, 2260 PROCESSOR_GEODE,
2251 PROCESSOR_K6, 2261 PROCESSOR_K6,
2252 PROCESSOR_ATHLON, 2262 PROCESSOR_ATHLON,
2253 PROCESSOR_K8, 2263 PROCESSOR_K8,
2260 PROCESSOR_BTVER2, 2270 PROCESSOR_BTVER2,
2261 PROCESSOR_ZNVER1, 2271 PROCESSOR_ZNVER1,
2262 PROCESSOR_max 2272 PROCESSOR_max
2263 }; 2273 };
2264 2274
2275 #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
2276 extern const char *const processor_names[PROCESSOR_max];
2277
2278 #include "wide-int-bitmask.h"
2279
2280 const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
2281 const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
2282 const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
2283 const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
2284 const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
2285 const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
2286 const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
2287 const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
2288 const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
2289 const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
2290 const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
2291 const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
2292 const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
2293 const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
2294 const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
2295 const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
2296 const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
2297 const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
2298 const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
2299 const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
2300 const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
2301 const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
2302 const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
2303 const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
2304 const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
2305 const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
2306 const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
2307 const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
2308 const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
2309 const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
2310 const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
2311 const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
2312 const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
2313 const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
2314 const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
2315 const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
2316 const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
2317 const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
2318 const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
2319 const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
2320 const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
2321 const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
2322 const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
2323 const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
2324 /* Hole after PTA_MPX was removed. */
2325 const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
2326 const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
2327 const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
2328 const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
2329 const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
2330 const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
2331 const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
2332 const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
2333 const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
2334 const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
2335 const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
2336 const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
2337 const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
2338 const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
2339 const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
2340 const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
2341 const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
2342 const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
2343 const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
2344 const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
2345 const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
2346 const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
2347 const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
2348 const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
2349 const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
2350 const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
2351 const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
2352 const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
2353 const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
2354
2355 const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2356 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
2357 const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
2358 | PTA_POPCNT;
2359 const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
2360 const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
2361 | PTA_XSAVEOPT;
2362 const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
2363 | PTA_RDRND | PTA_F16C;
2364 const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
2365 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
2366 const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
2367 | PTA_RDSEED;
2368 const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
2369 | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
2370 const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
2371 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2372 | PTA_CLWB;
2373 const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
2374 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2375 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
2376 const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
2377 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
2378 | PTA_RDPID | PTA_CLWB;
2379 const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
2380 | PTA_WBNOINVD;
2381 const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
2382 | PTA_AVX512F | PTA_AVX512CD;
2383 const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
2384 const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
2385 const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
2386 | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
2387 | PTA_FSGSBASE;
2388 const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
2389 | PTA_SGX;
2390 const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
2391 | PTA_GFNI;
2392 const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
2393 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
2394
2395 #ifndef GENERATOR_FILE
2396
2397 #include "insn-attr-common.h"
2398
2399 struct pta
2400 {
2401 const char *const name; /* processor name or nickname. */
2402 const enum processor_type processor;
2403 const enum attr_cpu schedule;
2404 const wide_int_bitmask flags;
2405 };
2406
2407 extern const pta processor_alias_table[];
2408 extern int const pta_size;
2409 #endif
2410
2411 #endif
2412
2265 extern enum processor_type ix86_tune; 2413 extern enum processor_type ix86_tune;
2266 extern enum processor_type ix86_arch; 2414 extern enum processor_type ix86_arch;
2267 2415
2268 /* Size of the RED_ZONE area. */ 2416 /* Size of the RED_ZONE area. */
2269 #define RED_ZONE_SIZE 128 2417 #define RED_ZONE_SIZE 128
2302 SLOT_TEMP = 0, 2450 SLOT_TEMP = 0,
2303 SLOT_CW_STORED, 2451 SLOT_CW_STORED,
2304 SLOT_CW_TRUNC, 2452 SLOT_CW_TRUNC,
2305 SLOT_CW_FLOOR, 2453 SLOT_CW_FLOOR,
2306 SLOT_CW_CEIL, 2454 SLOT_CW_CEIL,
2307 SLOT_CW_MASK_PM,
2308 SLOT_STV_TEMP, 2455 SLOT_STV_TEMP,
2309 MAX_386_STACK_LOCALS 2456 MAX_386_STACK_LOCALS
2310 }; 2457 };
2311 2458
2312 enum ix86_entity 2459 enum ix86_entity
2314 X86_DIRFLAG = 0, 2461 X86_DIRFLAG = 0,
2315 AVX_U128, 2462 AVX_U128,
2316 I387_TRUNC, 2463 I387_TRUNC,
2317 I387_FLOOR, 2464 I387_FLOOR,
2318 I387_CEIL, 2465 I387_CEIL,
2319 I387_MASK_PM,
2320 MAX_386_ENTITIES 2466 MAX_386_ENTITIES
2321 }; 2467 };
2322 2468
2323 enum x86_dirflag_state 2469 enum x86_dirflag_state
2324 { 2470 {
2347 starting counting at zero - determines the integer that is used to 2493 starting counting at zero - determines the integer that is used to
2348 refer to the mode-switched entity in question. */ 2494 refer to the mode-switched entity in question. */
2349 2495
2350 #define NUM_MODES_FOR_MODE_SWITCHING \ 2496 #define NUM_MODES_FOR_MODE_SWITCHING \
2351 { X86_DIRFLAG_ANY, AVX_U128_ANY, \ 2497 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2352 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2498 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2353 2499
2354 2500
2355 /* Avoid renaming of stack registers, as doing so in combination with 2501 /* Avoid renaming of stack registers, as doing so in combination with
2356 scheduling just increases amount of live registers at time and in 2502 scheduling just increases amount of live registers at time and in
2357 the turn amount of fxch instructions needed. 2503 the turn amount of fxch instructions needed.
2555 BOOL_BITFIELD no_drap_save_restore : 1; 2701 BOOL_BITFIELD no_drap_save_restore : 1;
2556 2702
2557 /* Function type. */ 2703 /* Function type. */
2558 ENUM_BITFIELD(function_type) func_type : 2; 2704 ENUM_BITFIELD(function_type) func_type : 2;
2559 2705
2706 /* How to generate indirec branch. */
2707 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
2708
2709 /* If true, the current function has local indirect jumps, like
2710 "indirect_jump" or "tablejump". */
2711 BOOL_BITFIELD has_local_indirect_jump : 1;
2712
2713 /* How to generate function return. */
2714 ENUM_BITFIELD(indirect_branch) function_return_type : 3;
2715
2560 /* If true, the current function is a function specified with 2716 /* If true, the current function is a function specified with
2561 the "interrupt" or "no_caller_saved_registers" attribute. */ 2717 the "interrupt" or "no_caller_saved_registers" attribute. */
2562 BOOL_BITFIELD no_caller_saved_registers : 1; 2718 BOOL_BITFIELD no_caller_saved_registers : 1;
2563 2719
2564 /* If true, there is register available for argument passing. This 2720 /* If true, there is register available for argument passing. This
2582 frame pointer.) */ 2738 frame pointer.) */
2583 unsigned int call_ms2sysv_extra_regs:3; 2739 unsigned int call_ms2sysv_extra_regs:3;
2584 2740
2585 /* Nonzero if the function places outgoing arguments on stack. */ 2741 /* Nonzero if the function places outgoing arguments on stack. */
2586 BOOL_BITFIELD outgoing_args_on_stack : 1; 2742 BOOL_BITFIELD outgoing_args_on_stack : 1;
2743
2744 /* If true, ENDBR is queued at function entrance. */
2745 BOOL_BITFIELD endbr_queued_at_entrance : 1;
2746
2747 /* The largest alignment, in bytes, of stack slot actually used. */
2748 unsigned int max_used_stack_alignment;
2587 2749
2588 /* During prologue/epilogue generation, the current frame state. 2750 /* During prologue/epilogue generation, the current frame state.
2589 Otherwise, the frame state at the end of the prologue. */ 2751 Otherwise, the frame state at the end of the prologue. */
2590 struct machine_frame_state fs; 2752 struct machine_frame_state fs;
2591 2753
2669 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2831 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2670 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2832 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2671 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2833 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2672 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2834 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2673 2835
2836 /* Use 128-bit AVX instructions in the auto-vectorizer. */
2837 #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2838 /* Use 256-bit AVX instructions in the auto-vectorizer. */
2839 #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2840 || prefer_vector_width_type == PVW_AVX256)
2841
2842 #define TARGET_INDIRECT_BRANCH_REGISTER \
2843 (ix86_indirect_branch_register \
2844 || cfun->machine->indirect_branch_type != indirect_branch_keep)
2845
2674 #define IX86_HLE_ACQUIRE (1 << 16) 2846 #define IX86_HLE_ACQUIRE (1 << 16)
2675 #define IX86_HLE_RELEASE (1 << 17) 2847 #define IX86_HLE_RELEASE (1 << 17)
2676 2848
2677 /* For switching between functions with different target attributes. */ 2849 /* For switching between functions with different target attributes. */
2678 #define SWITCHABLE_TARGET 1 2850 #define SWITCHABLE_TARGET 1