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comparison gcc/config/i386/sse.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 ;; GCC machine description for SSE instructions 1 ;; GCC machine description for SSE instructions
2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2005-2018 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
153 ;; For AVX5124FMAPS/AVX5124VNNIW support 153 ;; For AVX5124FMAPS/AVX5124VNNIW support
154 UNSPEC_VP4FMADD 154 UNSPEC_VP4FMADD
155 UNSPEC_VP4FNMADD 155 UNSPEC_VP4FNMADD
156 UNSPEC_VP4DPWSSD 156 UNSPEC_VP4DPWSSD
157 UNSPEC_VP4DPWSSDS 157 UNSPEC_VP4DPWSSDS
158
159 ;; For GFNI support
160 UNSPEC_GF2P8AFFINEINV
161 UNSPEC_GF2P8AFFINE
162 UNSPEC_GF2P8MUL
163
164 ;; For AVX512VBMI2 support
165 UNSPEC_VPSHLD
166 UNSPEC_VPSHRD
167 UNSPEC_VPSHRDV
168 UNSPEC_VPSHLDV
169
170 ;; For AVX512VNNI support
171 UNSPEC_VPMADDUBSWACCD
172 UNSPEC_VPMADDUBSWACCSSD
173 UNSPEC_VPMADDWDACCD
174 UNSPEC_VPMADDWDACCSSD
175
176 ;; For VAES support
177 UNSPEC_VAESDEC
178 UNSPEC_VAESDECLAST
179 UNSPEC_VAESENC
180 UNSPEC_VAESENCLAST
181
182 ;; For VPCLMULQDQ support
183 UNSPEC_VPCLMULQDQ
184
185 ;; For AVX512BITALG support
186 UNSPEC_VPSHUFBIT
158 ]) 187 ])
159 188
160 (define_c_enum "unspecv" [ 189 (define_c_enum "unspecv" [
161 UNSPECV_LDMXCSR 190 UNSPECV_LDMXCSR
162 UNSPECV_STMXCSR 191 UNSPECV_STMXCSR
187 ;; 1,2 byte AVX-512{BW,VL} vector modes. Supposed TARGET_AVX512BW baseline. 216 ;; 1,2 byte AVX-512{BW,VL} vector modes. Supposed TARGET_AVX512BW baseline.
188 (define_mode_iterator VI12_AVX512VL 217 (define_mode_iterator VI12_AVX512VL
189 [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") 218 [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")
190 V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) 219 V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")])
191 220
221 ;; Same iterator, but without supposed TARGET_AVX512BW
222 (define_mode_iterator VI12_AVX512VLBW
223 [(V64QI "TARGET_AVX512BW") (V16QI "TARGET_AVX512VL")
224 (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") (V32HI "TARGET_AVX512BW")
225 (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")])
226
192 (define_mode_iterator VI1_AVX512VL 227 (define_mode_iterator VI1_AVX512VL
193 [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) 228 [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")])
194 229
195 ;; All vector modes 230 ;; All vector modes
196 (define_mode_iterator V 231 (define_mode_iterator V
197 [(V32QI "TARGET_AVX") V16QI 232 [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI
198 (V16HI "TARGET_AVX") V8HI 233 (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI
199 (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI 234 (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI
200 (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI 235 (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI
201 (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF 236 (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF
202 (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) 237 (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
203 238
206 [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")]) 241 [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")])
207 242
208 ;; All 256bit vector modes 243 ;; All 256bit vector modes
209 (define_mode_iterator V_256 244 (define_mode_iterator V_256
210 [V32QI V16HI V8SI V4DI V8SF V4DF]) 245 [V32QI V16HI V8SI V4DI V8SF V4DF])
246
247 ;; All 128bit and 256bit vector modes
248 (define_mode_iterator V_128_256
249 [V32QI V16QI V16HI V8HI V8SI V4SI V4DI V2DI V8SF V4SF V4DF V2DF])
211 250
212 ;; All 512bit vector modes 251 ;; All 512bit vector modes
213 (define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF]) 252 (define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF])
214 253
215 ;; All 256bit and 512bit vector modes 254 ;; All 256bit and 512bit vector modes
309 (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")]) 348 (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")])
310 349
311 (define_mode_iterator VI8 350 (define_mode_iterator VI8
312 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) 351 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI])
313 352
353 (define_mode_iterator VI8_FVL
354 [(V8DI "TARGET_AVX512F") V4DI (V2DI "TARGET_AVX512VL")])
355
314 (define_mode_iterator VI8_AVX512VL 356 (define_mode_iterator VI8_AVX512VL
315 [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) 357 [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
316 358
317 (define_mode_iterator VI8_256_512 359 (define_mode_iterator VI8_256_512
318 [V8DI (V4DI "TARGET_AVX512VL")]) 360 [V8DI (V4DI "TARGET_AVX512VL")])
320 (define_mode_iterator VI1_AVX2 362 (define_mode_iterator VI1_AVX2
321 [(V32QI "TARGET_AVX2") V16QI]) 363 [(V32QI "TARGET_AVX2") V16QI])
322 364
323 (define_mode_iterator VI1_AVX512 365 (define_mode_iterator VI1_AVX512
324 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI]) 366 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI])
367
368 (define_mode_iterator VI1_AVX512F
369 [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI])
325 370
326 (define_mode_iterator VI2_AVX2 371 (define_mode_iterator VI2_AVX2
327 [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) 372 [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
328 373
329 (define_mode_iterator VI2_AVX512F 374 (define_mode_iterator VI2_AVX512F
346 (V2DI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8DI "TARGET_AVX512F")]) 391 (V2DI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8DI "TARGET_AVX512F")])
347 392
348 (define_mode_iterator VI2_AVX512VL 393 (define_mode_iterator VI2_AVX512VL
349 [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI]) 394 [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI])
350 395
396 (define_mode_iterator VI1_AVX512VL_F
397 [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")])
398
351 (define_mode_iterator VI8_AVX2_AVX512BW 399 (define_mode_iterator VI8_AVX2_AVX512BW
352 [(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX2") V2DI]) 400 [(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX2") V2DI])
353 401
354 (define_mode_iterator VI8_AVX2 402 (define_mode_iterator VI8_AVX2
355 [(V4DI "TARGET_AVX2") V2DI]) 403 [(V4DI "TARGET_AVX2") V2DI])
356 404
357 (define_mode_iterator VI8_AVX2_AVX512F 405 (define_mode_iterator VI8_AVX2_AVX512F
358 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) 406 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI])
407
408 (define_mode_iterator VI8_AVX_AVX512F
409 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX")])
359 410
360 (define_mode_iterator VI4_128_8_256 411 (define_mode_iterator VI4_128_8_256
361 [V4SI V4DI]) 412 [V4SI V4DI])
362 413
363 ;; All V8D* modes 414 ;; All V8D* modes
401 (V16HI "TARGET_AVX2") V8HI 452 (V16HI "TARGET_AVX2") V8HI
402 (V8SI "TARGET_AVX2") V4SI]) 453 (V8SI "TARGET_AVX2") V4SI])
403 454
404 (define_mode_iterator VI2_AVX2_AVX512BW 455 (define_mode_iterator VI2_AVX2_AVX512BW
405 [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) 456 [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
457
458 (define_mode_iterator VI248_AVX512VL
459 [V32HI V16SI V8DI
460 (V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL")
461 (V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")
462 (V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
406 463
407 (define_mode_iterator VI48_AVX2 464 (define_mode_iterator VI48_AVX2
408 [(V8SI "TARGET_AVX2") V4SI 465 [(V8SI "TARGET_AVX2") V4SI
409 (V4DI "TARGET_AVX2") V2DI]) 466 (V4DI "TARGET_AVX2") V2DI])
410 467
452 [V4SF V2DF 509 [V4SF V2DF
453 V8SF V4DF 510 V8SF V4DF
454 (V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2") 511 (V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2")
455 (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")]) 512 (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")])
456 513
514 (define_mode_iterator VI1_AVX512VLBW
515 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL")
516 (V16QI "TARGET_AVX512VL")])
517
457 (define_mode_attr avx512 518 (define_mode_attr avx512
458 [(V16QI "avx512vl") (V32QI "avx512vl") (V64QI "avx512bw") 519 [(V16QI "avx512vl") (V32QI "avx512vl") (V64QI "avx512bw")
459 (V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw") 520 (V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw")
460 (V4SI "avx512vl") (V8SI "avx512vl") (V16SI "avx512f") 521 (V4SI "avx512vl") (V8SI "avx512vl") (V16SI "avx512f")
461 (V2DI "avx512vl") (V4DI "avx512vl") (V8DI "avx512f") 522 (V2DI "avx512vl") (V4DI "avx512vl") (V8DI "avx512f")
517 (V64QI "i") (V32QI "i") (V16QI "i") 578 (V64QI "i") (V32QI "i") (V16QI "i")
518 (V4TI "i") (V2TI "i") (V1TI "i")]) 579 (V4TI "i") (V2TI "i") (V1TI "i")])
519 580
520 (define_mode_attr ssequartermode 581 (define_mode_attr ssequartermode
521 [(V16SF "V4SF") (V8DF "V2DF") (V16SI "V4SI") (V8DI "V2DI")]) 582 [(V16SF "V4SF") (V8DF "V2DF") (V16SI "V4SI") (V8DI "V2DI")])
583
584 (define_mode_attr ssequarterinsnmode
585 [(V16SF "V4SF") (V8DF "V2DF") (V16SI "TI") (V8DI "TI")])
522 586
523 (define_mode_attr ssedoublemodelower 587 (define_mode_attr ssedoublemodelower
524 [(V16QI "v16hi") (V32QI "v32hi") (V64QI "v64hi") 588 [(V16QI "v16hi") (V32QI "v32hi") (V64QI "v64hi")
525 (V8HI "v8si") (V16HI "v16si") (V32HI "v32si") 589 (V8HI "v8si") (V16HI "v16si") (V32HI "v32si")
526 (V4SI "v4di") (V8SI "v8di") (V16SI "v16di")]) 590 (V4SI "v4di") (V8SI "v8di") (V16SI "v16di")])
566 ;; Int-float size matches 630 ;; Int-float size matches
567 (define_mode_iterator VI4F_128 [V4SI V4SF]) 631 (define_mode_iterator VI4F_128 [V4SI V4SF])
568 (define_mode_iterator VI8F_128 [V2DI V2DF]) 632 (define_mode_iterator VI8F_128 [V2DI V2DF])
569 (define_mode_iterator VI4F_256 [V8SI V8SF]) 633 (define_mode_iterator VI4F_256 [V8SI V8SF])
570 (define_mode_iterator VI8F_256 [V4DI V4DF]) 634 (define_mode_iterator VI8F_256 [V4DI V4DF])
635 (define_mode_iterator VI4F_256_512
636 [V8SI V8SF
637 (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")])
571 (define_mode_iterator VI48F_256_512 638 (define_mode_iterator VI48F_256_512
572 [V8SI V8SF 639 [V8SI V8SF
573 (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") 640 (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
574 (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F") 641 (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F")
575 (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) 642 (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")])
581 (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") 648 (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")
582 (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") 649 (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
583 (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) 650 (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
584 (define_mode_iterator VI48F_256 [V8SI V8SF V4DI V4DF]) 651 (define_mode_iterator VI48F_256 [V8SI V8SF V4DI V4DF])
585 652
653 (define_mode_iterator VF_AVX512
654 [(V4SF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")
655 (V8SF "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")
656 V16SF V8DF])
657
658 (define_mode_attr avx512bcst
659 [(V4SI "%{1to4%}") (V2DI "%{1to2%}")
660 (V8SI "%{1to8%}") (V4DI "%{1to4%}")
661 (V16SI "%{1to16%}") (V8DI "%{1to8%}")
662 (V4SF "%{1to4%}") (V2DF "%{1to2%}")
663 (V8SF "%{1to8%}") (V4DF "%{1to4%}")
664 (V16SF "%{1to16%}") (V8DF "%{1to8%}")])
665
586 ;; Mapping from float mode to required SSE level 666 ;; Mapping from float mode to required SSE level
587 (define_mode_attr sse 667 (define_mode_attr sse
588 [(SF "sse") (DF "sse2") 668 [(SF "sse") (DF "sse2")
589 (V4SF "sse") (V2DF "sse2") 669 (V4SF "sse") (V2DF "sse2")
590 (V16SF "avx512f") (V8SF "avx") 670 (V16SF "avx512f") (V8SF "avx")
738 ;; Pointer size override for scalar modes (Intel asm dialect) 818 ;; Pointer size override for scalar modes (Intel asm dialect)
739 (define_mode_attr iptr 819 (define_mode_attr iptr
740 [(V64QI "b") (V32HI "w") (V16SI "k") (V8DI "q") 820 [(V64QI "b") (V32HI "w") (V16SI "k") (V8DI "q")
741 (V32QI "b") (V16HI "w") (V8SI "k") (V4DI "q") 821 (V32QI "b") (V16HI "w") (V8SI "k") (V4DI "q")
742 (V16QI "b") (V8HI "w") (V4SI "k") (V2DI "q") 822 (V16QI "b") (V8HI "w") (V4SI "k") (V2DI "q")
823 (V16SF "k") (V8DF "q")
743 (V8SF "k") (V4DF "q") 824 (V8SF "k") (V4DF "q")
744 (V4SF "k") (V2DF "q") 825 (V4SF "k") (V2DF "q")
745 (SF "k") (DF "q")]) 826 (SF "k") (DF "q")])
746 827
747 ;; Number of scalar elements in each vector type 828 ;; Number of scalar elements in each vector type
782 (V64QI "p") (V32HI "p")]) 863 (V64QI "p") (V32HI "p")])
783 864
784 ;; SSE scalar suffix for vector modes 865 ;; SSE scalar suffix for vector modes
785 (define_mode_attr ssescalarmodesuffix 866 (define_mode_attr ssescalarmodesuffix
786 [(SF "ss") (DF "sd") 867 [(SF "ss") (DF "sd")
868 (V16SF "ss") (V8DF "sd")
787 (V8SF "ss") (V4DF "sd") 869 (V8SF "ss") (V4DF "sd")
788 (V4SF "ss") (V2DF "sd") 870 (V4SF "ss") (V2DF "sd")
789 (V8SI "ss") (V4DI "sd") 871 (V16SI "d") (V8DI "q")
790 (V4SI "d")]) 872 (V8SI "d") (V4DI "q")
873 (V4SI "d") (V2DI "q")])
791 874
792 ;; Pack/unpack vector modes 875 ;; Pack/unpack vector modes
793 (define_mode_attr sseunpackmode 876 (define_mode_attr sseunpackmode
794 [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") 877 [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")
795 (V32QI "V16HI") (V16HI "V8SI") (V8SI "V4DI") 878 (V32QI "V16HI") (V16HI "V8SI") (V8SI "V4DI")
841 (V8DI "q") (V4DI "q") (V2DI "q") 924 (V8DI "q") (V4DI "q") (V2DI "q")
842 (V16SF "ss") (V8SF "ss") (V4SF "ss") 925 (V16SF "ss") (V8SF "ss") (V4SF "ss")
843 (V8DF "sd") (V4DF "sd") (V2DF "sd")]) 926 (V8DF "sd") (V4DF "sd") (V2DF "sd")])
844 927
845 ;; Tie mode of assembler operand to mode iterator 928 ;; Tie mode of assembler operand to mode iterator
846 (define_mode_attr concat_tg_mode
847 [(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t")
848 (V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")])
849
850 ;; Tie mode of assembler operand to mode iterator
851 (define_mode_attr xtg_mode 929 (define_mode_attr xtg_mode
852 [(V16QI "x") (V8HI "x") (V4SI "x") (V2DI "x") (V4SF "x") (V2DF "x") 930 [(V16QI "x") (V8HI "x") (V4SI "x") (V2DI "x") (V4SF "x") (V2DF "x")
853 (V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t") 931 (V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t")
854 (V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")]) 932 (V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")])
855 933
895 || register_operand (operands[1], <MODE>mode))" 973 || register_operand (operands[1], <MODE>mode))"
896 { 974 {
897 switch (get_attr_type (insn)) 975 switch (get_attr_type (insn))
898 { 976 {
899 case TYPE_SSELOG1: 977 case TYPE_SSELOG1:
900 return standard_sse_constant_opcode (insn, operands[1]); 978 return standard_sse_constant_opcode (insn, operands);
901 979
902 case TYPE_SSEMOV: 980 case TYPE_SSEMOV:
903 /* There is no evex-encoded vmov* for sizes smaller than 64-bytes 981 /* There is no evex-encoded vmov* for sizes smaller than 64-bytes
904 in avx512f, so we need to use workarounds, to access sse registers 982 in avx512f, so we need to use workarounds, to access sse registers
905 16-31, which are evex-only. In avx512vl we don't need workarounds. */ 983 16-31, which are evex-only. In avx512vl we don't need workarounds. */
965 1043
966 case MODE_OI: 1044 case MODE_OI:
967 case MODE_TI: 1045 case MODE_TI:
968 if (misaligned_operand (operands[0], <MODE>mode) 1046 if (misaligned_operand (operands[0], <MODE>mode)
969 || misaligned_operand (operands[1], <MODE>mode)) 1047 || misaligned_operand (operands[1], <MODE>mode))
970 return TARGET_AVX512VL ? "vmovdqu<ssescalarsize>\t{%1, %0|%0, %1}" 1048 return TARGET_AVX512VL
971 : "%vmovdqu\t{%1, %0|%0, %1}"; 1049 && (<MODE>mode == V4SImode
1050 || <MODE>mode == V2DImode
1051 || <MODE>mode == V8SImode
1052 || <MODE>mode == V4DImode
1053 || TARGET_AVX512BW)
1054 ? "vmovdqu<ssescalarsize>\t{%1, %0|%0, %1}"
1055 : "%vmovdqu\t{%1, %0|%0, %1}";
972 else 1056 else
973 return TARGET_AVX512VL ? "vmovdqa64\t{%1, %0|%0, %1}" 1057 return TARGET_AVX512VL ? "vmovdqa64\t{%1, %0|%0, %1}"
974 : "%vmovdqa\t{%1, %0|%0, %1}"; 1058 : "%vmovdqa\t{%1, %0|%0, %1}";
975 case MODE_XI: 1059 case MODE_XI:
976 if (misaligned_operand (operands[0], <MODE>mode) 1060 if (misaligned_operand (operands[0], <MODE>mode)
1024 1108
1025 (define_insn "<avx512>_load<mode>_mask" 1109 (define_insn "<avx512>_load<mode>_mask"
1026 [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v") 1110 [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v")
1027 (vec_merge:V48_AVX512VL 1111 (vec_merge:V48_AVX512VL
1028 (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "v,m") 1112 (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "v,m")
1029 (match_operand:V48_AVX512VL 2 "vector_move_operand" "0C,0C") 1113 (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
1030 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] 1114 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
1031 "TARGET_AVX512F" 1115 "TARGET_AVX512F"
1032 { 1116 {
1033 if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode))) 1117 if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode)))
1034 { 1118 {
1052 1136
1053 (define_insn "<avx512>_load<mode>_mask" 1137 (define_insn "<avx512>_load<mode>_mask"
1054 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v") 1138 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v")
1055 (vec_merge:VI12_AVX512VL 1139 (vec_merge:VI12_AVX512VL
1056 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v,m") 1140 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v,m")
1057 (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C,0C") 1141 (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
1058 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] 1142 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
1059 "TARGET_AVX512BW" 1143 "TARGET_AVX512BW"
1060 "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 1144 "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
1061 [(set_attr "type" "ssemov") 1145 [(set_attr "type" "ssemov")
1062 (set_attr "prefix" "evex") 1146 (set_attr "prefix" "evex")
1068 (vec_merge:V48_AVX512VL 1152 (vec_merge:V48_AVX512VL
1069 (match_operand:V48_AVX512VL 2 "nonimmediate_operand" "vm") 1153 (match_operand:V48_AVX512VL 2 "nonimmediate_operand" "vm")
1070 (match_operand:V48_AVX512VL 1 "register_operand" "v") 1154 (match_operand:V48_AVX512VL 1 "register_operand" "v")
1071 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] 1155 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
1072 "TARGET_AVX512F" 1156 "TARGET_AVX512F"
1073 "vblendm<ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" 1157 "v<sseintprefix>blendm<ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
1074 [(set_attr "type" "ssemov") 1158 [(set_attr "type" "ssemov")
1075 (set_attr "prefix" "evex") 1159 (set_attr "prefix" "evex")
1076 (set_attr "mode" "<sseinsnmode>")]) 1160 (set_attr "mode" "<sseinsnmode>")])
1077 1161
1078 (define_insn "<avx512>_blendm<mode>" 1162 (define_insn "<avx512>_blendm<mode>"
1170 gen_highpart (SImode, operands[1]))); 1254 gen_highpart (SImode, operands[1])));
1171 emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0], 1255 emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0],
1172 operands[2])); 1256 operands[2]));
1173 } 1257 }
1174 else if (memory_operand (operands[1], DImode)) 1258 else if (memory_operand (operands[1], DImode))
1175 { 1259 emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]),
1176 rtx tmp = gen_reg_rtx (V2DImode); 1260 operands[1], const0_rtx));
1177 emit_insn (gen_vec_concatv2di (tmp, operands[1], const0_rtx));
1178 emit_move_insn (operands[0], gen_lowpart (V4SImode, tmp));
1179 }
1180 else 1261 else
1181 gcc_unreachable (); 1262 gcc_unreachable ();
1182 DONE; 1263 DONE;
1183 }) 1264 })
1184 1265
1594 (define_insn "*<plusminus_insn><mode>3<mask_name><round_name>" 1675 (define_insn "*<plusminus_insn><mode>3<mask_name><round_name>"
1595 [(set (match_operand:VF 0 "register_operand" "=x,v") 1676 [(set (match_operand:VF 0 "register_operand" "=x,v")
1596 (plusminus:VF 1677 (plusminus:VF
1597 (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v") 1678 (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v")
1598 (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] 1679 (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
1599 "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" 1680 "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
1681 && <mask_mode512bit_condition> && <round_mode512bit_condition>"
1600 "@ 1682 "@
1601 <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} 1683 <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
1602 v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}" 1684 v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
1603 [(set_attr "isa" "noavx,avx") 1685 [(set_attr "isa" "noavx,avx")
1604 (set_attr "type" "sseadd") 1686 (set_attr "type" "sseadd")
1605 (set_attr "prefix" "<mask_prefix3>") 1687 (set_attr "prefix" "<mask_prefix3>")
1688 (set_attr "mode" "<MODE>")])
1689
1690 (define_insn "*sub<mode>3<mask_name>_bcst"
1691 [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
1692 (minus:VF_AVX512
1693 (match_operand:VF_AVX512 1 "register_operand" "v")
1694 (vec_duplicate:VF_AVX512
1695 (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
1696 "TARGET_AVX512F
1697 && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)
1698 && <mask_mode512bit_condition>"
1699 "vsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<avx512bcst>}"
1700 [(set_attr "prefix" "evex")
1701 (set_attr "type" "sseadd")
1702 (set_attr "mode" "<MODE>")])
1703
1704 (define_insn "*add<mode>3<mask_name>_bcst"
1705 [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
1706 (plus:VF_AVX512
1707 (vec_duplicate:VF_AVX512
1708 (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
1709 (match_operand:VF_AVX512 2 "register_operand" "v")))]
1710 "TARGET_AVX512F
1711 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
1712 && <mask_mode512bit_condition>"
1713 "vadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
1714 [(set_attr "prefix" "evex")
1715 (set_attr "type" "sseadd")
1606 (set_attr "mode" "<MODE>")]) 1716 (set_attr "mode" "<MODE>")])
1607 1717
1608 (define_insn "<sse>_vm<plusminus_insn><mode>3<mask_scalar_name><round_scalar_name>" 1718 (define_insn "<sse>_vm<plusminus_insn><mode>3<mask_scalar_name><round_scalar_name>"
1609 [(set (match_operand:VF_128 0 "register_operand" "=x,v") 1719 [(set (match_operand:VF_128 0 "register_operand" "=x,v")
1610 (vec_merge:VF_128 1720 (vec_merge:VF_128
1633 (define_insn "*mul<mode>3<mask_name><round_name>" 1743 (define_insn "*mul<mode>3<mask_name><round_name>"
1634 [(set (match_operand:VF 0 "register_operand" "=x,v") 1744 [(set (match_operand:VF 0 "register_operand" "=x,v")
1635 (mult:VF 1745 (mult:VF
1636 (match_operand:VF 1 "<round_nimm_predicate>" "%0,v") 1746 (match_operand:VF 1 "<round_nimm_predicate>" "%0,v")
1637 (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] 1747 (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
1638 "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" 1748 "TARGET_SSE
1749 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
1750 && <mask_mode512bit_condition> && <round_mode512bit_condition>"
1639 "@ 1751 "@
1640 mul<ssemodesuffix>\t{%2, %0|%0, %2} 1752 mul<ssemodesuffix>\t{%2, %0|%0, %2}
1641 vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}" 1753 vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
1642 [(set_attr "isa" "noavx,avx") 1754 [(set_attr "isa" "noavx,avx")
1643 (set_attr "type" "ssemul") 1755 (set_attr "type" "ssemul")
1644 (set_attr "prefix" "<mask_prefix3>") 1756 (set_attr "prefix" "<mask_prefix3>")
1645 (set_attr "btver2_decode" "direct,double") 1757 (set_attr "btver2_decode" "direct,double")
1758 (set_attr "mode" "<MODE>")])
1759
1760 (define_insn "*mul<mode>3<mask_name>_bcst"
1761 [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
1762 (mult:VF_AVX512
1763 (vec_duplicate:VF_AVX512
1764 (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
1765 (match_operand:VF_AVX512 2 "register_operand" "v")))]
1766 "TARGET_AVX512F && <mask_mode512bit_condition>"
1767 "vmul<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<<avx512bcst>>}"
1768 [(set_attr "prefix" "evex")
1769 (set_attr "type" "ssemul")
1646 (set_attr "mode" "<MODE>")]) 1770 (set_attr "mode" "<MODE>")])
1647 1771
1648 (define_insn "<sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name><round_scalar_name>" 1772 (define_insn "<sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name><round_scalar_name>"
1649 [(set (match_operand:VF_128 0 "register_operand" "=x,v") 1773 [(set (match_operand:VF_128 0 "register_operand" "=x,v")
1650 (vec_merge:VF_128 1774 (vec_merge:VF_128
1701 [(set_attr "isa" "noavx,avx") 1825 [(set_attr "isa" "noavx,avx")
1702 (set_attr "type" "ssediv") 1826 (set_attr "type" "ssediv")
1703 (set_attr "prefix" "<mask_prefix3>") 1827 (set_attr "prefix" "<mask_prefix3>")
1704 (set_attr "mode" "<MODE>")]) 1828 (set_attr "mode" "<MODE>")])
1705 1829
1830 (define_insn "*<avx512>_div<mode>3<mask_name>_bcst"
1831 [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
1832 (div:VF_AVX512
1833 (match_operand:VF_AVX512 1 "register_operand" "v")
1834 (vec_duplicate:VF_AVX512
1835 (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
1836 "TARGET_AVX512F && <mask_mode512bit_condition>"
1837 "vdiv<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<<avx512bcst>>}"
1838 [(set_attr "prefix" "evex")
1839 (set_attr "type" "ssediv")
1840 (set_attr "mode" "<MODE>")])
1841
1706 (define_insn "<sse>_rcp<mode>2" 1842 (define_insn "<sse>_rcp<mode>2"
1707 [(set (match_operand:VF1_128_256 0 "register_operand" "=x") 1843 [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
1708 (unspec:VF1_128_256 1844 (unspec:VF1_128_256
1709 [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RCP))] 1845 [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RCP))]
1710 "TARGET_SSE" 1846 "TARGET_SSE"
1763 (vec_merge:VF_128 1899 (vec_merge:VF_128
1764 (vec_merge:VF_128 1900 (vec_merge:VF_128
1765 (unspec:VF_128 1901 (unspec:VF_128
1766 [(match_operand:VF_128 1 "nonimmediate_operand" "vm")] 1902 [(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
1767 UNSPEC_RCP14) 1903 UNSPEC_RCP14)
1768 (match_operand:VF_128 3 "vector_move_operand" "0C") 1904 (match_operand:VF_128 3 "nonimm_or_0_operand" "0C")
1769 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")) 1905 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
1770 (match_operand:VF_128 2 "register_operand" "v") 1906 (match_operand:VF_128 2 "register_operand" "v")
1771 (const_int 1)))] 1907 (const_int 1)))]
1772 "TARGET_AVX512F" 1908 "TARGET_AVX512F"
1773 "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}" 1909 "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
1808 (set_attr "atom_sse_attr" "sqrt") 1944 (set_attr "atom_sse_attr" "sqrt")
1809 (set_attr "btver2_sse_attr" "sqrt") 1945 (set_attr "btver2_sse_attr" "sqrt")
1810 (set_attr "prefix" "maybe_vex") 1946 (set_attr "prefix" "maybe_vex")
1811 (set_attr "mode" "<MODE>")]) 1947 (set_attr "mode" "<MODE>")])
1812 1948
1813 (define_insn "<sse>_vmsqrt<mode>2<round_name>" 1949 (define_insn "<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>"
1814 [(set (match_operand:VF_128 0 "register_operand" "=x,v") 1950 [(set (match_operand:VF_128 0 "register_operand" "=x,v")
1815 (vec_merge:VF_128 1951 (vec_merge:VF_128
1816 (sqrt:VF_128 1952 (sqrt:VF_128
1817 (match_operand:VF_128 1 "vector_operand" "xBm,<round_constraint>")) 1953 (match_operand:VF_128 1 "vector_operand" "xBm,<round_scalar_constraint>"))
1818 (match_operand:VF_128 2 "register_operand" "0,v") 1954 (match_operand:VF_128 2 "register_operand" "0,v")
1819 (const_int 1)))] 1955 (const_int 1)))]
1820 "TARGET_SSE" 1956 "TARGET_SSE"
1821 "@ 1957 "@
1822 sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %<iptr>1} 1958 sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %<iptr>1}
1823 vsqrt<ssescalarmodesuffix>\t{<round_op3>%1, %2, %0|%0, %2, %<iptr>1<round_op3>}" 1959 vsqrt<ssescalarmodesuffix>\t{<round_scalar_mask_op3>%1, %2, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %2, %<iptr>1<round_scalar_mask_op3>}"
1824 [(set_attr "isa" "noavx,avx") 1960 [(set_attr "isa" "noavx,avx")
1825 (set_attr "type" "sse") 1961 (set_attr "type" "sse")
1826 (set_attr "atom_sse_attr" "sqrt") 1962 (set_attr "atom_sse_attr" "sqrt")
1827 (set_attr "prefix" "<round_prefix>") 1963 (set_attr "prefix" "<round_scalar_prefix>")
1828 (set_attr "btver2_sse_attr" "sqrt") 1964 (set_attr "btver2_sse_attr" "sqrt")
1829 (set_attr "mode" "<ssescalarmode>")]) 1965 (set_attr "mode" "<ssescalarmode>")])
1830 1966
1831 (define_expand "rsqrt<mode>2" 1967 (define_expand "rsqrt<mode>2"
1832 [(set (match_operand:VF1_128_256 0 "register_operand") 1968 [(set (match_operand:VF1_128_256 0 "register_operand")
1889 (vec_merge:VF_128 2025 (vec_merge:VF_128
1890 (vec_merge:VF_128 2026 (vec_merge:VF_128
1891 (unspec:VF_128 2027 (unspec:VF_128
1892 [(match_operand:VF_128 1 "nonimmediate_operand" "vm")] 2028 [(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
1893 UNSPEC_RSQRT14) 2029 UNSPEC_RSQRT14)
1894 (match_operand:VF_128 3 "vector_move_operand" "0C") 2030 (match_operand:VF_128 3 "nonimm_or_0_operand" "0C")
1895 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")) 2031 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
1896 (match_operand:VF_128 2 "register_operand" "v") 2032 (match_operand:VF_128 2 "register_operand" "v")
1897 (const_int 1)))] 2033 (const_int 1)))]
1898 "TARGET_AVX512F" 2034 "TARGET_AVX512F"
1899 "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}" 2035 "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
1945 (define_insn "*<code><mode>3<mask_name><round_saeonly_name>" 2081 (define_insn "*<code><mode>3<mask_name><round_saeonly_name>"
1946 [(set (match_operand:VF 0 "register_operand" "=x,v") 2082 [(set (match_operand:VF 0 "register_operand" "=x,v")
1947 (smaxmin:VF 2083 (smaxmin:VF
1948 (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v") 2084 (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
1949 (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] 2085 (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))]
1950 "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) 2086 "TARGET_SSE
2087 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
1951 && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" 2088 && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
1952 "@ 2089 "@
1953 <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2} 2090 <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
1954 v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}" 2091 v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
1955 [(set_attr "isa" "noavx,avx") 2092 [(set_attr "isa" "noavx,avx")
2383 (set_attr "atom_unit" "complex") 2520 (set_attr "atom_unit" "complex")
2384 (set_attr "prefix" "orig,vex") 2521 (set_attr "prefix" "orig,vex")
2385 (set_attr "prefix_rep" "1,*") 2522 (set_attr "prefix_rep" "1,*")
2386 (set_attr "mode" "V4SF")]) 2523 (set_attr "mode" "V4SF")])
2387 2524
2388 (define_expand "reduc_plus_scal_v8df" 2525 (define_mode_iterator REDUC_SSE_PLUS_MODE
2389 [(match_operand:DF 0 "register_operand") 2526 [(V2DF "TARGET_SSE") (V4SF "TARGET_SSE")])
2390 (match_operand:V8DF 1 "register_operand")] 2527
2391 "TARGET_AVX512F" 2528 (define_expand "reduc_plus_scal_<mode>"
2392 { 2529 [(plus:REDUC_SSE_PLUS_MODE
2393 rtx tmp = gen_reg_rtx (V8DFmode); 2530 (match_operand:<ssescalarmode> 0 "register_operand")
2394 ix86_expand_reduc (gen_addv8df3, tmp, operands[1]); 2531 (match_operand:REDUC_SSE_PLUS_MODE 1 "register_operand"))]
2395 emit_insn (gen_vec_extractv8dfdf (operands[0], tmp, const0_rtx)); 2532 ""
2533 {
2534 rtx tmp = gen_reg_rtx (<MODE>mode);
2535 ix86_expand_reduc (gen_add<mode>3, tmp, operands[1]);
2536 emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
2537 const0_rtx));
2396 DONE; 2538 DONE;
2397 }) 2539 })
2398 2540
2399 (define_expand "reduc_plus_scal_v4df" 2541 (define_mode_iterator REDUC_PLUS_MODE
2400 [(match_operand:DF 0 "register_operand") 2542 [(V4DF "TARGET_AVX") (V8SF "TARGET_AVX")
2401 (match_operand:V4DF 1 "register_operand")] 2543 (V8DF "TARGET_AVX512F") (V16SF "TARGET_AVX512F")])
2402 "TARGET_AVX" 2544
2403 { 2545 (define_expand "reduc_plus_scal_<mode>"
2404 rtx tmp = gen_reg_rtx (V4DFmode); 2546 [(plus:REDUC_PLUS_MODE
2405 rtx tmp2 = gen_reg_rtx (V4DFmode); 2547 (match_operand:<ssescalarmode> 0 "register_operand")
2406 rtx vec_res = gen_reg_rtx (V4DFmode); 2548 (match_operand:REDUC_PLUS_MODE 1 "register_operand"))]
2407 emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1])); 2549 ""
2408 emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1))); 2550 {
2409 emit_insn (gen_addv4df3 (vec_res, tmp, tmp2)); 2551 rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
2410 emit_insn (gen_vec_extractv4dfdf (operands[0], vec_res, const0_rtx)); 2552 emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
2553 rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
2554 emit_insn (gen_add<ssehalfvecmodelower>3
2555 (tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
2556 emit_insn (gen_reduc_plus_scal_<ssehalfvecmodelower> (operands[0], tmp2));
2411 DONE; 2557 DONE;
2412 }) 2558 })
2413 2559
2414 (define_expand "reduc_plus_scal_v2df" 2560 ;; Modes handled by reduc_sm{in,ax}* patterns.
2415 [(match_operand:DF 0 "register_operand") 2561 (define_mode_iterator REDUC_SSE_SMINMAX_MODE
2416 (match_operand:V2DF 1 "register_operand")] 2562 [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE")
2417 "TARGET_SSE3" 2563 (V2DI "TARGET_SSE") (V4SI "TARGET_SSE") (V8HI "TARGET_SSE")
2418 { 2564 (V16QI "TARGET_SSE")])
2419 rtx tmp = gen_reg_rtx (V2DFmode); 2565
2420 emit_insn (gen_sse3_haddv2df3 (tmp, operands[1], operands[1])); 2566 (define_expand "reduc_<code>_scal_<mode>"
2421 emit_insn (gen_vec_extractv2dfdf (operands[0], tmp, const0_rtx)); 2567 [(smaxmin:REDUC_SSE_SMINMAX_MODE
2568 (match_operand:<ssescalarmode> 0 "register_operand")
2569 (match_operand:REDUC_SSE_SMINMAX_MODE 1 "register_operand"))]
2570 ""
2571 {
2572 rtx tmp = gen_reg_rtx (<MODE>mode);
2573 ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
2574 emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
2575 const0_rtx));
2422 DONE; 2576 DONE;
2423 }) 2577 })
2424 2578
2425 (define_expand "reduc_plus_scal_v16sf"
2426 [(match_operand:SF 0 "register_operand")
2427 (match_operand:V16SF 1 "register_operand")]
2428 "TARGET_AVX512F"
2429 {
2430 rtx tmp = gen_reg_rtx (V16SFmode);
2431 ix86_expand_reduc (gen_addv16sf3, tmp, operands[1]);
2432 emit_insn (gen_vec_extractv16sfsf (operands[0], tmp, const0_rtx));
2433 DONE;
2434 })
2435
2436 (define_expand "reduc_plus_scal_v8sf"
2437 [(match_operand:SF 0 "register_operand")
2438 (match_operand:V8SF 1 "register_operand")]
2439 "TARGET_AVX"
2440 {
2441 rtx tmp = gen_reg_rtx (V8SFmode);
2442 rtx tmp2 = gen_reg_rtx (V8SFmode);
2443 rtx vec_res = gen_reg_rtx (V8SFmode);
2444 emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1]));
2445 emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp));
2446 emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1)));
2447 emit_insn (gen_addv8sf3 (vec_res, tmp, tmp2));
2448 emit_insn (gen_vec_extractv8sfsf (operands[0], vec_res, const0_rtx));
2449 DONE;
2450 })
2451
2452 (define_expand "reduc_plus_scal_v4sf"
2453 [(match_operand:SF 0 "register_operand")
2454 (match_operand:V4SF 1 "register_operand")]
2455 "TARGET_SSE"
2456 {
2457 rtx vec_res = gen_reg_rtx (V4SFmode);
2458 if (TARGET_SSE3)
2459 {
2460 rtx tmp = gen_reg_rtx (V4SFmode);
2461 emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
2462 emit_insn (gen_sse3_haddv4sf3 (vec_res, tmp, tmp));
2463 }
2464 else
2465 ix86_expand_reduc (gen_addv4sf3, vec_res, operands[1]);
2466 emit_insn (gen_vec_extractv4sfsf (operands[0], vec_res, const0_rtx));
2467 DONE;
2468 })
2469
2470 ;; Modes handled by reduc_sm{in,ax}* patterns.
2471 (define_mode_iterator REDUC_SMINMAX_MODE 2579 (define_mode_iterator REDUC_SMINMAX_MODE
2472 [(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2") 2580 [(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")
2473 (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") 2581 (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")
2474 (V8SF "TARGET_AVX") (V4DF "TARGET_AVX") 2582 (V8SF "TARGET_AVX") (V4DF "TARGET_AVX")
2475 (V4SF "TARGET_SSE") (V64QI "TARGET_AVX512BW") 2583 (V64QI "TARGET_AVX512BW")
2476 (V32HI "TARGET_AVX512BW") (V16SI "TARGET_AVX512F") 2584 (V32HI "TARGET_AVX512BW") (V16SI "TARGET_AVX512F")
2477 (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") 2585 (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
2478 (V8DF "TARGET_AVX512F")]) 2586 (V8DF "TARGET_AVX512F")])
2479 2587
2480 (define_expand "reduc_<code>_scal_<mode>" 2588 (define_expand "reduc_<code>_scal_<mode>"
2481 [(smaxmin:REDUC_SMINMAX_MODE 2589 [(smaxmin:REDUC_SMINMAX_MODE
2482 (match_operand:<ssescalarmode> 0 "register_operand") 2590 (match_operand:<ssescalarmode> 0 "register_operand")
2483 (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))] 2591 (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))]
2484 "" 2592 ""
2485 { 2593 {
2486 rtx tmp = gen_reg_rtx (<MODE>mode); 2594 rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
2487 ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]); 2595 emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
2488 emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp, 2596 rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
2489 const0_rtx)); 2597 emit_insn (gen_<code><ssehalfvecmodelower>3
2598 (tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
2599 emit_insn (gen_reduc_<code>_scal_<ssehalfvecmodelower> (operands[0], tmp2));
2490 DONE; 2600 DONE;
2491 }) 2601 })
2492 2602
2493 (define_expand "reduc_<code>_scal_<mode>" 2603 (define_expand "reduc_<code>_scal_<mode>"
2494 [(umaxmin:VI_AVX512BW 2604 [(umaxmin:VI_AVX512BW
2495 (match_operand:<ssescalarmode> 0 "register_operand") 2605 (match_operand:<ssescalarmode> 0 "register_operand")
2496 (match_operand:VI_AVX512BW 1 "register_operand"))] 2606 (match_operand:VI_AVX512BW 1 "register_operand"))]
2497 "TARGET_AVX512F" 2607 "TARGET_AVX512F"
2498 { 2608 {
2499 rtx tmp = gen_reg_rtx (<MODE>mode); 2609 rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
2500 ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]); 2610 emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
2501 emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp, 2611 rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
2502 const0_rtx)); 2612 emit_insn (gen_<code><ssehalfvecmodelower>3
2613 (tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
2614 emit_insn (gen_reduc_<code>_scal_<ssehalfvecmodelower> (operands[0], tmp2));
2503 DONE; 2615 DONE;
2504 }) 2616 })
2505 2617
2506 (define_expand "reduc_<code>_scal_<mode>" 2618 (define_expand "reduc_<code>_scal_<mode>"
2507 [(umaxmin:VI_256 2619 [(umaxmin:VI_256
2508 (match_operand:<ssescalarmode> 0 "register_operand") 2620 (match_operand:<ssescalarmode> 0 "register_operand")
2509 (match_operand:VI_256 1 "register_operand"))] 2621 (match_operand:VI_256 1 "register_operand"))]
2510 "TARGET_AVX2" 2622 "TARGET_AVX2"
2511 { 2623 {
2512 rtx tmp = gen_reg_rtx (<MODE>mode); 2624 rtx tmp = gen_reg_rtx (<ssehalfvecmode>mode);
2513 ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]); 2625 emit_insn (gen_vec_extract_hi_<mode> (tmp, operands[1]));
2514 emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp, 2626 rtx tmp2 = gen_reg_rtx (<ssehalfvecmode>mode);
2515 const0_rtx)); 2627 emit_insn (gen_<code><ssehalfvecmodelower>3
2628 (tmp2, tmp, gen_lowpart (<ssehalfvecmode>mode, operands[1])));
2629 rtx tmp3 = gen_reg_rtx (<ssehalfvecmode>mode);
2630 ix86_expand_reduc (gen_<code><ssehalfvecmodelower>3, tmp3, tmp2);
2631 emit_insn (gen_vec_extract<ssehalfvecmodelower><ssescalarmodelower>
2632 (operands[0], tmp3, const0_rtx));
2516 DONE; 2633 DONE;
2517 }) 2634 })
2518 2635
2519 (define_expand "reduc_umin_scal_v8hi" 2636 (define_expand "reduc_umin_scal_v8hi"
2520 [(umin:V8HI 2637 [(umin:V8HI
2549 (match_operand:SI 3 "const_0_to_255_operand")] 2666 (match_operand:SI 3 "const_0_to_255_operand")]
2550 UNSPEC_REDUCE) 2667 UNSPEC_REDUCE)
2551 (match_dup 1) 2668 (match_dup 1)
2552 (const_int 1)))] 2669 (const_int 1)))]
2553 "TARGET_AVX512DQ" 2670 "TARGET_AVX512DQ"
2554 "vreduce<ssescalarmodesuffix>\t{%3, %2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2, %3}" 2671 "vreduce<ssescalarmodesuffix>\t{%3, %2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2, %3}"
2555 [(set_attr "type" "sse") 2672 [(set_attr "type" "sse")
2556 (set_attr "prefix" "evex") 2673 (set_attr "prefix" "evex")
2557 (set_attr "mode" "<MODE>")]) 2674 (set_attr "mode" "<MODE>")])
2558 2675
2559 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2676 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2717 (match_operand:VF_128 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") 2834 (match_operand:VF_128 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
2718 (match_operand:SI 3 "const_0_to_31_operand" "n")] 2835 (match_operand:SI 3 "const_0_to_31_operand" "n")]
2719 UNSPEC_PCMP) 2836 UNSPEC_PCMP)
2720 (const_int 1)))] 2837 (const_int 1)))]
2721 "TARGET_AVX512F" 2838 "TARGET_AVX512F"
2722 "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}" 2839 "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %<iptr>2<round_saeonly_op4>, %3}"
2723 [(set_attr "type" "ssecmp") 2840 [(set_attr "type" "ssecmp")
2724 (set_attr "length_immediate" "1") 2841 (set_attr "length_immediate" "1")
2725 (set_attr "prefix" "evex") 2842 (set_attr "prefix" "evex")
2726 (set_attr "mode" "<ssescalarmode>")]) 2843 (set_attr "mode" "<ssescalarmode>")])
2727 2844
2735 UNSPEC_PCMP) 2852 UNSPEC_PCMP)
2736 (and:<avx512fmaskmode> 2853 (and:<avx512fmaskmode>
2737 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk") 2854 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")
2738 (const_int 1))))] 2855 (const_int 1))))]
2739 "TARGET_AVX512F" 2856 "TARGET_AVX512F"
2740 "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_saeonly_op5>, %3}" 2857 "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %<iptr>2<round_saeonly_op5>, %3}"
2741 [(set_attr "type" "ssecmp") 2858 [(set_attr "type" "ssecmp")
2742 (set_attr "length_immediate" "1") 2859 (set_attr "length_immediate" "1")
2743 (set_attr "prefix" "evex") 2860 (set_attr "prefix" "evex")
2744 (set_attr "mode" "<ssescalarmode>")]) 2861 (set_attr "mode" "<ssescalarmode>")])
2745 2862
2753 [(set_attr "type" "ssecmp") 2870 [(set_attr "type" "ssecmp")
2754 (set_attr "length_immediate" "1") 2871 (set_attr "length_immediate" "1")
2755 (set_attr "prefix" "evex") 2872 (set_attr "prefix" "evex")
2756 (set_attr "mode" "<sseinsnmode>")]) 2873 (set_attr "mode" "<sseinsnmode>")])
2757 2874
2758 (define_insn "<sse>_comi<round_saeonly_name>" 2875 (define_insn "<sse>_<unord>comi<round_saeonly_name>"
2759 [(set (reg:CCFP FLAGS_REG) 2876 [(set (reg:CCFP FLAGS_REG)
2760 (compare:CCFP 2877 (compare:CCFP
2761 (vec_select:MODEF 2878 (vec_select:MODEF
2762 (match_operand:<ssevecmode> 0 "register_operand" "v") 2879 (match_operand:<ssevecmode> 0 "register_operand" "v")
2763 (parallel [(const_int 0)])) 2880 (parallel [(const_int 0)]))
2764 (vec_select:MODEF 2881 (vec_select:MODEF
2765 (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") 2882 (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
2766 (parallel [(const_int 0)]))))] 2883 (parallel [(const_int 0)]))))]
2767 "SSE_FLOAT_MODE_P (<MODE>mode)" 2884 "SSE_FLOAT_MODE_P (<MODE>mode)"
2768 "%vcomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}" 2885 "%v<unord>comi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}"
2769 [(set_attr "type" "ssecomi")
2770 (set_attr "prefix" "maybe_vex")
2771 (set_attr "prefix_rep" "0")
2772 (set (attr "prefix_data16")
2773 (if_then_else (eq_attr "mode" "DF")
2774 (const_string "1")
2775 (const_string "0")))
2776 (set_attr "mode" "<MODE>")])
2777
2778 (define_insn "<sse>_ucomi<round_saeonly_name>"
2779 [(set (reg:CCFPU FLAGS_REG)
2780 (compare:CCFPU
2781 (vec_select:MODEF
2782 (match_operand:<ssevecmode> 0 "register_operand" "v")
2783 (parallel [(const_int 0)]))
2784 (vec_select:MODEF
2785 (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
2786 (parallel [(const_int 0)]))))]
2787 "SSE_FLOAT_MODE_P (<MODE>mode)"
2788 "%vucomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}"
2789 [(set_attr "type" "ssecomi") 2886 [(set_attr "type" "ssecomi")
2790 (set_attr "prefix" "maybe_vex") 2887 (set_attr "prefix" "maybe_vex")
2791 (set_attr "prefix_rep" "0") 2888 (set_attr "prefix_rep" "0")
2792 (set (attr "prefix_data16") 2889 (set (attr "prefix_data16")
2793 (if_then_else (eq_attr "mode" "DF") 2890 (if_then_else (eq_attr "mode" "DF")
3004 3101
3005 (define_expand "vcond_mask_<mode><avx512fmaskmodelower>" 3102 (define_expand "vcond_mask_<mode><avx512fmaskmodelower>"
3006 [(set (match_operand:V48_AVX512VL 0 "register_operand") 3103 [(set (match_operand:V48_AVX512VL 0 "register_operand")
3007 (vec_merge:V48_AVX512VL 3104 (vec_merge:V48_AVX512VL
3008 (match_operand:V48_AVX512VL 1 "nonimmediate_operand") 3105 (match_operand:V48_AVX512VL 1 "nonimmediate_operand")
3009 (match_operand:V48_AVX512VL 2 "vector_move_operand") 3106 (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand")
3010 (match_operand:<avx512fmaskmode> 3 "register_operand")))] 3107 (match_operand:<avx512fmaskmode> 3 "register_operand")))]
3011 "TARGET_AVX512F") 3108 "TARGET_AVX512F")
3012 3109
3013 (define_expand "vcond_mask_<mode><avx512fmaskmodelower>" 3110 (define_expand "vcond_mask_<mode><avx512fmaskmodelower>"
3014 [(set (match_operand:VI12_AVX512VL 0 "register_operand") 3111 [(set (match_operand:VI12_AVX512VL 0 "register_operand")
3015 (vec_merge:VI12_AVX512VL 3112 (vec_merge:VI12_AVX512VL
3016 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") 3113 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
3017 (match_operand:VI12_AVX512VL 2 "vector_move_operand") 3114 (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand")
3018 (match_operand:<avx512fmaskmode> 3 "register_operand")))] 3115 (match_operand:<avx512fmaskmode> 3 "register_operand")))]
3019 "TARGET_AVX512BW") 3116 "TARGET_AVX512BW")
3020 3117
3021 (define_expand "vcond_mask_<mode><sseintvecmodelower>" 3118 (define_expand "vcond_mask_<mode><sseintvecmodelower>"
3022 [(set (match_operand:VI_256 0 "register_operand") 3119 [(set (match_operand:VI_256 0 "register_operand")
3023 (vec_merge:VI_256 3120 (vec_merge:VI_256
3024 (match_operand:VI_256 1 "nonimmediate_operand") 3121 (match_operand:VI_256 1 "nonimmediate_operand")
3025 (match_operand:VI_256 2 "vector_move_operand") 3122 (match_operand:VI_256 2 "nonimm_or_0_operand")
3026 (match_operand:<sseintvecmode> 3 "register_operand")))] 3123 (match_operand:<sseintvecmode> 3 "register_operand")))]
3027 "TARGET_AVX2" 3124 "TARGET_AVX2"
3028 { 3125 {
3029 ix86_expand_sse_movcc (operands[0], operands[3], 3126 ix86_expand_sse_movcc (operands[0], operands[3],
3030 operands[1], operands[2]); 3127 operands[1], operands[2]);
3033 3130
3034 (define_expand "vcond_mask_<mode><sseintvecmodelower>" 3131 (define_expand "vcond_mask_<mode><sseintvecmodelower>"
3035 [(set (match_operand:VI124_128 0 "register_operand") 3132 [(set (match_operand:VI124_128 0 "register_operand")
3036 (vec_merge:VI124_128 3133 (vec_merge:VI124_128
3037 (match_operand:VI124_128 1 "vector_operand") 3134 (match_operand:VI124_128 1 "vector_operand")
3038 (match_operand:VI124_128 2 "vector_move_operand") 3135 (match_operand:VI124_128 2 "nonimm_or_0_operand")
3039 (match_operand:<sseintvecmode> 3 "register_operand")))] 3136 (match_operand:<sseintvecmode> 3 "register_operand")))]
3040 "TARGET_SSE2" 3137 "TARGET_SSE2"
3041 { 3138 {
3042 ix86_expand_sse_movcc (operands[0], operands[3], 3139 ix86_expand_sse_movcc (operands[0], operands[3],
3043 operands[1], operands[2]); 3140 operands[1], operands[2]);
3046 3143
3047 (define_expand "vcond_mask_v2div2di" 3144 (define_expand "vcond_mask_v2div2di"
3048 [(set (match_operand:V2DI 0 "register_operand") 3145 [(set (match_operand:V2DI 0 "register_operand")
3049 (vec_merge:V2DI 3146 (vec_merge:V2DI
3050 (match_operand:V2DI 1 "vector_operand") 3147 (match_operand:V2DI 1 "vector_operand")
3051 (match_operand:V2DI 2 "vector_move_operand") 3148 (match_operand:V2DI 2 "nonimm_or_0_operand")
3052 (match_operand:V2DI 3 "register_operand")))] 3149 (match_operand:V2DI 3 "register_operand")))]
3053 "TARGET_SSE4_2" 3150 "TARGET_SSE4_2"
3054 { 3151 {
3055 ix86_expand_sse_movcc (operands[0], operands[3], 3152 ix86_expand_sse_movcc (operands[0], operands[3],
3056 operands[1], operands[2]); 3153 operands[1], operands[2]);
3059 3156
3060 (define_expand "vcond_mask_<mode><sseintvecmodelower>" 3157 (define_expand "vcond_mask_<mode><sseintvecmodelower>"
3061 [(set (match_operand:VF_256 0 "register_operand") 3158 [(set (match_operand:VF_256 0 "register_operand")
3062 (vec_merge:VF_256 3159 (vec_merge:VF_256
3063 (match_operand:VF_256 1 "nonimmediate_operand") 3160 (match_operand:VF_256 1 "nonimmediate_operand")
3064 (match_operand:VF_256 2 "vector_move_operand") 3161 (match_operand:VF_256 2 "nonimm_or_0_operand")
3065 (match_operand:<sseintvecmode> 3 "register_operand")))] 3162 (match_operand:<sseintvecmode> 3 "register_operand")))]
3066 "TARGET_AVX" 3163 "TARGET_AVX"
3067 { 3164 {
3068 ix86_expand_sse_movcc (operands[0], operands[3], 3165 ix86_expand_sse_movcc (operands[0], operands[3],
3069 operands[1], operands[2]); 3166 operands[1], operands[2]);
3072 3169
3073 (define_expand "vcond_mask_<mode><sseintvecmodelower>" 3170 (define_expand "vcond_mask_<mode><sseintvecmodelower>"
3074 [(set (match_operand:VF_128 0 "register_operand") 3171 [(set (match_operand:VF_128 0 "register_operand")
3075 (vec_merge:VF_128 3172 (vec_merge:VF_128
3076 (match_operand:VF_128 1 "vector_operand") 3173 (match_operand:VF_128 1 "vector_operand")
3077 (match_operand:VF_128 2 "vector_move_operand") 3174 (match_operand:VF_128 2 "nonimm_or_0_operand")
3078 (match_operand:<sseintvecmode> 3 "register_operand")))] 3175 (match_operand:<sseintvecmode> 3 "register_operand")))]
3079 "TARGET_SSE" 3176 "TARGET_SSE"
3080 { 3177 {
3081 ix86_expand_sse_movcc (operands[0], operands[3], 3178 ix86_expand_sse_movcc (operands[0], operands[3],
3082 operands[1], operands[2]); 3179 operands[1], operands[2]);
3209 [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") 3306 [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v")
3210 (any_logic:VF_128_256 3307 (any_logic:VF_128_256
3211 (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") 3308 (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v")
3212 (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] 3309 (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))]
3213 "TARGET_SSE && <mask_avx512vl_condition> 3310 "TARGET_SSE && <mask_avx512vl_condition>
3214 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 3311 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3215 { 3312 {
3216 static char buf[128]; 3313 static char buf[128];
3217 const char *ops; 3314 const char *ops;
3218 const char *suffix; 3315 const char *suffix;
3219 3316
3273 (define_insn "*<code><mode>3<mask_name>" 3370 (define_insn "*<code><mode>3<mask_name>"
3274 [(set (match_operand:VF_512 0 "register_operand" "=v") 3371 [(set (match_operand:VF_512 0 "register_operand" "=v")
3275 (any_logic:VF_512 3372 (any_logic:VF_512
3276 (match_operand:VF_512 1 "nonimmediate_operand" "%v") 3373 (match_operand:VF_512 1 "nonimmediate_operand" "%v")
3277 (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] 3374 (match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
3278 "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 3375 "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3279 { 3376 {
3280 static char buf[128]; 3377 static char buf[128];
3281 const char *ops; 3378 const char *ops;
3282 const char *suffix; 3379 const char *suffix;
3283 3380
3527 (define_insn "*<code>tf3" 3624 (define_insn "*<code>tf3"
3528 [(set (match_operand:TF 0 "register_operand" "=x,x,v,v") 3625 [(set (match_operand:TF 0 "register_operand" "=x,x,v,v")
3529 (any_logic:TF 3626 (any_logic:TF
3530 (match_operand:TF 1 "vector_operand" "%0,x,v,v") 3627 (match_operand:TF 1 "vector_operand" "%0,x,v,v")
3531 (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))] 3628 (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
3532 "TARGET_SSE 3629 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3533 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
3534 { 3630 {
3535 static char buf[128]; 3631 static char buf[128];
3536 const char *ops; 3632 const char *ops;
3537 const char *tmp 3633 const char *tmp
3538 = (which_alternative >= 2 ? "p<logic>q" 3634 = (which_alternative >= 2 ? "p<logic>q"
3653 (fma:FMAMODE_AVX512 3749 (fma:FMAMODE_AVX512
3654 (match_operand:FMAMODE_AVX512 1 "nonimmediate_operand") 3750 (match_operand:FMAMODE_AVX512 1 "nonimmediate_operand")
3655 (match_operand:FMAMODE_AVX512 2 "nonimmediate_operand") 3751 (match_operand:FMAMODE_AVX512 2 "nonimmediate_operand")
3656 (match_operand:FMAMODE_AVX512 3 "nonimmediate_operand")))]) 3752 (match_operand:FMAMODE_AVX512 3 "nonimmediate_operand")))])
3657 3753
3754 (define_expand "fma4i_fmsub_<mode>"
3755 [(set (match_operand:FMAMODE_AVX512 0 "register_operand")
3756 (fma:FMAMODE_AVX512
3757 (match_operand:FMAMODE_AVX512 1 "nonimmediate_operand")
3758 (match_operand:FMAMODE_AVX512 2 "nonimmediate_operand")
3759 (neg:FMAMODE_AVX512
3760 (match_operand:FMAMODE_AVX512 3 "nonimmediate_operand"))))])
3761
3762 (define_expand "fma4i_fnmadd_<mode>"
3763 [(set (match_operand:FMAMODE_AVX512 0 "register_operand")
3764 (fma:FMAMODE_AVX512
3765 (neg:FMAMODE_AVX512
3766 (match_operand:FMAMODE_AVX512 1 "nonimmediate_operand"))
3767 (match_operand:FMAMODE_AVX512 2 "nonimmediate_operand")
3768 (match_operand:FMAMODE_AVX512 3 "nonimmediate_operand")))])
3769
3770 (define_expand "fma4i_fnmsub_<mode>"
3771 [(set (match_operand:FMAMODE_AVX512 0 "register_operand")
3772 (fma:FMAMODE_AVX512
3773 (neg:FMAMODE_AVX512
3774 (match_operand:FMAMODE_AVX512 1 "nonimmediate_operand"))
3775 (match_operand:FMAMODE_AVX512 2 "nonimmediate_operand")
3776 (neg:FMAMODE_AVX512
3777 (match_operand:FMAMODE_AVX512 3 "nonimmediate_operand"))))])
3778
3658 (define_expand "<avx512>_fmadd_<mode>_maskz<round_expand_name>" 3779 (define_expand "<avx512>_fmadd_<mode>_maskz<round_expand_name>"
3659 [(match_operand:VF_AVX512VL 0 "register_operand") 3780 [(match_operand:VF_AVX512VL 0 "register_operand")
3660 (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>") 3781 (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
3661 (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>") 3782 (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
3662 (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>") 3783 (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
3700 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" 3821 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
3701 "@ 3822 "@
3702 vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} 3823 vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
3703 vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} 3824 vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
3704 vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" 3825 vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
3826 [(set_attr "type" "ssemuladd")
3827 (set_attr "mode" "<MODE>")])
3828
3829 (define_insn "*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1"
3830 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3831 (fma:VF_AVX512
3832 (match_operand:VF_AVX512 1 "register_operand" "0,v")
3833 (match_operand:VF_AVX512 2 "register_operand" "v,0")
3834 (vec_duplicate:VF_AVX512
3835 (match_operand:<ssescalarmode> 3 "memory_operand" "m,m"))))]
3836 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3837 "vfmadd213<ssemodesuffix>\t{%3<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<avx512bcst>}"
3838 [(set_attr "type" "ssemuladd")
3839 (set_attr "mode" "<MODE>")])
3840
3841 (define_insn "*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_2"
3842 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3843 (fma:VF_AVX512
3844 (vec_duplicate:VF_AVX512
3845 (match_operand:<ssescalarmode> 1 "memory_operand" "m,m"))
3846 (match_operand:VF_AVX512 2 "register_operand" "0,v")
3847 (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
3848 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3849 "@
3850 vfmadd132<ssemodesuffix>\t{%1<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %1<avx512bcst>}
3851 vfmadd231<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %1<avx512bcst>}"
3852 [(set_attr "type" "ssemuladd")
3853 (set_attr "mode" "<MODE>")])
3854
3855 (define_insn "*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_3"
3856 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3857 (fma:VF_AVX512
3858 (match_operand:VF_AVX512 1 "register_operand" "0,v")
3859 (vec_duplicate:VF_AVX512
3860 (match_operand:<ssescalarmode> 2 "memory_operand" "m,m"))
3861 (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
3862 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3863 "@
3864 vfmadd132<ssemodesuffix>\t{%2<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<avx512bcst>}
3865 vfmadd231<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<avx512bcst>}"
3705 [(set_attr "type" "ssemuladd") 3866 [(set_attr "type" "ssemuladd")
3706 (set_attr "mode" "<MODE>")]) 3867 (set_attr "mode" "<MODE>")])
3707 3868
3708 (define_insn "<avx512>_fmadd_<mode>_mask<round_name>" 3869 (define_insn "<avx512>_fmadd_<mode>_mask<round_name>"
3709 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v") 3870 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
3751 vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" 3912 vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
3752 [(set_attr "isa" "fma,fma,fma,fma4,fma4") 3913 [(set_attr "isa" "fma,fma,fma,fma4,fma4")
3753 (set_attr "type" "ssemuladd") 3914 (set_attr "type" "ssemuladd")
3754 (set_attr "mode" "<MODE>")]) 3915 (set_attr "mode" "<MODE>")])
3755 3916
3917 (define_expand "<avx512>_fmsub_<mode>_maskz<round_expand_name>"
3918 [(match_operand:VF_AVX512VL 0 "register_operand")
3919 (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
3920 (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
3921 (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
3922 (match_operand:<avx512fmaskmode> 4 "register_operand")]
3923 "TARGET_AVX512F && <round_mode512bit_condition>"
3924 {
3925 emit_insn (gen_fma_fmsub_<mode>_maskz_1<round_expand_name> (
3926 operands[0], operands[1], operands[2], operands[3],
3927 CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>));
3928 DONE;
3929 })
3930
3756 (define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>" 3931 (define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"
3757 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v") 3932 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v")
3758 (fma:VF_SF_AVX512VL 3933 (fma:VF_SF_AVX512VL
3759 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v") 3934 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
3760 (match_operand:VF_SF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") 3935 (match_operand:VF_SF_AVX512VL 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>")
3763 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" 3938 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
3764 "@ 3939 "@
3765 vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} 3940 vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
3766 vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} 3941 vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
3767 vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" 3942 vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
3943 [(set_attr "type" "ssemuladd")
3944 (set_attr "mode" "<MODE>")])
3945
3946 (define_insn "*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1"
3947 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3948 (fma:VF_AVX512
3949 (match_operand:VF_AVX512 1 "register_operand" "0,v")
3950 (match_operand:VF_AVX512 2 "register_operand" "v,0")
3951 (neg:VF_AVX512
3952 (vec_duplicate:VF_AVX512
3953 (match_operand:<ssescalarmode> 3 "memory_operand" "m,m")))))]
3954 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3955 "vfmsub213<ssemodesuffix>\t{%3<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<avx512bcst>}"
3956 [(set_attr "type" "ssemuladd")
3957 (set_attr "mode" "<MODE>")])
3958
3959 (define_insn "*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_2"
3960 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3961 (fma:VF_AVX512
3962 (vec_duplicate:VF_AVX512
3963 (match_operand:<ssescalarmode> 1 "memory_operand" "m,m"))
3964 (match_operand:VF_AVX512 2 "register_operand" "0,v")
3965 (neg:VF_AVX512
3966 (match_operand:VF_AVX512 3 "register_operand" "v,0"))))]
3967 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3968 "@
3969 vfmsub132<ssemodesuffix>\t{%1<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %1<avx512bcst>}
3970 vfmsub231<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %1<avx512bcst>}"
3971 [(set_attr "type" "ssemuladd")
3972 (set_attr "mode" "<MODE>")])
3973
3974 (define_insn "*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_3"
3975 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
3976 (fma:VF_AVX512
3977 (match_operand:VF_AVX512 1 "register_operand" "0,v")
3978 (vec_duplicate:VF_AVX512
3979 (match_operand:<ssescalarmode> 2 "memory_operand" "m,m"))
3980 (neg:VF_AVX512
3981 (match_operand:VF_AVX512 3 "nonimmediate_operand" "v,0"))))]
3982 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
3983 "@
3984 vfmsub132<ssemodesuffix>\t{%2<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<avx512bcst>}
3985 vfmsub231<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<avx512bcst>}"
3768 [(set_attr "type" "ssemuladd") 3986 [(set_attr "type" "ssemuladd")
3769 (set_attr "mode" "<MODE>")]) 3987 (set_attr "mode" "<MODE>")])
3770 3988
3771 (define_insn "<avx512>_fmsub_<mode>_mask<round_name>" 3989 (define_insn "<avx512>_fmsub_<mode>_mask<round_name>"
3772 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v") 3990 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
3816 vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" 4034 vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
3817 [(set_attr "isa" "fma,fma,fma,fma4,fma4") 4035 [(set_attr "isa" "fma,fma,fma,fma4,fma4")
3818 (set_attr "type" "ssemuladd") 4036 (set_attr "type" "ssemuladd")
3819 (set_attr "mode" "<MODE>")]) 4037 (set_attr "mode" "<MODE>")])
3820 4038
4039 (define_expand "<avx512>_fnmadd_<mode>_maskz<round_expand_name>"
4040 [(match_operand:VF_AVX512VL 0 "register_operand")
4041 (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
4042 (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
4043 (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
4044 (match_operand:<avx512fmaskmode> 4 "register_operand")]
4045 "TARGET_AVX512F && <round_mode512bit_condition>"
4046 {
4047 emit_insn (gen_fma_fnmadd_<mode>_maskz_1<round_expand_name> (
4048 operands[0], operands[1], operands[2], operands[3],
4049 CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>));
4050 DONE;
4051 })
4052
3821 (define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>" 4053 (define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"
3822 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v") 4054 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v")
3823 (fma:VF_SF_AVX512VL 4055 (fma:VF_SF_AVX512VL
3824 (neg:VF_SF_AVX512VL 4056 (neg:VF_SF_AVX512VL
3825 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")) 4057 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v"))
3828 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" 4060 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
3829 "@ 4061 "@
3830 vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} 4062 vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
3831 vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} 4063 vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
3832 vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" 4064 vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
4065 [(set_attr "type" "ssemuladd")
4066 (set_attr "mode" "<MODE>")])
4067
4068 (define_insn "*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1"
4069 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4070 (fma:VF_AVX512
4071 (neg:VF_AVX512
4072 (match_operand:VF_AVX512 1 "register_operand" "0,v"))
4073 (match_operand:VF_AVX512 2 "register_operand" "v,0")
4074 (vec_duplicate:VF_AVX512
4075 (match_operand:<ssescalarmode> 3 "memory_operand" "m,m"))))]
4076 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4077 "vfnmadd213<ssemodesuffix>\t{%3<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<avx512bcst>}"
4078 [(set_attr "type" "ssemuladd")
4079 (set_attr "mode" "<MODE>")])
4080
4081 (define_insn "*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_2"
4082 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4083 (fma:VF_AVX512
4084 (neg:VF_AVX512
4085 (vec_duplicate:VF_AVX512
4086 (match_operand:<ssescalarmode> 1 "memory_operand" "m,m")))
4087 (match_operand:VF_AVX512 2 "register_operand" "0,v")
4088 (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
4089 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4090 "@
4091 vfnmadd132<ssemodesuffix>\t{%1<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %1<avx512bcst>}
4092 vfnmadd231<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %1<avx512bcst>}"
4093 [(set_attr "type" "ssemuladd")
4094 (set_attr "mode" "<MODE>")])
4095
4096 (define_insn "*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_3"
4097 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4098 (fma:VF_AVX512
4099 (neg:VF_AVX512
4100 (match_operand:VF_AVX512 1 "register_operand" "0,v"))
4101 (vec_duplicate:VF_AVX512
4102 (match_operand:<ssescalarmode> 2 "memory_operand" "m,m"))
4103 (match_operand:VF_AVX512 3 "register_operand" "v,0")))]
4104 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4105 "@
4106 vfnmadd132<ssemodesuffix>\t{%2<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<avx512bcst>}
4107 vfnmadd231<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<avx512bcst>}"
3833 [(set_attr "type" "ssemuladd") 4108 [(set_attr "type" "ssemuladd")
3834 (set_attr "mode" "<MODE>")]) 4109 (set_attr "mode" "<MODE>")])
3835 4110
3836 (define_insn "<avx512>_fnmadd_<mode>_mask<round_name>" 4111 (define_insn "<avx512>_fnmadd_<mode>_mask<round_name>"
3837 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v") 4112 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
3882 vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" 4157 vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
3883 [(set_attr "isa" "fma,fma,fma,fma4,fma4") 4158 [(set_attr "isa" "fma,fma,fma,fma4,fma4")
3884 (set_attr "type" "ssemuladd") 4159 (set_attr "type" "ssemuladd")
3885 (set_attr "mode" "<MODE>")]) 4160 (set_attr "mode" "<MODE>")])
3886 4161
4162 (define_expand "<avx512>_fnmsub_<mode>_maskz<round_expand_name>"
4163 [(match_operand:VF_AVX512VL 0 "register_operand")
4164 (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
4165 (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
4166 (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
4167 (match_operand:<avx512fmaskmode> 4 "register_operand")]
4168 "TARGET_AVX512F && <round_mode512bit_condition>"
4169 {
4170 emit_insn (gen_fma_fnmsub_<mode>_maskz_1<round_expand_name> (
4171 operands[0], operands[1], operands[2], operands[3],
4172 CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>));
4173 DONE;
4174 })
4175
3887 (define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>" 4176 (define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"
3888 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v") 4177 [(set (match_operand:VF_SF_AVX512VL 0 "register_operand" "=v,v,v")
3889 (fma:VF_SF_AVX512VL 4178 (fma:VF_SF_AVX512VL
3890 (neg:VF_SF_AVX512VL 4179 (neg:VF_SF_AVX512VL
3891 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")) 4180 (match_operand:VF_SF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v"))
3895 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" 4184 "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
3896 "@ 4185 "@
3897 vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} 4186 vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
3898 vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} 4187 vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
3899 vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" 4188 vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
4189 [(set_attr "type" "ssemuladd")
4190 (set_attr "mode" "<MODE>")])
4191
4192 (define_insn "*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1"
4193 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4194 (fma:VF_AVX512
4195 (neg:VF_AVX512
4196 (match_operand:VF_AVX512 1 "register_operand" "0,v"))
4197 (match_operand:VF_AVX512 2 "register_operand" "v,0")
4198 (neg:VF_AVX512
4199 (vec_duplicate:VF_AVX512
4200 (match_operand:<ssescalarmode> 3 "memory_operand" "m,m")))))]
4201 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4202 "vfnmsub213<ssemodesuffix>\t{%3<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<avx512bcst>}"
4203 [(set_attr "type" "ssemuladd")
4204 (set_attr "mode" "<MODE>")])
4205
4206 (define_insn "*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_2"
4207 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4208 (fma:VF_AVX512
4209 (neg:VF_AVX512
4210 (vec_duplicate:VF_AVX512
4211 (match_operand:<ssescalarmode> 1 "memory_operand" "m,m")))
4212 (match_operand:VF_AVX512 2 "register_operand" "0,v")
4213 (neg:VF_AVX512
4214 (match_operand:VF_AVX512 3 "register_operand" "v,0"))))]
4215 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4216 "@
4217 vfnmsub132<ssemodesuffix>\t{%1<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %1<avx512bcst>}
4218 vfnmsub231<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %1<avx512bcst>}"
4219 [(set_attr "type" "ssemuladd")
4220 (set_attr "mode" "<MODE>")])
4221
4222 (define_insn "*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_3"
4223 [(set (match_operand:VF_AVX512 0 "register_operand" "=v,v")
4224 (fma:VF_AVX512
4225 (neg:VF_AVX512
4226 (match_operand:VF_AVX512 1 "register_operand" "0,v"))
4227 (vec_duplicate:VF_AVX512
4228 (match_operand:<ssescalarmode> 2 "memory_operand" "m,m"))
4229 (neg:VF_AVX512
4230 (match_operand:VF_AVX512 3 "register_operand" "v,0"))))]
4231 "TARGET_AVX512F && <sd_mask_mode512bit_condition>"
4232 "@
4233 vfnmsub132<ssemodesuffix>\t{%2<avx512bcst>, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<avx512bcst>}
4234 vfnmsub231<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<avx512bcst>}"
3900 [(set_attr "type" "ssemuladd") 4235 [(set_attr "type" "ssemuladd")
3901 (set_attr "mode" "<MODE>")]) 4236 (set_attr "mode" "<MODE>")])
3902 4237
3903 (define_insn "<avx512>_fnmsub_<mode>_mask<round_name>" 4238 (define_insn "<avx512>_fnmsub_<mode>_mask<round_name>"
3904 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v") 4239 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
4114 (match_operand:VF_128 3 "<round_nimm_predicate>")) 4449 (match_operand:VF_128 3 "<round_nimm_predicate>"))
4115 (match_dup 1) 4450 (match_dup 1)
4116 (const_int 1)))] 4451 (const_int 1)))]
4117 "TARGET_FMA") 4452 "TARGET_FMA")
4118 4453
4454 (define_expand "fmai_vmfmsub_<mode><round_name>"
4455 [(set (match_operand:VF_128 0 "register_operand")
4456 (vec_merge:VF_128
4457 (fma:VF_128
4458 (match_operand:VF_128 1 "<round_nimm_predicate>")
4459 (match_operand:VF_128 2 "<round_nimm_predicate>")
4460 (neg:VF_128
4461 (match_operand:VF_128 3 "<round_nimm_predicate>")))
4462 (match_dup 1)
4463 (const_int 1)))]
4464 "TARGET_FMA")
4465
4466 (define_expand "fmai_vmfnmadd_<mode><round_name>"
4467 [(set (match_operand:VF_128 0 "register_operand")
4468 (vec_merge:VF_128
4469 (fma:VF_128
4470 (neg:VF_128
4471 (match_operand:VF_128 2 "<round_nimm_predicate>"))
4472 (match_operand:VF_128 1 "<round_nimm_predicate>")
4473 (match_operand:VF_128 3 "<round_nimm_predicate>"))
4474 (match_dup 1)
4475 (const_int 1)))]
4476 "TARGET_FMA")
4477
4478 (define_expand "fmai_vmfnmsub_<mode><round_name>"
4479 [(set (match_operand:VF_128 0 "register_operand")
4480 (vec_merge:VF_128
4481 (fma:VF_128
4482 (neg:VF_128
4483 (match_operand:VF_128 2 "<round_nimm_predicate>"))
4484 (match_operand:VF_128 1 "<round_nimm_predicate>")
4485 (neg:VF_128
4486 (match_operand:VF_128 3 "<round_nimm_predicate>")))
4487 (match_dup 1)
4488 (const_int 1)))]
4489 "TARGET_FMA")
4490
4119 (define_insn "*fmai_fmadd_<mode>" 4491 (define_insn "*fmai_fmadd_<mode>"
4120 [(set (match_operand:VF_128 0 "register_operand" "=v,v") 4492 [(set (match_operand:VF_128 0 "register_operand" "=v,v")
4121 (vec_merge:VF_128 4493 (vec_merge:VF_128
4122 (fma:VF_128 4494 (fma:VF_128
4123 (match_operand:VF_128 1 "<round_nimm_predicate>" " 0, 0") 4495 (match_operand:VF_128 1 "<round_nimm_predicate>" " 0, 0")
4299 [(set_attr "type" "ssecvt") 4671 [(set_attr "type" "ssecvt")
4300 (set_attr "unit" "mmx") 4672 (set_attr "unit" "mmx")
4301 (set_attr "prefix_rep" "0") 4673 (set_attr "prefix_rep" "0")
4302 (set_attr "mode" "SF")]) 4674 (set_attr "mode" "SF")])
4303 4675
4304 (define_insn "sse_cvtsi2ss<round_name>" 4676 (define_insn "sse_cvtsi2ss<rex64namesuffix><round_name>"
4305 [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") 4677 [(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
4306 (vec_merge:V4SF 4678 (vec_merge:V4SF
4307 (vec_duplicate:V4SF 4679 (vec_duplicate:V4SF
4308 (float:SF (match_operand:SI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) 4680 (float:SF (match_operand:SWI48 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>")))
4309 (match_operand:V4SF 1 "register_operand" "0,0,v") 4681 (match_operand:V4SF 1 "register_operand" "0,0,v")
4310 (const_int 1)))] 4682 (const_int 1)))]
4311 "TARGET_SSE" 4683 "TARGET_SSE"
4312 "@ 4684 "@
4313 cvtsi2ss\t{%2, %0|%0, %2} 4685 cvtsi2ss<rex64suffix>\t{%2, %0|%0, %2}
4314 cvtsi2ss\t{%2, %0|%0, %2} 4686 cvtsi2ss<rex64suffix>\t{%2, %0|%0, %2}
4315 vcvtsi2ss\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}" 4687 vcvtsi2ss<rex64suffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
4316 [(set_attr "isa" "noavx,noavx,avx") 4688 [(set_attr "isa" "noavx,noavx,avx")
4317 (set_attr "type" "sseicvt") 4689 (set_attr "type" "sseicvt")
4318 (set_attr "athlon_decode" "vector,double,*") 4690 (set_attr "athlon_decode" "vector,double,*")
4319 (set_attr "amdfam10_decode" "vector,double,*") 4691 (set_attr "amdfam10_decode" "vector,double,*")
4320 (set_attr "bdver1_decode" "double,direct,*") 4692 (set_attr "bdver1_decode" "double,direct,*")
4321 (set_attr "btver2_decode" "double,double,double") 4693 (set_attr "btver2_decode" "double,double,double")
4322 (set_attr "znver1_decode" "double,double,double") 4694 (set_attr "znver1_decode" "double,double,double")
4695 (set (attr "length_vex")
4696 (if_then_else
4697 (and (match_test "<MODE>mode == DImode")
4698 (eq_attr "alternative" "2"))
4699 (const_string "4")
4700 (const_string "*")))
4701 (set (attr "prefix_rex")
4702 (if_then_else
4703 (and (match_test "<MODE>mode == DImode")
4704 (eq_attr "alternative" "0,1"))
4705 (const_string "1")
4706 (const_string "*")))
4323 (set_attr "prefix" "orig,orig,maybe_evex") 4707 (set_attr "prefix" "orig,orig,maybe_evex")
4324 (set_attr "mode" "SF")]) 4708 (set_attr "mode" "SF")])
4325 4709
4326 (define_insn "sse_cvtsi2ssq<round_name>" 4710 (define_insn "sse_cvtss2si<rex64namesuffix><round_name>"
4327 [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") 4711 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4328 (vec_merge:V4SF 4712 (unspec:SWI48
4329 (vec_duplicate:V4SF
4330 (float:SF (match_operand:DI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>")))
4331 (match_operand:V4SF 1 "register_operand" "0,0,v")
4332 (const_int 1)))]
4333 "TARGET_SSE && TARGET_64BIT"
4334 "@
4335 cvtsi2ssq\t{%2, %0|%0, %2}
4336 cvtsi2ssq\t{%2, %0|%0, %2}
4337 vcvtsi2ssq\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
4338 [(set_attr "isa" "noavx,noavx,avx")
4339 (set_attr "type" "sseicvt")
4340 (set_attr "athlon_decode" "vector,double,*")
4341 (set_attr "amdfam10_decode" "vector,double,*")
4342 (set_attr "bdver1_decode" "double,direct,*")
4343 (set_attr "btver2_decode" "double,double,double")
4344 (set_attr "length_vex" "*,*,4")
4345 (set_attr "prefix_rex" "1,1,*")
4346 (set_attr "prefix" "orig,orig,maybe_evex")
4347 (set_attr "mode" "SF")])
4348
4349 (define_insn "sse_cvtss2si<round_name>"
4350 [(set (match_operand:SI 0 "register_operand" "=r,r")
4351 (unspec:SI
4352 [(vec_select:SF 4713 [(vec_select:SF
4353 (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") 4714 (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>")
4354 (parallel [(const_int 0)]))] 4715 (parallel [(const_int 0)]))]
4355 UNSPEC_FIX_NOTRUNC))] 4716 UNSPEC_FIX_NOTRUNC))]
4356 "TARGET_SSE" 4717 "TARGET_SSE"
4357 "%vcvtss2si\t{<round_op2>%1, %0|%0, %k1<round_op2>}" 4718 "%vcvtss2si<rex64suffix>\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
4358 [(set_attr "type" "sseicvt") 4719 [(set_attr "type" "sseicvt")
4359 (set_attr "athlon_decode" "double,vector") 4720 (set_attr "athlon_decode" "double,vector")
4360 (set_attr "bdver1_decode" "double,double") 4721 (set_attr "bdver1_decode" "double,double")
4361 (set_attr "prefix_rep" "1") 4722 (set_attr "prefix_rep" "1")
4362 (set_attr "prefix" "maybe_vex") 4723 (set_attr "prefix" "maybe_vex")
4363 (set_attr "mode" "SI")]) 4724 (set_attr "mode" "<MODE>")])
4364 4725
4365 (define_insn "sse_cvtss2si_2" 4726 (define_insn "sse_cvtss2si<rex64namesuffix>_2"
4366 [(set (match_operand:SI 0 "register_operand" "=r,r") 4727 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4367 (unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "v,m")] 4728 (unspec:SWI48 [(match_operand:SF 1 "nonimmediate_operand" "v,m")]
4368 UNSPEC_FIX_NOTRUNC))] 4729 UNSPEC_FIX_NOTRUNC))]
4369 "TARGET_SSE" 4730 "TARGET_SSE"
4370 "%vcvtss2si\t{%1, %0|%0, %k1}" 4731 "%vcvtss2si<rex64suffix>\t{%1, %0|%0, %k1}"
4371 [(set_attr "type" "sseicvt") 4732 [(set_attr "type" "sseicvt")
4372 (set_attr "athlon_decode" "double,vector") 4733 (set_attr "athlon_decode" "double,vector")
4373 (set_attr "amdfam10_decode" "double,double") 4734 (set_attr "amdfam10_decode" "double,double")
4374 (set_attr "bdver1_decode" "double,double") 4735 (set_attr "bdver1_decode" "double,double")
4375 (set_attr "prefix_rep" "1") 4736 (set_attr "prefix_rep" "1")
4376 (set_attr "prefix" "maybe_vex") 4737 (set_attr "prefix" "maybe_vex")
4377 (set_attr "mode" "SI")]) 4738 (set_attr "mode" "<MODE>")])
4378 4739
4379 (define_insn "sse_cvtss2siq<round_name>" 4740 (define_insn "sse_cvttss2si<rex64namesuffix><round_saeonly_name>"
4380 [(set (match_operand:DI 0 "register_operand" "=r,r") 4741 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4381 (unspec:DI 4742 (fix:SWI48
4382 [(vec_select:SF 4743 (vec_select:SF
4383 (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") 4744 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint>")
4384 (parallel [(const_int 0)]))] 4745 (parallel [(const_int 0)]))))]
4385 UNSPEC_FIX_NOTRUNC))] 4746 "TARGET_SSE"
4386 "TARGET_SSE && TARGET_64BIT" 4747 "%vcvttss2si<rex64suffix>\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
4387 "%vcvtss2si{q}\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
4388 [(set_attr "type" "sseicvt")
4389 (set_attr "athlon_decode" "double,vector")
4390 (set_attr "bdver1_decode" "double,double")
4391 (set_attr "prefix_rep" "1")
4392 (set_attr "prefix" "maybe_vex")
4393 (set_attr "mode" "DI")])
4394
4395 (define_insn "sse_cvtss2siq_2"
4396 [(set (match_operand:DI 0 "register_operand" "=r,r")
4397 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "v,m")]
4398 UNSPEC_FIX_NOTRUNC))]
4399 "TARGET_SSE && TARGET_64BIT"
4400 "%vcvtss2si{q}\t{%1, %0|%0, %k1}"
4401 [(set_attr "type" "sseicvt") 4748 [(set_attr "type" "sseicvt")
4402 (set_attr "athlon_decode" "double,vector") 4749 (set_attr "athlon_decode" "double,vector")
4403 (set_attr "amdfam10_decode" "double,double") 4750 (set_attr "amdfam10_decode" "double,double")
4404 (set_attr "bdver1_decode" "double,double") 4751 (set_attr "bdver1_decode" "double,double")
4405 (set_attr "prefix_rep" "1") 4752 (set_attr "prefix_rep" "1")
4406 (set_attr "prefix" "maybe_vex") 4753 (set_attr "prefix" "maybe_vex")
4407 (set_attr "mode" "DI")]) 4754 (set_attr "mode" "<MODE>")])
4408
4409 (define_insn "sse_cvttss2si<round_saeonly_name>"
4410 [(set (match_operand:SI 0 "register_operand" "=r,r")
4411 (fix:SI
4412 (vec_select:SF
4413 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>")
4414 (parallel [(const_int 0)]))))]
4415 "TARGET_SSE"
4416 "%vcvttss2si\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
4417 [(set_attr "type" "sseicvt")
4418 (set_attr "athlon_decode" "double,vector")
4419 (set_attr "amdfam10_decode" "double,double")
4420 (set_attr "bdver1_decode" "double,double")
4421 (set_attr "prefix_rep" "1")
4422 (set_attr "prefix" "maybe_vex")
4423 (set_attr "mode" "SI")])
4424
4425 (define_insn "sse_cvttss2siq<round_saeonly_name>"
4426 [(set (match_operand:DI 0 "register_operand" "=r,r")
4427 (fix:DI
4428 (vec_select:SF
4429 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint>")
4430 (parallel [(const_int 0)]))))]
4431 "TARGET_SSE && TARGET_64BIT"
4432 "%vcvttss2si{q}\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
4433 [(set_attr "type" "sseicvt")
4434 (set_attr "athlon_decode" "double,vector")
4435 (set_attr "amdfam10_decode" "double,double")
4436 (set_attr "bdver1_decode" "double,double")
4437 (set_attr "prefix_rep" "1")
4438 (set_attr "prefix" "maybe_vex")
4439 (set_attr "mode" "DI")])
4440 4755
4441 (define_insn "cvtusi2<ssescalarmodesuffix>32<round_name>" 4756 (define_insn "cvtusi2<ssescalarmodesuffix>32<round_name>"
4442 [(set (match_operand:VF_128 0 "register_operand" "=v") 4757 [(set (match_operand:VF_128 0 "register_operand" "=v")
4443 (vec_merge:VF_128 4758 (vec_merge:VF_128
4444 (vec_duplicate:VF_128 4759 (vec_duplicate:VF_128
4459 (unsigned_float:<ssescalarmode> 4774 (unsigned_float:<ssescalarmode>
4460 (match_operand:DI 2 "<round_nimm_predicate>" "<round_constraint3>"))) 4775 (match_operand:DI 2 "<round_nimm_predicate>" "<round_constraint3>")))
4461 (match_operand:VF_128 1 "register_operand" "v") 4776 (match_operand:VF_128 1 "register_operand" "v")
4462 (const_int 1)))] 4777 (const_int 1)))]
4463 "TARGET_AVX512F && TARGET_64BIT" 4778 "TARGET_AVX512F && TARGET_64BIT"
4464 "vcvtusi2<ssescalarmodesuffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}" 4779 "vcvtusi2<ssescalarmodesuffix>{q}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
4465 [(set_attr "type" "sseicvt") 4780 [(set_attr "type" "sseicvt")
4466 (set_attr "prefix" "evex") 4781 (set_attr "prefix" "evex")
4467 (set_attr "mode" "<ssescalarmode>")]) 4782 (set_attr "mode" "<ssescalarmode>")])
4468 4783
4469 (define_insn "float<sseintvecmodelower><mode>2<mask_name><round_name>" 4784 (define_insn "float<sseintvecmodelower><mode>2<mask_name><round_name>"
4739 (set_attr "length_vex" "*,*,4") 5054 (set_attr "length_vex" "*,*,4")
4740 (set_attr "prefix_rex" "1,1,*") 5055 (set_attr "prefix_rex" "1,1,*")
4741 (set_attr "prefix" "orig,orig,maybe_evex") 5056 (set_attr "prefix" "orig,orig,maybe_evex")
4742 (set_attr "mode" "DF")]) 5057 (set_attr "mode" "DF")])
4743 5058
4744 (define_insn "avx512f_vcvtss2usi<round_name>" 5059 (define_insn "avx512f_vcvtss2usi<rex64namesuffix><round_name>"
4745 [(set (match_operand:SI 0 "register_operand" "=r") 5060 [(set (match_operand:SWI48 0 "register_operand" "=r")
4746 (unspec:SI 5061 (unspec:SWI48
4747 [(vec_select:SF 5062 [(vec_select:SF
4748 (match_operand:V4SF 1 "<round_nimm_predicate>" "<round_constraint>") 5063 (match_operand:V4SF 1 "<round_nimm_predicate>" "<round_constraint>")
4749 (parallel [(const_int 0)]))] 5064 (parallel [(const_int 0)]))]
4750 UNSPEC_UNSIGNED_FIX_NOTRUNC))] 5065 UNSPEC_UNSIGNED_FIX_NOTRUNC))]
4751 "TARGET_AVX512F" 5066 "TARGET_AVX512F"
4752 "vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}" 5067 "vcvtss2usi\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
4753 [(set_attr "type" "sseicvt") 5068 [(set_attr "type" "sseicvt")
4754 (set_attr "prefix" "evex") 5069 (set_attr "prefix" "evex")
4755 (set_attr "mode" "SI")]) 5070 (set_attr "mode" "<MODE>")])
4756 5071
4757 (define_insn "avx512f_vcvtss2usiq<round_name>" 5072 (define_insn "avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>"
4758 [(set (match_operand:DI 0 "register_operand" "=r") 5073 [(set (match_operand:SWI48 0 "register_operand" "=r")
4759 (unspec:DI 5074 (unsigned_fix:SWI48
4760 [(vec_select:SF
4761 (match_operand:V4SF 1 "<round_nimm_predicate>" "<round_constraint>")
4762 (parallel [(const_int 0)]))]
4763 UNSPEC_UNSIGNED_FIX_NOTRUNC))]
4764 "TARGET_AVX512F && TARGET_64BIT"
4765 "vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
4766 [(set_attr "type" "sseicvt")
4767 (set_attr "prefix" "evex")
4768 (set_attr "mode" "DI")])
4769
4770 (define_insn "avx512f_vcvttss2usi<round_saeonly_name>"
4771 [(set (match_operand:SI 0 "register_operand" "=r")
4772 (unsigned_fix:SI
4773 (vec_select:SF 5075 (vec_select:SF
4774 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") 5076 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
4775 (parallel [(const_int 0)]))))] 5077 (parallel [(const_int 0)]))))]
4776 "TARGET_AVX512F" 5078 "TARGET_AVX512F"
4777 "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" 5079 "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
4778 [(set_attr "type" "sseicvt") 5080 [(set_attr "type" "sseicvt")
4779 (set_attr "prefix" "evex") 5081 (set_attr "prefix" "evex")
4780 (set_attr "mode" "SI")]) 5082 (set_attr "mode" "<MODE>")])
4781 5083
4782 (define_insn "avx512f_vcvttss2usiq<round_saeonly_name>" 5084 (define_insn "avx512f_vcvtsd2usi<rex64namesuffix><round_name>"
4783 [(set (match_operand:DI 0 "register_operand" "=r") 5085 [(set (match_operand:SWI48 0 "register_operand" "=r")
4784 (unsigned_fix:DI 5086 (unspec:SWI48
4785 (vec_select:SF
4786 (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
4787 (parallel [(const_int 0)]))))]
4788 "TARGET_AVX512F && TARGET_64BIT"
4789 "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
4790 [(set_attr "type" "sseicvt")
4791 (set_attr "prefix" "evex")
4792 (set_attr "mode" "DI")])
4793
4794 (define_insn "avx512f_vcvtsd2usi<round_name>"
4795 [(set (match_operand:SI 0 "register_operand" "=r")
4796 (unspec:SI
4797 [(vec_select:DF 5087 [(vec_select:DF
4798 (match_operand:V2DF 1 "<round_nimm_predicate>" "<round_constraint>") 5088 (match_operand:V2DF 1 "<round_nimm_predicate>" "<round_constraint>")
4799 (parallel [(const_int 0)]))] 5089 (parallel [(const_int 0)]))]
4800 UNSPEC_UNSIGNED_FIX_NOTRUNC))] 5090 UNSPEC_UNSIGNED_FIX_NOTRUNC))]
4801 "TARGET_AVX512F" 5091 "TARGET_AVX512F"
4802 "vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}" 5092 "vcvtsd2usi\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
4803 [(set_attr "type" "sseicvt") 5093 [(set_attr "type" "sseicvt")
4804 (set_attr "prefix" "evex") 5094 (set_attr "prefix" "evex")
4805 (set_attr "mode" "SI")]) 5095 (set_attr "mode" "<MODE>")])
4806 5096
4807 (define_insn "avx512f_vcvtsd2usiq<round_name>" 5097 (define_insn "avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>"
4808 [(set (match_operand:DI 0 "register_operand" "=r") 5098 [(set (match_operand:SWI48 0 "register_operand" "=r")
4809 (unspec:DI 5099 (unsigned_fix:SWI48
4810 [(vec_select:DF
4811 (match_operand:V2DF 1 "<round_nimm_predicate>" "<round_constraint>")
4812 (parallel [(const_int 0)]))]
4813 UNSPEC_UNSIGNED_FIX_NOTRUNC))]
4814 "TARGET_AVX512F && TARGET_64BIT"
4815 "vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
4816 [(set_attr "type" "sseicvt")
4817 (set_attr "prefix" "evex")
4818 (set_attr "mode" "DI")])
4819
4820 (define_insn "avx512f_vcvttsd2usi<round_saeonly_name>"
4821 [(set (match_operand:SI 0 "register_operand" "=r")
4822 (unsigned_fix:SI
4823 (vec_select:DF 5100 (vec_select:DF
4824 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") 5101 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
4825 (parallel [(const_int 0)]))))] 5102 (parallel [(const_int 0)]))))]
4826 "TARGET_AVX512F" 5103 "TARGET_AVX512F"
4827 "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" 5104 "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
4828 [(set_attr "type" "sseicvt") 5105 [(set_attr "type" "sseicvt")
4829 (set_attr "prefix" "evex") 5106 (set_attr "prefix" "evex")
4830 (set_attr "mode" "SI")]) 5107 (set_attr "mode" "<MODE>")])
4831 5108
4832 (define_insn "avx512f_vcvttsd2usiq<round_saeonly_name>" 5109 (define_insn "sse2_cvtsd2si<rex64namesuffix><round_name>"
4833 [(set (match_operand:DI 0 "register_operand" "=r") 5110 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4834 (unsigned_fix:DI 5111 (unspec:SWI48
4835 (vec_select:DF
4836 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
4837 (parallel [(const_int 0)]))))]
4838 "TARGET_AVX512F && TARGET_64BIT"
4839 "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
4840 [(set_attr "type" "sseicvt")
4841 (set_attr "prefix" "evex")
4842 (set_attr "mode" "DI")])
4843
4844 (define_insn "sse2_cvtsd2si<round_name>"
4845 [(set (match_operand:SI 0 "register_operand" "=r,r")
4846 (unspec:SI
4847 [(vec_select:DF 5112 [(vec_select:DF
4848 (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") 5113 (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>")
4849 (parallel [(const_int 0)]))] 5114 (parallel [(const_int 0)]))]
4850 UNSPEC_FIX_NOTRUNC))] 5115 UNSPEC_FIX_NOTRUNC))]
4851 "TARGET_SSE2" 5116 "TARGET_SSE2"
4852 "%vcvtsd2si\t{<round_op2>%1, %0|%0, %q1<round_op2>}" 5117 "%vcvtsd2si<rex64suffix>\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
4853 [(set_attr "type" "sseicvt") 5118 [(set_attr "type" "sseicvt")
4854 (set_attr "athlon_decode" "double,vector") 5119 (set_attr "athlon_decode" "double,vector")
4855 (set_attr "bdver1_decode" "double,double") 5120 (set_attr "bdver1_decode" "double,double")
4856 (set_attr "btver2_decode" "double,double") 5121 (set_attr "btver2_decode" "double,double")
4857 (set_attr "prefix_rep" "1") 5122 (set_attr "prefix_rep" "1")
4858 (set_attr "prefix" "maybe_vex") 5123 (set_attr "prefix" "maybe_vex")
4859 (set_attr "mode" "SI")]) 5124 (set_attr "mode" "<MODE>")])
4860 5125
4861 (define_insn "sse2_cvtsd2si_2" 5126 (define_insn "sse2_cvtsd2si<rex64namesuffix>_2"
4862 [(set (match_operand:SI 0 "register_operand" "=r,r") 5127 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4863 (unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "v,m")] 5128 (unspec:SWI48 [(match_operand:DF 1 "nonimmediate_operand" "v,m")]
4864 UNSPEC_FIX_NOTRUNC))] 5129 UNSPEC_FIX_NOTRUNC))]
4865 "TARGET_SSE2" 5130 "TARGET_SSE2"
4866 "%vcvtsd2si\t{%1, %0|%0, %q1}" 5131 "%vcvtsd2si<rex64suffix>\t{%1, %0|%0, %q1}"
4867 [(set_attr "type" "sseicvt") 5132 [(set_attr "type" "sseicvt")
4868 (set_attr "athlon_decode" "double,vector") 5133 (set_attr "athlon_decode" "double,vector")
4869 (set_attr "amdfam10_decode" "double,double") 5134 (set_attr "amdfam10_decode" "double,double")
4870 (set_attr "bdver1_decode" "double,double") 5135 (set_attr "bdver1_decode" "double,double")
4871 (set_attr "prefix_rep" "1") 5136 (set_attr "prefix_rep" "1")
4872 (set_attr "prefix" "maybe_vex") 5137 (set_attr "prefix" "maybe_vex")
4873 (set_attr "mode" "SI")]) 5138 (set_attr "mode" "<MODE>")])
4874 5139
4875 (define_insn "sse2_cvtsd2siq<round_name>" 5140 (define_insn "sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>"
4876 [(set (match_operand:DI 0 "register_operand" "=r,r") 5141 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
4877 (unspec:DI 5142 (fix:SWI48
4878 [(vec_select:DF
4879 (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>")
4880 (parallel [(const_int 0)]))]
4881 UNSPEC_FIX_NOTRUNC))]
4882 "TARGET_SSE2 && TARGET_64BIT"
4883 "%vcvtsd2si{q}\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
4884 [(set_attr "type" "sseicvt")
4885 (set_attr "athlon_decode" "double,vector")
4886 (set_attr "bdver1_decode" "double,double")
4887 (set_attr "prefix_rep" "1")
4888 (set_attr "prefix" "maybe_vex")
4889 (set_attr "mode" "DI")])
4890
4891 (define_insn "sse2_cvtsd2siq_2"
4892 [(set (match_operand:DI 0 "register_operand" "=r,r")
4893 (unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "v,m")]
4894 UNSPEC_FIX_NOTRUNC))]
4895 "TARGET_SSE2 && TARGET_64BIT"
4896 "%vcvtsd2si{q}\t{%1, %0|%0, %q1}"
4897 [(set_attr "type" "sseicvt")
4898 (set_attr "athlon_decode" "double,vector")
4899 (set_attr "amdfam10_decode" "double,double")
4900 (set_attr "bdver1_decode" "double,double")
4901 (set_attr "prefix_rep" "1")
4902 (set_attr "prefix" "maybe_vex")
4903 (set_attr "mode" "DI")])
4904
4905 (define_insn "sse2_cvttsd2si<round_saeonly_name>"
4906 [(set (match_operand:SI 0 "register_operand" "=r,r")
4907 (fix:SI
4908 (vec_select:DF 5143 (vec_select:DF
4909 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") 5144 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>")
4910 (parallel [(const_int 0)]))))] 5145 (parallel [(const_int 0)]))))]
4911 "TARGET_SSE2" 5146 "TARGET_SSE2"
4912 "%vcvttsd2si\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}" 5147 "%vcvttsd2si<rex64suffix>\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
4913 [(set_attr "type" "sseicvt") 5148 [(set_attr "type" "sseicvt")
4914 (set_attr "athlon_decode" "double,vector") 5149 (set_attr "athlon_decode" "double,vector")
4915 (set_attr "amdfam10_decode" "double,double") 5150 (set_attr "amdfam10_decode" "double,double")
4916 (set_attr "bdver1_decode" "double,double") 5151 (set_attr "bdver1_decode" "double,double")
4917 (set_attr "btver2_decode" "double,double") 5152 (set_attr "btver2_decode" "double,double")
4918 (set_attr "prefix_rep" "1") 5153 (set_attr "prefix_rep" "1")
4919 (set_attr "prefix" "maybe_vex") 5154 (set_attr "prefix" "maybe_vex")
4920 (set_attr "mode" "SI")]) 5155 (set_attr "mode" "<MODE>")])
4921
4922 (define_insn "sse2_cvttsd2siq<round_saeonly_name>"
4923 [(set (match_operand:DI 0 "register_operand" "=r,r")
4924 (fix:DI
4925 (vec_select:DF
4926 (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>")
4927 (parallel [(const_int 0)]))))]
4928 "TARGET_SSE2 && TARGET_64BIT"
4929 "%vcvttsd2si{q}\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
4930 [(set_attr "type" "sseicvt")
4931 (set_attr "athlon_decode" "double,vector")
4932 (set_attr "amdfam10_decode" "double,double")
4933 (set_attr "bdver1_decode" "double,double")
4934 (set_attr "prefix_rep" "1")
4935 (set_attr "prefix" "maybe_vex")
4936 (set_attr "mode" "DI")])
4937 5156
4938 ;; For float<si2dfmode><mode>2 insn pattern 5157 ;; For float<si2dfmode><mode>2 insn pattern
4939 (define_mode_attr si2dfmode 5158 (define_mode_attr si2dfmode
4940 [(V8DF "V8SI") (V4DF "V4SI")]) 5159 [(V8DF "V8SI") (V4DF "V4SI")])
4941 (define_mode_attr si2dfmodelower 5160 (define_mode_attr si2dfmodelower
4948 "vcvtdq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 5167 "vcvtdq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
4949 [(set_attr "type" "ssecvt") 5168 [(set_attr "type" "ssecvt")
4950 (set_attr "prefix" "maybe_vex") 5169 (set_attr "prefix" "maybe_vex")
4951 (set_attr "mode" "<MODE>")]) 5170 (set_attr "mode" "<MODE>")])
4952 5171
4953 (define_insn "<floatsuffix>float<sseintvecmodelower><mode>2<mask_name><round_name>" 5172 (define_insn "float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>"
4954 [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v") 5173 [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v")
4955 (any_float:VF2_AVX512VL 5174 (any_float:VF2_AVX512VL
4956 (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] 5175 (match_operand:<sseintvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
4957 "TARGET_AVX512DQ" 5176 "TARGET_AVX512DQ"
4958 "vcvt<floatsuffix>qq2pd\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" 5177 "vcvt<floatsuffix>qq2pd\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
4959 [(set_attr "type" "ssecvt") 5178 [(set_attr "type" "ssecvt")
4960 (set_attr "prefix" "evex") 5179 (set_attr "prefix" "evex")
4961 (set_attr "mode" "<MODE>")]) 5180 (set_attr "mode" "<MODE>")])
4962 5181
4963 ;; For <floatsuffix>float<sselondveclower><mode> insn patterns 5182 ;; For float<floatunssuffix><sselondveclower><mode> insn patterns
4964 (define_mode_attr qq2pssuff 5183 (define_mode_attr qq2pssuff
4965 [(V8SF "") (V4SF "{y}")]) 5184 [(V8SF "") (V4SF "{y}")])
4966 5185
4967 (define_mode_attr sselongvecmode 5186 (define_mode_attr sselongvecmode
4968 [(V8SF "V8DI") (V4SF "V4DI")]) 5187 [(V8SF "V8DI") (V4SF "V4DI")])
4972 5191
4973 (define_mode_attr sseintvecmode3 5192 (define_mode_attr sseintvecmode3
4974 [(V8SF "XI") (V4SF "OI") 5193 [(V8SF "XI") (V4SF "OI")
4975 (V8DF "OI") (V4DF "TI")]) 5194 (V8DF "OI") (V4DF "TI")])
4976 5195
4977 (define_insn "<floatsuffix>float<sselongvecmodelower><mode>2<mask_name><round_name>" 5196 (define_insn "float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>"
4978 [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v") 5197 [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v")
4979 (any_float:VF1_128_256VL 5198 (any_float:VF1_128_256VL
4980 (match_operand:<sselongvecmode> 1 "nonimmediate_operand" "<round_constraint>")))] 5199 (match_operand:<sselongvecmode> 1 "nonimmediate_operand" "<round_constraint>")))]
4981 "TARGET_AVX512DQ && <round_modev8sf_condition>" 5200 "TARGET_AVX512DQ && <round_modev8sf_condition>"
4982 "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" 5201 "vcvt<floatsuffix>qq2ps<qq2pssuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
4983 [(set_attr "type" "ssecvt") 5202 [(set_attr "type" "ssecvt")
4984 (set_attr "prefix" "evex") 5203 (set_attr "prefix" "evex")
4985 (set_attr "mode" "<MODE>")]) 5204 (set_attr "mode" "<MODE>")])
4986 5205
4987 (define_insn "*<floatsuffix>floatv2div2sf2" 5206 (define_insn "float<floatunssuffix>v2div2sf2"
4988 [(set (match_operand:V4SF 0 "register_operand" "=v") 5207 [(set (match_operand:V4SF 0 "register_operand" "=v")
4989 (vec_concat:V4SF 5208 (vec_concat:V4SF
4990 (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) 5209 (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
4991 (const_vector:V2SF [(const_int 0) (const_int 0)])))] 5210 (const_vector:V2SF [(const_int 0) (const_int 0)])))]
4992 "TARGET_AVX512DQ && TARGET_AVX512VL" 5211 "TARGET_AVX512DQ && TARGET_AVX512VL"
4993 "vcvt<floatsuffix>qq2ps{x}\t{%1, %0|%0, %1}" 5212 "vcvt<floatsuffix>qq2ps{x}\t{%1, %0|%0, %1}"
4994 [(set_attr "type" "ssecvt") 5213 [(set_attr "type" "ssecvt")
4995 (set_attr "prefix" "evex") 5214 (set_attr "prefix" "evex")
4996 (set_attr "mode" "V4SF")]) 5215 (set_attr "mode" "V4SF")])
4997 5216
4998 (define_insn "<floatsuffix>floatv2div2sf2_mask" 5217 (define_mode_attr vpckfloat_concat_mode
5218 [(V8DI "v16sf") (V4DI "v8sf") (V2DI "v8sf")])
5219 (define_mode_attr vpckfloat_temp_mode
5220 [(V8DI "V8SF") (V4DI "V4SF") (V2DI "V4SF")])
5221 (define_mode_attr vpckfloat_op_mode
5222 [(V8DI "v8sf") (V4DI "v4sf") (V2DI "v2sf")])
5223
5224 (define_expand "vec_pack<floatprefix>_float_<mode>"
5225 [(match_operand:<ssePSmode> 0 "register_operand")
5226 (any_float:<ssePSmode>
5227 (match_operand:VI8_AVX512VL 1 "register_operand"))
5228 (match_operand:VI8_AVX512VL 2 "register_operand")]
5229 "TARGET_AVX512DQ"
5230 {
5231 rtx r1 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
5232 rtx r2 = gen_reg_rtx (<vpckfloat_temp_mode>mode);
5233 rtx (*gen) (rtx, rtx) = gen_float<floatunssuffix><mode><vpckfloat_op_mode>2;
5234 emit_insn (gen (r1, operands[1]));
5235 emit_insn (gen (r2, operands[2]));
5236 if (<MODE>mode == V2DImode)
5237 emit_insn (gen_sse_movlhps (operands[0], r1, r2));
5238 else
5239 emit_insn (gen_avx_vec_concat<vpckfloat_concat_mode> (operands[0],
5240 r1, r2));
5241 DONE;
5242 })
5243
5244 (define_insn "float<floatunssuffix>v2div2sf2_mask"
4999 [(set (match_operand:V4SF 0 "register_operand" "=v") 5245 [(set (match_operand:V4SF 0 "register_operand" "=v")
5000 (vec_concat:V4SF 5246 (vec_concat:V4SF
5001 (vec_merge:V2SF 5247 (vec_merge:V2SF
5002 (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) 5248 (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
5003 (vec_select:V2SF 5249 (vec_select:V2SF
5004 (match_operand:V4SF 2 "vector_move_operand" "0C") 5250 (match_operand:V4SF 2 "nonimm_or_0_operand" "0C")
5005 (parallel [(const_int 0) (const_int 1)])) 5251 (parallel [(const_int 0) (const_int 1)]))
5006 (match_operand:QI 3 "register_operand" "Yk")) 5252 (match_operand:QI 3 "register_operand" "Yk"))
5007 (const_vector:V2SF [(const_int 0) (const_int 0)])))] 5253 (const_vector:V2SF [(const_int 0) (const_int 0)])))]
5008 "TARGET_AVX512DQ && TARGET_AVX512VL" 5254 "TARGET_AVX512DQ && TARGET_AVX512VL"
5009 "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 5255 "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
5010 [(set_attr "type" "ssecvt") 5256 [(set_attr "type" "ssecvt")
5011 (set_attr "prefix" "evex") 5257 (set_attr "prefix" "evex")
5012 (set_attr "mode" "V4SF")]) 5258 (set_attr "mode" "V4SF")])
5013 5259
5014 (define_insn "*<floatsuffix>floatv2div2sf2_mask_1" 5260 (define_insn "*float<floatunssuffix>v2div2sf2_mask_1"
5015 [(set (match_operand:V4SF 0 "register_operand" "=v") 5261 [(set (match_operand:V4SF 0 "register_operand" "=v")
5016 (vec_concat:V4SF 5262 (vec_concat:V4SF
5017 (vec_merge:V2SF 5263 (vec_merge:V2SF
5018 (any_float:V2SF (match_operand:V2DI 1 5264 (any_float:V2SF (match_operand:V2DI 1
5019 "nonimmediate_operand" "vm")) 5265 "nonimmediate_operand" "vm"))
5041 (unsigned_float:V2DF 5287 (unsigned_float:V2DF
5042 (vec_select:V2SI 5288 (vec_select:V2SI
5043 (match_operand:V4SI 1 "nonimmediate_operand" "vm") 5289 (match_operand:V4SI 1 "nonimmediate_operand" "vm")
5044 (parallel [(const_int 0) (const_int 1)]))))] 5290 (parallel [(const_int 0) (const_int 1)]))))]
5045 "TARGET_AVX512VL" 5291 "TARGET_AVX512VL"
5046 "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 5292 "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
5047 [(set_attr "type" "ssecvt") 5293 [(set_attr "type" "ssecvt")
5048 (set_attr "prefix" "evex") 5294 (set_attr "prefix" "evex")
5049 (set_attr "mode" "V2DF")]) 5295 (set_attr "mode" "V2DF")])
5050 5296
5051 (define_insn "avx512f_cvtdq2pd512_2" 5297 (define_insn "avx512f_cvtdq2pd512_2"
5179 "vcvtpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 5425 "vcvtpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
5180 [(set_attr "type" "ssecvt") 5426 [(set_attr "type" "ssecvt")
5181 (set_attr "prefix" "evex") 5427 (set_attr "prefix" "evex")
5182 (set_attr "mode" "TI")]) 5428 (set_attr "mode" "TI")])
5183 5429
5184 (define_insn "<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>" 5430 (define_insn "fix<fixunssuffix>_truncv8dfv8si2<mask_name><round_saeonly_name>"
5185 [(set (match_operand:V8SI 0 "register_operand" "=v") 5431 [(set (match_operand:V8SI 0 "register_operand" "=v")
5186 (any_fix:V8SI 5432 (any_fix:V8SI
5187 (match_operand:V8DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] 5433 (match_operand:V8DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
5188 "TARGET_AVX512F" 5434 "TARGET_AVX512F"
5189 "vcvttpd2<fixsuffix>dq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}" 5435 "vcvttpd2<fixsuffix>dq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
5218 "vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 5464 "vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
5219 [(set_attr "type" "ssecvt") 5465 [(set_attr "type" "ssecvt")
5220 (set_attr "prefix" "maybe_evex") 5466 (set_attr "prefix" "maybe_evex")
5221 (set_attr "mode" "OI")]) 5467 (set_attr "mode" "OI")])
5222 5468
5223 (define_insn "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>" 5469 (define_insn "fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"
5224 [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v") 5470 [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
5225 (any_fix:<sseintvecmode> 5471 (any_fix:<sseintvecmode>
5226 (match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] 5472 (match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
5227 "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>" 5473 "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
5228 "vcvttpd2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}" 5474 "vcvttpd2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
5250 "vcvtpd2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" 5496 "vcvtpd2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
5251 [(set_attr "type" "ssecvt") 5497 [(set_attr "type" "ssecvt")
5252 (set_attr "prefix" "evex") 5498 (set_attr "prefix" "evex")
5253 (set_attr "mode" "<sseintvecmode2>")]) 5499 (set_attr "mode" "<sseintvecmode2>")])
5254 5500
5255 (define_insn "<fixsuffix>fix_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>" 5501 (define_insn "fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>"
5256 [(set (match_operand:<sselongvecmode> 0 "register_operand" "=v") 5502 [(set (match_operand:<sselongvecmode> 0 "register_operand" "=v")
5257 (any_fix:<sselongvecmode> 5503 (any_fix:<sselongvecmode>
5258 (match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))] 5504 (match_operand:VF1_128_256VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
5259 "TARGET_AVX512DQ && <round_saeonly_modev8sf_condition>" 5505 "TARGET_AVX512DQ && <round_saeonly_modev8sf_condition>"
5260 "vcvttps2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}" 5506 "vcvttps2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
5261 [(set_attr "type" "ssecvt") 5507 [(set_attr "type" "ssecvt")
5262 (set_attr "prefix" "evex") 5508 (set_attr "prefix" "evex")
5263 (set_attr "mode" "<sseintvecmode3>")]) 5509 (set_attr "mode" "<sseintvecmode3>")])
5264 5510
5265 (define_insn "<fixsuffix>fix_truncv2sfv2di2<mask_name>" 5511 (define_insn "fix<fixunssuffix>_truncv2sfv2di2<mask_name>"
5266 [(set (match_operand:V2DI 0 "register_operand" "=v") 5512 [(set (match_operand:V2DI 0 "register_operand" "=v")
5267 (any_fix:V2DI 5513 (any_fix:V2DI
5268 (vec_select:V2SF 5514 (vec_select:V2SF
5269 (match_operand:V4SF 1 "nonimmediate_operand" "vm") 5515 (match_operand:V4SF 1 "nonimmediate_operand" "vm")
5270 (parallel [(const_int 0) (const_int 1)]))))] 5516 (parallel [(const_int 0) (const_int 1)]))))]
5271 "TARGET_AVX512DQ && TARGET_AVX512VL" 5517 "TARGET_AVX512DQ && TARGET_AVX512VL"
5272 "vcvttps2<fixsuffix>qq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" 5518 "vcvttps2<fixsuffix>qq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
5273 [(set_attr "type" "ssecvt") 5519 [(set_attr "type" "ssecvt")
5274 (set_attr "prefix" "evex") 5520 (set_attr "prefix" "evex")
5275 (set_attr "mode" "TI")]) 5521 (set_attr "mode" "TI")])
5522
5523 (define_mode_attr vunpckfixt_mode
5524 [(V16SF "V8DI") (V8SF "V4DI") (V4SF "V2DI")])
5525 (define_mode_attr vunpckfixt_model
5526 [(V16SF "v8di") (V8SF "v4di") (V4SF "v2di")])
5527 (define_mode_attr vunpckfixt_extract_mode
5528 [(V16SF "v16sf") (V8SF "v8sf") (V4SF "v8sf")])
5529
5530 (define_expand "vec_unpack_<fixprefix>fix_trunc_lo_<mode>"
5531 [(match_operand:<vunpckfixt_mode> 0 "register_operand")
5532 (any_fix:<vunpckfixt_mode>
5533 (match_operand:VF1_AVX512VL 1 "register_operand"))]
5534 "TARGET_AVX512DQ"
5535 {
5536 rtx tem = operands[1];
5537 if (<MODE>mode != V4SFmode)
5538 {
5539 tem = gen_reg_rtx (<ssehalfvecmode>mode);
5540 emit_insn (gen_vec_extract_lo_<vunpckfixt_extract_mode> (tem,
5541 operands[1]));
5542 }
5543 rtx (*gen) (rtx, rtx)
5544 = gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
5545 emit_insn (gen (operands[0], tem));
5546 DONE;
5547 })
5548
5549 (define_expand "vec_unpack_<fixprefix>fix_trunc_hi_<mode>"
5550 [(match_operand:<vunpckfixt_mode> 0 "register_operand")
5551 (any_fix:<vunpckfixt_mode>
5552 (match_operand:VF1_AVX512VL 1 "register_operand"))]
5553 "TARGET_AVX512DQ"
5554 {
5555 rtx tem;
5556 if (<MODE>mode != V4SFmode)
5557 {
5558 tem = gen_reg_rtx (<ssehalfvecmode>mode);
5559 emit_insn (gen_vec_extract_hi_<vunpckfixt_extract_mode> (tem,
5560 operands[1]));
5561 }
5562 else
5563 {
5564 tem = gen_reg_rtx (V4SFmode);
5565 emit_insn (gen_avx_vpermilv4sf (tem, operands[1], GEN_INT (0x4e)));
5566 }
5567 rtx (*gen) (rtx, rtx)
5568 = gen_fix<fixunssuffix>_trunc<ssehalfvecmodelower><vunpckfixt_model>2;
5569 emit_insn (gen (operands[0], tem));
5570 DONE;
5571 })
5276 5572
5277 (define_insn "ufix_trunc<mode><sseintvecmodelower>2<mask_name>" 5573 (define_insn "ufix_trunc<mode><sseintvecmodelower>2<mask_name>"
5278 [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v") 5574 [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
5279 (unsigned_fix:<sseintvecmode> 5575 (unsigned_fix:<sseintvecmode>
5280 (match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))] 5576 (match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))]
6056 rtx r1, r2; 6352 rtx r1, r2;
6057 6353
6058 r1 = gen_reg_rtx (V8SImode); 6354 r1 = gen_reg_rtx (V8SImode);
6059 r2 = gen_reg_rtx (V8SImode); 6355 r2 = gen_reg_rtx (V8SImode);
6060 6356
6061 emit_insn (gen_ufix_truncv8dfv8si2 (r1, operands[1])); 6357 emit_insn (gen_fixuns_truncv8dfv8si2 (r1, operands[1]));
6062 emit_insn (gen_ufix_truncv8dfv8si2 (r2, operands[2])); 6358 emit_insn (gen_fixuns_truncv8dfv8si2 (r2, operands[2]));
6063 emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2)); 6359 emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2));
6064 } 6360 }
6065 else 6361 else
6066 { 6362 {
6067 rtx tmp[7]; 6363 rtx tmp[7];
6385 (vec_concat:V8SF 6681 (vec_concat:V8SF
6386 (match_operand:V4SF 1 "register_operand" "v") 6682 (match_operand:V4SF 1 "register_operand" "v")
6387 (match_operand:V4SF 2 "nonimmediate_operand" "vm")) 6683 (match_operand:V4SF 2 "nonimmediate_operand" "vm"))
6388 (parallel [(const_int 0) (const_int 4) 6684 (parallel [(const_int 0) (const_int 4)
6389 (const_int 1) (const_int 5)])) 6685 (const_int 1) (const_int 5)]))
6390 (match_operand:V4SF 3 "vector_move_operand" "0C") 6686 (match_operand:V4SF 3 "nonimm_or_0_operand" "0C")
6391 (match_operand:QI 4 "register_operand" "Yk")))] 6687 (match_operand:QI 4 "register_operand" "Yk")))]
6392 "TARGET_AVX512VL" 6688 "TARGET_AVX512VL"
6393 "vunpcklps\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" 6689 "vunpcklps\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
6394 [(set_attr "type" "sselog") 6690 [(set_attr "type" "sselog")
6395 (set_attr "prefix" "evex") 6691 (set_attr "prefix" "evex")
6641 (match_operand:V4SF 2 "nonimmediate_operand" "vm")) 6937 (match_operand:V4SF 2 "nonimmediate_operand" "vm"))
6642 (parallel [(match_operand 3 "const_0_to_3_operand") 6938 (parallel [(match_operand 3 "const_0_to_3_operand")
6643 (match_operand 4 "const_0_to_3_operand") 6939 (match_operand 4 "const_0_to_3_operand")
6644 (match_operand 5 "const_4_to_7_operand") 6940 (match_operand 5 "const_4_to_7_operand")
6645 (match_operand 6 "const_4_to_7_operand")])) 6941 (match_operand 6 "const_4_to_7_operand")]))
6646 (match_operand:V4SF 7 "vector_move_operand" "0C") 6942 (match_operand:V4SF 7 "nonimm_or_0_operand" "0C")
6647 (match_operand:QI 8 "register_operand" "Yk")))] 6943 (match_operand:QI 8 "register_operand" "Yk")))]
6648 "TARGET_AVX512VL" 6944 "TARGET_AVX512VL"
6649 { 6945 {
6650 int mask = 0; 6946 int mask = 0;
6651 mask |= INTVAL (operands[3]) << 0; 6947 mask |= INTVAL (operands[3]) << 0;
6863 [(set (match_operand:V2SF 0 "register_operand" 7159 [(set (match_operand:V2SF 0 "register_operand"
6864 "=Yr,*x, v,Yr,*x,v,v,*y ,*y") 7160 "=Yr,*x, v,Yr,*x,v,v,*y ,*y")
6865 (vec_concat:V2SF 7161 (vec_concat:V2SF
6866 (match_operand:SF 1 "nonimmediate_operand" 7162 (match_operand:SF 1 "nonimmediate_operand"
6867 " 0, 0,Yv, 0,0, v,m, 0 , m") 7163 " 0, 0,Yv, 0,0, v,m, 0 , m")
6868 (match_operand:SF 2 "vector_move_operand" 7164 (match_operand:SF 2 "nonimm_or_0_operand"
6869 " Yr,*x,Yv, m,m, m,C,*ym, C")))] 7165 " Yr,*x,Yv, m,m, m,C,*ym, C")))]
6870 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" 7166 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6871 "@ 7167 "@
6872 unpcklps\t{%2, %0|%0, %2} 7168 unpcklps\t{%2, %0|%0, %2}
6873 unpcklps\t{%2, %0|%0, %2} 7169 unpcklps\t{%2, %0|%0, %2}
6950 7246
6951 ;; Avoid combining registers from different units in a single alternative, 7247 ;; Avoid combining registers from different units in a single alternative,
6952 ;; see comment above inline_secondary_memory_needed function in i386.c 7248 ;; see comment above inline_secondary_memory_needed function in i386.c
6953 (define_insn "vec_set<mode>_0" 7249 (define_insn "vec_set<mode>_0"
6954 [(set (match_operand:VI4F_128 0 "nonimmediate_operand" 7250 [(set (match_operand:VI4F_128 0 "nonimmediate_operand"
6955 "=Yr,*x,v,v,Yi,x,x,v,Yr ,*x ,x ,m ,m ,m") 7251 "=Yr,*x,v,v,v,x,x,v,Yr ,*x ,x ,m ,m ,m")
6956 (vec_merge:VI4F_128 7252 (vec_merge:VI4F_128
6957 (vec_duplicate:VI4F_128 7253 (vec_duplicate:VI4F_128
6958 (match_operand:<ssescalarmode> 2 "general_operand" 7254 (match_operand:<ssescalarmode> 2 "general_operand"
6959 " Yr,*x,v,m,r ,m,x,v,*rm,*rm,*rm,!x,!*re,!*fF")) 7255 " Yr,*x,v,m,r ,m,x,v,*rm,*rm,*rm,!x,!*re,!*fF"))
6960 (match_operand:VI4F_128 1 "vector_move_operand" 7256 (match_operand:VI4F_128 1 "nonimm_or_0_operand"
6961 " C , C,C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0") 7257 " C , C,C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0")
6962 (const_int 1)))] 7258 (const_int 1)))]
6963 "TARGET_SSE" 7259 "TARGET_SSE"
6964 "@ 7260 "@
6965 insertps\t{$0xe, %2, %0|%0, %2, 0xe} 7261 insertps\t{$0xe, %2, %0|%0, %2, 0xe}
7013 (const_string "maybe_vex") 7309 (const_string "maybe_vex")
7014 (eq_attr "alternative" "7,10") 7310 (eq_attr "alternative" "7,10")
7015 (const_string "vex") 7311 (const_string "vex")
7016 ] 7312 ]
7017 (const_string "*"))) 7313 (const_string "*")))
7018 (set_attr "mode" "SF,SF,SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,TI,*,*,*")]) 7314 (set_attr "mode" "SF,SF,SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,TI,*,*,*")
7315 (set (attr "preferred_for_speed")
7316 (cond [(eq_attr "alternative" "4")
7317 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
7318 ]
7319 (symbol_ref "true")))])
7019 7320
7020 ;; A subset is vec_setv4sf. 7321 ;; A subset is vec_setv4sf.
7021 (define_insn "*vec_setv4sf_sse4_1" 7322 (define_insn "*vec_setv4sf_sse4_1"
7022 [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v") 7323 [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v")
7023 (vec_merge:V4SF 7324 (vec_merge:V4SF
7046 (set_attr "prefix_data16" "1,1,*") 7347 (set_attr "prefix_data16" "1,1,*")
7047 (set_attr "prefix_extra" "1") 7348 (set_attr "prefix_extra" "1")
7048 (set_attr "length_immediate" "1") 7349 (set_attr "length_immediate" "1")
7049 (set_attr "prefix" "orig,orig,maybe_evex") 7350 (set_attr "prefix" "orig,orig,maybe_evex")
7050 (set_attr "mode" "V4SF")]) 7351 (set_attr "mode" "V4SF")])
7352
7353 ;; All of vinsertps, vmovss, vmovd clear also the higher bits.
7354 (define_insn "vec_set<mode>_0"
7355 [(set (match_operand:VI4F_256_512 0 "register_operand" "=v,v,v")
7356 (vec_merge:VI4F_256_512
7357 (vec_duplicate:VI4F_256_512
7358 (match_operand:<ssescalarmode> 2 "general_operand" "v,m,r"))
7359 (match_operand:VI4F_256_512 1 "const0_operand" "C,C,C")
7360 (const_int 1)))]
7361 "TARGET_AVX"
7362 "@
7363 vinsertps\t{$0xe, %2, %2, %x0|%x0, %2, %2, 0xe}
7364 vmov<ssescalarmodesuffix>\t{%x2, %x0|%x0, %2}
7365 vmovd\t{%2, %x0|%x0, %2}"
7366 [(set (attr "type")
7367 (if_then_else (eq_attr "alternative" "0")
7368 (const_string "sselog")
7369 (const_string "ssemov")))
7370 (set_attr "prefix" "maybe_evex")
7371 (set_attr "mode" "SF,<ssescalarmode>,SI")
7372 (set (attr "preferred_for_speed")
7373 (cond [(eq_attr "alternative" "2")
7374 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
7375 ]
7376 (symbol_ref "true")))])
7051 7377
7052 (define_insn "sse4_1_insertps" 7378 (define_insn "sse4_1_insertps"
7053 [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v") 7379 [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v")
7054 (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "Yrm,*xm,vm") 7380 (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "Yrm,*xm,vm")
7055 (match_operand:V4SF 1 "register_operand" "0,0,v") 7381 (match_operand:V4SF 1 "register_operand" "0,0,v")
7278 (set_attr "prefix_extra" "1") 7604 (set_attr "prefix_extra" "1")
7279 (set_attr "length_immediate" "1") 7605 (set_attr "length_immediate" "1")
7280 (set_attr "prefix" "evex") 7606 (set_attr "prefix" "evex")
7281 (set_attr "mode" "<sseinsnmode>")]) 7607 (set_attr "mode" "<sseinsnmode>")])
7282 7608
7609 (define_split
7610 [(set (match_operand:<ssequartermode> 0 "nonimmediate_operand")
7611 (vec_select:<ssequartermode>
7612 (match_operand:V8FI 1 "register_operand")
7613 (parallel [(const_int 0) (const_int 1)])))]
7614 "TARGET_AVX512DQ
7615 && reload_completed
7616 && (TARGET_AVX512VL
7617 || REG_P (operands[0])
7618 || !EXT_REX_SSE_REG_P (operands[1]))"
7619 [(set (match_dup 0) (match_dup 1))]
7620 {
7621 if (!TARGET_AVX512VL
7622 && REG_P (operands[0])
7623 && EXT_REX_SSE_REG_P (operands[1]))
7624 operands[0]
7625 = lowpart_subreg (<MODE>mode, operands[0], <ssequartermode>mode);
7626 else
7627 operands[1] = gen_lowpart (<ssequartermode>mode, operands[1]);
7628 })
7629
7283 (define_insn "<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>" 7630 (define_insn "<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>"
7284 [(set (match_operand:<ssequartermode> 0 "<store_mask_predicate>" "=<store_mask_constraint>") 7631 [(set (match_operand:<ssequartermode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
7285 (vec_select:<ssequartermode> 7632 (vec_select:<ssequartermode>
7286 (match_operand:V16FI 1 "register_operand" "v") 7633 (match_operand:V16FI 1 "register_operand" "v")
7287 (parallel [(match_operand 2 "const_0_to_15_operand") 7634 (parallel [(match_operand 2 "const_0_to_15_operand")
7300 [(set_attr "type" "sselog1") 7647 [(set_attr "type" "sselog1")
7301 (set_attr "prefix_extra" "1") 7648 (set_attr "prefix_extra" "1")
7302 (set_attr "length_immediate" "1") 7649 (set_attr "length_immediate" "1")
7303 (set_attr "prefix" "evex") 7650 (set_attr "prefix" "evex")
7304 (set_attr "mode" "<sseinsnmode>")]) 7651 (set_attr "mode" "<sseinsnmode>")])
7652
7653 (define_split
7654 [(set (match_operand:<ssequartermode> 0 "nonimmediate_operand")
7655 (vec_select:<ssequartermode>
7656 (match_operand:V16FI 1 "register_operand")
7657 (parallel [(const_int 0) (const_int 1)
7658 (const_int 2) (const_int 3)])))]
7659 "TARGET_AVX512F
7660 && reload_completed
7661 && (TARGET_AVX512VL
7662 || REG_P (operands[0])
7663 || !EXT_REX_SSE_REG_P (operands[1]))"
7664 [(set (match_dup 0) (match_dup 1))]
7665 {
7666 if (!TARGET_AVX512VL
7667 && REG_P (operands[0])
7668 && EXT_REX_SSE_REG_P (operands[1]))
7669 operands[0]
7670 = lowpart_subreg (<MODE>mode, operands[0], <ssequartermode>mode);
7671 else
7672 operands[1] = gen_lowpart (<ssequartermode>mode, operands[1]);
7673 })
7305 7674
7306 (define_mode_attr extract_type_2 7675 (define_mode_attr extract_type_2
7307 [(V16SF "avx512dq") (V16SI "avx512dq") (V8DF "avx512f") (V8DI "avx512f")]) 7676 [(V16SF "avx512dq") (V16SI "avx512dq") (V8DF "avx512f") (V8DI "avx512f")])
7308 7677
7309 (define_mode_attr extract_suf_2 7678 (define_mode_attr extract_suf_2
7374 (set_attr "length_immediate" "1") 7743 (set_attr "length_immediate" "1")
7375 (set_attr "prefix" "evex") 7744 (set_attr "prefix" "evex")
7376 (set_attr "mode" "<sseinsnmode>")]) 7745 (set_attr "mode" "<sseinsnmode>")])
7377 7746
7378 (define_insn "vec_extract_lo_<mode><mask_name>" 7747 (define_insn "vec_extract_lo_<mode><mask_name>"
7379 [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v") 7748 [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,<store_mask_constraint>,v")
7380 (vec_select:<ssehalfvecmode> 7749 (vec_select:<ssehalfvecmode>
7381 (match_operand:V8FI 1 "<store_mask_predicate>" "v,<store_mask_constraint>") 7750 (match_operand:V8FI 1 "<store_mask_predicate>" "v,v,<store_mask_constraint>")
7382 (parallel [(const_int 0) (const_int 1) 7751 (parallel [(const_int 0) (const_int 1)
7383 (const_int 2) (const_int 3)])))] 7752 (const_int 2) (const_int 3)])))]
7384 "TARGET_AVX512F 7753 "TARGET_AVX512F
7385 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))" 7754 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
7386 { 7755 {
7390 return "#"; 7759 return "#";
7391 } 7760 }
7392 [(set_attr "type" "sselog1") 7761 [(set_attr "type" "sselog1")
7393 (set_attr "prefix_extra" "1") 7762 (set_attr "prefix_extra" "1")
7394 (set_attr "length_immediate" "1") 7763 (set_attr "length_immediate" "1")
7764 (set_attr "memory" "none,store,load")
7395 (set_attr "prefix" "evex") 7765 (set_attr "prefix" "evex")
7396 (set_attr "mode" "<sseinsnmode>")]) 7766 (set_attr "mode" "<sseinsnmode>")])
7397 7767
7398 (define_insn "vec_extract_hi_<mode>_maskm" 7768 (define_insn "vec_extract_hi_<mode>_maskm"
7399 [(set (match_operand:<ssehalfvecmode> 0 "memory_operand" "=m") 7769 [(set (match_operand:<ssehalfvecmode> 0 "memory_operand" "=m")
7469 7839
7470 (define_expand "avx512vl_vextractf128<mode>" 7840 (define_expand "avx512vl_vextractf128<mode>"
7471 [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand") 7841 [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
7472 (match_operand:VI48F_256 1 "register_operand") 7842 (match_operand:VI48F_256 1 "register_operand")
7473 (match_operand:SI 2 "const_0_to_1_operand") 7843 (match_operand:SI 2 "const_0_to_1_operand")
7474 (match_operand:<ssehalfvecmode> 3 "vector_move_operand") 7844 (match_operand:<ssehalfvecmode> 3 "nonimm_or_0_operand")
7475 (match_operand:QI 4 "register_operand")] 7845 (match_operand:QI 4 "register_operand")]
7476 "TARGET_AVX512DQ && TARGET_AVX512VL" 7846 "TARGET_AVX512DQ && TARGET_AVX512VL"
7477 { 7847 {
7478 rtx (*insn)(rtx, rtx, rtx, rtx); 7848 rtx (*insn)(rtx, rtx, rtx, rtx);
7479 rtx dest = operands[0]; 7849 rtx dest = operands[0];
7530 emit_insn (insn (operands[0], operands[1])); 7900 emit_insn (insn (operands[0], operands[1]));
7531 DONE; 7901 DONE;
7532 }) 7902 })
7533 7903
7534 (define_insn "vec_extract_lo_<mode><mask_name>" 7904 (define_insn "vec_extract_lo_<mode><mask_name>"
7535 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m") 7905 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
7536 (vec_select:<ssehalfvecmode> 7906 (vec_select:<ssehalfvecmode>
7537 (match_operand:V16FI 1 "<store_mask_predicate>" 7907 (match_operand:V16FI 1 "<store_mask_predicate>"
7538 "<store_mask_constraint>,v") 7908 "v,<store_mask_constraint>,v")
7539 (parallel [(const_int 0) (const_int 1) 7909 (parallel [(const_int 0) (const_int 1)
7540 (const_int 2) (const_int 3) 7910 (const_int 2) (const_int 3)
7541 (const_int 4) (const_int 5) 7911 (const_int 4) (const_int 5)
7542 (const_int 6) (const_int 7)])))] 7912 (const_int 6) (const_int 7)])))]
7543 "TARGET_AVX512F 7913 "TARGET_AVX512F
7544 && <mask_mode512bit_condition> 7914 && <mask_mode512bit_condition>
7545 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))" 7915 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
7546 { 7916 {
7547 if (<mask_applied>) 7917 if (<mask_applied>
7918 || (!TARGET_AVX512VL
7919 && !REG_P (operands[0])
7920 && EXT_REX_SSE_REG_P (operands[1])))
7548 return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}"; 7921 return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
7549 else 7922 else
7550 return "#"; 7923 return "#";
7551 }) 7924 }
7925 [(set_attr "type" "sselog1")
7926 (set_attr "prefix_extra" "1")
7927 (set_attr "length_immediate" "1")
7928 (set_attr "memory" "none,load,store")
7929 (set_attr "prefix" "evex")
7930 (set_attr "mode" "<sseinsnmode>")])
7552 7931
7553 (define_split 7932 (define_split
7554 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand") 7933 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
7555 (vec_select:<ssehalfvecmode> 7934 (vec_select:<ssehalfvecmode>
7556 (match_operand:V16FI 1 "nonimmediate_operand") 7935 (match_operand:V16FI 1 "nonimmediate_operand")
7557 (parallel [(const_int 0) (const_int 1) 7936 (parallel [(const_int 0) (const_int 1)
7558 (const_int 2) (const_int 3) 7937 (const_int 2) (const_int 3)
7559 (const_int 4) (const_int 5) 7938 (const_int 4) (const_int 5)
7560 (const_int 6) (const_int 7)])))] 7939 (const_int 6) (const_int 7)])))]
7561 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1])) 7940 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))
7562 && reload_completed" 7941 && reload_completed
7942 && (TARGET_AVX512VL
7943 || REG_P (operands[0])
7944 || !EXT_REX_SSE_REG_P (operands[1]))"
7563 [(set (match_dup 0) (match_dup 1))] 7945 [(set (match_dup 0) (match_dup 1))]
7564 "operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);") 7946 {
7947 if (!TARGET_AVX512VL
7948 && REG_P (operands[0])
7949 && EXT_REX_SSE_REG_P (operands[1]))
7950 operands[0]
7951 = lowpart_subreg (<MODE>mode, operands[0], <ssehalfvecmode>mode);
7952 else
7953 operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);
7954 })
7565 7955
7566 (define_insn "vec_extract_lo_<mode><mask_name>" 7956 (define_insn "vec_extract_lo_<mode><mask_name>"
7567 [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,m") 7957 [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
7568 (vec_select:<ssehalfvecmode> 7958 (vec_select:<ssehalfvecmode>
7569 (match_operand:VI8F_256 1 "<store_mask_predicate>" 7959 (match_operand:VI8F_256 1 "<store_mask_predicate>"
7570 "<store_mask_constraint>,v") 7960 "v,<store_mask_constraint>,v")
7571 (parallel [(const_int 0) (const_int 1)])))] 7961 (parallel [(const_int 0) (const_int 1)])))]
7572 "TARGET_AVX 7962 "TARGET_AVX
7573 && <mask_avx512vl_condition> && <mask_avx512dq_condition> 7963 && <mask_avx512vl_condition> && <mask_avx512dq_condition>
7574 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))" 7964 && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
7575 { 7965 {
7576 if (<mask_applied>) 7966 if (<mask_applied>)
7577 return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}"; 7967 return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
7578 else 7968 else
7579 return "#"; 7969 return "#";
7580 } 7970 }
7581 [(set_attr "type" "sselog") 7971 [(set_attr "type" "sselog1")
7582 (set_attr "prefix_extra" "1") 7972 (set_attr "prefix_extra" "1")
7583 (set_attr "length_immediate" "1") 7973 (set_attr "length_immediate" "1")
7584 (set_attr "memory" "none,store") 7974 (set_attr "memory" "none,load,store")
7585 (set_attr "prefix" "evex") 7975 (set_attr "prefix" "evex")
7586 (set_attr "mode" "XI")]) 7976 (set_attr "mode" "XI")])
7587 7977
7588 (define_split 7978 (define_split
7589 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand") 7979 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
7610 return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}"; 8000 return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}";
7611 } 8001 }
7612 else 8002 else
7613 return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}"; 8003 return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
7614 } 8004 }
7615 [(set_attr "type" "sselog") 8005 [(set_attr "type" "sselog1")
7616 (set_attr "prefix_extra" "1") 8006 (set_attr "prefix_extra" "1")
7617 (set_attr "length_immediate" "1") 8007 (set_attr "length_immediate" "1")
7618 (set_attr "memory" "none,store")
7619 (set_attr "prefix" "vex") 8008 (set_attr "prefix" "vex")
7620 (set_attr "mode" "<sseinsnmode>")]) 8009 (set_attr "mode" "<sseinsnmode>")])
7621 8010
7622 (define_split 8011 (define_split
7623 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand") 8012 [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
7693 (vec_merge:<ssehalfvecmode> 8082 (vec_merge:<ssehalfvecmode>
7694 (vec_select:<ssehalfvecmode> 8083 (vec_select:<ssehalfvecmode>
7695 (match_operand:VI4F_256 1 "register_operand" "v") 8084 (match_operand:VI4F_256 1 "register_operand" "v")
7696 (parallel [(const_int 4) (const_int 5) 8085 (parallel [(const_int 4) (const_int 5)
7697 (const_int 6) (const_int 7)])) 8086 (const_int 6) (const_int 7)]))
7698 (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "0C") 8087 (match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand" "0C")
7699 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] 8088 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
7700 "TARGET_AVX512VL" 8089 "TARGET_AVX512VL"
7701 "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}" 8090 "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
7702 [(set_attr "type" "sselog1") 8091 [(set_attr "type" "sselog1")
7703 (set_attr "length_immediate" "1") 8092 (set_attr "length_immediate" "1")
7719 (set_attr "type" "sselog1") 8108 (set_attr "type" "sselog1")
7720 (set_attr "length_immediate" "1") 8109 (set_attr "length_immediate" "1")
7721 (set_attr "mode" "<sseinsnmode>")]) 8110 (set_attr "mode" "<sseinsnmode>")])
7722 8111
7723 (define_insn_and_split "vec_extract_lo_v32hi" 8112 (define_insn_and_split "vec_extract_lo_v32hi"
7724 [(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,m") 8113 [(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,v,m")
7725 (vec_select:V16HI 8114 (vec_select:V16HI
7726 (match_operand:V32HI 1 "nonimmediate_operand" "vm,v") 8115 (match_operand:V32HI 1 "nonimmediate_operand" "v,m,v")
7727 (parallel [(const_int 0) (const_int 1) 8116 (parallel [(const_int 0) (const_int 1)
7728 (const_int 2) (const_int 3) 8117 (const_int 2) (const_int 3)
7729 (const_int 4) (const_int 5) 8118 (const_int 4) (const_int 5)
7730 (const_int 6) (const_int 7) 8119 (const_int 6) (const_int 7)
7731 (const_int 8) (const_int 9) 8120 (const_int 8) (const_int 9)
7732 (const_int 10) (const_int 11) 8121 (const_int 10) (const_int 11)
7733 (const_int 12) (const_int 13) 8122 (const_int 12) (const_int 13)
7734 (const_int 14) (const_int 15)])))] 8123 (const_int 14) (const_int 15)])))]
7735 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))" 8124 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7736 "#" 8125 {
7737 "&& reload_completed" 8126 if (TARGET_AVX512VL
8127 || REG_P (operands[0])
8128 || !EXT_REX_SSE_REG_P (operands[1]))
8129 return "#";
8130 else
8131 return "vextracti64x4\t{$0x0, %1, %0|%0, %1, 0x0}";
8132 }
8133 "&& reload_completed
8134 && (TARGET_AVX512VL
8135 || REG_P (operands[0])
8136 || !EXT_REX_SSE_REG_P (operands[1]))"
7738 [(set (match_dup 0) (match_dup 1))] 8137 [(set (match_dup 0) (match_dup 1))]
7739 "operands[1] = gen_lowpart (V16HImode, operands[1]);") 8138 {
8139 if (!TARGET_AVX512VL
8140 && REG_P (operands[0])
8141 && EXT_REX_SSE_REG_P (operands[1]))
8142 operands[0] = lowpart_subreg (V32HImode, operands[0], V16HImode);
8143 else
8144 operands[1] = gen_lowpart (V16HImode, operands[1]);
8145 }
8146 [(set_attr "type" "sselog1")
8147 (set_attr "prefix_extra" "1")
8148 (set_attr "length_immediate" "1")
8149 (set_attr "memory" "none,load,store")
8150 (set_attr "prefix" "evex")
8151 (set_attr "mode" "XI")])
7740 8152
7741 (define_insn "vec_extract_hi_v32hi" 8153 (define_insn "vec_extract_hi_v32hi"
7742 [(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,m") 8154 [(set (match_operand:V16HI 0 "nonimmediate_operand" "=vm")
7743 (vec_select:V16HI 8155 (vec_select:V16HI
7744 (match_operand:V32HI 1 "register_operand" "v,v") 8156 (match_operand:V32HI 1 "register_operand" "v")
7745 (parallel [(const_int 16) (const_int 17) 8157 (parallel [(const_int 16) (const_int 17)
7746 (const_int 18) (const_int 19) 8158 (const_int 18) (const_int 19)
7747 (const_int 20) (const_int 21) 8159 (const_int 20) (const_int 21)
7748 (const_int 22) (const_int 23) 8160 (const_int 22) (const_int 23)
7749 (const_int 24) (const_int 25) 8161 (const_int 24) (const_int 25)
7750 (const_int 26) (const_int 27) 8162 (const_int 26) (const_int 27)
7751 (const_int 28) (const_int 29) 8163 (const_int 28) (const_int 29)
7752 (const_int 30) (const_int 31)])))] 8164 (const_int 30) (const_int 31)])))]
7753 "TARGET_AVX512F" 8165 "TARGET_AVX512F"
7754 "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" 8166 "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
7755 [(set_attr "type" "sselog") 8167 [(set_attr "type" "sselog1")
7756 (set_attr "prefix_extra" "1") 8168 (set_attr "prefix_extra" "1")
7757 (set_attr "length_immediate" "1") 8169 (set_attr "length_immediate" "1")
7758 (set_attr "memory" "none,store")
7759 (set_attr "prefix" "evex") 8170 (set_attr "prefix" "evex")
7760 (set_attr "mode" "XI")]) 8171 (set_attr "mode" "XI")])
7761 8172
7762 (define_insn_and_split "vec_extract_lo_v16hi" 8173 (define_insn_and_split "vec_extract_lo_v16hi"
7763 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=v,m") 8174 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=v,m")
7772 "&& reload_completed" 8183 "&& reload_completed"
7773 [(set (match_dup 0) (match_dup 1))] 8184 [(set (match_dup 0) (match_dup 1))]
7774 "operands[1] = gen_lowpart (V8HImode, operands[1]);") 8185 "operands[1] = gen_lowpart (V8HImode, operands[1]);")
7775 8186
7776 (define_insn "vec_extract_hi_v16hi" 8187 (define_insn "vec_extract_hi_v16hi"
7777 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m,v,m,v,m") 8188 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm,vm,vm")
7778 (vec_select:V8HI 8189 (vec_select:V8HI
7779 (match_operand:V16HI 1 "register_operand" "x,x,v,v,v,v") 8190 (match_operand:V16HI 1 "register_operand" "x,v,v")
7780 (parallel [(const_int 8) (const_int 9) 8191 (parallel [(const_int 8) (const_int 9)
7781 (const_int 10) (const_int 11) 8192 (const_int 10) (const_int 11)
7782 (const_int 12) (const_int 13) 8193 (const_int 12) (const_int 13)
7783 (const_int 14) (const_int 15)])))] 8194 (const_int 14) (const_int 15)])))]
7784 "TARGET_AVX" 8195 "TARGET_AVX"
7785 "@ 8196 "@
7786 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1} 8197 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
7787 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
7788 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1} 8198 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
7789 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
7790 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}
7791 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}" 8199 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}"
7792 [(set_attr "type" "sselog") 8200 [(set_attr "type" "sselog1")
7793 (set_attr "prefix_extra" "1") 8201 (set_attr "prefix_extra" "1")
7794 (set_attr "length_immediate" "1") 8202 (set_attr "length_immediate" "1")
7795 (set_attr "isa" "*,*,avx512dq,avx512dq,avx512f,avx512f") 8203 (set_attr "isa" "*,avx512dq,avx512f")
7796 (set_attr "memory" "none,store,none,store,none,store") 8204 (set_attr "prefix" "vex,evex,evex")
7797 (set_attr "prefix" "vex,vex,evex,evex,evex,evex")
7798 (set_attr "mode" "OI")]) 8205 (set_attr "mode" "OI")])
7799 8206
7800 (define_insn_and_split "vec_extract_lo_v64qi" 8207 (define_insn_and_split "vec_extract_lo_v64qi"
7801 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m") 8208 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,v,m")
7802 (vec_select:V32QI 8209 (vec_select:V32QI
7803 (match_operand:V64QI 1 "nonimmediate_operand" "vm,v") 8210 (match_operand:V64QI 1 "nonimmediate_operand" "v,m,v")
7804 (parallel [(const_int 0) (const_int 1) 8211 (parallel [(const_int 0) (const_int 1)
7805 (const_int 2) (const_int 3) 8212 (const_int 2) (const_int 3)
7806 (const_int 4) (const_int 5) 8213 (const_int 4) (const_int 5)
7807 (const_int 6) (const_int 7) 8214 (const_int 6) (const_int 7)
7808 (const_int 8) (const_int 9) 8215 (const_int 8) (const_int 9)
7816 (const_int 24) (const_int 25) 8223 (const_int 24) (const_int 25)
7817 (const_int 26) (const_int 27) 8224 (const_int 26) (const_int 27)
7818 (const_int 28) (const_int 29) 8225 (const_int 28) (const_int 29)
7819 (const_int 30) (const_int 31)])))] 8226 (const_int 30) (const_int 31)])))]
7820 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))" 8227 "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7821 "#" 8228 {
7822 "&& reload_completed" 8229 if (TARGET_AVX512VL
8230 || REG_P (operands[0])
8231 || !EXT_REX_SSE_REG_P (operands[1]))
8232 return "#";
8233 else
8234 return "vextracti64x4\t{$0x0, %1, %0|%0, %1, 0x0}";
8235 }
8236 "&& reload_completed
8237 && (TARGET_AVX512VL
8238 || REG_P (operands[0])
8239 || !EXT_REX_SSE_REG_P (operands[1]))"
7823 [(set (match_dup 0) (match_dup 1))] 8240 [(set (match_dup 0) (match_dup 1))]
7824 "operands[1] = gen_lowpart (V32QImode, operands[1]);") 8241 {
8242 if (!TARGET_AVX512VL
8243 && REG_P (operands[0])
8244 && EXT_REX_SSE_REG_P (operands[1]))
8245 operands[0] = lowpart_subreg (V64QImode, operands[0], V32QImode);
8246 else
8247 operands[1] = gen_lowpart (V32QImode, operands[1]);
8248 }
8249 [(set_attr "type" "sselog1")
8250 (set_attr "prefix_extra" "1")
8251 (set_attr "length_immediate" "1")
8252 (set_attr "memory" "none,load,store")
8253 (set_attr "prefix" "evex")
8254 (set_attr "mode" "XI")])
7825 8255
7826 (define_insn "vec_extract_hi_v64qi" 8256 (define_insn "vec_extract_hi_v64qi"
7827 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m") 8257 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=vm")
7828 (vec_select:V32QI 8258 (vec_select:V32QI
7829 (match_operand:V64QI 1 "register_operand" "v,v") 8259 (match_operand:V64QI 1 "register_operand" "v")
7830 (parallel [(const_int 32) (const_int 33) 8260 (parallel [(const_int 32) (const_int 33)
7831 (const_int 34) (const_int 35) 8261 (const_int 34) (const_int 35)
7832 (const_int 36) (const_int 37) 8262 (const_int 36) (const_int 37)
7833 (const_int 38) (const_int 39) 8263 (const_int 38) (const_int 39)
7834 (const_int 40) (const_int 41) 8264 (const_int 40) (const_int 41)
7843 (const_int 58) (const_int 59) 8273 (const_int 58) (const_int 59)
7844 (const_int 60) (const_int 61) 8274 (const_int 60) (const_int 61)
7845 (const_int 62) (const_int 63)])))] 8275 (const_int 62) (const_int 63)])))]
7846 "TARGET_AVX512F" 8276 "TARGET_AVX512F"
7847 "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" 8277 "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
7848 [(set_attr "type" "sselog") 8278 [(set_attr "type" "sselog1")
7849 (set_attr "prefix_extra" "1") 8279 (set_attr "prefix_extra" "1")
7850 (set_attr "length_immediate" "1") 8280 (set_attr "length_immediate" "1")
7851 (set_attr "memory" "none,store")
7852 (set_attr "prefix" "evex") 8281 (set_attr "prefix" "evex")
7853 (set_attr "mode" "XI")]) 8282 (set_attr "mode" "XI")])
7854 8283
7855 (define_insn_and_split "vec_extract_lo_v32qi" 8284 (define_insn_and_split "vec_extract_lo_v32qi"
7856 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=v,m") 8285 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=v,m")
7869 "&& reload_completed" 8298 "&& reload_completed"
7870 [(set (match_dup 0) (match_dup 1))] 8299 [(set (match_dup 0) (match_dup 1))]
7871 "operands[1] = gen_lowpart (V16QImode, operands[1]);") 8300 "operands[1] = gen_lowpart (V16QImode, operands[1]);")
7872 8301
7873 (define_insn "vec_extract_hi_v32qi" 8302 (define_insn "vec_extract_hi_v32qi"
7874 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m,v,m,v,m") 8303 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=xm,vm,vm")
7875 (vec_select:V16QI 8304 (vec_select:V16QI
7876 (match_operand:V32QI 1 "register_operand" "x,x,v,v,v,v") 8305 (match_operand:V32QI 1 "register_operand" "x,v,v")
7877 (parallel [(const_int 16) (const_int 17) 8306 (parallel [(const_int 16) (const_int 17)
7878 (const_int 18) (const_int 19) 8307 (const_int 18) (const_int 19)
7879 (const_int 20) (const_int 21) 8308 (const_int 20) (const_int 21)
7880 (const_int 22) (const_int 23) 8309 (const_int 22) (const_int 23)
7881 (const_int 24) (const_int 25) 8310 (const_int 24) (const_int 25)
7883 (const_int 28) (const_int 29) 8312 (const_int 28) (const_int 29)
7884 (const_int 30) (const_int 31)])))] 8313 (const_int 30) (const_int 31)])))]
7885 "TARGET_AVX" 8314 "TARGET_AVX"
7886 "@ 8315 "@
7887 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1} 8316 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
7888 vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
7889 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1} 8317 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
7890 vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
7891 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}
7892 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}" 8318 vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}"
7893 [(set_attr "type" "sselog") 8319 [(set_attr "type" "sselog1")
7894 (set_attr "prefix_extra" "1") 8320 (set_attr "prefix_extra" "1")
7895 (set_attr "length_immediate" "1") 8321 (set_attr "length_immediate" "1")
7896 (set_attr "isa" "*,*,avx512dq,avx512dq,avx512f,avx512f") 8322 (set_attr "isa" "*,avx512dq,avx512f")
7897 (set_attr "memory" "none,store,none,store,none,store") 8323 (set_attr "prefix" "vex,evex,evex")
7898 (set_attr "prefix" "vex,vex,evex,evex,evex,evex")
7899 (set_attr "mode" "OI")]) 8324 (set_attr "mode" "OI")])
7900 8325
7901 ;; Modes handled by vec_extract patterns. 8326 ;; Modes handled by vec_extract patterns.
7902 (define_mode_iterator VEC_EXTRACT_MODE 8327 (define_mode_iterator VEC_EXTRACT_MODE
7903 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX") V16QI 8328 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX") V16QI
8004 (vec_select:V2DF 8429 (vec_select:V2DF
8005 (vec_concat:V4DF 8430 (vec_concat:V4DF
8006 (match_operand:V2DF 1 "register_operand" "v") 8431 (match_operand:V2DF 1 "register_operand" "v")
8007 (match_operand:V2DF 2 "nonimmediate_operand" "vm")) 8432 (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
8008 (parallel [(const_int 1) (const_int 3)])) 8433 (parallel [(const_int 1) (const_int 3)]))
8009 (match_operand:V2DF 3 "vector_move_operand" "0C") 8434 (match_operand:V2DF 3 "nonimm_or_0_operand" "0C")
8010 (match_operand:QI 4 "register_operand" "Yk")))] 8435 (match_operand:QI 4 "register_operand" "Yk")))]
8011 "TARGET_AVX512VL" 8436 "TARGET_AVX512VL"
8012 "vunpckhpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" 8437 "vunpckhpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
8013 [(set_attr "type" "sselog") 8438 [(set_attr "type" "sselog")
8014 (set_attr "prefix" "evex") 8439 (set_attr "prefix" "evex")
8166 (vec_select:V2DF 8591 (vec_select:V2DF
8167 (vec_concat:V4DF 8592 (vec_concat:V4DF
8168 (match_operand:V2DF 1 "register_operand" "v") 8593 (match_operand:V2DF 1 "register_operand" "v")
8169 (match_operand:V2DF 2 "nonimmediate_operand" "vm")) 8594 (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
8170 (parallel [(const_int 0) (const_int 2)])) 8595 (parallel [(const_int 0) (const_int 2)]))
8171 (match_operand:V2DF 3 "vector_move_operand" "0C") 8596 (match_operand:V2DF 3 "nonimm_or_0_operand" "0C")
8172 (match_operand:QI 4 "register_operand" "Yk")))] 8597 (match_operand:QI 4 "register_operand" "Yk")))]
8173 "TARGET_AVX512VL" 8598 "TARGET_AVX512VL"
8174 "vunpcklpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" 8599 "vunpcklpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
8175 [(set_attr "type" "sselog") 8600 [(set_attr "type" "sselog")
8176 (set_attr "prefix" "evex") 8601 (set_attr "prefix" "evex")
8245 [(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))] 8670 [(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))]
8246 { 8671 {
8247 operands[1] = adjust_address (operands[1], DFmode, INTVAL (operands[2]) * 8); 8672 operands[1] = adjust_address (operands[1], DFmode, INTVAL (operands[2]) * 8);
8248 }) 8673 })
8249 8674
8250 (define_insn "avx512f_vmscalef<mode><round_name>" 8675 (define_insn "avx512f_vmscalef<mode><mask_scalar_name><round_scalar_name>"
8251 [(set (match_operand:VF_128 0 "register_operand" "=v") 8676 [(set (match_operand:VF_128 0 "register_operand" "=v")
8252 (vec_merge:VF_128 8677 (vec_merge:VF_128
8253 (unspec:VF_128 8678 (unspec:VF_128
8254 [(match_operand:VF_128 1 "register_operand" "v") 8679 [(match_operand:VF_128 1 "register_operand" "v")
8255 (match_operand:VF_128 2 "<round_nimm_predicate>" "<round_constraint>")] 8680 (match_operand:VF_128 2 "<round_scalar_nimm_predicate>" "<round_scalar_constraint>")]
8256 UNSPEC_SCALEF) 8681 UNSPEC_SCALEF)
8257 (match_dup 1) 8682 (match_dup 1)
8258 (const_int 1)))] 8683 (const_int 1)))]
8259 "TARGET_AVX512F" 8684 "TARGET_AVX512F"
8260 "vscalef<ssescalarmodesuffix>\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}" 8685 "vscalef<ssescalarmodesuffix>\t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1, %2<round_scalar_mask_op3>}"
8261 [(set_attr "prefix" "evex") 8686 [(set_attr "prefix" "evex")
8262 (set_attr "mode" "<ssescalarmode>")]) 8687 (set_attr "mode" "<ssescalarmode>")])
8263 8688
8264 (define_insn "<avx512>_scalef<mode><mask_name><round_name>" 8689 (define_insn "<avx512>_scalef<mode><mask_name><round_name>"
8265 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") 8690 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
8335 (match_operand:VF_128 2 "<round_saeonly_scalar_nimm_predicate>" "<round_saeonly_scalar_constraint>")] 8760 (match_operand:VF_128 2 "<round_saeonly_scalar_nimm_predicate>" "<round_saeonly_scalar_constraint>")]
8336 UNSPEC_GETEXP) 8761 UNSPEC_GETEXP)
8337 (match_dup 1) 8762 (match_dup 1)
8338 (const_int 1)))] 8763 (const_int 1)))]
8339 "TARGET_AVX512F" 8764 "TARGET_AVX512F"
8340 "vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1, %2<round_saeonly_scalar_mask_op3>}"; 8765 "vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1, %<iptr>2<round_saeonly_scalar_mask_op3>}";
8341 [(set_attr "prefix" "evex") 8766 [(set_attr "prefix" "evex")
8342 (set_attr "mode" "<ssescalarmode>")]) 8767 (set_attr "mode" "<ssescalarmode>")])
8343 8768
8344 (define_insn "<mask_codefor><avx512>_align<mode><mask_name>" 8769 (define_insn "<mask_codefor><avx512>_align<mode><mask_name>"
8345 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") 8770 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
8455 (match_operand:SI 4 "const_0_to_255_operand")] 8880 (match_operand:SI 4 "const_0_to_255_operand")]
8456 UNSPEC_FIXUPIMM) 8881 UNSPEC_FIXUPIMM)
8457 (match_dup 1) 8882 (match_dup 1)
8458 (const_int 1)))] 8883 (const_int 1)))]
8459 "TARGET_AVX512F" 8884 "TARGET_AVX512F"
8460 "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %3<round_saeonly_sd_mask_op5>, %4}"; 8885 "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %<iptr>3<round_saeonly_sd_mask_op5>, %4}";
8461 [(set_attr "prefix" "evex") 8886 [(set_attr "prefix" "evex")
8462 (set_attr "mode" "<ssescalarmode>")]) 8887 (set_attr "mode" "<ssescalarmode>")])
8463 8888
8464 (define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>" 8889 (define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>"
8465 [(set (match_operand:VF_128 0 "register_operand" "=v") 8890 [(set (match_operand:VF_128 0 "register_operand" "=v")
8474 (match_dup 1) 8899 (match_dup 1)
8475 (const_int 1)) 8900 (const_int 1))
8476 (match_dup 1) 8901 (match_dup 1)
8477 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] 8902 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
8478 "TARGET_AVX512F" 8903 "TARGET_AVX512F"
8479 "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2, %0%{%5%}|%0%{%5%}, %2, %3<round_saeonly_op6>, %4}"; 8904 "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2, %0%{%5%}|%0%{%5%}, %2, %<iptr>3<round_saeonly_op6>, %4}";
8480 [(set_attr "prefix" "evex") 8905 [(set_attr "prefix" "evex")
8481 (set_attr "mode" "<ssescalarmode>")]) 8906 (set_attr "mode" "<ssescalarmode>")])
8482 8907
8483 (define_insn "<avx512>_rndscale<mode><mask_name><round_saeonly_name>" 8908 (define_insn "<avx512>_rndscale<mode><mask_name><round_saeonly_name>"
8484 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") 8909 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
8501 (match_operand:SI 3 "const_0_to_255_operand")] 8926 (match_operand:SI 3 "const_0_to_255_operand")]
8502 UNSPEC_ROUND) 8927 UNSPEC_ROUND)
8503 (match_dup 1) 8928 (match_dup 1)
8504 (const_int 1)))] 8929 (const_int 1)))]
8505 "TARGET_AVX512F" 8930 "TARGET_AVX512F"
8506 "vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}" 8931 "vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %<iptr>2<round_saeonly_op4>, %3}"
8507 [(set_attr "length_immediate" "1") 8932 [(set_attr "length_immediate" "1")
8508 (set_attr "prefix" "evex") 8933 (set_attr "prefix" "evex")
8509 (set_attr "mode" "<MODE>")]) 8934 (set_attr "mode" "<MODE>")])
8510 8935
8511 ;; One bit in mask selects 2 elements. 8936 ;; One bit in mask selects 2 elements.
8683 (vec_concat:V4DF 9108 (vec_concat:V4DF
8684 (match_operand:V2DF 1 "register_operand" "v") 9109 (match_operand:V2DF 1 "register_operand" "v")
8685 (match_operand:V2DF 2 "nonimmediate_operand" "vm")) 9110 (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
8686 (parallel [(match_operand 3 "const_0_to_1_operand") 9111 (parallel [(match_operand 3 "const_0_to_1_operand")
8687 (match_operand 4 "const_2_to_3_operand")])) 9112 (match_operand 4 "const_2_to_3_operand")]))
8688 (match_operand:V2DF 5 "vector_move_operand" "0C") 9113 (match_operand:V2DF 5 "nonimm_or_0_operand" "0C")
8689 (match_operand:QI 6 "register_operand" "Yk")))] 9114 (match_operand:QI 6 "register_operand" "Yk")))]
8690 "TARGET_AVX512VL" 9115 "TARGET_AVX512VL"
8691 { 9116 {
8692 int mask; 9117 int mask;
8693 mask = INTVAL (operands[3]); 9118 mask = INTVAL (operands[3]);
8694 mask |= (INTVAL (operands[4]) - 2) << 1; 9119 mask |= (INTVAL (operands[4]) - 2) << 1;
8695 operands[3] = GEN_INT (mask); 9120 operands[3] = GEN_INT (mask);
8696 9121
8697 return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{6%}%N5, %1, %2, %3}"; 9122 return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{%6%}%N5, %1, %2, %3}";
8698 } 9123 }
8699 [(set_attr "type" "sseshuf") 9124 [(set_attr "type" "sseshuf")
8700 (set_attr "length_immediate" "1") 9125 (set_attr "length_immediate" "1")
8701 (set_attr "prefix" "evex") 9126 (set_attr "prefix" "evex")
8702 (set_attr "mode" "V2DF")]) 9127 (set_attr "mode" "V2DF")])
8949 9374
8950 ;; Avoid combining registers from different units in a single alternative, 9375 ;; Avoid combining registers from different units in a single alternative,
8951 ;; see comment above inline_secondary_memory_needed function in i386.c 9376 ;; see comment above inline_secondary_memory_needed function in i386.c
8952 (define_insn "sse2_loadhpd" 9377 (define_insn "sse2_loadhpd"
8953 [(set (match_operand:V2DF 0 "nonimmediate_operand" 9378 [(set (match_operand:V2DF 0 "nonimmediate_operand"
8954 "=x,v,x,v,o,o ,o") 9379 "=x,v,x,v ,o,o ,o")
8955 (vec_concat:V2DF 9380 (vec_concat:V2DF
8956 (vec_select:DF 9381 (vec_select:DF
8957 (match_operand:V2DF 1 "nonimmediate_operand" 9382 (match_operand:V2DF 1 "nonimmediate_operand"
8958 " 0,v,0,v,0,0 ,0") 9383 " 0,v,0,v ,0,0 ,0")
8959 (parallel [(const_int 0)])) 9384 (parallel [(const_int 0)]))
8960 (match_operand:DF 2 "nonimmediate_operand" 9385 (match_operand:DF 2 "nonimmediate_operand"
8961 " m,m,x,v,x,*f,r")))] 9386 " m,m,x,Yv,x,*f,r")))]
8962 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" 9387 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
8963 "@ 9388 "@
8964 movhpd\t{%2, %0|%0, %2} 9389 movhpd\t{%2, %0|%0, %2}
8965 vmovhpd\t{%2, %1, %0|%0, %1, %2} 9390 vmovhpd\t{%2, %1, %0|%0, %1, %2}
8966 unpcklpd\t{%2, %0|%0, %2} 9391 unpcklpd\t{%2, %0|%0, %2}
9013 "=v,x,v,x,v,x,x,v,m,m ,m") 9438 "=v,x,v,x,v,x,x,v,m,m ,m")
9014 (vec_concat:V2DF 9439 (vec_concat:V2DF
9015 (match_operand:DF 2 "nonimmediate_operand" 9440 (match_operand:DF 2 "nonimmediate_operand"
9016 "vm,m,m,x,v,0,0,v,x,*f,r") 9441 "vm,m,m,x,v,0,0,v,x,*f,r")
9017 (vec_select:DF 9442 (vec_select:DF
9018 (match_operand:V2DF 1 "vector_move_operand" 9443 (match_operand:V2DF 1 "nonimm_or_0_operand"
9019 " C,0,v,0,v,x,o,o,0,0 ,0") 9444 " C,0,v,0,v,x,o,o,0,0 ,0")
9020 (parallel [(const_int 1)]))))] 9445 (parallel [(const_int 1)]))))]
9021 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" 9446 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9022 "@ 9447 "@
9023 %vmovq\t{%2, %0|%0, %2} 9448 %vmovq\t{%2, %0|%0, %2}
9127 9552
9128 (define_insn "vec_concatv2df" 9553 (define_insn "vec_concatv2df"
9129 [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x, v,x,x") 9554 [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x, v,x,x")
9130 (vec_concat:V2DF 9555 (vec_concat:V2DF
9131 (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,xm,0,0") 9556 (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,xm,0,0")
9132 (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m, C,x,m")))] 9557 (match_operand:DF 2 "nonimm_or_0_operand" " x,x,v,1,1,m,m, C,x,m")))]
9133 "TARGET_SSE 9558 "TARGET_SSE
9134 && (!(MEM_P (operands[1]) && MEM_P (operands[2])) 9559 && (!(MEM_P (operands[1]) && MEM_P (operands[2]))
9135 || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" 9560 || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
9136 "@ 9561 "@
9137 unpcklpd\t{%2, %0|%0, %2} 9562 unpcklpd\t{%2, %0|%0, %2}
9175 (const_string "maybe_vex") 9600 (const_string "maybe_vex")
9176 ] 9601 ]
9177 (const_string "orig"))) 9602 (const_string "orig")))
9178 (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) 9603 (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
9179 9604
9605 ;; vmovq clears also the higher bits.
9606 (define_insn "vec_set<mode>_0"
9607 [(set (match_operand:VF2_512_256 0 "register_operand" "=v")
9608 (vec_merge:VF2_512_256
9609 (vec_duplicate:VF2_512_256
9610 (match_operand:<ssescalarmode> 2 "general_operand" "xm"))
9611 (match_operand:VF2_512_256 1 "const0_operand" "C")
9612 (const_int 1)))]
9613 "TARGET_AVX"
9614 "vmovq\t{%2, %x0|%x0, %2}"
9615 [(set_attr "type" "ssemov")
9616 (set_attr "prefix" "maybe_evex")
9617 (set_attr "mode" "DF")])
9618
9180 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 9619 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9181 ;; 9620 ;;
9182 ;; Parallel integer down-conversion operations 9621 ;; Parallel integer down-conversion operations
9183 ;; 9622 ;;
9184 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 9623 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9205 (define_insn "avx512f_<code><pmov_src_lower><mode>2_mask" 9644 (define_insn "avx512f_<code><pmov_src_lower><mode>2_mask"
9206 [(set (match_operand:PMOV_DST_MODE_1 0 "nonimmediate_operand" "=v,m") 9645 [(set (match_operand:PMOV_DST_MODE_1 0 "nonimmediate_operand" "=v,m")
9207 (vec_merge:PMOV_DST_MODE_1 9646 (vec_merge:PMOV_DST_MODE_1
9208 (any_truncate:PMOV_DST_MODE_1 9647 (any_truncate:PMOV_DST_MODE_1
9209 (match_operand:<pmov_src_mode> 1 "register_operand" "v,v")) 9648 (match_operand:<pmov_src_mode> 1 "register_operand" "v,v"))
9210 (match_operand:PMOV_DST_MODE_1 2 "vector_move_operand" "0C,0") 9649 (match_operand:PMOV_DST_MODE_1 2 "nonimm_or_0_operand" "0C,0")
9211 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] 9650 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
9212 "TARGET_AVX512F" 9651 "TARGET_AVX512F"
9213 "vpmov<trunsuffix><pmov_suff_1>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 9652 "vpmov<trunsuffix><pmov_suff_1>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
9214 [(set_attr "type" "ssemov") 9653 [(set_attr "type" "ssemov")
9215 (set_attr "memory" "none,store") 9654 (set_attr "memory" "none,store")
9239 (define_insn "avx512bw_<code>v32hiv32qi2_mask" 9678 (define_insn "avx512bw_<code>v32hiv32qi2_mask"
9240 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m") 9679 [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m")
9241 (vec_merge:V32QI 9680 (vec_merge:V32QI
9242 (any_truncate:V32QI 9681 (any_truncate:V32QI
9243 (match_operand:V32HI 1 "register_operand" "v,v")) 9682 (match_operand:V32HI 1 "register_operand" "v,v"))
9244 (match_operand:V32QI 2 "vector_move_operand" "0C,0") 9683 (match_operand:V32QI 2 "nonimm_or_0_operand" "0C,0")
9245 (match_operand:SI 3 "register_operand" "Yk,Yk")))] 9684 (match_operand:SI 3 "register_operand" "Yk,Yk")))]
9246 "TARGET_AVX512BW" 9685 "TARGET_AVX512BW"
9247 "vpmov<trunsuffix>wb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 9686 "vpmov<trunsuffix>wb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
9248 [(set_attr "type" "ssemov") 9687 [(set_attr "type" "ssemov")
9249 (set_attr "memory" "none,store") 9688 (set_attr "memory" "none,store")
9278 (define_insn "<avx512>_<code><ssedoublemodelower><mode>2_mask" 9717 (define_insn "<avx512>_<code><ssedoublemodelower><mode>2_mask"
9279 [(set (match_operand:PMOV_DST_MODE_2 0 "nonimmediate_operand" "=v,m") 9718 [(set (match_operand:PMOV_DST_MODE_2 0 "nonimmediate_operand" "=v,m")
9280 (vec_merge:PMOV_DST_MODE_2 9719 (vec_merge:PMOV_DST_MODE_2
9281 (any_truncate:PMOV_DST_MODE_2 9720 (any_truncate:PMOV_DST_MODE_2
9282 (match_operand:<ssedoublemode> 1 "register_operand" "v,v")) 9721 (match_operand:<ssedoublemode> 1 "register_operand" "v,v"))
9283 (match_operand:PMOV_DST_MODE_2 2 "vector_move_operand" "0C,0") 9722 (match_operand:PMOV_DST_MODE_2 2 "nonimm_or_0_operand" "0C,0")
9284 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] 9723 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
9285 "TARGET_AVX512VL" 9724 "TARGET_AVX512VL"
9286 "vpmov<trunsuffix><pmov_suff_2>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 9725 "vpmov<trunsuffix><pmov_suff_2>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
9287 [(set_attr "type" "ssemov") 9726 [(set_attr "type" "ssemov")
9288 (set_attr "memory" "none,store") 9727 (set_attr "memory" "none,store")
9331 (const_int 8) (const_int 9) 9770 (const_int 8) (const_int 9)
9332 (const_int 10) (const_int 11) 9771 (const_int 10) (const_int 11)
9333 (const_int 12) (const_int 13) 9772 (const_int 12) (const_int 13)
9334 (const_int 14) (const_int 15)]))))] 9773 (const_int 14) (const_int 15)]))))]
9335 "TARGET_AVX512VL" 9774 "TARGET_AVX512VL"
9336 "vpmov<trunsuffix>qb\t{%1, %0|%0, %1}" 9775 "vpmov<trunsuffix>qb\t{%1, %0|%w0, %1}"
9337 [(set_attr "type" "ssemov") 9776 [(set_attr "type" "ssemov")
9338 (set_attr "memory" "store") 9777 (set_attr "memory" "store")
9339 (set_attr "prefix" "evex") 9778 (set_attr "prefix" "evex")
9340 (set_attr "mode" "TI")]) 9779 (set_attr "mode" "TI")])
9341 9780
9344 (vec_concat:V16QI 9783 (vec_concat:V16QI
9345 (vec_merge:V2QI 9784 (vec_merge:V2QI
9346 (any_truncate:V2QI 9785 (any_truncate:V2QI
9347 (match_operand:V2DI 1 "register_operand" "v")) 9786 (match_operand:V2DI 1 "register_operand" "v"))
9348 (vec_select:V2QI 9787 (vec_select:V2QI
9349 (match_operand:V16QI 2 "vector_move_operand" "0C") 9788 (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
9350 (parallel [(const_int 0) (const_int 1)])) 9789 (parallel [(const_int 0) (const_int 1)]))
9351 (match_operand:QI 3 "register_operand" "Yk")) 9790 (match_operand:QI 3 "register_operand" "Yk"))
9352 (const_vector:V14QI [(const_int 0) (const_int 0) 9791 (const_vector:V14QI [(const_int 0) (const_int 0)
9353 (const_int 0) (const_int 0) 9792 (const_int 0) (const_int 0)
9354 (const_int 0) (const_int 0) 9793 (const_int 0) (const_int 0)
9421 (const_int 8) (const_int 9) 9860 (const_int 8) (const_int 9)
9422 (const_int 10) (const_int 11) 9861 (const_int 10) (const_int 11)
9423 (const_int 12) (const_int 13) 9862 (const_int 12) (const_int 13)
9424 (const_int 14) (const_int 15)]))))] 9863 (const_int 14) (const_int 15)]))))]
9425 "TARGET_AVX512VL" 9864 "TARGET_AVX512VL"
9426 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}" 9865 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%k0, %1}"
9427 [(set_attr "type" "ssemov") 9866 [(set_attr "type" "ssemov")
9428 (set_attr "memory" "store") 9867 (set_attr "memory" "store")
9429 (set_attr "prefix" "evex") 9868 (set_attr "prefix" "evex")
9430 (set_attr "mode" "TI")]) 9869 (set_attr "mode" "TI")])
9431 9870
9434 (vec_concat:V16QI 9873 (vec_concat:V16QI
9435 (vec_merge:V4QI 9874 (vec_merge:V4QI
9436 (any_truncate:V4QI 9875 (any_truncate:V4QI
9437 (match_operand:VI4_128_8_256 1 "register_operand" "v")) 9876 (match_operand:VI4_128_8_256 1 "register_operand" "v"))
9438 (vec_select:V4QI 9877 (vec_select:V4QI
9439 (match_operand:V16QI 2 "vector_move_operand" "0C") 9878 (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
9440 (parallel [(const_int 0) (const_int 1) 9879 (parallel [(const_int 0) (const_int 1)
9441 (const_int 2) (const_int 3)])) 9880 (const_int 2) (const_int 3)]))
9442 (match_operand:QI 3 "register_operand" "Yk")) 9881 (match_operand:QI 3 "register_operand" "Yk"))
9443 (const_vector:V12QI [(const_int 0) (const_int 0) 9882 (const_vector:V12QI [(const_int 0) (const_int 0)
9444 (const_int 0) (const_int 0) 9883 (const_int 0) (const_int 0)
9491 (const_int 8) (const_int 9) 9930 (const_int 8) (const_int 9)
9492 (const_int 10) (const_int 11) 9931 (const_int 10) (const_int 11)
9493 (const_int 12) (const_int 13) 9932 (const_int 12) (const_int 13)
9494 (const_int 14) (const_int 15)]))))] 9933 (const_int 14) (const_int 15)]))))]
9495 "TARGET_AVX512VL" 9934 "TARGET_AVX512VL"
9496 { 9935 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}"
9497 if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 8)
9498 return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}";
9499 return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
9500 }
9501 [(set_attr "type" "ssemov") 9936 [(set_attr "type" "ssemov")
9502 (set_attr "memory" "store") 9937 (set_attr "memory" "store")
9503 (set_attr "prefix" "evex") 9938 (set_attr "prefix" "evex")
9504 (set_attr "mode" "TI")]) 9939 (set_attr "mode" "TI")])
9505 9940
9516 (parallel [(const_int 8) (const_int 9) 9951 (parallel [(const_int 8) (const_int 9)
9517 (const_int 10) (const_int 11) 9952 (const_int 10) (const_int 11)
9518 (const_int 12) (const_int 13) 9953 (const_int 12) (const_int 13)
9519 (const_int 14) (const_int 15)]))))] 9954 (const_int 14) (const_int 15)]))))]
9520 "TARGET_AVX512VL" 9955 "TARGET_AVX512VL"
9521 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}" 9956 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%q0, %1}"
9522 [(set_attr "type" "ssemov") 9957 [(set_attr "type" "ssemov")
9523 (set_attr "memory" "store") 9958 (set_attr "memory" "store")
9524 (set_attr "prefix" "evex") 9959 (set_attr "prefix" "evex")
9525 (set_attr "mode" "TI")]) 9960 (set_attr "mode" "TI")])
9526 9961
9529 (vec_concat:V16QI 9964 (vec_concat:V16QI
9530 (vec_merge:V8QI 9965 (vec_merge:V8QI
9531 (any_truncate:V8QI 9966 (any_truncate:V8QI
9532 (match_operand:VI2_128_BW_4_256 1 "register_operand" "v")) 9967 (match_operand:VI2_128_BW_4_256 1 "register_operand" "v"))
9533 (vec_select:V8QI 9968 (vec_select:V8QI
9534 (match_operand:V16QI 2 "vector_move_operand" "0C") 9969 (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
9535 (parallel [(const_int 0) (const_int 1) 9970 (parallel [(const_int 0) (const_int 1)
9536 (const_int 2) (const_int 3) 9971 (const_int 2) (const_int 3)
9537 (const_int 4) (const_int 5) 9972 (const_int 4) (const_int 5)
9538 (const_int 6) (const_int 7)])) 9973 (const_int 6) (const_int 7)]))
9539 (match_operand:QI 3 "register_operand" "Yk")) 9974 (match_operand:QI 3 "register_operand" "Yk"))
9586 (parallel [(const_int 8) (const_int 9) 10021 (parallel [(const_int 8) (const_int 9)
9587 (const_int 10) (const_int 11) 10022 (const_int 10) (const_int 11)
9588 (const_int 12) (const_int 13) 10023 (const_int 12) (const_int 13)
9589 (const_int 14) (const_int 15)]))))] 10024 (const_int 14) (const_int 15)]))))]
9590 "TARGET_AVX512VL" 10025 "TARGET_AVX512VL"
9591 { 10026 "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%q0%{%2%}, %1}"
9592 if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4)
9593 return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
9594 return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
9595 }
9596 [(set_attr "type" "ssemov") 10027 [(set_attr "type" "ssemov")
9597 (set_attr "memory" "store") 10028 (set_attr "memory" "store")
9598 (set_attr "prefix" "evex") 10029 (set_attr "prefix" "evex")
9599 (set_attr "mode" "TI")]) 10030 (set_attr "mode" "TI")])
9600 10031
9639 (vec_concat:V8HI 10070 (vec_concat:V8HI
9640 (vec_merge:V4HI 10071 (vec_merge:V4HI
9641 (any_truncate:V4HI 10072 (any_truncate:V4HI
9642 (match_operand:VI4_128_8_256 1 "register_operand" "v")) 10073 (match_operand:VI4_128_8_256 1 "register_operand" "v"))
9643 (vec_select:V4HI 10074 (vec_select:V4HI
9644 (match_operand:V8HI 2 "vector_move_operand" "0C") 10075 (match_operand:V8HI 2 "nonimm_or_0_operand" "0C")
9645 (parallel [(const_int 0) (const_int 1) 10076 (parallel [(const_int 0) (const_int 1)
9646 (const_int 2) (const_int 3)])) 10077 (const_int 2) (const_int 3)]))
9647 (match_operand:QI 3 "register_operand" "Yk")) 10078 (match_operand:QI 3 "register_operand" "Yk"))
9648 (const_vector:V4HI [(const_int 0) (const_int 0) 10079 (const_vector:V4HI [(const_int 0) (const_int 0)
9649 (const_int 0) (const_int 0)])))] 10080 (const_int 0) (const_int 0)])))]
9718 (vec_concat:V8HI 10149 (vec_concat:V8HI
9719 (vec_merge:V2HI 10150 (vec_merge:V2HI
9720 (any_truncate:V2HI 10151 (any_truncate:V2HI
9721 (match_operand:V2DI 1 "register_operand" "v")) 10152 (match_operand:V2DI 1 "register_operand" "v"))
9722 (vec_select:V2HI 10153 (vec_select:V2HI
9723 (match_operand:V8HI 2 "vector_move_operand" "0C") 10154 (match_operand:V8HI 2 "nonimm_or_0_operand" "0C")
9724 (parallel [(const_int 0) (const_int 1)])) 10155 (parallel [(const_int 0) (const_int 1)]))
9725 (match_operand:QI 3 "register_operand" "Yk")) 10156 (match_operand:QI 3 "register_operand" "Yk"))
9726 (const_vector:V6HI [(const_int 0) (const_int 0) 10157 (const_vector:V6HI [(const_int 0) (const_int 0)
9727 (const_int 0) (const_int 0) 10158 (const_int 0) (const_int 0)
9728 (const_int 0) (const_int 0)])))] 10159 (const_int 0) (const_int 0)])))]
9803 (vec_concat:V4SI 10234 (vec_concat:V4SI
9804 (vec_merge:V2SI 10235 (vec_merge:V2SI
9805 (any_truncate:V2SI 10236 (any_truncate:V2SI
9806 (match_operand:V2DI 1 "register_operand" "v")) 10237 (match_operand:V2DI 1 "register_operand" "v"))
9807 (vec_select:V2SI 10238 (vec_select:V2SI
9808 (match_operand:V4SI 2 "vector_move_operand" "0C") 10239 (match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
9809 (parallel [(const_int 0) (const_int 1)])) 10240 (parallel [(const_int 0) (const_int 1)]))
9810 (match_operand:QI 3 "register_operand" "Yk")) 10241 (match_operand:QI 3 "register_operand" "Yk"))
9811 (const_vector:V2SI [(const_int 0) (const_int 0)])))] 10242 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
9812 "TARGET_AVX512VL" 10243 "TARGET_AVX512VL"
9813 "vpmov<trunsuffix>qd\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 10244 "vpmov<trunsuffix>qd\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
9888 (vec_concat:V16QI 10319 (vec_concat:V16QI
9889 (vec_merge:V8QI 10320 (vec_merge:V8QI
9890 (any_truncate:V8QI 10321 (any_truncate:V8QI
9891 (match_operand:V8DI 1 "register_operand" "v")) 10322 (match_operand:V8DI 1 "register_operand" "v"))
9892 (vec_select:V8QI 10323 (vec_select:V8QI
9893 (match_operand:V16QI 2 "vector_move_operand" "0C") 10324 (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
9894 (parallel [(const_int 0) (const_int 1) 10325 (parallel [(const_int 0) (const_int 1)
9895 (const_int 2) (const_int 3) 10326 (const_int 2) (const_int 3)
9896 (const_int 4) (const_int 5) 10327 (const_int 4) (const_int 5)
9897 (const_int 6) (const_int 7)])) 10328 (const_int 6) (const_int 7)]))
9898 (match_operand:QI 3 "register_operand" "Yk")) 10329 (match_operand:QI 3 "register_operand" "Yk"))
9979 [(set (match_operand:VI48_AVX512VL 0 "register_operand") 10410 [(set (match_operand:VI48_AVX512VL 0 "register_operand")
9980 (vec_merge:VI48_AVX512VL 10411 (vec_merge:VI48_AVX512VL
9981 (plusminus:VI48_AVX512VL 10412 (plusminus:VI48_AVX512VL
9982 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") 10413 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
9983 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) 10414 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
9984 (match_operand:VI48_AVX512VL 3 "vector_move_operand") 10415 (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
9985 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 10416 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
9986 "TARGET_AVX512F" 10417 "TARGET_AVX512F"
9987 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") 10418 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
9988 10419
9989 (define_expand "<plusminus_insn><mode>3_mask" 10420 (define_expand "<plusminus_insn><mode>3_mask"
9990 [(set (match_operand:VI12_AVX512VL 0 "register_operand") 10421 [(set (match_operand:VI12_AVX512VL 0 "register_operand")
9991 (vec_merge:VI12_AVX512VL 10422 (vec_merge:VI12_AVX512VL
9992 (plusminus:VI12_AVX512VL 10423 (plusminus:VI12_AVX512VL
9993 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") 10424 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
9994 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) 10425 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand"))
9995 (match_operand:VI12_AVX512VL 3 "vector_move_operand") 10426 (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand")
9996 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 10427 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
9997 "TARGET_AVX512BW" 10428 "TARGET_AVX512BW"
9998 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") 10429 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
9999 10430
10000 (define_insn "*<plusminus_insn><mode>3" 10431 (define_insn "*<plusminus_insn><mode>3"
10001 [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") 10432 [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v")
10002 (plusminus:VI_AVX2 10433 (plusminus:VI_AVX2
10003 (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v") 10434 (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v")
10004 (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))] 10435 (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))]
10005 "TARGET_SSE2 10436 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10006 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10007 "@ 10437 "@
10008 p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} 10438 p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
10009 vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10439 vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
10010 [(set_attr "isa" "noavx,avx") 10440 [(set_attr "isa" "noavx,avx")
10011 (set_attr "type" "sseiadd") 10441 (set_attr "type" "sseiadd")
10012 (set_attr "prefix_data16" "1,*") 10442 (set_attr "prefix_data16" "1,*")
10013 (set_attr "prefix" "<mask_prefix3>") 10443 (set_attr "prefix" "orig,vex")
10444 (set_attr "mode" "<sseinsnmode>")])
10445
10446 (define_insn "*sub<mode>3_bcst"
10447 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
10448 (minus:VI48_AVX512VL
10449 (match_operand:VI48_AVX512VL 1 "register_operand" "v")
10450 (vec_duplicate:VI48_AVX512VL
10451 (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
10452 "TARGET_AVX512F && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
10453 "vpsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
10454 [(set_attr "type" "sseiadd")
10455 (set_attr "prefix" "evex")
10456 (set_attr "mode" "<sseinsnmode>")])
10457
10458 (define_insn "*add<mode>3_bcst"
10459 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
10460 (plus:VI48_AVX512VL
10461 (vec_duplicate:VI48_AVX512VL
10462 (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
10463 (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
10464 "TARGET_AVX512F && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
10465 "vpadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0|%0, %2, %1<avx512bcst>}"
10466 [(set_attr "type" "sseiadd")
10467 (set_attr "prefix" "evex")
10014 (set_attr "mode" "<sseinsnmode>")]) 10468 (set_attr "mode" "<sseinsnmode>")])
10015 10469
10016 (define_insn "*<plusminus_insn><mode>3_mask" 10470 (define_insn "*<plusminus_insn><mode>3_mask"
10017 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") 10471 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
10018 (vec_merge:VI48_AVX512VL 10472 (vec_merge:VI48_AVX512VL
10019 (plusminus:VI48_AVX512VL 10473 (plusminus:VI48_AVX512VL
10020 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "<comm>v") 10474 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "<comm>v")
10021 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) 10475 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
10022 (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C") 10476 (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C")
10023 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] 10477 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
10024 "TARGET_AVX512F 10478 "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10025 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10026 "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" 10479 "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
10027 [(set_attr "type" "sseiadd") 10480 [(set_attr "type" "sseiadd")
10028 (set_attr "prefix" "evex") 10481 (set_attr "prefix" "evex")
10029 (set_attr "mode" "<sseinsnmode>")]) 10482 (set_attr "mode" "<sseinsnmode>")])
10030 10483
10032 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") 10485 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
10033 (vec_merge:VI12_AVX512VL 10486 (vec_merge:VI12_AVX512VL
10034 (plusminus:VI12_AVX512VL 10487 (plusminus:VI12_AVX512VL
10035 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "<comm>v") 10488 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "<comm>v")
10036 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) 10489 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm"))
10037 (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C") 10490 (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand" "0C")
10038 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] 10491 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
10039 "TARGET_AVX512BW && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 10492 "TARGET_AVX512BW && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10040 "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" 10493 "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
10041 [(set_attr "type" "sseiadd") 10494 [(set_attr "type" "sseiadd")
10042 (set_attr "prefix" "evex") 10495 (set_attr "prefix" "evex")
10085 10538
10086 (define_insn "*mul<mode>3<mask_name>" 10539 (define_insn "*mul<mode>3<mask_name>"
10087 [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v") 10540 [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
10088 (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v") 10541 (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")
10089 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))] 10542 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))]
10090 "TARGET_SSE2 10543 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
10091 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
10092 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" 10544 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
10093 "@ 10545 "@
10094 pmullw\t{%2, %0|%0, %2} 10546 pmullw\t{%2, %0|%0, %2}
10095 vpmullw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10547 vpmullw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10096 [(set_attr "isa" "noavx,avx") 10548 [(set_attr "isa" "noavx,avx")
10121 (any_extend:<ssedoublemode> 10573 (any_extend:<ssedoublemode>
10122 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")) 10574 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v"))
10123 (any_extend:<ssedoublemode> 10575 (any_extend:<ssedoublemode>
10124 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) 10576 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
10125 (const_int 16))))] 10577 (const_int 16))))]
10126 "TARGET_SSE2 10578 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
10127 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
10128 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" 10579 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
10129 "@ 10580 "@
10130 pmulh<u>w\t{%2, %0|%0, %2} 10581 pmulh<u>w\t{%2, %0|%0, %2}
10131 vpmulh<u>w\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10582 vpmulh<u>w\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10132 [(set_attr "isa" "noavx,avx") 10583 [(set_attr "isa" "noavx,avx")
10170 (match_operand:V16SI 2 "nonimmediate_operand" "vm") 10621 (match_operand:V16SI 2 "nonimmediate_operand" "vm")
10171 (parallel [(const_int 0) (const_int 2) 10622 (parallel [(const_int 0) (const_int 2)
10172 (const_int 4) (const_int 6) 10623 (const_int 4) (const_int 6)
10173 (const_int 8) (const_int 10) 10624 (const_int 8) (const_int 10)
10174 (const_int 12) (const_int 14)])))))] 10625 (const_int 12) (const_int 14)])))))]
10175 "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)" 10626 "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10176 "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10627 "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10177 [(set_attr "type" "sseimul") 10628 [(set_attr "type" "sseimul")
10178 (set_attr "prefix_extra" "1") 10629 (set_attr "prefix_extra" "1")
10179 (set_attr "prefix" "evex") 10630 (set_attr "prefix" "evex")
10180 (set_attr "mode" "XI")]) 10631 (set_attr "mode" "XI")])
10207 (vec_select:V4SI 10658 (vec_select:V4SI
10208 (match_operand:V8SI 2 "nonimmediate_operand" "vm") 10659 (match_operand:V8SI 2 "nonimmediate_operand" "vm")
10209 (parallel [(const_int 0) (const_int 2) 10660 (parallel [(const_int 0) (const_int 2)
10210 (const_int 4) (const_int 6)])))))] 10661 (const_int 4) (const_int 6)])))))]
10211 "TARGET_AVX2 && <mask_avx512vl_condition> 10662 "TARGET_AVX2 && <mask_avx512vl_condition>
10212 && ix86_binary_operator_ok (MULT, V8SImode, operands)" 10663 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10213 "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10664 "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10214 [(set_attr "type" "sseimul") 10665 [(set_attr "type" "sseimul")
10215 (set_attr "prefix" "maybe_evex") 10666 (set_attr "prefix" "maybe_evex")
10216 (set_attr "mode" "OI")]) 10667 (set_attr "mode" "OI")])
10217 10668
10239 (zero_extend:V2DI 10690 (zero_extend:V2DI
10240 (vec_select:V2SI 10691 (vec_select:V2SI
10241 (match_operand:V4SI 2 "vector_operand" "xBm,vm") 10692 (match_operand:V4SI 2 "vector_operand" "xBm,vm")
10242 (parallel [(const_int 0) (const_int 2)])))))] 10693 (parallel [(const_int 0) (const_int 2)])))))]
10243 "TARGET_SSE2 && <mask_avx512vl_condition> 10694 "TARGET_SSE2 && <mask_avx512vl_condition>
10244 && ix86_binary_operator_ok (MULT, V4SImode, operands)" 10695 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10245 "@ 10696 "@
10246 pmuludq\t{%2, %0|%0, %2} 10697 pmuludq\t{%2, %0|%0, %2}
10247 vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10698 vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10248 [(set_attr "isa" "noavx,avx") 10699 [(set_attr "isa" "noavx,avx")
10249 (set_attr "type" "sseimul") 10700 (set_attr "type" "sseimul")
10286 (match_operand:V16SI 2 "nonimmediate_operand" "vm") 10737 (match_operand:V16SI 2 "nonimmediate_operand" "vm")
10287 (parallel [(const_int 0) (const_int 2) 10738 (parallel [(const_int 0) (const_int 2)
10288 (const_int 4) (const_int 6) 10739 (const_int 4) (const_int 6)
10289 (const_int 8) (const_int 10) 10740 (const_int 8) (const_int 10)
10290 (const_int 12) (const_int 14)])))))] 10741 (const_int 12) (const_int 14)])))))]
10291 "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)" 10742 "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10292 "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10743 "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10293 [(set_attr "type" "sseimul") 10744 [(set_attr "type" "sseimul")
10294 (set_attr "prefix_extra" "1") 10745 (set_attr "prefix_extra" "1")
10295 (set_attr "prefix" "evex") 10746 (set_attr "prefix" "evex")
10296 (set_attr "mode" "XI")]) 10747 (set_attr "mode" "XI")])
10322 (sign_extend:V4DI 10773 (sign_extend:V4DI
10323 (vec_select:V4SI 10774 (vec_select:V4SI
10324 (match_operand:V8SI 2 "nonimmediate_operand" "vm") 10775 (match_operand:V8SI 2 "nonimmediate_operand" "vm")
10325 (parallel [(const_int 0) (const_int 2) 10776 (parallel [(const_int 0) (const_int 2)
10326 (const_int 4) (const_int 6)])))))] 10777 (const_int 4) (const_int 6)])))))]
10327 "TARGET_AVX2 10778 "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10328 && ix86_binary_operator_ok (MULT, V8SImode, operands)"
10329 "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10779 "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10330 [(set_attr "type" "sseimul") 10780 [(set_attr "type" "sseimul")
10331 (set_attr "prefix_extra" "1") 10781 (set_attr "prefix_extra" "1")
10332 (set_attr "prefix" "vex") 10782 (set_attr "prefix" "vex")
10333 (set_attr "mode" "OI")]) 10783 (set_attr "mode" "OI")])
10356 (sign_extend:V2DI 10806 (sign_extend:V2DI
10357 (vec_select:V2SI 10807 (vec_select:V2SI
10358 (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm") 10808 (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm")
10359 (parallel [(const_int 0) (const_int 2)])))))] 10809 (parallel [(const_int 0) (const_int 2)])))))]
10360 "TARGET_SSE4_1 && <mask_avx512vl_condition> 10810 "TARGET_SSE4_1 && <mask_avx512vl_condition>
10361 && ix86_binary_operator_ok (MULT, V4SImode, operands)" 10811 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10362 "@ 10812 "@
10363 pmuldq\t{%2, %0|%0, %2} 10813 pmuldq\t{%2, %0|%0, %2}
10364 pmuldq\t{%2, %0|%0, %2} 10814 pmuldq\t{%2, %0|%0, %2}
10365 vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 10815 vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10366 [(set_attr "isa" "noavx,noavx,avx") 10816 [(set_attr "isa" "noavx,noavx,avx")
10445 (vec_select:V8HI (match_dup 2) 10895 (vec_select:V8HI (match_dup 2)
10446 (parallel [(const_int 1) (const_int 3) 10896 (parallel [(const_int 1) (const_int 3)
10447 (const_int 5) (const_int 7) 10897 (const_int 5) (const_int 7)
10448 (const_int 9) (const_int 11) 10898 (const_int 9) (const_int 11)
10449 (const_int 13) (const_int 15)]))))))] 10899 (const_int 13) (const_int 15)]))))))]
10450 "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)" 10900 "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10451 "vpmaddwd\t{%2, %1, %0|%0, %1, %2}" 10901 "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
10452 [(set_attr "type" "sseiadd") 10902 [(set_attr "type" "sseiadd")
10453 (set_attr "isa" "*,avx512bw") 10903 (set_attr "isa" "*,avx512bw")
10454 (set_attr "prefix" "vex,evex") 10904 (set_attr "prefix" "vex,evex")
10455 (set_attr "mode" "OI")]) 10905 (set_attr "mode" "OI")])
10501 (const_int 5) (const_int 7)]))) 10951 (const_int 5) (const_int 7)])))
10502 (sign_extend:V4SI 10952 (sign_extend:V4SI
10503 (vec_select:V4HI (match_dup 2) 10953 (vec_select:V4HI (match_dup 2)
10504 (parallel [(const_int 1) (const_int 3) 10954 (parallel [(const_int 1) (const_int 3)
10505 (const_int 5) (const_int 7)]))))))] 10955 (const_int 5) (const_int 7)]))))))]
10506 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)" 10956 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10507 "@ 10957 "@
10508 pmaddwd\t{%2, %0|%0, %2} 10958 pmaddwd\t{%2, %0|%0, %2}
10509 vpmaddwd\t{%2, %1, %0|%0, %1, %2} 10959 vpmaddwd\t{%2, %1, %0|%0, %1, %2}
10510 vpmaddwd\t{%2, %1, %0|%0, %1, %2}" 10960 vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
10511 [(set_attr "isa" "noavx,avx,avx512bw") 10961 [(set_attr "isa" "noavx,avx,avx512bw")
10551 (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>" 11001 (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>"
10552 [(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v") 11002 [(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v")
10553 (mult:VI4_AVX512F 11003 (mult:VI4_AVX512F
10554 (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v") 11004 (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v")
10555 (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))] 11005 (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))]
10556 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition>" 11006 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
11007 && <mask_mode512bit_condition>"
10557 "@ 11008 "@
10558 pmulld\t{%2, %0|%0, %2} 11009 pmulld\t{%2, %0|%0, %2}
10559 pmulld\t{%2, %0|%0, %2} 11010 pmulld\t{%2, %0|%0, %2}
10560 vpmulld\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 11011 vpmulld\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10561 [(set_attr "isa" "noavx,noavx,avx") 11012 [(set_attr "isa" "noavx,noavx,avx")
10656 emit_insn (gen_xop_pmacsdqh (t, operands[1], operands[2], operands[3])); 11107 emit_insn (gen_xop_pmacsdqh (t, operands[1], operands[2], operands[3]));
10657 emit_insn (gen_xop_pmacsdql (operands[0], operands[1], operands[2], t)); 11108 emit_insn (gen_xop_pmacsdql (operands[0], operands[1], operands[2], t));
10658 DONE; 11109 DONE;
10659 }) 11110 })
10660 11111
11112 (define_expand "uavg<mode>3_ceil"
11113 [(set (match_operand:VI12_AVX2 0 "register_operand")
11114 (truncate:VI12_AVX2
11115 (lshiftrt:<ssedoublemode>
11116 (plus:<ssedoublemode>
11117 (plus:<ssedoublemode>
11118 (zero_extend:<ssedoublemode>
11119 (match_operand:VI12_AVX2 1 "vector_operand"))
11120 (zero_extend:<ssedoublemode>
11121 (match_operand:VI12_AVX2 2 "vector_operand")))
11122 (match_dup 3))
11123 (const_int 1))))]
11124 "TARGET_SSE2"
11125 {
11126 operands[3] = CONST1_RTX(<MODE>mode);
11127 ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
11128 })
11129
10661 (define_expand "usadv16qi" 11130 (define_expand "usadv16qi"
10662 [(match_operand:V4SI 0 "register_operand") 11131 [(match_operand:V4SI 0 "register_operand")
10663 (match_operand:V16QI 1 "register_operand") 11132 (match_operand:V16QI 1 "register_operand")
10664 (match_operand:V16QI 2 "vector_operand") 11133 (match_operand:V16QI 2 "vector_operand")
10665 (match_operand:V4SI 3 "vector_operand")] 11134 (match_operand:V4SI 3 "vector_operand")]
10683 rtx t1 = gen_reg_rtx (V4DImode); 11152 rtx t1 = gen_reg_rtx (V4DImode);
10684 rtx t2 = gen_reg_rtx (V8SImode); 11153 rtx t2 = gen_reg_rtx (V8SImode);
10685 emit_insn (gen_avx2_psadbw (t1, operands[1], operands[2])); 11154 emit_insn (gen_avx2_psadbw (t1, operands[1], operands[2]));
10686 convert_move (t2, t1, 0); 11155 convert_move (t2, t1, 0);
10687 emit_insn (gen_addv8si3 (operands[0], t2, operands[3])); 11156 emit_insn (gen_addv8si3 (operands[0], t2, operands[3]));
11157 DONE;
11158 })
11159
11160 (define_expand "usadv64qi"
11161 [(match_operand:V16SI 0 "register_operand")
11162 (match_operand:V64QI 1 "register_operand")
11163 (match_operand:V64QI 2 "nonimmediate_operand")
11164 (match_operand:V16SI 3 "nonimmediate_operand")]
11165 "TARGET_AVX512BW"
11166 {
11167 rtx t1 = gen_reg_rtx (V8DImode);
11168 rtx t2 = gen_reg_rtx (V16SImode);
11169 emit_insn (gen_avx512f_psadbw (t1, operands[1], operands[2]));
11170 convert_move (t2, t1, 0);
11171 emit_insn (gen_addv16si3 (operands[0], t2, operands[3]));
10688 DONE; 11172 DONE;
10689 }) 11173 })
10690 11174
10691 (define_insn "<mask_codefor>ashr<mode>3<mask_name>" 11175 (define_insn "<mask_codefor>ashr<mode>3<mask_name>"
10692 [(set (match_operand:VI248_AVX512BW_1 0 "register_operand" "=v,v") 11176 [(set (match_operand:VI248_AVX512BW_1 0 "register_operand" "=v,v")
10869 (define_insn "*avx2_<code><mode>3" 11353 (define_insn "*avx2_<code><mode>3"
10870 [(set (match_operand:VI124_256 0 "register_operand" "=v") 11354 [(set (match_operand:VI124_256 0 "register_operand" "=v")
10871 (maxmin:VI124_256 11355 (maxmin:VI124_256
10872 (match_operand:VI124_256 1 "nonimmediate_operand" "%v") 11356 (match_operand:VI124_256 1 "nonimmediate_operand" "%v")
10873 (match_operand:VI124_256 2 "nonimmediate_operand" "vm")))] 11357 (match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
10874 "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 11358 "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10875 "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" 11359 "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
10876 [(set_attr "type" "sseiadd") 11360 [(set_attr "type" "sseiadd")
10877 (set_attr "prefix_extra" "1") 11361 (set_attr "prefix_extra" "1")
10878 (set_attr "prefix" "vex") 11362 (set_attr "prefix" "vex")
10879 (set_attr "mode" "OI")]) 11363 (set_attr "mode" "OI")])
10882 [(set (match_operand:VI48_AVX512VL 0 "register_operand") 11366 [(set (match_operand:VI48_AVX512VL 0 "register_operand")
10883 (vec_merge:VI48_AVX512VL 11367 (vec_merge:VI48_AVX512VL
10884 (maxmin:VI48_AVX512VL 11368 (maxmin:VI48_AVX512VL
10885 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") 11369 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
10886 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) 11370 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
10887 (match_operand:VI48_AVX512VL 3 "vector_move_operand") 11371 (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
10888 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 11372 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
10889 "TARGET_AVX512F" 11373 "TARGET_AVX512F"
10890 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") 11374 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
10891 11375
10892 (define_insn "*avx512f_<code><mode>3<mask_name>" 11376 (define_insn "*avx512f_<code><mode>3<mask_name>"
10893 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") 11377 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
10894 (maxmin:VI48_AVX512VL 11378 (maxmin:VI48_AVX512VL
10895 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v") 11379 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
10896 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))] 11380 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))]
10897 "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 11381 "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
10898 "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 11382 "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
10899 [(set_attr "type" "sseiadd") 11383 [(set_attr "type" "sseiadd")
10900 (set_attr "prefix_extra" "1") 11384 (set_attr "prefix_extra" "1")
10901 (set_attr "prefix" "maybe_evex") 11385 (set_attr "prefix" "maybe_evex")
10902 (set_attr "mode" "<sseinsnmode>")]) 11386 (set_attr "mode" "<sseinsnmode>")])
10998 (smaxmin:VI14_128 11482 (smaxmin:VI14_128
10999 (match_operand:VI14_128 1 "vector_operand" "%0,0,v") 11483 (match_operand:VI14_128 1 "vector_operand" "%0,0,v")
11000 (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))] 11484 (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))]
11001 "TARGET_SSE4_1 11485 "TARGET_SSE4_1
11002 && <mask_mode512bit_condition> 11486 && <mask_mode512bit_condition>
11003 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 11487 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11004 "@ 11488 "@
11005 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} 11489 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
11006 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} 11490 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
11007 vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 11491 vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
11008 [(set_attr "isa" "noavx,noavx,avx") 11492 [(set_attr "isa" "noavx,noavx,avx")
11014 (define_insn "*<code>v8hi3" 11498 (define_insn "*<code>v8hi3"
11015 [(set (match_operand:V8HI 0 "register_operand" "=x,x,v") 11499 [(set (match_operand:V8HI 0 "register_operand" "=x,x,v")
11016 (smaxmin:V8HI 11500 (smaxmin:V8HI
11017 (match_operand:V8HI 1 "vector_operand" "%0,x,v") 11501 (match_operand:V8HI 1 "vector_operand" "%0,x,v")
11018 (match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))] 11502 (match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))]
11019 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" 11503 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11020 "@ 11504 "@
11021 p<maxmin_int>w\t{%2, %0|%0, %2} 11505 p<maxmin_int>w\t{%2, %0|%0, %2}
11022 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2} 11506 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}
11023 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}" 11507 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
11024 [(set_attr "isa" "noavx,avx,avx512bw") 11508 [(set_attr "isa" "noavx,avx,avx512bw")
11083 (umaxmin:VI24_128 11567 (umaxmin:VI24_128
11084 (match_operand:VI24_128 1 "vector_operand" "%0,0,v") 11568 (match_operand:VI24_128 1 "vector_operand" "%0,0,v")
11085 (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))] 11569 (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))]
11086 "TARGET_SSE4_1 11570 "TARGET_SSE4_1
11087 && <mask_mode512bit_condition> 11571 && <mask_mode512bit_condition>
11088 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 11572 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11089 "@ 11573 "@
11090 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} 11574 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
11091 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} 11575 p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
11092 vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 11576 vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
11093 [(set_attr "isa" "noavx,noavx,avx") 11577 [(set_attr "isa" "noavx,noavx,avx")
11099 (define_insn "*<code>v16qi3" 11583 (define_insn "*<code>v16qi3"
11100 [(set (match_operand:V16QI 0 "register_operand" "=x,x,v") 11584 [(set (match_operand:V16QI 0 "register_operand" "=x,x,v")
11101 (umaxmin:V16QI 11585 (umaxmin:V16QI
11102 (match_operand:V16QI 1 "vector_operand" "%0,x,v") 11586 (match_operand:V16QI 1 "vector_operand" "%0,x,v")
11103 (match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))] 11587 (match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))]
11104 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" 11588 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11105 "@ 11589 "@
11106 p<maxmin_int>b\t{%2, %0|%0, %2} 11590 p<maxmin_int>b\t{%2, %0|%0, %2}
11107 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2} 11591 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}
11108 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}" 11592 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
11109 [(set_attr "isa" "noavx,avx,avx512bw") 11593 [(set_attr "isa" "noavx,avx,avx512bw")
11130 (define_insn "*avx2_eq<mode>3" 11614 (define_insn "*avx2_eq<mode>3"
11131 [(set (match_operand:VI_256 0 "register_operand" "=x") 11615 [(set (match_operand:VI_256 0 "register_operand" "=x")
11132 (eq:VI_256 11616 (eq:VI_256
11133 (match_operand:VI_256 1 "nonimmediate_operand" "%x") 11617 (match_operand:VI_256 1 "nonimmediate_operand" "%x")
11134 (match_operand:VI_256 2 "nonimmediate_operand" "xm")))] 11618 (match_operand:VI_256 2 "nonimmediate_operand" "xm")))]
11135 "TARGET_AVX2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" 11619 "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11136 "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" 11620 "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
11137 [(set_attr "type" "ssecmp") 11621 [(set_attr "type" "ssecmp")
11138 (set_attr "prefix_extra" "1") 11622 (set_attr "prefix_extra" "1")
11139 (set_attr "prefix" "vex") 11623 (set_attr "prefix" "vex")
11140 (set_attr "mode" "OI")]) 11624 (set_attr "mode" "OI")])
11141 11625
11142 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>" 11626 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
11143 [(set (match_operand:<avx512fmaskmode> 0 "register_operand") 11627 [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
11144 (unspec:<avx512fmaskmode> 11628 (unspec:<avx512fmaskmode>
11145 [(match_operand:VI12_AVX512VL 1 "register_operand") 11629 [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
11146 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")] 11630 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
11147 UNSPEC_MASKED_EQ))] 11631 UNSPEC_MASKED_EQ))]
11148 "TARGET_AVX512BW" 11632 "TARGET_AVX512BW"
11149 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") 11633 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
11150 11634
11151 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>" 11635 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
11152 [(set (match_operand:<avx512fmaskmode> 0 "register_operand") 11636 [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
11153 (unspec:<avx512fmaskmode> 11637 (unspec:<avx512fmaskmode>
11154 [(match_operand:VI48_AVX512VL 1 "register_operand") 11638 [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
11155 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")] 11639 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
11156 UNSPEC_MASKED_EQ))] 11640 UNSPEC_MASKED_EQ))]
11157 "TARGET_AVX512F" 11641 "TARGET_AVX512F"
11158 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") 11642 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
11159 11643
11160 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1" 11644 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
11161 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk") 11645 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk,Yk")
11162 (unspec:<avx512fmaskmode> 11646 (unspec:<avx512fmaskmode>
11163 [(match_operand:VI12_AVX512VL 1 "register_operand" "%v") 11647 [(match_operand:VI12_AVX512VL 1 "nonimm_or_0_operand" "%v,v")
11164 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] 11648 (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "vm,C")]
11165 UNSPEC_MASKED_EQ))] 11649 UNSPEC_MASKED_EQ))]
11166 "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" 11650 "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11167 "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" 11651 "@
11652 vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
11653 vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
11168 [(set_attr "type" "ssecmp") 11654 [(set_attr "type" "ssecmp")
11169 (set_attr "prefix_extra" "1") 11655 (set_attr "prefix_extra" "1")
11170 (set_attr "prefix" "evex") 11656 (set_attr "prefix" "evex")
11171 (set_attr "mode" "<sseinsnmode>")]) 11657 (set_attr "mode" "<sseinsnmode>")])
11172 11658
11173 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1" 11659 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
11174 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk") 11660 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk,Yk")
11175 (unspec:<avx512fmaskmode> 11661 (unspec:<avx512fmaskmode>
11176 [(match_operand:VI48_AVX512VL 1 "register_operand" "%v") 11662 [(match_operand:VI48_AVX512VL 1 "nonimm_or_0_operand" "%v,v")
11177 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] 11663 (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "vm,C")]
11178 UNSPEC_MASKED_EQ))] 11664 UNSPEC_MASKED_EQ))]
11179 "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" 11665 "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11180 "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" 11666 "@
11667 vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
11668 vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
11181 [(set_attr "type" "ssecmp") 11669 [(set_attr "type" "ssecmp")
11182 (set_attr "prefix_extra" "1") 11670 (set_attr "prefix_extra" "1")
11183 (set_attr "prefix" "evex") 11671 (set_attr "prefix" "evex")
11184 (set_attr "mode" "<sseinsnmode>")]) 11672 (set_attr "mode" "<sseinsnmode>")])
11185 11673
11186 (define_insn "*sse4_1_eqv2di3" 11674 (define_insn "*sse4_1_eqv2di3"
11187 [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x") 11675 [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x")
11188 (eq:V2DI 11676 (eq:V2DI
11189 (match_operand:V2DI 1 "vector_operand" "%0,0,x") 11677 (match_operand:V2DI 1 "vector_operand" "%0,0,x")
11190 (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] 11678 (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))]
11191 "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)" 11679 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11192 "@ 11680 "@
11193 pcmpeqq\t{%2, %0|%0, %2} 11681 pcmpeqq\t{%2, %0|%0, %2}
11194 pcmpeqq\t{%2, %0|%0, %2} 11682 pcmpeqq\t{%2, %0|%0, %2}
11195 vpcmpeqq\t{%2, %1, %0|%0, %1, %2}" 11683 vpcmpeqq\t{%2, %1, %0|%0, %1, %2}"
11196 [(set_attr "isa" "noavx,noavx,avx") 11684 [(set_attr "isa" "noavx,noavx,avx")
11203 [(set (match_operand:VI124_128 0 "register_operand" "=x,x") 11691 [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
11204 (eq:VI124_128 11692 (eq:VI124_128
11205 (match_operand:VI124_128 1 "vector_operand" "%0,x") 11693 (match_operand:VI124_128 1 "vector_operand" "%0,x")
11206 (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] 11694 (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))]
11207 "TARGET_SSE2 && !TARGET_XOP 11695 "TARGET_SSE2 && !TARGET_XOP
11208 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" 11696 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11209 "@ 11697 "@
11210 pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2} 11698 pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
11211 vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" 11699 vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
11212 [(set_attr "isa" "noavx,avx") 11700 [(set_attr "isa" "noavx,avx")
11213 (set_attr "type" "ssecmp") 11701 (set_attr "type" "ssecmp")
11463 { 11951 {
11464 ix86_expand_vec_perm (operands); 11952 ix86_expand_vec_perm (operands);
11465 DONE; 11953 DONE;
11466 }) 11954 })
11467 11955
11468 (define_mode_iterator VEC_PERM_CONST
11469 [(V4SF "TARGET_SSE") (V4SI "TARGET_SSE")
11470 (V2DF "TARGET_SSE") (V2DI "TARGET_SSE")
11471 (V16QI "TARGET_SSE2") (V8HI "TARGET_SSE2")
11472 (V8SF "TARGET_AVX") (V4DF "TARGET_AVX")
11473 (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")
11474 (V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")
11475 (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")
11476 (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")
11477 (V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512BW")])
11478
11479 (define_expand "vec_perm_const<mode>"
11480 [(match_operand:VEC_PERM_CONST 0 "register_operand")
11481 (match_operand:VEC_PERM_CONST 1 "register_operand")
11482 (match_operand:VEC_PERM_CONST 2 "register_operand")
11483 (match_operand:<sseintvecmode> 3)]
11484 ""
11485 {
11486 if (ix86_expand_vec_perm_const (operands))
11487 DONE;
11488 else
11489 FAIL;
11490 })
11491
11492 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11956 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11493 ;; 11957 ;;
11494 ;; Parallel bitwise logical operations 11958 ;; Parallel bitwise logical operations
11495 ;; 11959 ;;
11496 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11960 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11499 [(set (match_operand:VI 0 "register_operand") 11963 [(set (match_operand:VI 0 "register_operand")
11500 (xor:VI (match_operand:VI 1 "vector_operand") 11964 (xor:VI (match_operand:VI 1 "vector_operand")
11501 (match_dup 2)))] 11965 (match_dup 2)))]
11502 "TARGET_SSE" 11966 "TARGET_SSE"
11503 { 11967 {
11504 int i, n = GET_MODE_NUNITS (<MODE>mode); 11968 operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));
11505 rtvec v = rtvec_alloc (n);
11506
11507 for (i = 0; i < n; ++i)
11508 RTVEC_ELT (v, i) = constm1_rtx;
11509
11510 operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
11511 }) 11969 })
11512 11970
11513 (define_expand "<sse2_avx2>_andnot<mode>3" 11971 (define_expand "<sse2_avx2>_andnot<mode>3"
11514 [(set (match_operand:VI_AVX2 0 "register_operand") 11972 [(set (match_operand:VI_AVX2 0 "register_operand")
11515 (and:VI_AVX2 11973 (and:VI_AVX2
11522 (vec_merge:VI48_AVX512VL 11980 (vec_merge:VI48_AVX512VL
11523 (and:VI48_AVX512VL 11981 (and:VI48_AVX512VL
11524 (not:VI48_AVX512VL 11982 (not:VI48_AVX512VL
11525 (match_operand:VI48_AVX512VL 1 "register_operand")) 11983 (match_operand:VI48_AVX512VL 1 "register_operand"))
11526 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) 11984 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
11527 (match_operand:VI48_AVX512VL 3 "vector_move_operand") 11985 (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
11528 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 11986 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
11529 "TARGET_AVX512F") 11987 "TARGET_AVX512F")
11530 11988
11531 (define_expand "<sse2_avx2>_andnot<mode>3_mask" 11989 (define_expand "<sse2_avx2>_andnot<mode>3_mask"
11532 [(set (match_operand:VI12_AVX512VL 0 "register_operand") 11990 [(set (match_operand:VI12_AVX512VL 0 "register_operand")
11533 (vec_merge:VI12_AVX512VL 11991 (vec_merge:VI12_AVX512VL
11534 (and:VI12_AVX512VL 11992 (and:VI12_AVX512VL
11535 (not:VI12_AVX512VL 11993 (not:VI12_AVX512VL
11536 (match_operand:VI12_AVX512VL 1 "register_operand")) 11994 (match_operand:VI12_AVX512VL 1 "register_operand"))
11537 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) 11995 (match_operand:VI12_AVX512VL 2 "nonimmediate_operand"))
11538 (match_operand:VI12_AVX512VL 3 "vector_move_operand") 11996 (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand")
11539 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 11997 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
11540 "TARGET_AVX512BW") 11998 "TARGET_AVX512BW")
11541 11999
11542 (define_insn "*andnot<mode>3" 12000 (define_insn "*andnot<mode>3"
11543 [(set (match_operand:VI 0 "register_operand" "=x,x,v") 12001 [(set (match_operand:VI 0 "register_operand" "=x,x,v")
11642 (match_test "optimize_function_for_size_p (cfun)")) 12100 (match_test "optimize_function_for_size_p (cfun)"))
11643 (const_string "V4SF") 12101 (const_string "V4SF")
11644 ] 12102 ]
11645 (const_string "<sseinsnmode>")))]) 12103 (const_string "<sseinsnmode>")))])
11646 12104
12105 (define_insn "*andnot<mode>3_bcst"
12106 [(set (match_operand:VI 0 "register_operand" "=v")
12107 (and:VI
12108 (not:VI48_AVX512VL
12109 (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
12110 (vec_duplicate:VI48_AVX512VL
12111 (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
12112 "TARGET_AVX512F"
12113 "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
12114 [(set_attr "type" "sselog")
12115 (set_attr "prefix" "evex")
12116 (set_attr "mode" "<sseinsnmode>")])
12117
11647 (define_insn "*andnot<mode>3_mask" 12118 (define_insn "*andnot<mode>3_mask"
11648 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") 12119 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
11649 (vec_merge:VI48_AVX512VL 12120 (vec_merge:VI48_AVX512VL
11650 (and:VI48_AVX512VL 12121 (and:VI48_AVX512VL
11651 (not:VI48_AVX512VL 12122 (not:VI48_AVX512VL
11652 (match_operand:VI48_AVX512VL 1 "register_operand" "v")) 12123 (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
11653 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) 12124 (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
11654 (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C") 12125 (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C")
11655 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] 12126 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
11656 "TARGET_AVX512F" 12127 "TARGET_AVX512F"
11657 "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"; 12128 "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
11658 [(set_attr "type" "sselog") 12129 [(set_attr "type" "sselog")
11659 (set_attr "prefix" "evex") 12130 (set_attr "prefix" "evex")
11674 [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v") 12145 [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v")
11675 (any_logic:VI48_AVX_AVX512F 12146 (any_logic:VI48_AVX_AVX512F
11676 (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v") 12147 (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v")
11677 (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))] 12148 (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
11678 "TARGET_SSE && <mask_mode512bit_condition> 12149 "TARGET_SSE && <mask_mode512bit_condition>
11679 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 12150 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11680 { 12151 {
11681 static char buf[64]; 12152 static char buf[64];
11682 const char *ops; 12153 const char *ops;
11683 const char *tmp; 12154 const char *tmp;
11684 const char *ssesuffix; 12155 const char *ssesuffix;
11771 ] 12242 ]
11772 (const_string "<sseinsnmode>")))]) 12243 (const_string "<sseinsnmode>")))])
11773 12244
11774 (define_insn "*<code><mode>3" 12245 (define_insn "*<code><mode>3"
11775 [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,x,v") 12246 [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,x,v")
11776 (any_logic: VI12_AVX_AVX512F 12247 (any_logic:VI12_AVX_AVX512F
11777 (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v") 12248 (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v")
11778 (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))] 12249 (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
11779 "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" 12250 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
11780 { 12251 {
11781 static char buf[64]; 12252 static char buf[64];
11782 const char *ops; 12253 const char *ops;
11783 const char *tmp; 12254 const char *tmp;
11784 const char *ssesuffix; 12255 const char *ssesuffix;
11846 (if_then_else 12317 (if_then_else
11847 (and (eq_attr "alternative" "0") 12318 (and (eq_attr "alternative" "0")
11848 (eq_attr "mode" "TI")) 12319 (eq_attr "mode" "TI"))
11849 (const_string "1") 12320 (const_string "1")
11850 (const_string "*"))) 12321 (const_string "*")))
11851 (set_attr "prefix" "<mask_prefix3>,evex") 12322 (set_attr "prefix" "orig,vex,evex")
11852 (set (attr "mode") 12323 (set (attr "mode")
11853 (cond [(and (match_test "<MODE_SIZE> == 16") 12324 (cond [(and (match_test "<MODE_SIZE> == 16")
11854 (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) 12325 (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
11855 (const_string "<ssePSmode>") 12326 (const_string "<ssePSmode>")
11856 (match_test "TARGET_AVX2") 12327 (match_test "TARGET_AVX2")
11863 (ior (not (match_test "TARGET_SSE2")) 12334 (ior (not (match_test "TARGET_SSE2"))
11864 (match_test "optimize_function_for_size_p (cfun)")) 12335 (match_test "optimize_function_for_size_p (cfun)"))
11865 (const_string "V4SF") 12336 (const_string "V4SF")
11866 ] 12337 ]
11867 (const_string "<sseinsnmode>")))]) 12338 (const_string "<sseinsnmode>")))])
12339
12340 (define_insn "*<code><mode>3_bcst"
12341 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
12342 (any_logic:VI48_AVX512VL
12343 (vec_duplicate:VI48_AVX512VL
12344 (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
12345 (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
12346 "TARGET_AVX512F && <mask_avx512vl_condition>"
12347 "vp<logic><ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
12348 [(set_attr "type" "sseiadd")
12349 (set_attr "prefix" "evex")
12350 (set_attr "mode" "<sseinsnmode>")])
11868 12351
11869 (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>" 12352 (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
11870 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk") 12353 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
11871 (unspec:<avx512fmaskmode> 12354 (unspec:<avx512fmaskmode>
11872 [(match_operand:VI12_AVX512VL 1 "register_operand" "v") 12355 [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
12551 (match_operand:SI 3 "const_0_to_3_operand") 13034 (match_operand:SI 3 "const_0_to_3_operand")
12552 (match_operand:AVX512_VEC 4 "register_operand") 13035 (match_operand:AVX512_VEC 4 "register_operand")
12553 (match_operand:<avx512fmaskmode> 5 "register_operand")] 13036 (match_operand:<avx512fmaskmode> 5 "register_operand")]
12554 "TARGET_AVX512F" 13037 "TARGET_AVX512F"
12555 { 13038 {
12556 int mask,selector; 13039 int mask, selector;
12557 mask = INTVAL (operands[3]); 13040 mask = INTVAL (operands[3]);
12558 selector = GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 13041 selector = (GET_MODE_UNIT_SIZE (<MODE>mode) == 4
12559 0xFFFF ^ (0xF000 >> mask * 4) 13042 ? 0xFFFF ^ (0x000F << mask * 4)
12560 : 0xFF ^ (0xC0 >> mask * 2); 13043 : 0xFF ^ (0x03 << mask * 2));
12561 emit_insn (gen_<extract_type>_vinsert<shuffletype><extract_suf>_1_mask 13044 emit_insn (gen_<extract_type>_vinsert<shuffletype><extract_suf>_1_mask
12562 (operands[0], operands[1], operands[2], GEN_INT (selector), 13045 (operands[0], operands[1], operands[2], GEN_INT (selector),
12563 operands[4], operands[5])); 13046 operands[4], operands[5]));
12564 DONE; 13047 DONE;
12565 }) 13048 })
13049
13050 (define_insn "*<extract_type>_vinsert<shuffletype><extract_suf>_0"
13051 [(set (match_operand:AVX512_VEC 0 "register_operand" "=v,x,Yv")
13052 (vec_merge:AVX512_VEC
13053 (match_operand:AVX512_VEC 1 "reg_or_0_operand" "v,C,C")
13054 (vec_duplicate:AVX512_VEC
13055 (match_operand:<ssequartermode> 2 "nonimmediate_operand" "vm,xm,vm"))
13056 (match_operand:SI 3 "const_int_operand" "n,n,n")))]
13057 "TARGET_AVX512F
13058 && (INTVAL (operands[3])
13059 == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0xFFF0 : 0xFC))"
13060 {
13061 if (which_alternative == 0)
13062 return "vinsert<shuffletype><extract_suf>\t{$0, %2, %1, %0|%0, %1, %2, 0}";
13063 switch (<MODE>mode)
13064 {
13065 case E_V8DFmode:
13066 return "vmovapd\t{%2, %x0|%x0, %2}";
13067 case E_V16SFmode:
13068 return "vmovaps\t{%2, %x0|%x0, %2}";
13069 case E_V8DImode:
13070 return which_alternative == 2 ? "vmovdqa64\t{%2, %x0|%x0, %2}"
13071 : "vmovdqa\t{%2, %x0|%x0, %2}";
13072 case E_V16SImode:
13073 return which_alternative == 2 ? "vmovdqa32\t{%2, %x0|%x0, %2}"
13074 : "vmovdqa\t{%2, %x0|%x0, %2}";
13075 default:
13076 gcc_unreachable ();
13077 }
13078 }
13079 [(set_attr "type" "sselog,ssemov,ssemov")
13080 (set_attr "length_immediate" "1,0,0")
13081 (set_attr "prefix" "evex,vex,evex")
13082 (set_attr "mode" "<sseinsnmode>,<ssequarterinsnmode>,<ssequarterinsnmode>")])
12566 13083
12567 (define_insn "<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>_1<mask_name>" 13084 (define_insn "<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>_1<mask_name>"
12568 [(set (match_operand:AVX512_VEC 0 "register_operand" "=v") 13085 [(set (match_operand:AVX512_VEC 0 "register_operand" "=v")
12569 (vec_merge:AVX512_VEC 13086 (vec_merge:AVX512_VEC
12570 (match_operand:AVX512_VEC 1 "register_operand" "v") 13087 (match_operand:AVX512_VEC 1 "register_operand" "v")
12574 "TARGET_AVX512F" 13091 "TARGET_AVX512F"
12575 { 13092 {
12576 int mask; 13093 int mask;
12577 int selector = INTVAL (operands[3]); 13094 int selector = INTVAL (operands[3]);
12578 13095
12579 if (selector == 0xFFF || selector == 0x3F) 13096 if (selector == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0xFFF0 : 0xFC))
12580 mask = 0; 13097 mask = 0;
12581 else if ( selector == 0xF0FF || selector == 0xCF) 13098 else if (selector == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0xFF0F : 0xF3))
12582 mask = 1; 13099 mask = 1;
12583 else if ( selector == 0xFF0F || selector == 0xF3) 13100 else if (selector == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0xF0FF : 0xCF))
12584 mask = 2; 13101 mask = 2;
12585 else if ( selector == 0xFFF0 || selector == 0xFC) 13102 else if (selector == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0x0FFF : 0x3F))
12586 mask = 3; 13103 mask = 3;
12587 else 13104 else
12588 gcc_unreachable (); 13105 gcc_unreachable ();
12589 13106
12590 operands[3] = GEN_INT (mask); 13107 operands[3] = GEN_INT (mask);
12591 13108
12592 return "vinsert<shuffletype><extract_suf>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"; 13109 return "vinsert<shuffletype><extract_suf>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
12593 } 13110 }
13457 (const_int 1)))] 13974 (const_int 1)))]
13458 "TARGET_SSE" 13975 "TARGET_SSE"
13459 "operands[2] = CONST0_RTX (V4SImode);") 13976 "operands[2] = CONST0_RTX (V4SImode);")
13460 13977
13461 (define_insn "sse2_loadld" 13978 (define_insn "sse2_loadld"
13462 [(set (match_operand:V4SI 0 "register_operand" "=v,Yi,x,x,v") 13979 [(set (match_operand:V4SI 0 "register_operand" "=v,v,x,x,v")
13463 (vec_merge:V4SI 13980 (vec_merge:V4SI
13464 (vec_duplicate:V4SI 13981 (vec_duplicate:V4SI
13465 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x,v")) 13982 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x,v"))
13466 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,v") 13983 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,v")
13467 (const_int 1)))] 13984 (const_int 1)))]
13473 movss\t{%2, %0|%0, %2} 13990 movss\t{%2, %0|%0, %2}
13474 vmovss\t{%2, %1, %0|%0, %1, %2}" 13991 vmovss\t{%2, %1, %0|%0, %1, %2}"
13475 [(set_attr "isa" "sse2,sse2,noavx,noavx,avx") 13992 [(set_attr "isa" "sse2,sse2,noavx,noavx,avx")
13476 (set_attr "type" "ssemov") 13993 (set_attr "type" "ssemov")
13477 (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,maybe_evex") 13994 (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,maybe_evex")
13478 (set_attr "mode" "TI,TI,V4SF,SF,SF")]) 13995 (set_attr "mode" "TI,TI,V4SF,SF,SF")
13996 (set (attr "preferred_for_speed")
13997 (cond [(eq_attr "alternative" "1")
13998 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
13999 ]
14000 (symbol_ref "true")))])
13479 14001
13480 ;; QI and HI modes handled by pextr patterns. 14002 ;; QI and HI modes handled by pextr patterns.
13481 (define_mode_iterator PEXTR_MODE12 14003 (define_mode_iterator PEXTR_MODE12
13482 [(V16QI "TARGET_SSE4_1") V8HI]) 14004 [(V16QI "TARGET_SSE4_1") V8HI])
13483 14005
13538 [(match_operand 2 "const_0_to_<ssescalarnummask>_operand")])))] 14060 [(match_operand 2 "const_0_to_<ssescalarnummask>_operand")])))]
13539 "TARGET_SSE" 14061 "TARGET_SSE"
13540 "#") 14062 "#")
13541 14063
13542 (define_insn "*vec_extract<ssevecmodelower>_0" 14064 (define_insn "*vec_extract<ssevecmodelower>_0"
13543 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r ,v ,m") 14065 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,r,v ,m")
13544 (vec_select:SWI48 14066 (vec_select:SWI48
13545 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "mYj,vm,v") 14067 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "m ,v,vm,v")
13546 (parallel [(const_int 0)])))] 14068 (parallel [(const_int 0)])))]
13547 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" 14069 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13548 "#") 14070 "#"
14071 [(set_attr "isa" "*,sse2,*,*")
14072 (set (attr "preferred_for_speed")
14073 (cond [(eq_attr "alternative" "1")
14074 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
14075 ]
14076 (symbol_ref "true")))])
13549 14077
13550 (define_insn "*vec_extractv2di_0_sse" 14078 (define_insn "*vec_extractv2di_0_sse"
13551 [(set (match_operand:DI 0 "nonimmediate_operand" "=v,m") 14079 [(set (match_operand:DI 0 "nonimmediate_operand" "=v,m")
13552 (vec_select:DI 14080 (vec_select:DI
13553 (match_operand:V2DI 1 "nonimmediate_operand" "vm,v") 14081 (match_operand:V2DI 1 "nonimmediate_operand" "vm,v")
13567 14095
13568 (define_insn "*vec_extractv4si_0_zext_sse4" 14096 (define_insn "*vec_extractv4si_0_zext_sse4"
13569 [(set (match_operand:DI 0 "register_operand" "=r,x,v") 14097 [(set (match_operand:DI 0 "register_operand" "=r,x,v")
13570 (zero_extend:DI 14098 (zero_extend:DI
13571 (vec_select:SI 14099 (vec_select:SI
13572 (match_operand:V4SI 1 "register_operand" "Yj,x,v") 14100 (match_operand:V4SI 1 "register_operand" "v,x,v")
13573 (parallel [(const_int 0)]))))] 14101 (parallel [(const_int 0)]))))]
13574 "TARGET_SSE4_1" 14102 "TARGET_SSE4_1"
13575 "#" 14103 "#"
13576 [(set_attr "isa" "x64,*,avx512f")]) 14104 [(set_attr "isa" "x64,*,avx512f")
14105 (set (attr "preferred_for_speed")
14106 (cond [(eq_attr "alternative" "0")
14107 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
14108 ]
14109 (symbol_ref "true")))])
13577 14110
13578 (define_insn "*vec_extractv4si_0_zext" 14111 (define_insn "*vec_extractv4si_0_zext"
13579 [(set (match_operand:DI 0 "register_operand" "=r") 14112 [(set (match_operand:DI 0 "register_operand" "=r")
13580 (zero_extend:DI 14113 (zero_extend:DI
13581 (vec_select:SI 14114 (vec_select:SI
13839 [(set (match_operand:V2SI 0 "register_operand" 14372 [(set (match_operand:V2SI 0 "register_operand"
13840 "=Yr,*x, x, v,Yr,*x, v, v, *y,*y") 14373 "=Yr,*x, x, v,Yr,*x, v, v, *y,*y")
13841 (vec_concat:V2SI 14374 (vec_concat:V2SI
13842 (match_operand:SI 1 "nonimmediate_operand" 14375 (match_operand:SI 1 "nonimmediate_operand"
13843 " 0, 0, x,Yv, 0, 0,Yv,rm, 0,rm") 14376 " 0, 0, x,Yv, 0, 0,Yv,rm, 0,rm")
13844 (match_operand:SI 2 "vector_move_operand" 14377 (match_operand:SI 2 "nonimm_or_0_operand"
13845 " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))] 14378 " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))]
13846 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" 14379 "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
13847 "@ 14380 "@
13848 pinsrd\t{$1, %2, %0|%0, %2, 1} 14381 pinsrd\t{$1, %2, %0|%0, %2, 1}
13849 pinsrd\t{$1, %2, %0|%0, %2, 1} 14382 pinsrd\t{$1, %2, %0|%0, %2, 1}
13915 (set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")]) 14448 (set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")])
13916 14449
13917 ;; movd instead of movq is required to handle broken assemblers. 14450 ;; movd instead of movq is required to handle broken assemblers.
13918 (define_insn "vec_concatv2di" 14451 (define_insn "vec_concatv2di"
13919 [(set (match_operand:V2DI 0 "register_operand" 14452 [(set (match_operand:V2DI 0 "register_operand"
13920 "=Yr,*x,x ,v ,Yi,v ,x ,x,v ,x,x,v") 14453 "=Yr,*x,x ,v ,v,v ,x ,x,v ,x,x,v")
13921 (vec_concat:V2DI 14454 (vec_concat:V2DI
13922 (match_operand:DI 1 "nonimmediate_operand" 14455 (match_operand:DI 1 "nonimmediate_operand"
13923 " 0, 0,x ,Yv,r ,vm,?!*Yn,0,Yv,0,0,v") 14456 " 0, 0,x ,Yv,r,vm,?!*y,0,Yv,0,0,v")
13924 (match_operand:DI 2 "vector_move_operand" 14457 (match_operand:DI 2 "nonimm_or_0_operand"
13925 "*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))] 14458 " rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]
13926 "TARGET_SSE" 14459 "TARGET_SSE"
13927 "@ 14460 "@
13928 pinsrq\t{$1, %2, %0|%0, %2, 1} 14461 pinsrq\t{$1, %2, %0|%0, %2, 1}
13929 pinsrq\t{$1, %2, %0|%0, %2, 1} 14462 pinsrq\t{$1, %2, %0|%0, %2, 1}
13930 vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1} 14463 vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1}
13943 (eq_attr "alternative" "2") 14476 (eq_attr "alternative" "2")
13944 (const_string "x64_avx") 14477 (const_string "x64_avx")
13945 (eq_attr "alternative" "3") 14478 (eq_attr "alternative" "3")
13946 (const_string "x64_avx512dq") 14479 (const_string "x64_avx512dq")
13947 (eq_attr "alternative" "4") 14480 (eq_attr "alternative" "4")
13948 (const_string "x64") 14481 (const_string "x64_sse2")
13949 (eq_attr "alternative" "5,6") 14482 (eq_attr "alternative" "5,6")
13950 (const_string "sse2") 14483 (const_string "sse2")
13951 (eq_attr "alternative" "7") 14484 (eq_attr "alternative" "7")
13952 (const_string "sse2_noavx") 14485 (const_string "sse2_noavx")
13953 (eq_attr "alternative" "8,11") 14486 (eq_attr "alternative" "8,11")
13980 (const_string "maybe_vex") 14513 (const_string "maybe_vex")
13981 (eq_attr "alternative" "8,11") 14514 (eq_attr "alternative" "8,11")
13982 (const_string "maybe_evex") 14515 (const_string "maybe_evex")
13983 ] 14516 ]
13984 (const_string "orig"))) 14517 (const_string "orig")))
13985 (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")]) 14518 (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")
14519 (set (attr "preferred_for_speed")
14520 (cond [(eq_attr "alternative" "4")
14521 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
14522 (eq_attr "alternative" "6")
14523 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
14524 ]
14525 (symbol_ref "true")))])
14526
14527 ;; vmovq clears also the higher bits.
14528 (define_insn "vec_set<mode>_0"
14529 [(set (match_operand:VI8_AVX_AVX512F 0 "register_operand" "=v,v")
14530 (vec_merge:VI8_AVX_AVX512F
14531 (vec_duplicate:VI8_AVX_AVX512F
14532 (match_operand:<ssescalarmode> 2 "general_operand" "r,vm"))
14533 (match_operand:VI8_AVX_AVX512F 1 "const0_operand" "C,C")
14534 (const_int 1)))]
14535 "TARGET_AVX"
14536 "vmovq\t{%2, %x0|%x0, %2}"
14537 [(set_attr "isa" "x64,*")
14538 (set_attr "type" "ssemov")
14539 (set_attr "prefix_rex" "1,*")
14540 (set_attr "prefix" "maybe_evex")
14541 (set_attr "mode" "TI")
14542 (set (attr "preferred_for_speed")
14543 (cond [(eq_attr "alternative" "0")
14544 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
14545 ]
14546 (symbol_ref "true")))])
13986 14547
13987 (define_expand "vec_unpacks_lo_<mode>" 14548 (define_expand "vec_unpacks_lo_<mode>"
13988 [(match_operand:<sseunpackmode> 0 "register_operand") 14549 [(match_operand:<sseunpackmode> 0 "register_operand")
13989 (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")] 14550 (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")]
13990 "TARGET_SSE2" 14551 "TARGET_SSE2"
14059 (match_operand:VI12_AVX2 2 "vector_operand"))) 14620 (match_operand:VI12_AVX2 2 "vector_operand")))
14060 (match_dup <mask_expand_op3>)) 14621 (match_dup <mask_expand_op3>))
14061 (const_int 1))))] 14622 (const_int 1))))]
14062 "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" 14623 "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
14063 { 14624 {
14064 rtx tmp; 14625 operands[<mask_expand_op3>] = CONST1_RTX(<MODE>mode);
14065 if (<mask_applied>)
14066 tmp = operands[3];
14067 operands[3] = CONST1_RTX(<MODE>mode);
14068 ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands); 14626 ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
14069
14070 if (<mask_applied>)
14071 {
14072 operands[5] = operands[3];
14073 operands[3] = tmp;
14074 }
14075 }) 14627 })
14076 14628
14077 (define_insn "*<sse2_avx2>_uavg<mode>3<mask_name>" 14629 (define_insn "*<sse2_avx2>_uavg<mode>3<mask_name>"
14078 [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") 14630 [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v")
14079 (truncate:VI12_AVX2 14631 (truncate:VI12_AVX2
14085 (zero_extend:<ssedoublemode> 14637 (zero_extend:<ssedoublemode>
14086 (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm"))) 14638 (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm")))
14087 (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand")) 14639 (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand"))
14088 (const_int 1))))] 14640 (const_int 1))))]
14089 "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> 14641 "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
14090 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)" 14642 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
14091 "@ 14643 "@
14092 pavg<ssemodesuffix>\t{%2, %0|%0, %2} 14644 pavg<ssemodesuffix>\t{%2, %0|%0, %2}
14093 vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" 14645 vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
14094 [(set_attr "isa" "noavx,avx") 14646 [(set_attr "isa" "noavx,avx")
14095 (set_attr "type" "sseiadd") 14647 (set_attr "type" "sseiadd")
14759 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,xm,vm"))) 15311 (match_operand:VI2_AVX2 2 "vector_operand" "xBm,xm,vm")))
14760 (const_int 14)) 15312 (const_int 14))
14761 (match_operand:VI2_AVX2 3 "const1_operand")) 15313 (match_operand:VI2_AVX2 3 "const1_operand"))
14762 (const_int 1))))] 15314 (const_int 1))))]
14763 "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition> 15315 "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
14764 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)" 15316 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
14765 "@ 15317 "@
14766 pmulhrsw\t{%2, %0|%0, %2} 15318 pmulhrsw\t{%2, %0|%0, %2}
14767 vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2} 15319 vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
14768 vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}" 15320 vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
14769 [(set_attr "isa" "noavx,avx,avx512bw") 15321 [(set_attr "isa" "noavx,avx,avx512bw")
14785 (sign_extend:V4SI 15337 (sign_extend:V4SI
14786 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) 15338 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
14787 (const_int 14)) 15339 (const_int 14))
14788 (match_operand:V4HI 3 "const1_operand")) 15340 (match_operand:V4HI 3 "const1_operand"))
14789 (const_int 1))))] 15341 (const_int 1))))]
14790 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)" 15342 "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
14791 "pmulhrsw\t{%2, %0|%0, %2}" 15343 "pmulhrsw\t{%2, %0|%0, %2}"
14792 [(set_attr "type" "sseimul") 15344 [(set_attr "type" "sseimul")
14793 (set_attr "prefix_extra" "1") 15345 (set_attr "prefix_extra" "1")
14794 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) 15346 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
14795 (set_attr "mode" "DI")]) 15347 (set_attr "mode" "DI")])
14861 (unspec:VI1_AVX512 15413 (unspec:VI1_AVX512
14862 [(match_operand:VI1_AVX512 1 "register_operand" "v") 15414 [(match_operand:VI1_AVX512 1 "register_operand" "v")
14863 (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm") 15415 (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
14864 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] 15416 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
14865 UNSPEC_PALIGNR) 15417 UNSPEC_PALIGNR)
14866 (match_operand:VI1_AVX512 4 "vector_move_operand" "0C") 15418 (match_operand:VI1_AVX512 4 "nonimm_or_0_operand" "0C")
14867 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] 15419 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
14868 "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)" 15420 "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
14869 { 15421 {
14870 operands[3] = GEN_INT (INTVAL (operands[3]) / 8); 15422 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
14871 return "vpalignr\t{%3, %2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2, %3}"; 15423 return "vpalignr\t{%3, %2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2, %3}";
14949 (define_insn "abs<mode>2_mask" 15501 (define_insn "abs<mode>2_mask"
14950 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") 15502 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
14951 (vec_merge:VI48_AVX512VL 15503 (vec_merge:VI48_AVX512VL
14952 (abs:VI48_AVX512VL 15504 (abs:VI48_AVX512VL
14953 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")) 15505 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm"))
14954 (match_operand:VI48_AVX512VL 2 "vector_move_operand" "0C") 15506 (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "0C")
14955 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] 15507 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
14956 "TARGET_AVX512F" 15508 "TARGET_AVX512F"
14957 "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 15509 "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
14958 [(set_attr "type" "sselog1") 15510 [(set_attr "type" "sselog1")
14959 (set_attr "prefix" "evex") 15511 (set_attr "prefix" "evex")
14962 (define_insn "abs<mode>2_mask" 15514 (define_insn "abs<mode>2_mask"
14963 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") 15515 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
14964 (vec_merge:VI12_AVX512VL 15516 (vec_merge:VI12_AVX512VL
14965 (abs:VI12_AVX512VL 15517 (abs:VI12_AVX512VL
14966 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm")) 15518 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm"))
14967 (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C") 15519 (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C")
14968 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] 15520 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
14969 "TARGET_AVX512BW" 15521 "TARGET_AVX512BW"
14970 "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 15522 "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
14971 [(set_attr "type" "sselog1") 15523 [(set_attr "type" "sselog1")
14972 (set_attr "prefix" "evex") 15524 (set_attr "prefix" "evex")
14973 (set_attr "mode" "<sseinsnmode>")]) 15525 (set_attr "mode" "<sseinsnmode>")])
14974 15526
14975 (define_expand "abs<mode>2" 15527 (define_expand "abs<mode>2"
14976 [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand") 15528 [(set (match_operand:VI_AVX2 0 "register_operand")
14977 (abs:VI1248_AVX512VL_AVX512BW 15529 (abs:VI_AVX2
14978 (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand")))] 15530 (match_operand:VI_AVX2 1 "vector_operand")))]
14979 "TARGET_SSE2" 15531 "TARGET_SSE2"
14980 { 15532 {
14981 if (!TARGET_SSSE3) 15533 if (!TARGET_SSSE3
15534 || ((<MODE>mode == V2DImode || <MODE>mode == V4DImode)
15535 && !TARGET_AVX512VL))
14982 { 15536 {
14983 ix86_expand_sse2_abs (operands[0], operands[1]); 15537 ix86_expand_sse2_abs (operands[0], operands[1]);
14984 DONE; 15538 DONE;
14985 } 15539 }
14986 }) 15540 })
16261 [(match_operand:VF_128 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")] 16815 [(match_operand:VF_128 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
16262 UNSPEC_RCP28) 16816 UNSPEC_RCP28)
16263 (match_operand:VF_128 2 "register_operand" "v") 16817 (match_operand:VF_128 2 "register_operand" "v")
16264 (const_int 1)))] 16818 (const_int 1)))]
16265 "TARGET_AVX512ER" 16819 "TARGET_AVX512ER"
16266 "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %1<round_saeonly_op3>}" 16820 "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %<iptr>1<round_saeonly_op3>}"
16267 [(set_attr "length_immediate" "1") 16821 [(set_attr "length_immediate" "1")
16268 (set_attr "prefix" "evex") 16822 (set_attr "prefix" "evex")
16269 (set_attr "type" "sse") 16823 (set_attr "type" "sse")
16270 (set_attr "mode" "<MODE>")]) 16824 (set_attr "mode" "<MODE>")])
16271 16825
16287 [(match_operand:VF_128 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")] 16841 [(match_operand:VF_128 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
16288 UNSPEC_RSQRT28) 16842 UNSPEC_RSQRT28)
16289 (match_operand:VF_128 2 "register_operand" "v") 16843 (match_operand:VF_128 2 "register_operand" "v")
16290 (const_int 1)))] 16844 (const_int 1)))]
16291 "TARGET_AVX512ER" 16845 "TARGET_AVX512ER"
16292 "vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %1<round_saeonly_op3>}" 16846 "vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2, %<iptr>1<round_saeonly_op3>}"
16293 [(set_attr "length_immediate" "1") 16847 [(set_attr "length_immediate" "1")
16294 (set_attr "type" "sse") 16848 (set_attr "type" "sse")
16295 (set_attr "prefix" "evex") 16849 (set_attr "prefix" "evex")
16296 (set_attr "mode" "<MODE>")]) 16850 (set_attr "mode" "<MODE>")])
16297 16851
16409 [(set_attr "type" "ssemuladd") 16963 [(set_attr "type" "ssemuladd")
16410 (set_attr "mode" "TI")]) 16964 (set_attr "mode" "TI")])
16411 16965
16412 ;; XOP parallel XMM conditional moves 16966 ;; XOP parallel XMM conditional moves
16413 (define_insn "xop_pcmov_<mode><avxsizesuffix>" 16967 (define_insn "xop_pcmov_<mode><avxsizesuffix>"
16414 [(set (match_operand:V 0 "register_operand" "=x,x") 16968 [(set (match_operand:V_128_256 0 "register_operand" "=x,x")
16415 (if_then_else:V 16969 (if_then_else:V_128_256
16416 (match_operand:V 3 "nonimmediate_operand" "x,m") 16970 (match_operand:V_128_256 3 "nonimmediate_operand" "x,m")
16417 (match_operand:V 1 "register_operand" "x,x") 16971 (match_operand:V_128_256 1 "register_operand" "x,x")
16418 (match_operand:V 2 "nonimmediate_operand" "xm,x")))] 16972 (match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))]
16419 "TARGET_XOP" 16973 "TARGET_XOP"
16420 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" 16974 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
16421 [(set_attr "type" "sse4arg")]) 16975 [(set_attr "type" "sse4arg")])
16422 16976
16423 ;; XOP horizontal add/subtract instructions 16977 ;; XOP horizontal add/subtract instructions
17313 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx), 17867 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
17314 UNSPECV_VZEROALL); 17868 UNSPECV_VZEROALL);
17315 17869
17316 for (regno = 0; regno < nregs; regno++) 17870 for (regno = 0; regno < nregs; regno++)
17317 XVECEXP (operands[0], 0, regno + 1) 17871 XVECEXP (operands[0], 0, regno + 1)
17318 = gen_rtx_SET (gen_rtx_REG (V8SImode, SSE_REGNO (regno)), 17872 = gen_rtx_SET (gen_rtx_REG (V8SImode, GET_SSE_REGNO (regno)),
17319 CONST0_RTX (V8SImode)); 17873 CONST0_RTX (V8SImode));
17320 }) 17874 })
17321 17875
17322 (define_insn "*avx_vzeroall" 17876 (define_insn "*avx_vzeroall"
17323 [(match_parallel 0 "vzeroall_operation" 17877 [(match_parallel 0 "vzeroall_operation"
17435 17989
17436 (define_expand "avx512vl_perm<mode>_mask" 17990 (define_expand "avx512vl_perm<mode>_mask"
17437 [(match_operand:VI8F_256 0 "register_operand") 17991 [(match_operand:VI8F_256 0 "register_operand")
17438 (match_operand:VI8F_256 1 "nonimmediate_operand") 17992 (match_operand:VI8F_256 1 "nonimmediate_operand")
17439 (match_operand:SI 2 "const_0_to_255_operand") 17993 (match_operand:SI 2 "const_0_to_255_operand")
17440 (match_operand:VI8F_256 3 "vector_move_operand") 17994 (match_operand:VI8F_256 3 "nonimm_or_0_operand")
17441 (match_operand:<avx512fmaskmode> 4 "register_operand")] 17995 (match_operand:<avx512fmaskmode> 4 "register_operand")]
17442 "TARGET_AVX512VL" 17996 "TARGET_AVX512VL"
17443 { 17997 {
17444 int mask = INTVAL (operands[2]); 17998 int mask = INTVAL (operands[2]);
17445 emit_insn (gen_<avx2_avx512>_perm<mode>_1_mask (operands[0], operands[1], 17999 emit_insn (gen_<avx2_avx512>_perm<mode>_1_mask (operands[0], operands[1],
17494 18048
17495 (define_expand "avx512f_perm<mode>_mask" 18049 (define_expand "avx512f_perm<mode>_mask"
17496 [(match_operand:V8FI 0 "register_operand") 18050 [(match_operand:V8FI 0 "register_operand")
17497 (match_operand:V8FI 1 "nonimmediate_operand") 18051 (match_operand:V8FI 1 "nonimmediate_operand")
17498 (match_operand:SI 2 "const_0_to_255_operand") 18052 (match_operand:SI 2 "const_0_to_255_operand")
17499 (match_operand:V8FI 3 "vector_move_operand") 18053 (match_operand:V8FI 3 "nonimm_or_0_operand")
17500 (match_operand:<avx512fmaskmode> 4 "register_operand")] 18054 (match_operand:<avx512fmaskmode> 4 "register_operand")]
17501 "TARGET_AVX512F" 18055 "TARGET_AVX512F"
17502 { 18056 {
17503 int mask = INTVAL (operands[2]); 18057 int mask = INTVAL (operands[2]);
17504 emit_insn (gen_avx512f_perm<mode>_1_mask (operands[0], operands[1], 18058 emit_insn (gen_avx512f_perm<mode>_1_mask (operands[0], operands[1],
17594 /* There is no DF broadcast (in AVX-512*) to 128b register. 18148 /* There is no DF broadcast (in AVX-512*) to 128b register.
17595 Mimic it with integer variant. */ 18149 Mimic it with integer variant. */
17596 if (<MODE>mode == V2DFmode) 18150 if (<MODE>mode == V2DFmode)
17597 return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"; 18151 return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
17598 18152
17599 if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4) 18153 return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptr>1}";
17600 return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}";
17601 else
17602 return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}";
17603 } 18154 }
17604 [(set_attr "type" "ssemov") 18155 [(set_attr "type" "ssemov")
17605 (set_attr "prefix" "evex") 18156 (set_attr "prefix" "evex")
17606 (set_attr "mode" "<sseinsnmode>")]) 18157 (set_attr "mode" "<sseinsnmode>")])
17607 18158
17610 (vec_duplicate:VI12_AVX512VL 18161 (vec_duplicate:VI12_AVX512VL
17611 (vec_select:<ssescalarmode> 18162 (vec_select:<ssescalarmode>
17612 (match_operand:<ssexmmmode> 1 "nonimmediate_operand" "vm") 18163 (match_operand:<ssexmmmode> 1 "nonimmediate_operand" "vm")
17613 (parallel [(const_int 0)]))))] 18164 (parallel [(const_int 0)]))))]
17614 "TARGET_AVX512BW" 18165 "TARGET_AVX512BW"
17615 "vpbroadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 18166 "vpbroadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptr>1}"
17616 [(set_attr "type" "ssemov") 18167 [(set_attr "type" "ssemov")
17617 (set_attr "prefix" "evex") 18168 (set_attr "prefix" "evex")
17618 (set_attr "mode" "<sseinsnmode>")]) 18169 (set_attr "mode" "<sseinsnmode>")])
17619 18170
17620 (define_insn "<mask_codefor>avx512f_broadcast<mode><mask_name>" 18171 (define_insn "<mask_codefor>avx512f_broadcast<mode><mask_name>"
17701 (set_attr "mode" "TI,V4SF,V4SF")]) 18252 (set_attr "mode" "TI,V4SF,V4SF")])
17702 18253
17703 (define_insn "*vec_dupv2di" 18254 (define_insn "*vec_dupv2di"
17704 [(set (match_operand:V2DI 0 "register_operand" "=x,v,v,x") 18255 [(set (match_operand:V2DI 0 "register_operand" "=x,v,v,x")
17705 (vec_duplicate:V2DI 18256 (vec_duplicate:V2DI
17706 (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,m,0")))] 18257 (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,0")))]
17707 "TARGET_SSE" 18258 "TARGET_SSE"
17708 "@ 18259 "@
17709 punpcklqdq\t%0, %0 18260 punpcklqdq\t%0, %0
17710 vpunpcklqdq\t{%d1, %0|%0, %d1} 18261 vpunpcklqdq\t{%d1, %0|%0, %d1}
17711 %vmovddup\t{%1, %0|%0, %1} 18262 %vmovddup\t{%1, %0|%0, %1}
17732 (set_attr "mode" "OI")]) 18283 (set_attr "mode" "OI")])
17733 18284
17734 ;; Modes handled by AVX vec_dup patterns. 18285 ;; Modes handled by AVX vec_dup patterns.
17735 (define_mode_iterator AVX_VEC_DUP_MODE 18286 (define_mode_iterator AVX_VEC_DUP_MODE
17736 [V8SI V8SF V4DI V4DF]) 18287 [V8SI V8SF V4DI V4DF])
18288 (define_mode_attr vecdupssescalarmodesuffix
18289 [(V8SF "ss") (V4DF "sd") (V8SI "ss") (V4DI "sd")])
17737 ;; Modes handled by AVX2 vec_dup patterns. 18290 ;; Modes handled by AVX2 vec_dup patterns.
17738 (define_mode_iterator AVX2_VEC_DUP_MODE 18291 (define_mode_iterator AVX2_VEC_DUP_MODE
17739 [V32QI V16QI V16HI V8HI V8SI V4SI]) 18292 [V32QI V16QI V16HI V8HI V8SI V4SI])
17740 18293
17741 (define_insn "*vec_dup<mode>" 18294 (define_insn "*vec_dup<mode>"
17742 [(set (match_operand:AVX2_VEC_DUP_MODE 0 "register_operand" "=x,x,Yi") 18295 [(set (match_operand:AVX2_VEC_DUP_MODE 0 "register_operand" "=x,x,v")
17743 (vec_duplicate:AVX2_VEC_DUP_MODE 18296 (vec_duplicate:AVX2_VEC_DUP_MODE
17744 (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,x,$r")))] 18297 (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,x,$r")))]
17745 "TARGET_AVX2" 18298 "TARGET_AVX2"
17746 "@ 18299 "@
17747 v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1} 18300 v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1}
17749 #" 18302 #"
17750 [(set_attr "isa" "*,*,noavx512vl") 18303 [(set_attr "isa" "*,*,noavx512vl")
17751 (set_attr "type" "ssemov") 18304 (set_attr "type" "ssemov")
17752 (set_attr "prefix_extra" "1") 18305 (set_attr "prefix_extra" "1")
17753 (set_attr "prefix" "maybe_evex") 18306 (set_attr "prefix" "maybe_evex")
17754 (set_attr "mode" "<sseinsnmode>")]) 18307 (set_attr "mode" "<sseinsnmode>")
18308 (set (attr "preferred_for_speed")
18309 (cond [(eq_attr "alternative" "2")
18310 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
18311 ]
18312 (symbol_ref "true")))])
17755 18313
17756 (define_insn "vec_dup<mode>" 18314 (define_insn "vec_dup<mode>"
17757 [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,x,v,x") 18315 [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,x,v,x")
17758 (vec_duplicate:AVX_VEC_DUP_MODE 18316 (vec_duplicate:AVX_VEC_DUP_MODE
17759 (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,m,x,v,?x")))] 18317 (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,m,x,v,?x")))]
17760 "TARGET_AVX" 18318 "TARGET_AVX"
17761 "@ 18319 "@
17762 v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1} 18320 v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1}
17763 vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1} 18321 vbroadcast<vecdupssescalarmodesuffix>\t{%1, %0|%0, %1}
17764 v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1} 18322 v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1}
17765 v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %g0|%g0, %x1} 18323 v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %g0|%g0, %x1}
17766 #" 18324 #"
17767 [(set_attr "type" "ssemov") 18325 [(set_attr "type" "ssemov")
17768 (set_attr "prefix_extra" "1") 18326 (set_attr "prefix_extra" "1")
17884 [(set (match_operand:VI8F_BRCST64x2 0 "register_operand" "=v,v") 18442 [(set (match_operand:VI8F_BRCST64x2 0 "register_operand" "=v,v")
17885 (vec_duplicate:VI8F_BRCST64x2 18443 (vec_duplicate:VI8F_BRCST64x2
17886 (match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))] 18444 (match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))]
17887 "TARGET_AVX512DQ" 18445 "TARGET_AVX512DQ"
17888 "@ 18446 "@
17889 vshuf<shuffletype>64x2\t{$0x0, %<concat_tg_mode>1, %<concat_tg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<concat_tg_mode>1, %<concat_tg_mode>1, 0x0} 18447 vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
17890 vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" 18448 vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
17891 [(set_attr "type" "ssemov") 18449 [(set_attr "type" "ssemov")
17892 (set_attr "prefix_extra" "1") 18450 (set_attr "prefix_extra" "1")
17893 (set_attr "prefix" "evex") 18451 (set_attr "prefix" "evex")
17894 (set_attr "mode" "<sseinsnmode>")]) 18452 (set_attr "mode" "<sseinsnmode>")])
18112 (match_operand:VPERMI2 3 "nonimmediate_operand")] 18670 (match_operand:VPERMI2 3 "nonimmediate_operand")]
18113 UNSPEC_VPERMT2) 18671 UNSPEC_VPERMT2)
18114 (match_dup 5) 18672 (match_dup 5)
18115 (match_operand:<avx512fmaskmode> 4 "register_operand")))] 18673 (match_operand:<avx512fmaskmode> 4 "register_operand")))]
18116 "TARGET_AVX512F" 18674 "TARGET_AVX512F"
18117 "operands[5] = gen_lowpart (<MODE>mode, operands[2]);") 18675 {
18676 operands[2] = force_reg (<sseintvecmode>mode, operands[2]);
18677 operands[5] = gen_lowpart (<MODE>mode, operands[2]);
18678 })
18118 18679
18119 (define_insn "*<avx512>_vpermi2var<mode>3_mask" 18680 (define_insn "*<avx512>_vpermi2var<mode>3_mask"
18120 [(set (match_operand:VPERMI2I 0 "register_operand" "=v") 18681 [(set (match_operand:VPERMI2I 0 "register_operand" "=v")
18121 (vec_merge:VPERMI2I 18682 (vec_merge:VPERMI2I
18122 (unspec:VPERMI2I 18683 (unspec:VPERMI2I
18724 19285
18725 (define_insn "avx_vec_concat<mode>" 19286 (define_insn "avx_vec_concat<mode>"
18726 [(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv") 19287 [(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv")
18727 (vec_concat:V_256_512 19288 (vec_concat:V_256_512
18728 (match_operand:<ssehalfvecmode> 1 "register_operand" "x,v,x,v") 19289 (match_operand:<ssehalfvecmode> 1 "register_operand" "x,v,x,v")
18729 (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,vm,C,C")))] 19290 (match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand" "xm,vm,C,C")))]
18730 "TARGET_AVX" 19291 "TARGET_AVX"
18731 { 19292 {
18732 switch (which_alternative) 19293 switch (which_alternative)
18733 { 19294 {
18734 case 0: 19295 case 0:
18735 return "vinsert<i128>\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}"; 19296 return "vinsert<i128>\t{$0x1, %2, %<xtg_mode>1, %0|%0, %<xtg_mode>1, %2, 0x1}";
18736 case 1: 19297 case 1:
18737 if (<MODE_SIZE> == 64) 19298 if (<MODE_SIZE> == 64)
18738 { 19299 {
18739 if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 4) 19300 if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 4)
18740 return "vinsert<shuffletype>32x8\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}"; 19301 return "vinsert<shuffletype>32x8\t{$0x1, %2, %<xtg_mode>1, %0|%0, %<xtg_mode>1, %2, 0x1}";
18741 else 19302 else
18742 return "vinsert<shuffletype>64x4\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}"; 19303 return "vinsert<shuffletype>64x4\t{$0x1, %2, %<xtg_mode>1, %0|%0, %<xtg_mode>1, %2, 0x1}";
18743 } 19304 }
18744 else 19305 else
18745 { 19306 {
18746 if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 8) 19307 if (TARGET_AVX512DQ && GET_MODE_SIZE (<ssescalarmode>mode) == 8)
18747 return "vinsert<shuffletype>64x2\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}"; 19308 return "vinsert<shuffletype>64x2\t{$0x1, %2, %<xtg_mode>1, %0|%0, %<xtg_mode>1, %2, 0x1}";
18748 else 19309 else
18749 return "vinsert<shuffletype>32x4\t{$0x1, %2, %<concat_tg_mode>1, %0|%0, %<concat_tg_mode>1, %2, 0x1}"; 19310 return "vinsert<shuffletype>32x4\t{$0x1, %2, %<xtg_mode>1, %0|%0, %<xtg_mode>1, %2, 0x1}";
18750 } 19311 }
18751 case 2: 19312 case 2:
18752 case 3: 19313 case 3:
18753 switch (get_attr_mode (insn)) 19314 switch (get_attr_mode (insn))
18754 { 19315 {
18838 (vec_concat:V8HI 19399 (vec_concat:V8HI
18839 (unspec:V4HI [(match_operand:V4SF 1 "register_operand") 19400 (unspec:V4HI [(match_operand:V4SF 1 "register_operand")
18840 (match_operand:SI 2 "const_0_to_255_operand")] 19401 (match_operand:SI 2 "const_0_to_255_operand")]
18841 UNSPEC_VCVTPS2PH) 19402 UNSPEC_VCVTPS2PH)
18842 (match_dup 5)) 19403 (match_dup 5))
18843 (match_operand:V8HI 3 "vector_move_operand") 19404 (match_operand:V8HI 3 "nonimm_or_0_operand")
18844 (match_operand:QI 4 "register_operand")))] 19405 (match_operand:QI 4 "register_operand")))]
18845 "TARGET_AVX512VL" 19406 "TARGET_AVX512VL"
18846 "operands[5] = CONST0_RTX (V4HImode);") 19407 "operands[5] = CONST0_RTX (V4HImode);")
18847 19408
18848 (define_expand "vcvtps2ph" 19409 (define_expand "vcvtps2ph"
19306 19867
19307 (define_insn "<avx512>_compress<mode>_mask" 19868 (define_insn "<avx512>_compress<mode>_mask"
19308 [(set (match_operand:VI48F 0 "register_operand" "=v") 19869 [(set (match_operand:VI48F 0 "register_operand" "=v")
19309 (unspec:VI48F 19870 (unspec:VI48F
19310 [(match_operand:VI48F 1 "register_operand" "v") 19871 [(match_operand:VI48F 1 "register_operand" "v")
19311 (match_operand:VI48F 2 "vector_move_operand" "0C") 19872 (match_operand:VI48F 2 "nonimm_or_0_operand" "0C")
19312 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")] 19873 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
19313 UNSPEC_COMPRESS))] 19874 UNSPEC_COMPRESS))]
19314 "TARGET_AVX512F" 19875 "TARGET_AVX512F"
19315 "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 19876 "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
19877 [(set_attr "type" "ssemov")
19878 (set_attr "prefix" "evex")
19879 (set_attr "mode" "<sseinsnmode>")])
19880
19881 (define_insn "compress<mode>_mask"
19882 [(set (match_operand:VI12_AVX512VLBW 0 "register_operand" "=v")
19883 (unspec:VI12_AVX512VLBW
19884 [(match_operand:VI12_AVX512VLBW 1 "register_operand" "v")
19885 (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand" "0C")
19886 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
19887 UNSPEC_COMPRESS))]
19888 "TARGET_AVX512VBMI2"
19889 "vpcompress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
19316 [(set_attr "type" "ssemov") 19890 [(set_attr "type" "ssemov")
19317 (set_attr "prefix" "evex") 19891 (set_attr "prefix" "evex")
19318 (set_attr "mode" "<sseinsnmode>")]) 19892 (set_attr "mode" "<sseinsnmode>")])
19319 19893
19320 (define_insn "<avx512>_compressstore<mode>_mask" 19894 (define_insn "<avx512>_compressstore<mode>_mask"
19329 [(set_attr "type" "ssemov") 19903 [(set_attr "type" "ssemov")
19330 (set_attr "prefix" "evex") 19904 (set_attr "prefix" "evex")
19331 (set_attr "memory" "store") 19905 (set_attr "memory" "store")
19332 (set_attr "mode" "<sseinsnmode>")]) 19906 (set_attr "mode" "<sseinsnmode>")])
19333 19907
19908 (define_insn "compressstore<mode>_mask"
19909 [(set (match_operand:VI12_AVX512VLBW 0 "memory_operand" "=m")
19910 (unspec:VI12_AVX512VLBW
19911 [(match_operand:VI12_AVX512VLBW 1 "register_operand" "x")
19912 (match_dup 0)
19913 (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
19914 UNSPEC_COMPRESS_STORE))]
19915 "TARGET_AVX512VBMI2"
19916 "vpcompress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
19917 [(set_attr "type" "ssemov")
19918 (set_attr "prefix" "evex")
19919 (set_attr "memory" "store")
19920 (set_attr "mode" "<sseinsnmode>")])
19921
19334 (define_expand "<avx512>_expand<mode>_maskz" 19922 (define_expand "<avx512>_expand<mode>_maskz"
19335 [(set (match_operand:VI48F 0 "register_operand") 19923 [(set (match_operand:VI48F 0 "register_operand")
19336 (unspec:VI48F 19924 (unspec:VI48F
19337 [(match_operand:VI48F 1 "nonimmediate_operand") 19925 [(match_operand:VI48F 1 "nonimmediate_operand")
19338 (match_operand:VI48F 2 "vector_move_operand") 19926 (match_operand:VI48F 2 "nonimm_or_0_operand")
19339 (match_operand:<avx512fmaskmode> 3 "register_operand")] 19927 (match_operand:<avx512fmaskmode> 3 "register_operand")]
19340 UNSPEC_EXPAND))] 19928 UNSPEC_EXPAND))]
19341 "TARGET_AVX512F" 19929 "TARGET_AVX512F"
19342 "operands[2] = CONST0_RTX (<MODE>mode);") 19930 "operands[2] = CONST0_RTX (<MODE>mode);")
19343 19931
19344 (define_insn "<avx512>_expand<mode>_mask" 19932 (define_insn "<avx512>_expand<mode>_mask"
19345 [(set (match_operand:VI48F 0 "register_operand" "=v,v") 19933 [(set (match_operand:VI48F 0 "register_operand" "=v,v")
19346 (unspec:VI48F 19934 (unspec:VI48F
19347 [(match_operand:VI48F 1 "nonimmediate_operand" "v,m") 19935 [(match_operand:VI48F 1 "nonimmediate_operand" "v,m")
19348 (match_operand:VI48F 2 "vector_move_operand" "0C,0C") 19936 (match_operand:VI48F 2 "nonimm_or_0_operand" "0C,0C")
19349 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")] 19937 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")]
19350 UNSPEC_EXPAND))] 19938 UNSPEC_EXPAND))]
19351 "TARGET_AVX512F" 19939 "TARGET_AVX512F"
19352 "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" 19940 "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
19353 [(set_attr "type" "ssemov") 19941 [(set_attr "type" "ssemov")
19354 (set_attr "prefix" "evex") 19942 (set_attr "prefix" "evex")
19355 (set_attr "memory" "none,load") 19943 (set_attr "memory" "none,load")
19356 (set_attr "mode" "<sseinsnmode>")]) 19944 (set_attr "mode" "<sseinsnmode>")])
19945
19946 (define_insn "expand<mode>_mask"
19947 [(set (match_operand:VI12_AVX512VLBW 0 "register_operand" "=v,v")
19948 (unspec:VI12_AVX512VLBW
19949 [(match_operand:VI12_AVX512VLBW 1 "nonimmediate_operand" "v,m")
19950 (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand" "0C,0C")
19951 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")]
19952 UNSPEC_EXPAND))]
19953 "TARGET_AVX512VBMI2"
19954 "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
19955 [(set_attr "type" "ssemov")
19956 (set_attr "prefix" "evex")
19957 (set_attr "memory" "none,load")
19958 (set_attr "mode" "<sseinsnmode>")])
19959
19960 (define_expand "expand<mode>_maskz"
19961 [(set (match_operand:VI12_AVX512VLBW 0 "register_operand")
19962 (unspec:VI12_AVX512VLBW
19963 [(match_operand:VI12_AVX512VLBW 1 "nonimmediate_operand")
19964 (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand")
19965 (match_operand:<avx512fmaskmode> 3 "register_operand")]
19966 UNSPEC_EXPAND))]
19967 "TARGET_AVX512VBMI2"
19968 "operands[2] = CONST0_RTX (<MODE>mode);")
19357 19969
19358 (define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>" 19970 (define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"
19359 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") 19971 [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
19360 (unspec:VF_AVX512VL 19972 (unspec:VF_AVX512VL
19361 [(match_operand:VF_AVX512VL 1 "register_operand" "v") 19973 [(match_operand:VF_AVX512VL 1 "register_operand" "v")
19366 "vrange<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}" 19978 "vrange<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}"
19367 [(set_attr "type" "sse") 19979 [(set_attr "type" "sse")
19368 (set_attr "prefix" "evex") 19980 (set_attr "prefix" "evex")
19369 (set_attr "mode" "<MODE>")]) 19981 (set_attr "mode" "<MODE>")])
19370 19982
19371 (define_insn "avx512dq_ranges<mode><round_saeonly_name>" 19983 (define_insn "avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>"
19372 [(set (match_operand:VF_128 0 "register_operand" "=v") 19984 [(set (match_operand:VF_128 0 "register_operand" "=v")
19373 (vec_merge:VF_128 19985 (vec_merge:VF_128
19374 (unspec:VF_128 19986 (unspec:VF_128
19375 [(match_operand:VF_128 1 "register_operand" "v") 19987 [(match_operand:VF_128 1 "register_operand" "v")
19376 (match_operand:VF_128 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") 19988 (match_operand:VF_128 2 "<round_saeonly_scalar_nimm_predicate>" "<round_saeonly_scalar_constraint>")
19377 (match_operand:SI 3 "const_0_to_15_operand")] 19989 (match_operand:SI 3 "const_0_to_15_operand")]
19378 UNSPEC_RANGE) 19990 UNSPEC_RANGE)
19379 (match_dup 1) 19991 (match_dup 1)
19380 (const_int 1)))] 19992 (const_int 1)))]
19381 "TARGET_AVX512DQ" 19993 "TARGET_AVX512DQ"
19382 "vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}" 19994 "vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
19383 [(set_attr "type" "sse") 19995 [(set_attr "type" "sse")
19384 (set_attr "prefix" "evex") 19996 (set_attr "prefix" "evex")
19385 (set_attr "mode" "<MODE>")]) 19997 (set_attr "mode" "<MODE>")])
19386 19998
19387 (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>" 19999 (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"
19432 (match_operand:SI 3 "const_0_to_15_operand")] 20044 (match_operand:SI 3 "const_0_to_15_operand")]
19433 UNSPEC_GETMANT) 20045 UNSPEC_GETMANT)
19434 (match_dup 1) 20046 (match_dup 1)
19435 (const_int 1)))] 20047 (const_int 1)))]
19436 "TARGET_AVX512F" 20048 "TARGET_AVX512F"
19437 "vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2<round_saeonly_scalar_mask_op4>, %3}"; 20049 "vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}";
19438 [(set_attr "prefix" "evex") 20050 [(set_attr "prefix" "evex")
19439 (set_attr "mode" "<ssescalarmode>")]) 20051 (set_attr "mode" "<ssescalarmode>")])
19440 20052
19441 ;; The correct representation for this is absolutely enormous, and 20053 ;; The correct representation for this is absolutely enormous, and
19442 ;; surely not generally useful. 20054 ;; surely not generally useful.
19672 (define_mode_attr imod4_narrow 20284 (define_mode_attr imod4_narrow
19673 [(V64SF "V16SF") (V64SI "V16SI")]) 20285 [(V64SF "V16SF") (V64SI "V16SI")])
19674 20286
19675 (define_expand "mov<mode>" 20287 (define_expand "mov<mode>"
19676 [(set (match_operand:IMOD4 0 "nonimmediate_operand") 20288 [(set (match_operand:IMOD4 0 "nonimmediate_operand")
19677 (match_operand:IMOD4 1 "vector_move_operand"))] 20289 (match_operand:IMOD4 1 "nonimm_or_0_operand"))]
19678 "TARGET_AVX512F" 20290 "TARGET_AVX512F"
19679 { 20291 {
19680 ix86_expand_vector_move (<MODE>mode, operands); 20292 ix86_expand_vector_move (<MODE>mode, operands);
19681 DONE; 20293 DONE;
19682 }) 20294 })
19683 20295
19684 (define_insn_and_split "*mov<mode>_internal" 20296 (define_insn_and_split "*mov<mode>_internal"
19685 [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m") 20297 [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m")
19686 (match_operand:IMOD4 1 "vector_move_operand" " C,vm,v"))] 20298 (match_operand:IMOD4 1 "nonimm_or_0_operand" " C,vm,v"))]
19687 "TARGET_AVX512F 20299 "TARGET_AVX512F
19688 && (register_operand (operands[0], <MODE>mode) 20300 && (register_operand (operands[0], <MODE>mode)
19689 || register_operand (operands[1], <MODE>mode))" 20301 || register_operand (operands[1], <MODE>mode))"
19690 "#" 20302 "#"
19691 "&& reload_completed" 20303 "&& reload_completed"
19707 20319
19708 (define_insn "avx5124fmaddps_4fmaddps" 20320 (define_insn "avx5124fmaddps_4fmaddps"
19709 [(set (match_operand:V16SF 0 "register_operand" "=v") 20321 [(set (match_operand:V16SF 0 "register_operand" "=v")
19710 (unspec:V16SF 20322 (unspec:V16SF
19711 [(match_operand:V16SF 1 "register_operand" "0") 20323 [(match_operand:V16SF 1 "register_operand" "0")
19712 (match_operand:V64SF 2 "register_operand" "Yh") 20324 (match_operand:V64SF 2 "register_operand" "v")
19713 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))] 20325 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))]
19714 "TARGET_AVX5124FMAPS" 20326 "TARGET_AVX5124FMAPS"
19715 "v4fmaddps\t{%3, %g2, %0|%0, %g2, %3}" 20327 "v4fmaddps\t{%3, %g2, %0|%0, %g2, %3}"
19716 [(set_attr ("type") ("ssemuladd")) 20328 [(set_attr ("type") ("ssemuladd"))
19717 (set_attr ("prefix") ("evex")) 20329 (set_attr ("prefix") ("evex"))
19719 20331
19720 (define_insn "avx5124fmaddps_4fmaddps_mask" 20332 (define_insn "avx5124fmaddps_4fmaddps_mask"
19721 [(set (match_operand:V16SF 0 "register_operand" "=v") 20333 [(set (match_operand:V16SF 0 "register_operand" "=v")
19722 (vec_merge:V16SF 20334 (vec_merge:V16SF
19723 (unspec:V16SF 20335 (unspec:V16SF
19724 [(match_operand:V64SF 1 "register_operand" "Yh") 20336 [(match_operand:V64SF 1 "register_operand" "v")
19725 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD) 20337 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD)
19726 (match_operand:V16SF 3 "register_operand" "0") 20338 (match_operand:V16SF 3 "register_operand" "0")
19727 (match_operand:HI 4 "register_operand" "Yk")))] 20339 (match_operand:HI 4 "register_operand" "Yk")))]
19728 "TARGET_AVX5124FMAPS" 20340 "TARGET_AVX5124FMAPS"
19729 "v4fmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}" 20341 "v4fmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
19730 [(set_attr ("type") ("ssemuladd")) 20342 [(set_attr ("type") ("ssemuladd"))
19731 (set_attr ("prefix") ("evex")) 20343 (set_attr ("prefix") ("evex"))
19732 (set_attr ("mode") ("V16SF"))]) 20344 (set_attr ("mode") ("V16SF"))])
19733 20345
19734 (define_insn "avx5124fmaddps_4fmaddps_maskz" 20346 (define_insn "avx5124fmaddps_4fmaddps_maskz"
19735 [(set (match_operand:V16SF 0 "register_operand" "=v") 20347 [(set (match_operand:V16SF 0 "register_operand" "=v")
19736 (vec_merge:V16SF 20348 (vec_merge:V16SF
19737 (unspec:V16SF 20349 (unspec:V16SF
19738 [(match_operand:V16SF 1 "register_operand" "0") 20350 [(match_operand:V16SF 1 "register_operand" "0")
19739 (match_operand:V64SF 2 "register_operand" "Yh") 20351 (match_operand:V64SF 2 "register_operand" "v")
19740 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD) 20352 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
19741 (match_operand:V16SF 4 "const0_operand" "C") 20353 (match_operand:V16SF 4 "const0_operand" "C")
19742 (match_operand:HI 5 "register_operand" "Yk")))] 20354 (match_operand:HI 5 "register_operand" "Yk")))]
19743 "TARGET_AVX5124FMAPS" 20355 "TARGET_AVX5124FMAPS"
19744 "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}" 20356 "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
19745 [(set_attr ("type") ("ssemuladd")) 20357 [(set_attr ("type") ("ssemuladd"))
19746 (set_attr ("prefix") ("evex")) 20358 (set_attr ("prefix") ("evex"))
19747 (set_attr ("mode") ("V16SF"))]) 20359 (set_attr ("mode") ("V16SF"))])
19748 20360
19749 (define_insn "avx5124fmaddps_4fmaddss" 20361 (define_insn "avx5124fmaddps_4fmaddss"
19750 [(set (match_operand:V4SF 0 "register_operand" "=v") 20362 [(set (match_operand:V4SF 0 "register_operand" "=v")
19751 (unspec:V4SF 20363 (unspec:V4SF
19752 [(match_operand:V4SF 1 "register_operand" "0") 20364 [(match_operand:V4SF 1 "register_operand" "0")
19753 (match_operand:V64SF 2 "register_operand" "Yh") 20365 (match_operand:V64SF 2 "register_operand" "v")
19754 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))] 20366 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))]
19755 "TARGET_AVX5124FMAPS" 20367 "TARGET_AVX5124FMAPS"
19756 "v4fmaddss\t{%3, %x2, %0|%0, %x2, %3}" 20368 "v4fmaddss\t{%3, %x2, %0|%0, %x2, %3}"
19757 [(set_attr ("type") ("ssemuladd")) 20369 [(set_attr ("type") ("ssemuladd"))
19758 (set_attr ("prefix") ("evex")) 20370 (set_attr ("prefix") ("evex"))
19760 20372
19761 (define_insn "avx5124fmaddps_4fmaddss_mask" 20373 (define_insn "avx5124fmaddps_4fmaddss_mask"
19762 [(set (match_operand:V4SF 0 "register_operand" "=v") 20374 [(set (match_operand:V4SF 0 "register_operand" "=v")
19763 (vec_merge:V4SF 20375 (vec_merge:V4SF
19764 (unspec:V4SF 20376 (unspec:V4SF
19765 [(match_operand:V64SF 1 "register_operand" "Yh") 20377 [(match_operand:V64SF 1 "register_operand" "v")
19766 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD) 20378 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD)
19767 (match_operand:V4SF 3 "register_operand" "0") 20379 (match_operand:V4SF 3 "register_operand" "0")
19768 (match_operand:QI 4 "register_operand" "Yk")))] 20380 (match_operand:QI 4 "register_operand" "Yk")))]
19769 "TARGET_AVX5124FMAPS" 20381 "TARGET_AVX5124FMAPS"
19770 "v4fmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}" 20382 "v4fmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
19771 [(set_attr ("type") ("ssemuladd")) 20383 [(set_attr ("type") ("ssemuladd"))
19772 (set_attr ("prefix") ("evex")) 20384 (set_attr ("prefix") ("evex"))
19773 (set_attr ("mode") ("SF"))]) 20385 (set_attr ("mode") ("SF"))])
19774 20386
19775 (define_insn "avx5124fmaddps_4fmaddss_maskz" 20387 (define_insn "avx5124fmaddps_4fmaddss_maskz"
19776 [(set (match_operand:V4SF 0 "register_operand" "=v") 20388 [(set (match_operand:V4SF 0 "register_operand" "=v")
19777 (vec_merge:V4SF 20389 (vec_merge:V4SF
19778 (unspec:V4SF 20390 (unspec:V4SF
19779 [(match_operand:V4SF 1 "register_operand" "0") 20391 [(match_operand:V4SF 1 "register_operand" "0")
19780 (match_operand:V64SF 2 "register_operand" "Yh") 20392 (match_operand:V64SF 2 "register_operand" "v")
19781 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD) 20393 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
19782 (match_operand:V4SF 4 "const0_operand" "C") 20394 (match_operand:V4SF 4 "const0_operand" "C")
19783 (match_operand:QI 5 "register_operand" "Yk")))] 20395 (match_operand:QI 5 "register_operand" "Yk")))]
19784 "TARGET_AVX5124FMAPS" 20396 "TARGET_AVX5124FMAPS"
19785 "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}" 20397 "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
19786 [(set_attr ("type") ("ssemuladd")) 20398 [(set_attr ("type") ("ssemuladd"))
19787 (set_attr ("prefix") ("evex")) 20399 (set_attr ("prefix") ("evex"))
19788 (set_attr ("mode") ("SF"))]) 20400 (set_attr ("mode") ("SF"))])
19789 20401
19790 (define_insn "avx5124fmaddps_4fnmaddps" 20402 (define_insn "avx5124fmaddps_4fnmaddps"
19791 [(set (match_operand:V16SF 0 "register_operand" "=v") 20403 [(set (match_operand:V16SF 0 "register_operand" "=v")
19792 (unspec:V16SF 20404 (unspec:V16SF
19793 [(match_operand:V16SF 1 "register_operand" "0") 20405 [(match_operand:V16SF 1 "register_operand" "0")
19794 (match_operand:V64SF 2 "register_operand" "Yh") 20406 (match_operand:V64SF 2 "register_operand" "v")
19795 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))] 20407 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))]
19796 "TARGET_AVX5124FMAPS" 20408 "TARGET_AVX5124FMAPS"
19797 "v4fnmaddps\t{%3, %g2, %0|%0, %g2, %3}" 20409 "v4fnmaddps\t{%3, %g2, %0|%0, %g2, %3}"
19798 [(set_attr ("type") ("ssemuladd")) 20410 [(set_attr ("type") ("ssemuladd"))
19799 (set_attr ("prefix") ("evex")) 20411 (set_attr ("prefix") ("evex"))
19801 20413
19802 (define_insn "avx5124fmaddps_4fnmaddps_mask" 20414 (define_insn "avx5124fmaddps_4fnmaddps_mask"
19803 [(set (match_operand:V16SF 0 "register_operand" "=v") 20415 [(set (match_operand:V16SF 0 "register_operand" "=v")
19804 (vec_merge:V16SF 20416 (vec_merge:V16SF
19805 (unspec:V16SF 20417 (unspec:V16SF
19806 [(match_operand:V64SF 1 "register_operand" "Yh") 20418 [(match_operand:V64SF 1 "register_operand" "v")
19807 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD) 20419 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD)
19808 (match_operand:V16SF 3 "register_operand" "0") 20420 (match_operand:V16SF 3 "register_operand" "0")
19809 (match_operand:HI 4 "register_operand" "Yk")))] 20421 (match_operand:HI 4 "register_operand" "Yk")))]
19810 "TARGET_AVX5124FMAPS" 20422 "TARGET_AVX5124FMAPS"
19811 "v4fnmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}" 20423 "v4fnmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
19812 [(set_attr ("type") ("ssemuladd")) 20424 [(set_attr ("type") ("ssemuladd"))
19813 (set_attr ("prefix") ("evex")) 20425 (set_attr ("prefix") ("evex"))
19814 (set_attr ("mode") ("V16SF"))]) 20426 (set_attr ("mode") ("V16SF"))])
19815 20427
19816 (define_insn "avx5124fmaddps_4fnmaddps_maskz" 20428 (define_insn "avx5124fmaddps_4fnmaddps_maskz"
19817 [(set (match_operand:V16SF 0 "register_operand" "=v") 20429 [(set (match_operand:V16SF 0 "register_operand" "=v")
19818 (vec_merge:V16SF 20430 (vec_merge:V16SF
19819 (unspec:V16SF 20431 (unspec:V16SF
19820 [(match_operand:V16SF 1 "register_operand" "0") 20432 [(match_operand:V16SF 1 "register_operand" "0")
19821 (match_operand:V64SF 2 "register_operand" "Yh") 20433 (match_operand:V64SF 2 "register_operand" "v")
19822 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD) 20434 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
19823 (match_operand:V16SF 4 "const0_operand" "C") 20435 (match_operand:V16SF 4 "const0_operand" "C")
19824 (match_operand:HI 5 "register_operand" "Yk")))] 20436 (match_operand:HI 5 "register_operand" "Yk")))]
19825 "TARGET_AVX5124FMAPS" 20437 "TARGET_AVX5124FMAPS"
19826 "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}" 20438 "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
19827 [(set_attr ("type") ("ssemuladd")) 20439 [(set_attr ("type") ("ssemuladd"))
19828 (set_attr ("prefix") ("evex")) 20440 (set_attr ("prefix") ("evex"))
19829 (set_attr ("mode") ("V16SF"))]) 20441 (set_attr ("mode") ("V16SF"))])
19830 20442
19831 (define_insn "avx5124fmaddps_4fnmaddss" 20443 (define_insn "avx5124fmaddps_4fnmaddss"
19832 [(set (match_operand:V4SF 0 "register_operand" "=v") 20444 [(set (match_operand:V4SF 0 "register_operand" "=v")
19833 (unspec:V4SF 20445 (unspec:V4SF
19834 [(match_operand:V4SF 1 "register_operand" "0") 20446 [(match_operand:V4SF 1 "register_operand" "0")
19835 (match_operand:V64SF 2 "register_operand" "Yh") 20447 (match_operand:V64SF 2 "register_operand" "v")
19836 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))] 20448 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))]
19837 "TARGET_AVX5124FMAPS" 20449 "TARGET_AVX5124FMAPS"
19838 "v4fnmaddss\t{%3, %x2, %0|%0, %x2, %3}" 20450 "v4fnmaddss\t{%3, %x2, %0|%0, %x2, %3}"
19839 [(set_attr ("type") ("ssemuladd")) 20451 [(set_attr ("type") ("ssemuladd"))
19840 (set_attr ("prefix") ("evex")) 20452 (set_attr ("prefix") ("evex"))
19842 20454
19843 (define_insn "avx5124fmaddps_4fnmaddss_mask" 20455 (define_insn "avx5124fmaddps_4fnmaddss_mask"
19844 [(set (match_operand:V4SF 0 "register_operand" "=v") 20456 [(set (match_operand:V4SF 0 "register_operand" "=v")
19845 (vec_merge:V4SF 20457 (vec_merge:V4SF
19846 (unspec:V4SF 20458 (unspec:V4SF
19847 [(match_operand:V64SF 1 "register_operand" "Yh") 20459 [(match_operand:V64SF 1 "register_operand" "v")
19848 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD) 20460 (match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD)
19849 (match_operand:V4SF 3 "register_operand" "0") 20461 (match_operand:V4SF 3 "register_operand" "0")
19850 (match_operand:QI 4 "register_operand" "Yk")))] 20462 (match_operand:QI 4 "register_operand" "Yk")))]
19851 "TARGET_AVX5124FMAPS" 20463 "TARGET_AVX5124FMAPS"
19852 "v4fnmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}" 20464 "v4fnmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
19853 [(set_attr ("type") ("ssemuladd")) 20465 [(set_attr ("type") ("ssemuladd"))
19854 (set_attr ("prefix") ("evex")) 20466 (set_attr ("prefix") ("evex"))
19855 (set_attr ("mode") ("SF"))]) 20467 (set_attr ("mode") ("SF"))])
19856 20468
19857 (define_insn "avx5124fmaddps_4fnmaddss_maskz" 20469 (define_insn "avx5124fmaddps_4fnmaddss_maskz"
19858 [(set (match_operand:V4SF 0 "register_operand" "=v") 20470 [(set (match_operand:V4SF 0 "register_operand" "=v")
19859 (vec_merge:V4SF 20471 (vec_merge:V4SF
19860 (unspec:V4SF 20472 (unspec:V4SF
19861 [(match_operand:V4SF 1 "register_operand" "0") 20473 [(match_operand:V4SF 1 "register_operand" "0")
19862 (match_operand:V64SF 2 "register_operand" "Yh") 20474 (match_operand:V64SF 2 "register_operand" "v")
19863 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD) 20475 (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
19864 (match_operand:V4SF 4 "const0_operand" "C") 20476 (match_operand:V4SF 4 "const0_operand" "C")
19865 (match_operand:QI 5 "register_operand" "Yk")))] 20477 (match_operand:QI 5 "register_operand" "Yk")))]
19866 "TARGET_AVX5124FMAPS" 20478 "TARGET_AVX5124FMAPS"
19867 "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}" 20479 "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
19868 [(set_attr ("type") ("ssemuladd")) 20480 [(set_attr ("type") ("ssemuladd"))
19869 (set_attr ("prefix") ("evex")) 20481 (set_attr ("prefix") ("evex"))
19870 (set_attr ("mode") ("SF"))]) 20482 (set_attr ("mode") ("SF"))])
19871 20483
19872 (define_insn "avx5124vnniw_vp4dpwssd" 20484 (define_insn "avx5124vnniw_vp4dpwssd"
19873 [(set (match_operand:V16SI 0 "register_operand" "=v") 20485 [(set (match_operand:V16SI 0 "register_operand" "=v")
19874 (unspec:V16SI 20486 (unspec:V16SI
19875 [(match_operand:V16SI 1 "register_operand" "0") 20487 [(match_operand:V16SI 1 "register_operand" "0")
19876 (match_operand:V64SI 2 "register_operand" "Yh") 20488 (match_operand:V64SI 2 "register_operand" "v")
19877 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD))] 20489 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD))]
19878 "TARGET_AVX5124VNNIW" 20490 "TARGET_AVX5124VNNIW"
19879 "vp4dpwssd\t{%3, %g2, %0|%0, %g2, %3}" 20491 "vp4dpwssd\t{%3, %g2, %0|%0, %g2, %3}"
19880 [(set_attr ("type") ("ssemuladd")) 20492 [(set_attr ("type") ("ssemuladd"))
19881 (set_attr ("prefix") ("evex")) 20493 (set_attr ("prefix") ("evex"))
19883 20495
19884 (define_insn "avx5124vnniw_vp4dpwssd_mask" 20496 (define_insn "avx5124vnniw_vp4dpwssd_mask"
19885 [(set (match_operand:V16SI 0 "register_operand" "=v") 20497 [(set (match_operand:V16SI 0 "register_operand" "=v")
19886 (vec_merge:V16SI 20498 (vec_merge:V16SI
19887 (unspec:V16SI 20499 (unspec:V16SI
19888 [(match_operand:V64SI 1 "register_operand" "Yh") 20500 [(match_operand:V64SI 1 "register_operand" "v")
19889 (match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSD) 20501 (match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSD)
19890 (match_operand:V16SI 3 "register_operand" "0") 20502 (match_operand:V16SI 3 "register_operand" "0")
19891 (match_operand:HI 4 "register_operand" "Yk")))] 20503 (match_operand:HI 4 "register_operand" "Yk")))]
19892 "TARGET_AVX5124VNNIW" 20504 "TARGET_AVX5124VNNIW"
19893 "vp4dpwssd\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}" 20505 "vp4dpwssd\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
19894 [(set_attr ("type") ("ssemuladd")) 20506 [(set_attr ("type") ("ssemuladd"))
19895 (set_attr ("prefix") ("evex")) 20507 (set_attr ("prefix") ("evex"))
19896 (set_attr ("mode") ("TI"))]) 20508 (set_attr ("mode") ("TI"))])
19897 20509
19898 (define_insn "avx5124vnniw_vp4dpwssd_maskz" 20510 (define_insn "avx5124vnniw_vp4dpwssd_maskz"
19899 [(set (match_operand:V16SI 0 "register_operand" "=v") 20511 [(set (match_operand:V16SI 0 "register_operand" "=v")
19900 (vec_merge:V16SI 20512 (vec_merge:V16SI
19901 (unspec:V16SI 20513 (unspec:V16SI
19902 [(match_operand:V16SI 1 "register_operand" "0") 20514 [(match_operand:V16SI 1 "register_operand" "0")
19903 (match_operand:V64SI 2 "register_operand" "Yh") 20515 (match_operand:V64SI 2 "register_operand" "v")
19904 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD) 20516 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD)
19905 (match_operand:V16SI 4 "const0_operand" "C") 20517 (match_operand:V16SI 4 "const0_operand" "C")
19906 (match_operand:HI 5 "register_operand" "Yk")))] 20518 (match_operand:HI 5 "register_operand" "Yk")))]
19907 "TARGET_AVX5124VNNIW" 20519 "TARGET_AVX5124VNNIW"
19908 "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}" 20520 "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
19909 [(set_attr ("type") ("ssemuladd")) 20521 [(set_attr ("type") ("ssemuladd"))
19910 (set_attr ("prefix") ("evex")) 20522 (set_attr ("prefix") ("evex"))
19911 (set_attr ("mode") ("TI"))]) 20523 (set_attr ("mode") ("TI"))])
19912 20524
19913 (define_insn "avx5124vnniw_vp4dpwssds" 20525 (define_insn "avx5124vnniw_vp4dpwssds"
19914 [(set (match_operand:V16SI 0 "register_operand" "=v") 20526 [(set (match_operand:V16SI 0 "register_operand" "=v")
19915 (unspec:V16SI 20527 (unspec:V16SI
19916 [(match_operand:V16SI 1 "register_operand" "0") 20528 [(match_operand:V16SI 1 "register_operand" "0")
19917 (match_operand:V64SI 2 "register_operand" "Yh") 20529 (match_operand:V64SI 2 "register_operand" "v")
19918 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS))] 20530 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS))]
19919 "TARGET_AVX5124VNNIW" 20531 "TARGET_AVX5124VNNIW"
19920 "vp4dpwssds\t{%3, %g2, %0|%0, %g2, %3}" 20532 "vp4dpwssds\t{%3, %g2, %0|%0, %g2, %3}"
19921 [(set_attr ("type") ("ssemuladd")) 20533 [(set_attr ("type") ("ssemuladd"))
19922 (set_attr ("prefix") ("evex")) 20534 (set_attr ("prefix") ("evex"))
19924 20536
19925 (define_insn "avx5124vnniw_vp4dpwssds_mask" 20537 (define_insn "avx5124vnniw_vp4dpwssds_mask"
19926 [(set (match_operand:V16SI 0 "register_operand" "=v") 20538 [(set (match_operand:V16SI 0 "register_operand" "=v")
19927 (vec_merge:V16SI 20539 (vec_merge:V16SI
19928 (unspec:V16SI 20540 (unspec:V16SI
19929 [(match_operand:V64SI 1 "register_operand" "Yh") 20541 [(match_operand:V64SI 1 "register_operand" "v")
19930 (match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSDS) 20542 (match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSDS)
19931 (match_operand:V16SI 3 "register_operand" "0") 20543 (match_operand:V16SI 3 "register_operand" "0")
19932 (match_operand:HI 4 "register_operand" "Yk")))] 20544 (match_operand:HI 4 "register_operand" "Yk")))]
19933 "TARGET_AVX5124VNNIW" 20545 "TARGET_AVX5124VNNIW"
19934 "vp4dpwssds\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}" 20546 "vp4dpwssds\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
19935 [(set_attr ("type") ("ssemuladd")) 20547 [(set_attr ("type") ("ssemuladd"))
19936 (set_attr ("prefix") ("evex")) 20548 (set_attr ("prefix") ("evex"))
19937 (set_attr ("mode") ("TI"))]) 20549 (set_attr ("mode") ("TI"))])
19938 20550
19939 (define_insn "avx5124vnniw_vp4dpwssds_maskz" 20551 (define_insn "avx5124vnniw_vp4dpwssds_maskz"
19940 [(set (match_operand:V16SI 0 "register_operand" "=v") 20552 [(set (match_operand:V16SI 0 "register_operand" "=v")
19941 (vec_merge:V16SI 20553 (vec_merge:V16SI
19942 (unspec:V16SI 20554 (unspec:V16SI
19943 [(match_operand:V16SI 1 "register_operand" "0") 20555 [(match_operand:V16SI 1 "register_operand" "0")
19944 (match_operand:V64SI 2 "register_operand" "Yh") 20556 (match_operand:V64SI 2 "register_operand" "v")
19945 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS) 20557 (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS)
19946 (match_operand:V16SI 4 "const0_operand" "C") 20558 (match_operand:V16SI 4 "const0_operand" "C")
19947 (match_operand:HI 5 "register_operand" "Yk")))] 20559 (match_operand:HI 5 "register_operand" "Yk")))]
19948 "TARGET_AVX5124VNNIW" 20560 "TARGET_AVX5124VNNIW"
19949 "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}" 20561 "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
19950 [(set_attr ("type") ("ssemuladd")) 20562 [(set_attr ("type") ("ssemuladd"))
19951 (set_attr ("prefix") ("evex")) 20563 (set_attr ("prefix") ("evex"))
19952 (set_attr ("mode") ("TI"))]) 20564 (set_attr ("mode") ("TI"))])
19953 20565
19954 (define_insn "vpopcount<mode><mask_name>" 20566 (define_insn "vpopcount<mode><mask_name>"
19955 [(set (match_operand:VI48_512 0 "register_operand" "=v") 20567 [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
19956 (popcount:VI48_512 20568 (popcount:VI48_AVX512VL
19957 (match_operand:VI48_512 1 "nonimmediate_operand" "vm")))] 20569 (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")))]
19958 "TARGET_AVX512VPOPCNTDQ" 20570 "TARGET_AVX512VPOPCNTDQ"
19959 "vpopcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}") 20571 "vpopcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}")
19960 20572
19961 ;; Save multiple registers out-of-line. 20573 ;; Save multiple registers out-of-line.
19962 (define_insn "save_multiple<mode>" 20574 (define_insn "save_multiple<mode>"
19992 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG))) 20604 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
19993 (clobber (mem:BLK (scratch))) 20605 (clobber (mem:BLK (scratch)))
19994 ])] 20606 ])]
19995 "TARGET_SSE && TARGET_64BIT" 20607 "TARGET_SSE && TARGET_64BIT"
19996 "jmp\t%P1") 20608 "jmp\t%P1")
20609
20610 (define_insn "vpopcount<mode><mask_name>"
20611 [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
20612 (popcount:VI12_AVX512VL
20613 (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm")))]
20614 "TARGET_AVX512BITALG"
20615 "vpopcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}")
20616
20617 (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
20618 [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
20619 (unspec:VI1_AVX512F
20620 [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
20621 (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
20622 (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
20623 UNSPEC_GF2P8AFFINEINV))]
20624 "TARGET_GFNI"
20625 "@
20626 gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
20627 vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
20628 vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
20629 [(set_attr "isa" "noavx,avx,avx512f")
20630 (set_attr "prefix_data16" "1,*,*")
20631 (set_attr "prefix_extra" "1")
20632 (set_attr "prefix" "orig,maybe_evex,evex")
20633 (set_attr "mode" "<sseinsnmode>")])
20634
20635 (define_insn "vgf2p8affineqb_<mode><mask_name>"
20636 [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
20637 (unspec:VI1_AVX512F
20638 [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
20639 (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
20640 (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
20641 UNSPEC_GF2P8AFFINE))]
20642 "TARGET_GFNI"
20643 "@
20644 gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
20645 vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
20646 vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
20647 [(set_attr "isa" "noavx,avx,avx512f")
20648 (set_attr "prefix_data16" "1,*,*")
20649 (set_attr "prefix_extra" "1")
20650 (set_attr "prefix" "orig,maybe_evex,evex")
20651 (set_attr "mode" "<sseinsnmode>")])
20652
20653 (define_insn "vgf2p8mulb_<mode><mask_name>"
20654 [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
20655 (unspec:VI1_AVX512F
20656 [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
20657 (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
20658 UNSPEC_GF2P8MUL))]
20659 "TARGET_GFNI"
20660 "@
20661 gf2p8mulb\t{%2, %0| %0, %2}
20662 vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}
20663 vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
20664 [(set_attr "isa" "noavx,avx,avx512f")
20665 (set_attr "prefix_data16" "1,*,*")
20666 (set_attr "prefix_extra" "1")
20667 (set_attr "prefix" "orig,maybe_evex,evex")
20668 (set_attr "mode" "<sseinsnmode>")])
20669
20670 (define_insn "vpshrd_<mode><mask_name>"
20671 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20672 (unspec:VI248_AVX512VL
20673 [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
20674 (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
20675 (match_operand:SI 3 "const_0_to_255_operand" "n")]
20676 UNSPEC_VPSHRD))]
20677 "TARGET_AVX512VBMI2"
20678 "vpshrd<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
20679 [(set_attr ("prefix") ("evex"))])
20680
20681 (define_insn "vpshld_<mode><mask_name>"
20682 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20683 (unspec:VI248_AVX512VL
20684 [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
20685 (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
20686 (match_operand:SI 3 "const_0_to_255_operand" "n")]
20687 UNSPEC_VPSHLD))]
20688 "TARGET_AVX512VBMI2"
20689 "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
20690 [(set_attr ("prefix") ("evex"))])
20691
20692 (define_insn "vpshrdv_<mode>"
20693 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20694 (unspec:VI248_AVX512VL
20695 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20696 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20697 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20698 UNSPEC_VPSHRDV))]
20699 "TARGET_AVX512VBMI2"
20700 "vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
20701 [(set_attr ("prefix") ("evex"))
20702 (set_attr "mode" "<sseinsnmode>")])
20703
20704 (define_insn "vpshrdv_<mode>_mask"
20705 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20706 (vec_merge:VI248_AVX512VL
20707 (unspec:VI248_AVX512VL
20708 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20709 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20710 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20711 UNSPEC_VPSHRDV)
20712 (match_dup 1)
20713 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20714 "TARGET_AVX512VBMI2"
20715 "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20716 [(set_attr ("prefix") ("evex"))
20717 (set_attr "mode" "<sseinsnmode>")])
20718
20719 (define_expand "vpshrdv_<mode>_maskz"
20720 [(match_operand:VI248_AVX512VL 0 "register_operand")
20721 (match_operand:VI248_AVX512VL 1 "register_operand")
20722 (match_operand:VI248_AVX512VL 2 "register_operand")
20723 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
20724 (match_operand:<avx512fmaskmode> 4 "register_operand")]
20725 "TARGET_AVX512VBMI2"
20726 {
20727 emit_insn (gen_vpshrdv_<mode>_maskz_1 (operands[0], operands[1],
20728 operands[2], operands[3],
20729 CONST0_RTX (<MODE>mode),
20730 operands[4]));
20731 DONE;
20732 })
20733
20734 (define_insn "vpshrdv_<mode>_maskz_1"
20735 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20736 (vec_merge:VI248_AVX512VL
20737 (unspec:VI248_AVX512VL
20738 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20739 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20740 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20741 UNSPEC_VPSHRDV)
20742 (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
20743 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
20744 "TARGET_AVX512VBMI2"
20745 "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
20746 [(set_attr ("prefix") ("evex"))
20747 (set_attr "mode" "<sseinsnmode>")])
20748
20749 (define_insn "vpshldv_<mode>"
20750 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20751 (unspec:VI248_AVX512VL
20752 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20753 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20754 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20755 UNSPEC_VPSHLDV))]
20756 "TARGET_AVX512VBMI2"
20757 "vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
20758 [(set_attr ("prefix") ("evex"))
20759 (set_attr "mode" "<sseinsnmode>")])
20760
20761 (define_insn "vpshldv_<mode>_mask"
20762 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20763 (vec_merge:VI248_AVX512VL
20764 (unspec:VI248_AVX512VL
20765 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20766 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20767 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20768 UNSPEC_VPSHLDV)
20769 (match_dup 1)
20770 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20771 "TARGET_AVX512VBMI2"
20772 "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20773 [(set_attr ("prefix") ("evex"))
20774 (set_attr "mode" "<sseinsnmode>")])
20775
20776 (define_expand "vpshldv_<mode>_maskz"
20777 [(match_operand:VI248_AVX512VL 0 "register_operand")
20778 (match_operand:VI248_AVX512VL 1 "register_operand")
20779 (match_operand:VI248_AVX512VL 2 "register_operand")
20780 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
20781 (match_operand:<avx512fmaskmode> 4 "register_operand")]
20782 "TARGET_AVX512VBMI2"
20783 {
20784 emit_insn (gen_vpshldv_<mode>_maskz_1 (operands[0], operands[1],
20785 operands[2], operands[3],
20786 CONST0_RTX (<MODE>mode),
20787 operands[4]));
20788 DONE;
20789 })
20790
20791 (define_insn "vpshldv_<mode>_maskz_1"
20792 [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
20793 (vec_merge:VI248_AVX512VL
20794 (unspec:VI248_AVX512VL
20795 [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
20796 (match_operand:VI248_AVX512VL 2 "register_operand" "v")
20797 (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
20798 UNSPEC_VPSHLDV)
20799 (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
20800 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
20801 "TARGET_AVX512VBMI2"
20802 "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
20803 [(set_attr ("prefix") ("evex"))
20804 (set_attr "mode" "<sseinsnmode>")])
20805
20806 (define_insn "vpdpbusd_<mode>"
20807 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20808 (unspec:VI4_AVX512VL
20809 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20810 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20811 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20812 UNSPEC_VPMADDUBSWACCD))]
20813 "TARGET_AVX512VNNI"
20814 "vpdpbusd\t{%3, %2, %0|%0, %2, %3 }"
20815 [(set_attr ("prefix") ("evex"))])
20816
20817 (define_insn "vpdpbusd_<mode>_mask"
20818 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20819 (vec_merge:VI4_AVX512VL
20820 (unspec:VI4_AVX512VL
20821 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20822 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20823 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20824 UNSPEC_VPMADDUBSWACCD)
20825 (match_dup 1)
20826 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20827 "TARGET_AVX512VNNI"
20828 "vpdpbusd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20829 [(set_attr ("prefix") ("evex"))])
20830
20831 (define_expand "vpdpbusd_<mode>_maskz"
20832 [(match_operand:VI4_AVX512VL 0 "register_operand")
20833 (match_operand:VI4_AVX512VL 1 "register_operand")
20834 (match_operand:VI4_AVX512VL 2 "register_operand")
20835 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand")
20836 (match_operand:<avx512fmaskmode> 4 "register_operand")]
20837 "TARGET_AVX512VNNI"
20838 {
20839 emit_insn (gen_vpdpbusd_<mode>_maskz_1 (operands[0], operands[1],
20840 operands[2], operands[3],
20841 CONST0_RTX (<MODE>mode),
20842 operands[4]));
20843 DONE;
20844 })
20845
20846 (define_insn "vpdpbusd_<mode>_maskz_1"
20847 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20848 (vec_merge:VI4_AVX512VL
20849 (unspec:VI4_AVX512VL
20850 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20851 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20852 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
20853 ] UNSPEC_VPMADDUBSWACCD)
20854 (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
20855 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
20856 "TARGET_AVX512VNNI"
20857 "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
20858 [(set_attr ("prefix") ("evex"))])
20859
20860
20861 (define_insn "vpdpbusds_<mode>"
20862 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20863 (unspec:VI4_AVX512VL
20864 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20865 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20866 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20867 UNSPEC_VPMADDUBSWACCSSD))]
20868 "TARGET_AVX512VNNI"
20869 "vpdpbusds\t{%3, %2, %0|%0, %2, %3 }"
20870 [(set_attr ("prefix") ("evex"))])
20871
20872 (define_insn "vpdpbusds_<mode>_mask"
20873 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20874 (vec_merge:VI4_AVX512VL
20875 (unspec:VI4_AVX512VL
20876 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20877 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20878 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20879 UNSPEC_VPMADDUBSWACCSSD)
20880 (match_dup 1)
20881 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20882 "TARGET_AVX512VNNI"
20883 "vpdpbusds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20884 [(set_attr ("prefix") ("evex"))])
20885
20886 (define_expand "vpdpbusds_<mode>_maskz"
20887 [(match_operand:VI4_AVX512VL 0 "register_operand")
20888 (match_operand:VI4_AVX512VL 1 "register_operand")
20889 (match_operand:VI4_AVX512VL 2 "register_operand")
20890 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand")
20891 (match_operand:<avx512fmaskmode> 4 "register_operand")]
20892 "TARGET_AVX512VNNI"
20893 {
20894 emit_insn (gen_vpdpbusds_<mode>_maskz_1 (operands[0], operands[1],
20895 operands[2], operands[3],
20896 CONST0_RTX (<MODE>mode),
20897 operands[4]));
20898 DONE;
20899 })
20900
20901 (define_insn "vpdpbusds_<mode>_maskz_1"
20902 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20903 (vec_merge:VI4_AVX512VL
20904 (unspec:VI4_AVX512VL
20905 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20906 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20907 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20908 UNSPEC_VPMADDUBSWACCSSD)
20909 (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
20910 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
20911 "TARGET_AVX512VNNI"
20912 "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
20913 [(set_attr ("prefix") ("evex"))])
20914
20915
20916 (define_insn "vpdpwssd_<mode>"
20917 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20918 (unspec:VI4_AVX512VL
20919 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20920 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20921 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20922 UNSPEC_VPMADDWDACCD))]
20923 "TARGET_AVX512VNNI"
20924 "vpdpwssd\t{%3, %2, %0|%0, %2, %3 }"
20925 [(set_attr ("prefix") ("evex"))])
20926
20927 (define_insn "vpdpwssd_<mode>_mask"
20928 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20929 (vec_merge:VI4_AVX512VL
20930 (unspec:VI4_AVX512VL
20931 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20932 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20933 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20934 UNSPEC_VPMADDWDACCD)
20935 (match_dup 1)
20936 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20937 "TARGET_AVX512VNNI"
20938 "vpdpwssd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20939 [(set_attr ("prefix") ("evex"))])
20940
20941 (define_expand "vpdpwssd_<mode>_maskz"
20942 [(match_operand:VI4_AVX512VL 0 "register_operand")
20943 (match_operand:VI4_AVX512VL 1 "register_operand")
20944 (match_operand:VI4_AVX512VL 2 "register_operand")
20945 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand")
20946 (match_operand:<avx512fmaskmode> 4 "register_operand")]
20947 "TARGET_AVX512VNNI"
20948 {
20949 emit_insn (gen_vpdpwssd_<mode>_maskz_1 (operands[0], operands[1],
20950 operands[2], operands[3],
20951 CONST0_RTX (<MODE>mode),
20952 operands[4]));
20953 DONE;
20954 })
20955
20956 (define_insn "vpdpwssd_<mode>_maskz_1"
20957 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20958 (vec_merge:VI4_AVX512VL
20959 (unspec:VI4_AVX512VL
20960 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20961 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20962 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20963 UNSPEC_VPMADDWDACCD)
20964 (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
20965 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
20966 "TARGET_AVX512VNNI"
20967 "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
20968 [(set_attr ("prefix") ("evex"))])
20969
20970
20971 (define_insn "vpdpwssds_<mode>"
20972 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20973 (unspec:VI4_AVX512VL
20974 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20975 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20976 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20977 UNSPEC_VPMADDWDACCSSD))]
20978 "TARGET_AVX512VNNI"
20979 "vpdpwssds\t{%3, %2, %0|%0, %2, %3 }"
20980 [(set_attr ("prefix") ("evex"))])
20981
20982 (define_insn "vpdpwssds_<mode>_mask"
20983 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
20984 (vec_merge:VI4_AVX512VL
20985 (unspec:VI4_AVX512VL
20986 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
20987 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
20988 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
20989 UNSPEC_VPMADDWDACCSSD)
20990 (match_dup 1)
20991 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
20992 "TARGET_AVX512VNNI"
20993 "vpdpwssds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
20994 [(set_attr ("prefix") ("evex"))])
20995
20996 (define_expand "vpdpwssds_<mode>_maskz"
20997 [(match_operand:VI4_AVX512VL 0 "register_operand")
20998 (match_operand:VI4_AVX512VL 1 "register_operand")
20999 (match_operand:VI4_AVX512VL 2 "register_operand")
21000 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand")
21001 (match_operand:<avx512fmaskmode> 4 "register_operand")]
21002 "TARGET_AVX512VNNI"
21003 {
21004 emit_insn (gen_vpdpwssds_<mode>_maskz_1 (operands[0], operands[1],
21005 operands[2], operands[3],
21006 CONST0_RTX (<MODE>mode),
21007 operands[4]));
21008 DONE;
21009 })
21010
21011 (define_insn "vpdpwssds_<mode>_maskz_1"
21012 [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
21013 (vec_merge:VI4_AVX512VL
21014 (unspec:VI4_AVX512VL
21015 [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
21016 (match_operand:VI4_AVX512VL 2 "register_operand" "v")
21017 (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
21018 UNSPEC_VPMADDWDACCSSD)
21019 (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
21020 (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
21021 "TARGET_AVX512VNNI"
21022 "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
21023 [(set_attr ("prefix") ("evex"))])
21024
21025 (define_insn "vaesdec_<mode>"
21026 [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
21027 (unspec:VI1_AVX512VL_F
21028 [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
21029 (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
21030 UNSPEC_VAESDEC))]
21031 "TARGET_VAES"
21032 "vaesdec\t{%2, %1, %0|%0, %1, %2}"
21033 )
21034
21035 (define_insn "vaesdeclast_<mode>"
21036 [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
21037 (unspec:VI1_AVX512VL_F
21038 [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
21039 (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
21040 UNSPEC_VAESDECLAST))]
21041 "TARGET_VAES"
21042 "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
21043 )
21044
21045 (define_insn "vaesenc_<mode>"
21046 [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
21047 (unspec:VI1_AVX512VL_F
21048 [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
21049 (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
21050 UNSPEC_VAESENC))]
21051 "TARGET_VAES"
21052 "vaesenc\t{%2, %1, %0|%0, %1, %2}"
21053 )
21054
21055 (define_insn "vaesenclast_<mode>"
21056 [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
21057 (unspec:VI1_AVX512VL_F
21058 [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
21059 (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
21060 UNSPEC_VAESENCLAST))]
21061 "TARGET_VAES"
21062 "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
21063 )
21064
21065 (define_insn "vpclmulqdq_<mode>"
21066 [(set (match_operand:VI8_FVL 0 "register_operand" "=v")
21067 (unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v")
21068 (match_operand:VI8_FVL 2 "vector_operand" "vm")
21069 (match_operand:SI 3 "const_0_to_255_operand" "n")]
21070 UNSPEC_VPCLMULQDQ))]
21071 "TARGET_VPCLMULQDQ"
21072 "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
21073 [(set_attr "mode" "DI")])
21074
21075 (define_insn "avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>"
21076 [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
21077 (unspec:<avx512fmaskmode>
21078 [(match_operand:VI1_AVX512VLBW 1 "register_operand" "v")
21079 (match_operand:VI1_AVX512VLBW 2 "nonimmediate_operand" "vm")]
21080 UNSPEC_VPSHUFBIT))]
21081 "TARGET_AVX512BITALG"
21082 "vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
21083 [(set_attr "prefix" "evex")
21084 (set_attr "mode" "<sseinsnmode>")])