Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/ia64/vect.md @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
---|---|
date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
comparison
equal
deleted
inserted
replaced
111:04ced10e8804 | 131:84e7813d76e9 |
---|---|
1 ;; IA-64 machine description for vector operations. | 1 ;; IA-64 machine description for vector operations. |
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2004-2018 Free Software Foundation, Inc. |
3 ;; | 3 ;; |
4 ;; This file is part of GCC. | 4 ;; This file is part of GCC. |
5 ;; | 5 ;; |
6 ;; GCC is free software; you can redistribute it and/or modify | 6 ;; GCC is free software; you can redistribute it and/or modify |
7 ;; it under the terms of the GNU General Public License as published by | 7 ;; it under the terms of the GNU General Public License as published by |
1136 (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "") | 1136 (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "") |
1137 (match_dup 3) | 1137 (match_dup 3) |
1138 (match_operand:V2SF 2 "fr_register_operand" "")))] | 1138 (match_operand:V2SF 2 "fr_register_operand" "")))] |
1139 "" | 1139 "" |
1140 { | 1140 { |
1141 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); | 1141 operands[3] = force_reg (V2SFmode, CONST1_RTX (V2SFmode)); |
1142 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); | |
1143 }) | 1142 }) |
1144 | 1143 |
1145 (define_expand "subv2sf3" | 1144 (define_expand "subv2sf3" |
1146 [(set (match_operand:V2SF 0 "fr_register_operand" "") | 1145 [(set (match_operand:V2SF 0 "fr_register_operand" "") |
1147 (fma:V2SF | 1146 (fma:V2SF |
1148 (match_operand:V2SF 1 "fr_register_operand" "") | 1147 (match_operand:V2SF 1 "fr_register_operand" "") |
1149 (match_dup 3) | 1148 (match_dup 3) |
1150 (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))] | 1149 (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))] |
1151 "" | 1150 "" |
1152 { | 1151 { |
1153 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); | 1152 operands[3] = force_reg (V2SFmode, CONST1_RTX (V2SFmode)); |
1154 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); | |
1155 }) | 1153 }) |
1156 | 1154 |
1157 (define_insn "mulv2sf3" | 1155 (define_insn "mulv2sf3" |
1158 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | 1156 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1159 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | 1157 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") |
1549 rtx op2 = gen_lowpart (V4HImode, operands[2]); | 1547 rtx op2 = gen_lowpart (V4HImode, operands[2]); |
1550 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); | 1548 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); |
1551 DONE; | 1549 DONE; |
1552 }) | 1550 }) |
1553 | 1551 |
1554 (define_expand "vec_perm_const<mode>" | |
1555 [(match_operand:VEC 0 "register_operand" "") | |
1556 (match_operand:VEC 1 "register_operand" "") | |
1557 (match_operand:VEC 2 "register_operand" "") | |
1558 (match_operand:<vecint> 3 "" "")] | |
1559 "" | |
1560 { | |
1561 if (ia64_expand_vec_perm_const (operands)) | |
1562 DONE; | |
1563 else | |
1564 FAIL; | |
1565 }) | |
1566 | |
1567 ;; Missing operations | 1552 ;; Missing operations |
1568 ;; fprcpa | 1553 ;; fprcpa |
1569 ;; fpsqrta | 1554 ;; fpsqrta |