Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/nds32/nds32-multiple.md @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
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date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
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111:04ced10e8804 | 131:84e7813d76e9 |
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1 ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler | 1 ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler |
2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc. |
3 ;; Contributed by Andes Technology Corporation.for NDS32. | 3 ;; Contributed by Andes Technology Corporation.for NDS32. |
4 ;; | 4 ;; |
5 ;; This file is part of GCC. | 5 ;; This file is part of GCC. |
6 ;; | 6 ;; |
7 ;; GCC is free software; you can redistribute it and/or modify it | 7 ;; GCC is free software; you can redistribute it and/or modify it |
52 (based on this nds32-multiple.md design). | 52 (based on this nds32-multiple.md design). |
53 3. Minimum 2 registers for lmw.bi instruction | 53 3. Minimum 2 registers for lmw.bi instruction |
54 (based on this nds32-multiple.md design). | 54 (based on this nds32-multiple.md design). |
55 4. operands[0] must be register for sure. | 55 4. operands[0] must be register for sure. |
56 5. operands[1] must be memory for sure. | 56 5. operands[1] must be memory for sure. |
57 6. Do not cross $r15 register because it is not allocatable. */ | 57 6. operands[1] is not volatile memory access. |
58 7. Do not cross $r15 register because it is not allocatable. */ | |
58 if (GET_CODE (operands[2]) != CONST_INT | 59 if (GET_CODE (operands[2]) != CONST_INT |
59 || INTVAL (operands[2]) > maximum | 60 || INTVAL (operands[2]) > maximum |
60 || INTVAL (operands[2]) < 2 | 61 || INTVAL (operands[2]) < 2 |
61 || GET_CODE (operands[0]) != REG | 62 || GET_CODE (operands[0]) != REG |
62 || GET_CODE (operands[1]) != MEM | 63 || GET_CODE (operands[1]) != MEM |
64 || MEM_VOLATILE_P (operands[1]) | |
63 || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM) | 65 || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM) |
64 FAIL; | 66 FAIL; |
65 | 67 |
66 /* For (mem addr), we force_reg on addr here, | 68 /* For (mem addr), we force_reg on addr here, |
67 so that nds32_expand_load_multiple can easily use it. */ | 69 so that nds32_expand_load_multiple can easily use it. */ |
68 operands[3] = nds32_expand_load_multiple (REGNO (operands[0]), | 70 operands[3] = nds32_expand_load_multiple (REGNO (operands[0]), |
69 INTVAL (operands[2]), | 71 INTVAL (operands[2]), |
70 force_reg (SImode, | 72 force_reg (SImode, |
71 XEXP (operands[1], 0)), | 73 XEXP (operands[1], 0)), |
72 operands[1]); | 74 operands[1], |
75 false, NULL); | |
73 }) | 76 }) |
74 | 77 |
75 ;; Ordinary Load Multiple. | 78 ;; Ordinary Load Multiple. |
79 (define_insn "*lmw_bim_si25" | |
80 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
81 [(set (match_operand:SI 1 "register_operand" "=r") | |
82 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 100))) | |
83 (set (match_operand:SI 3 "register_operand" "") | |
84 (mem:SI (match_dup 2))) | |
85 (set (match_operand:SI 4 "register_operand" "") | |
86 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
87 (set (match_operand:SI 5 "register_operand" "") | |
88 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
89 (set (match_operand:SI 6 "register_operand" "") | |
90 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
91 (set (match_operand:SI 7 "register_operand" "") | |
92 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
93 (set (match_operand:SI 8 "register_operand" "") | |
94 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
95 (set (match_operand:SI 9 "register_operand" "") | |
96 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
97 (set (match_operand:SI 10 "register_operand" "") | |
98 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
99 (set (match_operand:SI 11 "register_operand" "") | |
100 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
101 (set (match_operand:SI 12 "register_operand" "") | |
102 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
103 (set (match_operand:SI 13 "register_operand" "") | |
104 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
105 (set (match_operand:SI 14 "register_operand" "") | |
106 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
107 (set (match_operand:SI 15 "register_operand" "") | |
108 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
109 (set (match_operand:SI 16 "register_operand" "") | |
110 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
111 (set (match_operand:SI 17 "register_operand" "") | |
112 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
113 (set (match_operand:SI 18 "register_operand" "") | |
114 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
115 (set (match_operand:SI 19 "register_operand" "") | |
116 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
117 (set (match_operand:SI 20 "register_operand" "") | |
118 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
119 (set (match_operand:SI 21 "register_operand" "") | |
120 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
121 (set (match_operand:SI 22 "register_operand" "") | |
122 (mem:SI (plus:SI (match_dup 2) (const_int 76)))) | |
123 (set (match_operand:SI 23 "register_operand" "") | |
124 (mem:SI (plus:SI (match_dup 2) (const_int 80)))) | |
125 (set (match_operand:SI 24 "register_operand" "") | |
126 (mem:SI (plus:SI (match_dup 2) (const_int 84)))) | |
127 (set (match_operand:SI 25 "register_operand" "") | |
128 (mem:SI (plus:SI (match_dup 2) (const_int 88)))) | |
129 (set (match_operand:SI 26 "register_operand" "") | |
130 (mem:SI (plus:SI (match_dup 2) (const_int 92)))) | |
131 (set (match_operand:SI 27 "register_operand" "") | |
132 (mem:SI (plus:SI (match_dup 2) (const_int 96))))])] | |
133 "(XVECLEN (operands[0], 0) == 26)" | |
134 "lmw.bim\t%3, [%1], %27, 0x0" | |
135 [(set_attr "type" "load_multiple") | |
136 (set_attr "combo" "25") | |
137 (set_attr "length" "4")] | |
138 ) | |
139 | |
140 (define_insn "*lmw_bim_si24" | |
141 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
142 [(set (match_operand:SI 1 "register_operand" "=r") | |
143 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 96))) | |
144 (set (match_operand:SI 3 "register_operand" "") | |
145 (mem:SI (match_dup 2))) | |
146 (set (match_operand:SI 4 "register_operand" "") | |
147 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
148 (set (match_operand:SI 5 "register_operand" "") | |
149 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
150 (set (match_operand:SI 6 "register_operand" "") | |
151 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
152 (set (match_operand:SI 7 "register_operand" "") | |
153 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
154 (set (match_operand:SI 8 "register_operand" "") | |
155 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
156 (set (match_operand:SI 9 "register_operand" "") | |
157 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
158 (set (match_operand:SI 10 "register_operand" "") | |
159 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
160 (set (match_operand:SI 11 "register_operand" "") | |
161 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
162 (set (match_operand:SI 12 "register_operand" "") | |
163 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
164 (set (match_operand:SI 13 "register_operand" "") | |
165 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
166 (set (match_operand:SI 14 "register_operand" "") | |
167 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
168 (set (match_operand:SI 15 "register_operand" "") | |
169 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
170 (set (match_operand:SI 16 "register_operand" "") | |
171 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
172 (set (match_operand:SI 17 "register_operand" "") | |
173 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
174 (set (match_operand:SI 18 "register_operand" "") | |
175 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
176 (set (match_operand:SI 19 "register_operand" "") | |
177 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
178 (set (match_operand:SI 20 "register_operand" "") | |
179 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
180 (set (match_operand:SI 21 "register_operand" "") | |
181 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
182 (set (match_operand:SI 22 "register_operand" "") | |
183 (mem:SI (plus:SI (match_dup 2) (const_int 76)))) | |
184 (set (match_operand:SI 23 "register_operand" "") | |
185 (mem:SI (plus:SI (match_dup 2) (const_int 80)))) | |
186 (set (match_operand:SI 24 "register_operand" "") | |
187 (mem:SI (plus:SI (match_dup 2) (const_int 84)))) | |
188 (set (match_operand:SI 25 "register_operand" "") | |
189 (mem:SI (plus:SI (match_dup 2) (const_int 88)))) | |
190 (set (match_operand:SI 26 "register_operand" "") | |
191 (mem:SI (plus:SI (match_dup 2) (const_int 92))))])] | |
192 "(XVECLEN (operands[0], 0) == 25)" | |
193 "lmw.bim\t%3, [%1], %26, 0x0" | |
194 [(set_attr "type" "load_multiple") | |
195 (set_attr "combo" "24") | |
196 (set_attr "length" "4")] | |
197 ) | |
198 | |
199 (define_insn "*lmw_bim_si23" | |
200 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
201 [(set (match_operand:SI 1 "register_operand" "=r") | |
202 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 92))) | |
203 (set (match_operand:SI 3 "register_operand" "") | |
204 (mem:SI (match_dup 2))) | |
205 (set (match_operand:SI 4 "register_operand" "") | |
206 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
207 (set (match_operand:SI 5 "register_operand" "") | |
208 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
209 (set (match_operand:SI 6 "register_operand" "") | |
210 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
211 (set (match_operand:SI 7 "register_operand" "") | |
212 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
213 (set (match_operand:SI 8 "register_operand" "") | |
214 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
215 (set (match_operand:SI 9 "register_operand" "") | |
216 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
217 (set (match_operand:SI 10 "register_operand" "") | |
218 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
219 (set (match_operand:SI 11 "register_operand" "") | |
220 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
221 (set (match_operand:SI 12 "register_operand" "") | |
222 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
223 (set (match_operand:SI 13 "register_operand" "") | |
224 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
225 (set (match_operand:SI 14 "register_operand" "") | |
226 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
227 (set (match_operand:SI 15 "register_operand" "") | |
228 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
229 (set (match_operand:SI 16 "register_operand" "") | |
230 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
231 (set (match_operand:SI 17 "register_operand" "") | |
232 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
233 (set (match_operand:SI 18 "register_operand" "") | |
234 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
235 (set (match_operand:SI 19 "register_operand" "") | |
236 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
237 (set (match_operand:SI 20 "register_operand" "") | |
238 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
239 (set (match_operand:SI 21 "register_operand" "") | |
240 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
241 (set (match_operand:SI 22 "register_operand" "") | |
242 (mem:SI (plus:SI (match_dup 2) (const_int 76)))) | |
243 (set (match_operand:SI 23 "register_operand" "") | |
244 (mem:SI (plus:SI (match_dup 2) (const_int 80)))) | |
245 (set (match_operand:SI 24 "register_operand" "") | |
246 (mem:SI (plus:SI (match_dup 2) (const_int 84)))) | |
247 (set (match_operand:SI 25 "register_operand" "") | |
248 (mem:SI (plus:SI (match_dup 2) (const_int 88))))])] | |
249 "(XVECLEN (operands[0], 0) == 24)" | |
250 "lmw.bim\t%3, [%1], %25, 0x0" | |
251 [(set_attr "type" "load_multiple") | |
252 (set_attr "combo" "23") | |
253 (set_attr "length" "4")] | |
254 ) | |
255 | |
256 (define_insn "*lmw_bim_si22" | |
257 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
258 [(set (match_operand:SI 1 "register_operand" "=r") | |
259 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 88))) | |
260 (set (match_operand:SI 3 "register_operand" "") | |
261 (mem:SI (match_dup 2))) | |
262 (set (match_operand:SI 4 "register_operand" "") | |
263 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
264 (set (match_operand:SI 5 "register_operand" "") | |
265 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
266 (set (match_operand:SI 6 "register_operand" "") | |
267 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
268 (set (match_operand:SI 7 "register_operand" "") | |
269 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
270 (set (match_operand:SI 8 "register_operand" "") | |
271 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
272 (set (match_operand:SI 9 "register_operand" "") | |
273 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
274 (set (match_operand:SI 10 "register_operand" "") | |
275 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
276 (set (match_operand:SI 11 "register_operand" "") | |
277 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
278 (set (match_operand:SI 12 "register_operand" "") | |
279 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
280 (set (match_operand:SI 13 "register_operand" "") | |
281 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
282 (set (match_operand:SI 14 "register_operand" "") | |
283 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
284 (set (match_operand:SI 15 "register_operand" "") | |
285 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
286 (set (match_operand:SI 16 "register_operand" "") | |
287 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
288 (set (match_operand:SI 17 "register_operand" "") | |
289 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
290 (set (match_operand:SI 18 "register_operand" "") | |
291 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
292 (set (match_operand:SI 19 "register_operand" "") | |
293 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
294 (set (match_operand:SI 20 "register_operand" "") | |
295 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
296 (set (match_operand:SI 21 "register_operand" "") | |
297 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
298 (set (match_operand:SI 22 "register_operand" "") | |
299 (mem:SI (plus:SI (match_dup 2) (const_int 76)))) | |
300 (set (match_operand:SI 23 "register_operand" "") | |
301 (mem:SI (plus:SI (match_dup 2) (const_int 80)))) | |
302 (set (match_operand:SI 24 "register_operand" "") | |
303 (mem:SI (plus:SI (match_dup 2) (const_int 84))))])] | |
304 "(XVECLEN (operands[0], 0) == 23)" | |
305 "lmw.bim\t%3, [%1], %24, 0x0" | |
306 [(set_attr "type" "load_multiple") | |
307 (set_attr "combo" "22") | |
308 (set_attr "length" "4")] | |
309 ) | |
310 | |
311 (define_insn "*lmw_bim_si21" | |
312 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
313 [(set (match_operand:SI 1 "register_operand" "=r") | |
314 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 84))) | |
315 (set (match_operand:SI 3 "register_operand" "") | |
316 (mem:SI (match_dup 2))) | |
317 (set (match_operand:SI 4 "register_operand" "") | |
318 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
319 (set (match_operand:SI 5 "register_operand" "") | |
320 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
321 (set (match_operand:SI 6 "register_operand" "") | |
322 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
323 (set (match_operand:SI 7 "register_operand" "") | |
324 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
325 (set (match_operand:SI 8 "register_operand" "") | |
326 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
327 (set (match_operand:SI 9 "register_operand" "") | |
328 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
329 (set (match_operand:SI 10 "register_operand" "") | |
330 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
331 (set (match_operand:SI 11 "register_operand" "") | |
332 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
333 (set (match_operand:SI 12 "register_operand" "") | |
334 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
335 (set (match_operand:SI 13 "register_operand" "") | |
336 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
337 (set (match_operand:SI 14 "register_operand" "") | |
338 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
339 (set (match_operand:SI 15 "register_operand" "") | |
340 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
341 (set (match_operand:SI 16 "register_operand" "") | |
342 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
343 (set (match_operand:SI 17 "register_operand" "") | |
344 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
345 (set (match_operand:SI 18 "register_operand" "") | |
346 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
347 (set (match_operand:SI 19 "register_operand" "") | |
348 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
349 (set (match_operand:SI 20 "register_operand" "") | |
350 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
351 (set (match_operand:SI 21 "register_operand" "") | |
352 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
353 (set (match_operand:SI 22 "register_operand" "") | |
354 (mem:SI (plus:SI (match_dup 2) (const_int 76)))) | |
355 (set (match_operand:SI 23 "register_operand" "") | |
356 (mem:SI (plus:SI (match_dup 2) (const_int 80))))])] | |
357 "(XVECLEN (operands[0], 0) == 22)" | |
358 "lmw.bim\t%3, [%1], %23, 0x0" | |
359 [(set_attr "type" "load_multiple") | |
360 (set_attr "combo" "21") | |
361 (set_attr "length" "4")] | |
362 ) | |
363 | |
364 (define_insn "*lmw_bim_si20" | |
365 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
366 [(set (match_operand:SI 1 "register_operand" "=r") | |
367 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 80))) | |
368 (set (match_operand:SI 3 "register_operand" "") | |
369 (mem:SI (match_dup 2))) | |
370 (set (match_operand:SI 4 "register_operand" "") | |
371 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
372 (set (match_operand:SI 5 "register_operand" "") | |
373 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
374 (set (match_operand:SI 6 "register_operand" "") | |
375 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
376 (set (match_operand:SI 7 "register_operand" "") | |
377 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
378 (set (match_operand:SI 8 "register_operand" "") | |
379 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
380 (set (match_operand:SI 9 "register_operand" "") | |
381 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
382 (set (match_operand:SI 10 "register_operand" "") | |
383 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
384 (set (match_operand:SI 11 "register_operand" "") | |
385 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
386 (set (match_operand:SI 12 "register_operand" "") | |
387 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
388 (set (match_operand:SI 13 "register_operand" "") | |
389 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
390 (set (match_operand:SI 14 "register_operand" "") | |
391 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
392 (set (match_operand:SI 15 "register_operand" "") | |
393 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
394 (set (match_operand:SI 16 "register_operand" "") | |
395 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
396 (set (match_operand:SI 17 "register_operand" "") | |
397 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
398 (set (match_operand:SI 18 "register_operand" "") | |
399 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
400 (set (match_operand:SI 19 "register_operand" "") | |
401 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
402 (set (match_operand:SI 20 "register_operand" "") | |
403 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
404 (set (match_operand:SI 21 "register_operand" "") | |
405 (mem:SI (plus:SI (match_dup 2) (const_int 72)))) | |
406 (set (match_operand:SI 22 "register_operand" "") | |
407 (mem:SI (plus:SI (match_dup 2) (const_int 76))))])] | |
408 "(XVECLEN (operands[0], 0) == 21)" | |
409 "lmw.bim\t%3, [%1], %22, 0x0" | |
410 [(set_attr "type" "load_multiple") | |
411 (set_attr "combo" "20") | |
412 (set_attr "length" "4")] | |
413 ) | |
414 | |
415 (define_insn "*lmw_bim_si19" | |
416 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
417 [(set (match_operand:SI 1 "register_operand" "=r") | |
418 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 76))) | |
419 (set (match_operand:SI 3 "register_operand" "") | |
420 (mem:SI (match_dup 2))) | |
421 (set (match_operand:SI 4 "register_operand" "") | |
422 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
423 (set (match_operand:SI 5 "register_operand" "") | |
424 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
425 (set (match_operand:SI 6 "register_operand" "") | |
426 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
427 (set (match_operand:SI 7 "register_operand" "") | |
428 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
429 (set (match_operand:SI 8 "register_operand" "") | |
430 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
431 (set (match_operand:SI 9 "register_operand" "") | |
432 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
433 (set (match_operand:SI 10 "register_operand" "") | |
434 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
435 (set (match_operand:SI 11 "register_operand" "") | |
436 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
437 (set (match_operand:SI 12 "register_operand" "") | |
438 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
439 (set (match_operand:SI 13 "register_operand" "") | |
440 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
441 (set (match_operand:SI 14 "register_operand" "") | |
442 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
443 (set (match_operand:SI 15 "register_operand" "") | |
444 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
445 (set (match_operand:SI 16 "register_operand" "") | |
446 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
447 (set (match_operand:SI 17 "register_operand" "") | |
448 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
449 (set (match_operand:SI 18 "register_operand" "") | |
450 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
451 (set (match_operand:SI 19 "register_operand" "") | |
452 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
453 (set (match_operand:SI 20 "register_operand" "") | |
454 (mem:SI (plus:SI (match_dup 2) (const_int 68)))) | |
455 (set (match_operand:SI 21 "register_operand" "") | |
456 (mem:SI (plus:SI (match_dup 2) (const_int 72))))])] | |
457 "(XVECLEN (operands[0], 0) == 20)" | |
458 "lmw.bim\t%3, [%1], %21, 0x0" | |
459 [(set_attr "type" "load_multiple") | |
460 (set_attr "combo" "19") | |
461 (set_attr "length" "4")] | |
462 ) | |
463 | |
464 (define_insn "*lmw_bim_si18" | |
465 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
466 [(set (match_operand:SI 1 "register_operand" "=r") | |
467 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 72))) | |
468 (set (match_operand:SI 3 "register_operand" "") | |
469 (mem:SI (match_dup 2))) | |
470 (set (match_operand:SI 4 "register_operand" "") | |
471 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
472 (set (match_operand:SI 5 "register_operand" "") | |
473 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
474 (set (match_operand:SI 6 "register_operand" "") | |
475 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
476 (set (match_operand:SI 7 "register_operand" "") | |
477 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
478 (set (match_operand:SI 8 "register_operand" "") | |
479 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
480 (set (match_operand:SI 9 "register_operand" "") | |
481 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
482 (set (match_operand:SI 10 "register_operand" "") | |
483 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
484 (set (match_operand:SI 11 "register_operand" "") | |
485 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
486 (set (match_operand:SI 12 "register_operand" "") | |
487 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
488 (set (match_operand:SI 13 "register_operand" "") | |
489 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
490 (set (match_operand:SI 14 "register_operand" "") | |
491 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
492 (set (match_operand:SI 15 "register_operand" "") | |
493 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
494 (set (match_operand:SI 16 "register_operand" "") | |
495 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
496 (set (match_operand:SI 17 "register_operand" "") | |
497 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
498 (set (match_operand:SI 18 "register_operand" "") | |
499 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
500 (set (match_operand:SI 19 "register_operand" "") | |
501 (mem:SI (plus:SI (match_dup 2) (const_int 64)))) | |
502 (set (match_operand:SI 20 "register_operand" "") | |
503 (mem:SI (plus:SI (match_dup 2) (const_int 68))))])] | |
504 "(XVECLEN (operands[0], 0) == 19)" | |
505 "lmw.bim\t%3, [%1], %20, 0x0" | |
506 [(set_attr "type" "load_multiple") | |
507 (set_attr "combo" "18") | |
508 (set_attr "length" "4")] | |
509 ) | |
510 | |
511 (define_insn "*lmw_bim_si17" | |
512 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
513 [(set (match_operand:SI 1 "register_operand" "=r") | |
514 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 68))) | |
515 (set (match_operand:SI 3 "register_operand" "") | |
516 (mem:SI (match_dup 2))) | |
517 (set (match_operand:SI 4 "register_operand" "") | |
518 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
519 (set (match_operand:SI 5 "register_operand" "") | |
520 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
521 (set (match_operand:SI 6 "register_operand" "") | |
522 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
523 (set (match_operand:SI 7 "register_operand" "") | |
524 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
525 (set (match_operand:SI 8 "register_operand" "") | |
526 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
527 (set (match_operand:SI 9 "register_operand" "") | |
528 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
529 (set (match_operand:SI 10 "register_operand" "") | |
530 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
531 (set (match_operand:SI 11 "register_operand" "") | |
532 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
533 (set (match_operand:SI 12 "register_operand" "") | |
534 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
535 (set (match_operand:SI 13 "register_operand" "") | |
536 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
537 (set (match_operand:SI 14 "register_operand" "") | |
538 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
539 (set (match_operand:SI 15 "register_operand" "") | |
540 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
541 (set (match_operand:SI 16 "register_operand" "") | |
542 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
543 (set (match_operand:SI 17 "register_operand" "") | |
544 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
545 (set (match_operand:SI 18 "register_operand" "") | |
546 (mem:SI (plus:SI (match_dup 2) (const_int 60)))) | |
547 (set (match_operand:SI 19 "register_operand" "") | |
548 (mem:SI (plus:SI (match_dup 2) (const_int 64))))])] | |
549 "(XVECLEN (operands[0], 0) == 18)" | |
550 "lmw.bim\t%3, [%1], %19, 0x0" | |
551 [(set_attr "type" "load_multiple") | |
552 (set_attr "combo" "17") | |
553 (set_attr "length" "4")] | |
554 ) | |
555 | |
556 (define_insn "*lmw_bim_si16" | |
557 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
558 [(set (match_operand:SI 1 "register_operand" "=r") | |
559 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 64))) | |
560 (set (match_operand:SI 3 "register_operand" "") | |
561 (mem:SI (match_dup 2))) | |
562 (set (match_operand:SI 4 "register_operand" "") | |
563 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
564 (set (match_operand:SI 5 "register_operand" "") | |
565 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
566 (set (match_operand:SI 6 "register_operand" "") | |
567 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
568 (set (match_operand:SI 7 "register_operand" "") | |
569 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
570 (set (match_operand:SI 8 "register_operand" "") | |
571 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
572 (set (match_operand:SI 9 "register_operand" "") | |
573 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
574 (set (match_operand:SI 10 "register_operand" "") | |
575 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
576 (set (match_operand:SI 11 "register_operand" "") | |
577 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
578 (set (match_operand:SI 12 "register_operand" "") | |
579 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
580 (set (match_operand:SI 13 "register_operand" "") | |
581 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
582 (set (match_operand:SI 14 "register_operand" "") | |
583 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
584 (set (match_operand:SI 15 "register_operand" "") | |
585 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
586 (set (match_operand:SI 16 "register_operand" "") | |
587 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
588 (set (match_operand:SI 17 "register_operand" "") | |
589 (mem:SI (plus:SI (match_dup 2) (const_int 56)))) | |
590 (set (match_operand:SI 18 "register_operand" "") | |
591 (mem:SI (plus:SI (match_dup 2) (const_int 60))))])] | |
592 "(XVECLEN (operands[0], 0) == 17)" | |
593 "lmw.bim\t%3, [%1], %18, 0x0" | |
594 [(set_attr "type" "load_multiple") | |
595 (set_attr "combo" "16") | |
596 (set_attr "length" "4")] | |
597 ) | |
598 | |
599 (define_insn "*lmw_bim_si15" | |
600 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
601 [(set (match_operand:SI 1 "register_operand" "=r") | |
602 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 60))) | |
603 (set (match_operand:SI 3 "register_operand" "") | |
604 (mem:SI (match_dup 2))) | |
605 (set (match_operand:SI 4 "register_operand" "") | |
606 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
607 (set (match_operand:SI 5 "register_operand" "") | |
608 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
609 (set (match_operand:SI 6 "register_operand" "") | |
610 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
611 (set (match_operand:SI 7 "register_operand" "") | |
612 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
613 (set (match_operand:SI 8 "register_operand" "") | |
614 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
615 (set (match_operand:SI 9 "register_operand" "") | |
616 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
617 (set (match_operand:SI 10 "register_operand" "") | |
618 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
619 (set (match_operand:SI 11 "register_operand" "") | |
620 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
621 (set (match_operand:SI 12 "register_operand" "") | |
622 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
623 (set (match_operand:SI 13 "register_operand" "") | |
624 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
625 (set (match_operand:SI 14 "register_operand" "") | |
626 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
627 (set (match_operand:SI 15 "register_operand" "") | |
628 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
629 (set (match_operand:SI 16 "register_operand" "") | |
630 (mem:SI (plus:SI (match_dup 2) (const_int 52)))) | |
631 (set (match_operand:SI 17 "register_operand" "") | |
632 (mem:SI (plus:SI (match_dup 2) (const_int 56))))])] | |
633 "(XVECLEN (operands[0], 0) == 16)" | |
634 "lmw.bim\t%3, [%1], %17, 0x0" | |
635 [(set_attr "type" "load_multiple") | |
636 (set_attr "combo" "15") | |
637 (set_attr "length" "4")] | |
638 ) | |
639 | |
640 (define_insn "*lmw_bim_si14" | |
641 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
642 [(set (match_operand:SI 1 "register_operand" "=r") | |
643 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 56))) | |
644 (set (match_operand:SI 3 "register_operand" "") | |
645 (mem:SI (match_dup 2))) | |
646 (set (match_operand:SI 4 "register_operand" "") | |
647 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
648 (set (match_operand:SI 5 "register_operand" "") | |
649 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
650 (set (match_operand:SI 6 "register_operand" "") | |
651 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
652 (set (match_operand:SI 7 "register_operand" "") | |
653 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
654 (set (match_operand:SI 8 "register_operand" "") | |
655 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
656 (set (match_operand:SI 9 "register_operand" "") | |
657 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
658 (set (match_operand:SI 10 "register_operand" "") | |
659 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
660 (set (match_operand:SI 11 "register_operand" "") | |
661 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
662 (set (match_operand:SI 12 "register_operand" "") | |
663 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
664 (set (match_operand:SI 13 "register_operand" "") | |
665 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
666 (set (match_operand:SI 14 "register_operand" "") | |
667 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
668 (set (match_operand:SI 15 "register_operand" "") | |
669 (mem:SI (plus:SI (match_dup 2) (const_int 48)))) | |
670 (set (match_operand:SI 16 "register_operand" "") | |
671 (mem:SI (plus:SI (match_dup 2) (const_int 52))))])] | |
672 "(XVECLEN (operands[0], 0) == 15)" | |
673 "lmw.bim\t%3, [%1], %16, 0x0" | |
674 [(set_attr "type" "load_multiple") | |
675 (set_attr "combo" "14") | |
676 (set_attr "length" "4")] | |
677 ) | |
678 | |
679 (define_insn "*lmw_bim_si13" | |
680 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
681 [(set (match_operand:SI 1 "register_operand" "=r") | |
682 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 52))) | |
683 (set (match_operand:SI 3 "register_operand" "") | |
684 (mem:SI (match_dup 2))) | |
685 (set (match_operand:SI 4 "register_operand" "") | |
686 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
687 (set (match_operand:SI 5 "register_operand" "") | |
688 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
689 (set (match_operand:SI 6 "register_operand" "") | |
690 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
691 (set (match_operand:SI 7 "register_operand" "") | |
692 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
693 (set (match_operand:SI 8 "register_operand" "") | |
694 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
695 (set (match_operand:SI 9 "register_operand" "") | |
696 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
697 (set (match_operand:SI 10 "register_operand" "") | |
698 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
699 (set (match_operand:SI 11 "register_operand" "") | |
700 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
701 (set (match_operand:SI 12 "register_operand" "") | |
702 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
703 (set (match_operand:SI 13 "register_operand" "") | |
704 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
705 (set (match_operand:SI 14 "register_operand" "") | |
706 (mem:SI (plus:SI (match_dup 2) (const_int 44)))) | |
707 (set (match_operand:SI 15 "register_operand" "") | |
708 (mem:SI (plus:SI (match_dup 2) (const_int 48))))])] | |
709 "(XVECLEN (operands[0], 0) == 14)" | |
710 "lmw.bim\t%3, [%1], %15, 0x0" | |
711 [(set_attr "type" "load_multiple") | |
712 (set_attr "combo" "13") | |
713 (set_attr "length" "4")] | |
714 ) | |
715 | |
716 (define_insn "*lmw_bim_si12" | |
717 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
718 [(set (match_operand:SI 1 "register_operand" "=r") | |
719 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 48))) | |
720 (set (match_operand:SI 3 "register_operand" "") | |
721 (mem:SI (match_dup 2))) | |
722 (set (match_operand:SI 4 "register_operand" "") | |
723 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
724 (set (match_operand:SI 5 "register_operand" "") | |
725 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
726 (set (match_operand:SI 6 "register_operand" "") | |
727 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
728 (set (match_operand:SI 7 "register_operand" "") | |
729 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
730 (set (match_operand:SI 8 "register_operand" "") | |
731 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
732 (set (match_operand:SI 9 "register_operand" "") | |
733 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
734 (set (match_operand:SI 10 "register_operand" "") | |
735 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
736 (set (match_operand:SI 11 "register_operand" "") | |
737 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
738 (set (match_operand:SI 12 "register_operand" "") | |
739 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
740 (set (match_operand:SI 13 "register_operand" "") | |
741 (mem:SI (plus:SI (match_dup 2) (const_int 40)))) | |
742 (set (match_operand:SI 14 "register_operand" "") | |
743 (mem:SI (plus:SI (match_dup 2) (const_int 44))))])] | |
744 "(XVECLEN (operands[0], 0) == 13)" | |
745 "lmw.bim\t%3, [%1], %14, 0x0" | |
746 [(set_attr "type" "load_multiple") | |
747 (set_attr "combo" "12") | |
748 (set_attr "length" "4")] | |
749 ) | |
750 | |
751 (define_insn "*lmw_bim_si11" | |
752 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
753 [(set (match_operand:SI 1 "register_operand" "=r") | |
754 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 44))) | |
755 (set (match_operand:SI 3 "register_operand" "") | |
756 (mem:SI (match_dup 2))) | |
757 (set (match_operand:SI 4 "register_operand" "") | |
758 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
759 (set (match_operand:SI 5 "register_operand" "") | |
760 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
761 (set (match_operand:SI 6 "register_operand" "") | |
762 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
763 (set (match_operand:SI 7 "register_operand" "") | |
764 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
765 (set (match_operand:SI 8 "register_operand" "") | |
766 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
767 (set (match_operand:SI 9 "register_operand" "") | |
768 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
769 (set (match_operand:SI 10 "register_operand" "") | |
770 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
771 (set (match_operand:SI 11 "register_operand" "") | |
772 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
773 (set (match_operand:SI 12 "register_operand" "") | |
774 (mem:SI (plus:SI (match_dup 2) (const_int 36)))) | |
775 (set (match_operand:SI 13 "register_operand" "") | |
776 (mem:SI (plus:SI (match_dup 2) (const_int 40))))])] | |
777 "(XVECLEN (operands[0], 0) == 12)" | |
778 "lmw.bim\t%3, [%1], %13, 0x0" | |
779 [(set_attr "type" "load_multiple") | |
780 (set_attr "combo" "11") | |
781 (set_attr "length" "4")] | |
782 ) | |
783 | |
784 (define_insn "*lmw_bim_si10" | |
785 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
786 [(set (match_operand:SI 1 "register_operand" "=r") | |
787 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40))) | |
788 (set (match_operand:SI 3 "register_operand" "") | |
789 (mem:SI (match_dup 2))) | |
790 (set (match_operand:SI 4 "register_operand" "") | |
791 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
792 (set (match_operand:SI 5 "register_operand" "") | |
793 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
794 (set (match_operand:SI 6 "register_operand" "") | |
795 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
796 (set (match_operand:SI 7 "register_operand" "") | |
797 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
798 (set (match_operand:SI 8 "register_operand" "") | |
799 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
800 (set (match_operand:SI 9 "register_operand" "") | |
801 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
802 (set (match_operand:SI 10 "register_operand" "") | |
803 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
804 (set (match_operand:SI 11 "register_operand" "") | |
805 (mem:SI (plus:SI (match_dup 2) (const_int 32)))) | |
806 (set (match_operand:SI 12 "register_operand" "") | |
807 (mem:SI (plus:SI (match_dup 2) (const_int 36))))])] | |
808 "(XVECLEN (operands[0], 0) == 11)" | |
809 "lmw.bim\t%3, [%1], %12, 0x0" | |
810 [(set_attr "type" "load_multiple") | |
811 (set_attr "combo" "10") | |
812 (set_attr "length" "4")] | |
813 ) | |
814 | |
815 (define_insn "*lmw_bim_si9" | |
816 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
817 [(set (match_operand:SI 1 "register_operand" "=r") | |
818 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36))) | |
819 (set (match_operand:SI 3 "register_operand" "") | |
820 (mem:SI (match_dup 2))) | |
821 (set (match_operand:SI 4 "register_operand" "") | |
822 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
823 (set (match_operand:SI 5 "register_operand" "") | |
824 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
825 (set (match_operand:SI 6 "register_operand" "") | |
826 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
827 (set (match_operand:SI 7 "register_operand" "") | |
828 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
829 (set (match_operand:SI 8 "register_operand" "") | |
830 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
831 (set (match_operand:SI 9 "register_operand" "") | |
832 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
833 (set (match_operand:SI 10 "register_operand" "") | |
834 (mem:SI (plus:SI (match_dup 2) (const_int 28)))) | |
835 (set (match_operand:SI 11 "register_operand" "") | |
836 (mem:SI (plus:SI (match_dup 2) (const_int 32))))])] | |
837 "(XVECLEN (operands[0], 0) == 10)" | |
838 "lmw.bim\t%3, [%1], %11, 0x0" | |
839 [(set_attr "type" "load_multiple") | |
840 (set_attr "combo" "9") | |
841 (set_attr "length" "4")] | |
842 ) | |
843 | |
844 (define_insn "*lmw_bim_si8" | |
845 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
846 [(set (match_operand:SI 1 "register_operand" "=r") | |
847 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32))) | |
848 (set (match_operand:SI 3 "register_operand" "") | |
849 (mem:SI (match_dup 2))) | |
850 (set (match_operand:SI 4 "register_operand" "") | |
851 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
852 (set (match_operand:SI 5 "register_operand" "") | |
853 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
854 (set (match_operand:SI 6 "register_operand" "") | |
855 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
856 (set (match_operand:SI 7 "register_operand" "") | |
857 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
858 (set (match_operand:SI 8 "register_operand" "") | |
859 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
860 (set (match_operand:SI 9 "register_operand" "") | |
861 (mem:SI (plus:SI (match_dup 2) (const_int 24)))) | |
862 (set (match_operand:SI 10 "register_operand" "") | |
863 (mem:SI (plus:SI (match_dup 2) (const_int 28))))])] | |
864 "(XVECLEN (operands[0], 0) == 9)" | |
865 "lmw.bim\t%3, [%1], %10, 0x0" | |
866 [(set_attr "type" "load_multiple") | |
867 (set_attr "combo" "8") | |
868 (set_attr "length" "4")] | |
869 ) | |
870 | |
871 (define_insn "*lmw_bim_si7" | |
872 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
873 [(set (match_operand:SI 1 "register_operand" "=r") | |
874 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28))) | |
875 (set (match_operand:SI 3 "register_operand" "") | |
876 (mem:SI (match_dup 2))) | |
877 (set (match_operand:SI 4 "register_operand" "") | |
878 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
879 (set (match_operand:SI 5 "register_operand" "") | |
880 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
881 (set (match_operand:SI 6 "register_operand" "") | |
882 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
883 (set (match_operand:SI 7 "register_operand" "") | |
884 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
885 (set (match_operand:SI 8 "register_operand" "") | |
886 (mem:SI (plus:SI (match_dup 2) (const_int 20)))) | |
887 (set (match_operand:SI 9 "register_operand" "") | |
888 (mem:SI (plus:SI (match_dup 2) (const_int 24))))])] | |
889 "(XVECLEN (operands[0], 0) == 8)" | |
890 "lmw.bim\t%3, [%1], %9, 0x0" | |
891 [(set_attr "type" "load_multiple") | |
892 (set_attr "combo" "7") | |
893 (set_attr "length" "4")] | |
894 ) | |
895 | |
896 (define_insn "*lmw_bim_si6" | |
897 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
898 [(set (match_operand:SI 1 "register_operand" "=r") | |
899 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24))) | |
900 (set (match_operand:SI 3 "register_operand" "") | |
901 (mem:SI (match_dup 2))) | |
902 (set (match_operand:SI 4 "register_operand" "") | |
903 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
904 (set (match_operand:SI 5 "register_operand" "") | |
905 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
906 (set (match_operand:SI 6 "register_operand" "") | |
907 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
908 (set (match_operand:SI 7 "register_operand" "") | |
909 (mem:SI (plus:SI (match_dup 2) (const_int 16)))) | |
910 (set (match_operand:SI 8 "register_operand" "") | |
911 (mem:SI (plus:SI (match_dup 2) (const_int 20))))])] | |
912 "(XVECLEN (operands[0], 0) == 7)" | |
913 "lmw.bim\t%3, [%1], %8, 0x0" | |
914 [(set_attr "type" "load_multiple") | |
915 (set_attr "combo" "6") | |
916 (set_attr "length" "4")] | |
917 ) | |
918 | |
919 (define_insn "*lmw_bim_si5" | |
920 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
921 [(set (match_operand:SI 1 "register_operand" "=r") | |
922 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20))) | |
923 (set (match_operand:SI 3 "register_operand" "") | |
924 (mem:SI (match_dup 2))) | |
925 (set (match_operand:SI 4 "register_operand" "") | |
926 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
927 (set (match_operand:SI 5 "register_operand" "") | |
928 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
929 (set (match_operand:SI 6 "register_operand" "") | |
930 (mem:SI (plus:SI (match_dup 2) (const_int 12)))) | |
931 (set (match_operand:SI 7 "register_operand" "") | |
932 (mem:SI (plus:SI (match_dup 2) (const_int 16))))])] | |
933 "(XVECLEN (operands[0], 0) == 6)" | |
934 "lmw.bim\t%3, [%1], %7, 0x0" | |
935 [(set_attr "type" "load_multiple") | |
936 (set_attr "combo" "5") | |
937 (set_attr "length" "4")] | |
938 ) | |
939 | |
940 (define_insn "*lmw_bim_si4" | |
941 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
942 [(set (match_operand:SI 1 "register_operand" "=r") | |
943 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16))) | |
944 (set (match_operand:SI 3 "register_operand" "") | |
945 (mem:SI (match_dup 2))) | |
946 (set (match_operand:SI 4 "register_operand" "") | |
947 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
948 (set (match_operand:SI 5 "register_operand" "") | |
949 (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | |
950 (set (match_operand:SI 6 "register_operand" "") | |
951 (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] | |
952 "(XVECLEN (operands[0], 0) == 5)" | |
953 "lmw.bim\t%3, [%1], %6, 0x0" | |
954 [(set_attr "type" "load_multiple") | |
955 (set_attr "combo" "4") | |
956 (set_attr "length" "4")] | |
957 ) | |
958 | |
959 (define_insn "*lmw_bim_si3" | |
960 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
961 [(set (match_operand:SI 1 "register_operand" "=r") | |
962 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12))) | |
963 (set (match_operand:SI 3 "register_operand" "") | |
964 (mem:SI (match_dup 2))) | |
965 (set (match_operand:SI 4 "register_operand" "") | |
966 (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | |
967 (set (match_operand:SI 5 "register_operand" "") | |
968 (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] | |
969 "(XVECLEN (operands[0], 0) == 4)" | |
970 "lmw.bim\t%3, [%1], %5, 0x0" | |
971 [(set_attr "type" "load_multiple") | |
972 (set_attr "combo" "3") | |
973 (set_attr "length" "4")] | |
974 ) | |
975 | |
976 (define_insn "*lmw_bim_si2" | |
977 [(match_parallel 0 "nds32_load_multiple_and_update_address_operation" | |
978 [(set (match_operand:SI 1 "register_operand" "=r") | |
979 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8))) | |
980 (set (match_operand:SI 3 "register_operand" "") | |
981 (mem:SI (match_dup 2))) | |
982 (set (match_operand:SI 4 "register_operand" "") | |
983 (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] | |
984 "(XVECLEN (operands[0], 0) == 3)" | |
985 "lmw.bim\t%3, [%1], %4, 0x0" | |
986 [(set_attr "type" "load_multiple") | |
987 (set_attr "combo" "2") | |
988 (set_attr "length" "4")] | |
989 ) | |
990 | |
991 (define_expand "unaligned_load_update_base_w" | |
992 [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
993 (plus:SI (match_operand:SI 2 "register_operand" "") (const_int 4))) | |
994 (set (match_operand:SI 1 "register_operand" "") | |
995 (unspec:SI [(mem:SI (match_dup 2))] UNSPEC_UALOAD_W))])] | |
996 "" | |
997 { | |
998 emit_insn (gen_unaligned_load_w (operands[1], gen_rtx_MEM (SImode, operands[2]))); | |
999 emit_insn (gen_addsi3 (operands[0], operands[2], gen_int_mode (4, Pmode))); | |
1000 DONE; | |
1001 } | |
1002 [(set_attr "type" "load_multiple") | |
1003 (set_attr "combo" "1") | |
1004 (set_attr "length" "4")] | |
1005 ) | |
1006 | |
1007 (define_insn "*lmwsi25" | |
1008 [(match_parallel 0 "nds32_load_multiple_operation" | |
1009 [(set (match_operand:SI 2 "register_operand" "") | |
1010 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1011 (set (match_operand:SI 3 "register_operand" "") | |
1012 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1013 (set (match_operand:SI 4 "register_operand" "") | |
1014 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1015 (set (match_operand:SI 5 "register_operand" "") | |
1016 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1017 (set (match_operand:SI 6 "register_operand" "") | |
1018 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1019 (set (match_operand:SI 7 "register_operand" "") | |
1020 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1021 (set (match_operand:SI 8 "register_operand" "") | |
1022 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1023 (set (match_operand:SI 9 "register_operand" "") | |
1024 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1025 (set (match_operand:SI 10 "register_operand" "") | |
1026 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1027 (set (match_operand:SI 11 "register_operand" "") | |
1028 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1029 (set (match_operand:SI 12 "register_operand" "") | |
1030 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1031 (set (match_operand:SI 13 "register_operand" "") | |
1032 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1033 (set (match_operand:SI 14 "register_operand" "") | |
1034 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1035 (set (match_operand:SI 15 "register_operand" "") | |
1036 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1037 (set (match_operand:SI 16 "register_operand" "") | |
1038 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1039 (set (match_operand:SI 17 "register_operand" "") | |
1040 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1041 (set (match_operand:SI 18 "register_operand" "") | |
1042 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1043 (set (match_operand:SI 19 "register_operand" "") | |
1044 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1045 (set (match_operand:SI 20 "register_operand" "") | |
1046 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1047 (set (match_operand:SI 21 "register_operand" "") | |
1048 (mem:SI (plus:SI (match_dup 1) (const_int 76)))) | |
1049 (set (match_operand:SI 22 "register_operand" "") | |
1050 (mem:SI (plus:SI (match_dup 1) (const_int 80)))) | |
1051 (set (match_operand:SI 23 "register_operand" "") | |
1052 (mem:SI (plus:SI (match_dup 1) (const_int 84)))) | |
1053 (set (match_operand:SI 24 "register_operand" "") | |
1054 (mem:SI (plus:SI (match_dup 1) (const_int 88)))) | |
1055 (set (match_operand:SI 25 "register_operand" "") | |
1056 (mem:SI (plus:SI (match_dup 1) (const_int 92)))) | |
1057 (set (match_operand:SI 26 "register_operand" "") | |
1058 (mem:SI (plus:SI (match_dup 1) (const_int 96))))])] | |
1059 "(XVECLEN (operands[0], 0) == 25)" | |
1060 "lmw.bi\t%2, [%1], %26, 0x0" | |
1061 [(set_attr "type" "load_multiple") | |
1062 (set_attr "combo" "25") | |
1063 (set_attr "length" "4")] | |
1064 ) | |
1065 | |
1066 (define_insn "*lmwsi24" | |
1067 [(match_parallel 0 "nds32_load_multiple_operation" | |
1068 [(set (match_operand:SI 2 "register_operand" "") | |
1069 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1070 (set (match_operand:SI 3 "register_operand" "") | |
1071 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1072 (set (match_operand:SI 4 "register_operand" "") | |
1073 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1074 (set (match_operand:SI 5 "register_operand" "") | |
1075 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1076 (set (match_operand:SI 6 "register_operand" "") | |
1077 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1078 (set (match_operand:SI 7 "register_operand" "") | |
1079 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1080 (set (match_operand:SI 8 "register_operand" "") | |
1081 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1082 (set (match_operand:SI 9 "register_operand" "") | |
1083 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1084 (set (match_operand:SI 10 "register_operand" "") | |
1085 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1086 (set (match_operand:SI 11 "register_operand" "") | |
1087 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1088 (set (match_operand:SI 12 "register_operand" "") | |
1089 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1090 (set (match_operand:SI 13 "register_operand" "") | |
1091 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1092 (set (match_operand:SI 14 "register_operand" "") | |
1093 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1094 (set (match_operand:SI 15 "register_operand" "") | |
1095 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1096 (set (match_operand:SI 16 "register_operand" "") | |
1097 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1098 (set (match_operand:SI 17 "register_operand" "") | |
1099 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1100 (set (match_operand:SI 18 "register_operand" "") | |
1101 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1102 (set (match_operand:SI 19 "register_operand" "") | |
1103 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1104 (set (match_operand:SI 20 "register_operand" "") | |
1105 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1106 (set (match_operand:SI 21 "register_operand" "") | |
1107 (mem:SI (plus:SI (match_dup 1) (const_int 76)))) | |
1108 (set (match_operand:SI 22 "register_operand" "") | |
1109 (mem:SI (plus:SI (match_dup 1) (const_int 80)))) | |
1110 (set (match_operand:SI 23 "register_operand" "") | |
1111 (mem:SI (plus:SI (match_dup 1) (const_int 84)))) | |
1112 (set (match_operand:SI 24 "register_operand" "") | |
1113 (mem:SI (plus:SI (match_dup 1) (const_int 88)))) | |
1114 (set (match_operand:SI 25 "register_operand" "") | |
1115 (mem:SI (plus:SI (match_dup 1) (const_int 92))))])] | |
1116 "(XVECLEN (operands[0], 0) == 24)" | |
1117 "lmw.bi\t%2, [%1], %25, 0x0" | |
1118 [(set_attr "type" "load_multiple") | |
1119 (set_attr "combo" "24") | |
1120 (set_attr "length" "4")] | |
1121 ) | |
1122 | |
1123 (define_insn "*lmwsi23" | |
1124 [(match_parallel 0 "nds32_load_multiple_operation" | |
1125 [(set (match_operand:SI 2 "register_operand" "") | |
1126 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1127 (set (match_operand:SI 3 "register_operand" "") | |
1128 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1129 (set (match_operand:SI 4 "register_operand" "") | |
1130 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1131 (set (match_operand:SI 5 "register_operand" "") | |
1132 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1133 (set (match_operand:SI 6 "register_operand" "") | |
1134 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1135 (set (match_operand:SI 7 "register_operand" "") | |
1136 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1137 (set (match_operand:SI 8 "register_operand" "") | |
1138 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1139 (set (match_operand:SI 9 "register_operand" "") | |
1140 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1141 (set (match_operand:SI 10 "register_operand" "") | |
1142 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1143 (set (match_operand:SI 11 "register_operand" "") | |
1144 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1145 (set (match_operand:SI 12 "register_operand" "") | |
1146 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1147 (set (match_operand:SI 13 "register_operand" "") | |
1148 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1149 (set (match_operand:SI 14 "register_operand" "") | |
1150 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1151 (set (match_operand:SI 15 "register_operand" "") | |
1152 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1153 (set (match_operand:SI 16 "register_operand" "") | |
1154 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1155 (set (match_operand:SI 17 "register_operand" "") | |
1156 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1157 (set (match_operand:SI 18 "register_operand" "") | |
1158 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1159 (set (match_operand:SI 19 "register_operand" "") | |
1160 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1161 (set (match_operand:SI 20 "register_operand" "") | |
1162 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1163 (set (match_operand:SI 21 "register_operand" "") | |
1164 (mem:SI (plus:SI (match_dup 1) (const_int 76)))) | |
1165 (set (match_operand:SI 22 "register_operand" "") | |
1166 (mem:SI (plus:SI (match_dup 1) (const_int 80)))) | |
1167 (set (match_operand:SI 23 "register_operand" "") | |
1168 (mem:SI (plus:SI (match_dup 1) (const_int 84)))) | |
1169 (set (match_operand:SI 24 "register_operand" "") | |
1170 (mem:SI (plus:SI (match_dup 1) (const_int 88))))])] | |
1171 "(XVECLEN (operands[0], 0) == 23)" | |
1172 "lmw.bi\t%2, [%1], %24, 0x0" | |
1173 [(set_attr "type" "load_multiple") | |
1174 (set_attr "combo" "23") | |
1175 (set_attr "length" "4")] | |
1176 ) | |
1177 | |
1178 (define_insn "*lmwsi22" | |
1179 [(match_parallel 0 "nds32_load_multiple_operation" | |
1180 [(set (match_operand:SI 2 "register_operand" "") | |
1181 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1182 (set (match_operand:SI 3 "register_operand" "") | |
1183 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1184 (set (match_operand:SI 4 "register_operand" "") | |
1185 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1186 (set (match_operand:SI 5 "register_operand" "") | |
1187 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1188 (set (match_operand:SI 6 "register_operand" "") | |
1189 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1190 (set (match_operand:SI 7 "register_operand" "") | |
1191 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1192 (set (match_operand:SI 8 "register_operand" "") | |
1193 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1194 (set (match_operand:SI 9 "register_operand" "") | |
1195 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1196 (set (match_operand:SI 10 "register_operand" "") | |
1197 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1198 (set (match_operand:SI 11 "register_operand" "") | |
1199 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1200 (set (match_operand:SI 12 "register_operand" "") | |
1201 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1202 (set (match_operand:SI 13 "register_operand" "") | |
1203 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1204 (set (match_operand:SI 14 "register_operand" "") | |
1205 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1206 (set (match_operand:SI 15 "register_operand" "") | |
1207 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1208 (set (match_operand:SI 16 "register_operand" "") | |
1209 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1210 (set (match_operand:SI 17 "register_operand" "") | |
1211 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1212 (set (match_operand:SI 18 "register_operand" "") | |
1213 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1214 (set (match_operand:SI 19 "register_operand" "") | |
1215 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1216 (set (match_operand:SI 20 "register_operand" "") | |
1217 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1218 (set (match_operand:SI 21 "register_operand" "") | |
1219 (mem:SI (plus:SI (match_dup 1) (const_int 76)))) | |
1220 (set (match_operand:SI 22 "register_operand" "") | |
1221 (mem:SI (plus:SI (match_dup 1) (const_int 80)))) | |
1222 (set (match_operand:SI 23 "register_operand" "") | |
1223 (mem:SI (plus:SI (match_dup 1) (const_int 84))))])] | |
1224 "(XVECLEN (operands[0], 0) == 22)" | |
1225 "lmw.bi\t%2, [%1], %23, 0x0" | |
1226 [(set_attr "type" "load_multiple") | |
1227 (set_attr "combo" "22") | |
1228 (set_attr "length" "4")] | |
1229 ) | |
1230 | |
1231 (define_insn "*lmwsi21" | |
1232 [(match_parallel 0 "nds32_load_multiple_operation" | |
1233 [(set (match_operand:SI 2 "register_operand" "") | |
1234 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1235 (set (match_operand:SI 3 "register_operand" "") | |
1236 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1237 (set (match_operand:SI 4 "register_operand" "") | |
1238 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1239 (set (match_operand:SI 5 "register_operand" "") | |
1240 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1241 (set (match_operand:SI 6 "register_operand" "") | |
1242 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1243 (set (match_operand:SI 7 "register_operand" "") | |
1244 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1245 (set (match_operand:SI 8 "register_operand" "") | |
1246 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1247 (set (match_operand:SI 9 "register_operand" "") | |
1248 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1249 (set (match_operand:SI 10 "register_operand" "") | |
1250 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1251 (set (match_operand:SI 11 "register_operand" "") | |
1252 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1253 (set (match_operand:SI 12 "register_operand" "") | |
1254 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1255 (set (match_operand:SI 13 "register_operand" "") | |
1256 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1257 (set (match_operand:SI 14 "register_operand" "") | |
1258 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1259 (set (match_operand:SI 15 "register_operand" "") | |
1260 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1261 (set (match_operand:SI 16 "register_operand" "") | |
1262 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1263 (set (match_operand:SI 17 "register_operand" "") | |
1264 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1265 (set (match_operand:SI 18 "register_operand" "") | |
1266 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1267 (set (match_operand:SI 19 "register_operand" "") | |
1268 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1269 (set (match_operand:SI 20 "register_operand" "") | |
1270 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1271 (set (match_operand:SI 21 "register_operand" "") | |
1272 (mem:SI (plus:SI (match_dup 1) (const_int 76)))) | |
1273 (set (match_operand:SI 22 "register_operand" "") | |
1274 (mem:SI (plus:SI (match_dup 1) (const_int 80))))])] | |
1275 "(XVECLEN (operands[0], 0) == 21)" | |
1276 "lmw.bi\t%2, [%1], %22, 0x0" | |
1277 [(set_attr "type" "load_multiple") | |
1278 (set_attr "combo" "21") | |
1279 (set_attr "length" "4")] | |
1280 ) | |
1281 | |
1282 (define_insn "*lmwsi20" | |
1283 [(match_parallel 0 "nds32_load_multiple_operation" | |
1284 [(set (match_operand:SI 2 "register_operand" "") | |
1285 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1286 (set (match_operand:SI 3 "register_operand" "") | |
1287 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1288 (set (match_operand:SI 4 "register_operand" "") | |
1289 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1290 (set (match_operand:SI 5 "register_operand" "") | |
1291 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1292 (set (match_operand:SI 6 "register_operand" "") | |
1293 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1294 (set (match_operand:SI 7 "register_operand" "") | |
1295 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1296 (set (match_operand:SI 8 "register_operand" "") | |
1297 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1298 (set (match_operand:SI 9 "register_operand" "") | |
1299 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1300 (set (match_operand:SI 10 "register_operand" "") | |
1301 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1302 (set (match_operand:SI 11 "register_operand" "") | |
1303 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1304 (set (match_operand:SI 12 "register_operand" "") | |
1305 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1306 (set (match_operand:SI 13 "register_operand" "") | |
1307 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1308 (set (match_operand:SI 14 "register_operand" "") | |
1309 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1310 (set (match_operand:SI 15 "register_operand" "") | |
1311 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1312 (set (match_operand:SI 16 "register_operand" "") | |
1313 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1314 (set (match_operand:SI 17 "register_operand" "") | |
1315 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1316 (set (match_operand:SI 18 "register_operand" "") | |
1317 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1318 (set (match_operand:SI 19 "register_operand" "") | |
1319 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1320 (set (match_operand:SI 20 "register_operand" "") | |
1321 (mem:SI (plus:SI (match_dup 1) (const_int 72)))) | |
1322 (set (match_operand:SI 21 "register_operand" "") | |
1323 (mem:SI (plus:SI (match_dup 1) (const_int 76))))])] | |
1324 "(XVECLEN (operands[0], 0) == 20)" | |
1325 "lmw.bi\t%2, [%1], %21, 0x0" | |
1326 [(set_attr "type" "load_multiple") | |
1327 (set_attr "combo" "20") | |
1328 (set_attr "length" "4")] | |
1329 ) | |
1330 | |
1331 (define_insn "*lmwsi19" | |
1332 [(match_parallel 0 "nds32_load_multiple_operation" | |
1333 [(set (match_operand:SI 2 "register_operand" "") | |
1334 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1335 (set (match_operand:SI 3 "register_operand" "") | |
1336 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1337 (set (match_operand:SI 4 "register_operand" "") | |
1338 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1339 (set (match_operand:SI 5 "register_operand" "") | |
1340 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1341 (set (match_operand:SI 6 "register_operand" "") | |
1342 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1343 (set (match_operand:SI 7 "register_operand" "") | |
1344 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1345 (set (match_operand:SI 8 "register_operand" "") | |
1346 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1347 (set (match_operand:SI 9 "register_operand" "") | |
1348 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1349 (set (match_operand:SI 10 "register_operand" "") | |
1350 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1351 (set (match_operand:SI 11 "register_operand" "") | |
1352 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1353 (set (match_operand:SI 12 "register_operand" "") | |
1354 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1355 (set (match_operand:SI 13 "register_operand" "") | |
1356 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1357 (set (match_operand:SI 14 "register_operand" "") | |
1358 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1359 (set (match_operand:SI 15 "register_operand" "") | |
1360 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1361 (set (match_operand:SI 16 "register_operand" "") | |
1362 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1363 (set (match_operand:SI 17 "register_operand" "") | |
1364 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1365 (set (match_operand:SI 18 "register_operand" "") | |
1366 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1367 (set (match_operand:SI 19 "register_operand" "") | |
1368 (mem:SI (plus:SI (match_dup 1) (const_int 68)))) | |
1369 (set (match_operand:SI 20 "register_operand" "") | |
1370 (mem:SI (plus:SI (match_dup 1) (const_int 72))))])] | |
1371 "(XVECLEN (operands[0], 0) == 19)" | |
1372 "lmw.bi\t%2, [%1], %20, 0x0" | |
1373 [(set_attr "type" "load_multiple") | |
1374 (set_attr "combo" "19") | |
1375 (set_attr "length" "4")] | |
1376 ) | |
1377 | |
1378 (define_insn "*lmwsi18" | |
1379 [(match_parallel 0 "nds32_load_multiple_operation" | |
1380 [(set (match_operand:SI 2 "register_operand" "") | |
1381 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1382 (set (match_operand:SI 3 "register_operand" "") | |
1383 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1384 (set (match_operand:SI 4 "register_operand" "") | |
1385 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1386 (set (match_operand:SI 5 "register_operand" "") | |
1387 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1388 (set (match_operand:SI 6 "register_operand" "") | |
1389 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1390 (set (match_operand:SI 7 "register_operand" "") | |
1391 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1392 (set (match_operand:SI 8 "register_operand" "") | |
1393 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1394 (set (match_operand:SI 9 "register_operand" "") | |
1395 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1396 (set (match_operand:SI 10 "register_operand" "") | |
1397 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1398 (set (match_operand:SI 11 "register_operand" "") | |
1399 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1400 (set (match_operand:SI 12 "register_operand" "") | |
1401 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1402 (set (match_operand:SI 13 "register_operand" "") | |
1403 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1404 (set (match_operand:SI 14 "register_operand" "") | |
1405 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1406 (set (match_operand:SI 15 "register_operand" "") | |
1407 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1408 (set (match_operand:SI 16 "register_operand" "") | |
1409 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1410 (set (match_operand:SI 17 "register_operand" "") | |
1411 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1412 (set (match_operand:SI 18 "register_operand" "") | |
1413 (mem:SI (plus:SI (match_dup 1) (const_int 64)))) | |
1414 (set (match_operand:SI 19 "register_operand" "") | |
1415 (mem:SI (plus:SI (match_dup 1) (const_int 68))))])] | |
1416 "(XVECLEN (operands[0], 0) == 18)" | |
1417 "lmw.bi\t%2, [%1], %19, 0x0" | |
1418 [(set_attr "type" "load_multiple") | |
1419 (set_attr "combo" "18") | |
1420 (set_attr "length" "4")] | |
1421 ) | |
1422 | |
1423 (define_insn "*lmwsi17" | |
1424 [(match_parallel 0 "nds32_load_multiple_operation" | |
1425 [(set (match_operand:SI 2 "register_operand" "") | |
1426 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1427 (set (match_operand:SI 3 "register_operand" "") | |
1428 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1429 (set (match_operand:SI 4 "register_operand" "") | |
1430 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1431 (set (match_operand:SI 5 "register_operand" "") | |
1432 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1433 (set (match_operand:SI 6 "register_operand" "") | |
1434 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1435 (set (match_operand:SI 7 "register_operand" "") | |
1436 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1437 (set (match_operand:SI 8 "register_operand" "") | |
1438 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1439 (set (match_operand:SI 9 "register_operand" "") | |
1440 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1441 (set (match_operand:SI 10 "register_operand" "") | |
1442 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1443 (set (match_operand:SI 11 "register_operand" "") | |
1444 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1445 (set (match_operand:SI 12 "register_operand" "") | |
1446 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1447 (set (match_operand:SI 13 "register_operand" "") | |
1448 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1449 (set (match_operand:SI 14 "register_operand" "") | |
1450 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1451 (set (match_operand:SI 15 "register_operand" "") | |
1452 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1453 (set (match_operand:SI 16 "register_operand" "") | |
1454 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1455 (set (match_operand:SI 17 "register_operand" "") | |
1456 (mem:SI (plus:SI (match_dup 1) (const_int 60)))) | |
1457 (set (match_operand:SI 18 "register_operand" "") | |
1458 (mem:SI (plus:SI (match_dup 1) (const_int 64))))])] | |
1459 "(XVECLEN (operands[0], 0) == 17)" | |
1460 "lmw.bi\t%2, [%1], %18, 0x0" | |
1461 [(set_attr "type" "load_multiple") | |
1462 (set_attr "combo" "17") | |
1463 (set_attr "length" "4")] | |
1464 ) | |
1465 | |
1466 (define_insn "*lmwsi16" | |
1467 [(match_parallel 0 "nds32_load_multiple_operation" | |
1468 [(set (match_operand:SI 2 "register_operand" "") | |
1469 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1470 (set (match_operand:SI 3 "register_operand" "") | |
1471 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1472 (set (match_operand:SI 4 "register_operand" "") | |
1473 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1474 (set (match_operand:SI 5 "register_operand" "") | |
1475 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1476 (set (match_operand:SI 6 "register_operand" "") | |
1477 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1478 (set (match_operand:SI 7 "register_operand" "") | |
1479 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1480 (set (match_operand:SI 8 "register_operand" "") | |
1481 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1482 (set (match_operand:SI 9 "register_operand" "") | |
1483 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1484 (set (match_operand:SI 10 "register_operand" "") | |
1485 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1486 (set (match_operand:SI 11 "register_operand" "") | |
1487 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1488 (set (match_operand:SI 12 "register_operand" "") | |
1489 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1490 (set (match_operand:SI 13 "register_operand" "") | |
1491 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1492 (set (match_operand:SI 14 "register_operand" "") | |
1493 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1494 (set (match_operand:SI 15 "register_operand" "") | |
1495 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1496 (set (match_operand:SI 16 "register_operand" "") | |
1497 (mem:SI (plus:SI (match_dup 1) (const_int 56)))) | |
1498 (set (match_operand:SI 17 "register_operand" "") | |
1499 (mem:SI (plus:SI (match_dup 1) (const_int 60))))])] | |
1500 "(XVECLEN (operands[0], 0) == 16)" | |
1501 "lmw.bi\t%2, [%1], %17, 0x0" | |
1502 [(set_attr "type" "load_multiple") | |
1503 (set_attr "combo" "16") | |
1504 (set_attr "length" "4")] | |
1505 ) | |
1506 | |
1507 (define_insn "*lmwsi15" | |
1508 [(match_parallel 0 "nds32_load_multiple_operation" | |
1509 [(set (match_operand:SI 2 "register_operand" "") | |
1510 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1511 (set (match_operand:SI 3 "register_operand" "") | |
1512 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1513 (set (match_operand:SI 4 "register_operand" "") | |
1514 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1515 (set (match_operand:SI 5 "register_operand" "") | |
1516 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1517 (set (match_operand:SI 6 "register_operand" "") | |
1518 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1519 (set (match_operand:SI 7 "register_operand" "") | |
1520 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1521 (set (match_operand:SI 8 "register_operand" "") | |
1522 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1523 (set (match_operand:SI 9 "register_operand" "") | |
1524 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1525 (set (match_operand:SI 10 "register_operand" "") | |
1526 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1527 (set (match_operand:SI 11 "register_operand" "") | |
1528 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1529 (set (match_operand:SI 12 "register_operand" "") | |
1530 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1531 (set (match_operand:SI 13 "register_operand" "") | |
1532 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1533 (set (match_operand:SI 14 "register_operand" "") | |
1534 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1535 (set (match_operand:SI 15 "register_operand" "") | |
1536 (mem:SI (plus:SI (match_dup 1) (const_int 52)))) | |
1537 (set (match_operand:SI 16 "register_operand" "") | |
1538 (mem:SI (plus:SI (match_dup 1) (const_int 56))))])] | |
1539 "(XVECLEN (operands[0], 0) == 15)" | |
1540 "lmw.bi\t%2, [%1], %16, 0x0" | |
1541 [(set_attr "type" "load_multiple") | |
1542 (set_attr "combo" "15") | |
1543 (set_attr "length" "4")] | |
1544 ) | |
1545 | |
1546 (define_insn "*lmwsi14" | |
1547 [(match_parallel 0 "nds32_load_multiple_operation" | |
1548 [(set (match_operand:SI 2 "register_operand" "") | |
1549 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1550 (set (match_operand:SI 3 "register_operand" "") | |
1551 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1552 (set (match_operand:SI 4 "register_operand" "") | |
1553 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1554 (set (match_operand:SI 5 "register_operand" "") | |
1555 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1556 (set (match_operand:SI 6 "register_operand" "") | |
1557 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1558 (set (match_operand:SI 7 "register_operand" "") | |
1559 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1560 (set (match_operand:SI 8 "register_operand" "") | |
1561 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1562 (set (match_operand:SI 9 "register_operand" "") | |
1563 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1564 (set (match_operand:SI 10 "register_operand" "") | |
1565 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1566 (set (match_operand:SI 11 "register_operand" "") | |
1567 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1568 (set (match_operand:SI 12 "register_operand" "") | |
1569 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1570 (set (match_operand:SI 13 "register_operand" "") | |
1571 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1572 (set (match_operand:SI 14 "register_operand" "") | |
1573 (mem:SI (plus:SI (match_dup 1) (const_int 48)))) | |
1574 (set (match_operand:SI 15 "register_operand" "") | |
1575 (mem:SI (plus:SI (match_dup 1) (const_int 52))))])] | |
1576 "(XVECLEN (operands[0], 0) == 14)" | |
1577 "lmw.bi\t%2, [%1], %15, 0x0" | |
1578 [(set_attr "type" "load_multiple") | |
1579 (set_attr "combo" "14") | |
1580 (set_attr "length" "4")] | |
1581 ) | |
1582 | |
1583 (define_insn "*lmwsi13" | |
1584 [(match_parallel 0 "nds32_load_multiple_operation" | |
1585 [(set (match_operand:SI 2 "register_operand" "") | |
1586 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1587 (set (match_operand:SI 3 "register_operand" "") | |
1588 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1589 (set (match_operand:SI 4 "register_operand" "") | |
1590 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1591 (set (match_operand:SI 5 "register_operand" "") | |
1592 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1593 (set (match_operand:SI 6 "register_operand" "") | |
1594 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1595 (set (match_operand:SI 7 "register_operand" "") | |
1596 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1597 (set (match_operand:SI 8 "register_operand" "") | |
1598 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1599 (set (match_operand:SI 9 "register_operand" "") | |
1600 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1601 (set (match_operand:SI 10 "register_operand" "") | |
1602 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1603 (set (match_operand:SI 11 "register_operand" "") | |
1604 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1605 (set (match_operand:SI 12 "register_operand" "") | |
1606 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1607 (set (match_operand:SI 13 "register_operand" "") | |
1608 (mem:SI (plus:SI (match_dup 1) (const_int 44)))) | |
1609 (set (match_operand:SI 14 "register_operand" "") | |
1610 (mem:SI (plus:SI (match_dup 1) (const_int 48))))])] | |
1611 "(XVECLEN (operands[0], 0) == 13)" | |
1612 "lmw.bi\t%2, [%1], %14, 0x0" | |
1613 [(set_attr "type" "load_multiple") | |
1614 (set_attr "combo" "13") | |
1615 (set_attr "length" "4")] | |
1616 ) | |
1617 | |
1618 (define_insn "*lmwsi12" | |
1619 [(match_parallel 0 "nds32_load_multiple_operation" | |
1620 [(set (match_operand:SI 2 "register_operand" "") | |
1621 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1622 (set (match_operand:SI 3 "register_operand" "") | |
1623 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1624 (set (match_operand:SI 4 "register_operand" "") | |
1625 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1626 (set (match_operand:SI 5 "register_operand" "") | |
1627 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1628 (set (match_operand:SI 6 "register_operand" "") | |
1629 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1630 (set (match_operand:SI 7 "register_operand" "") | |
1631 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1632 (set (match_operand:SI 8 "register_operand" "") | |
1633 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1634 (set (match_operand:SI 9 "register_operand" "") | |
1635 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1636 (set (match_operand:SI 10 "register_operand" "") | |
1637 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1638 (set (match_operand:SI 11 "register_operand" "") | |
1639 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1640 (set (match_operand:SI 12 "register_operand" "") | |
1641 (mem:SI (plus:SI (match_dup 1) (const_int 40)))) | |
1642 (set (match_operand:SI 13 "register_operand" "") | |
1643 (mem:SI (plus:SI (match_dup 1) (const_int 44))))])] | |
1644 "(XVECLEN (operands[0], 0) == 12)" | |
1645 "lmw.bi\t%2, [%1], %13, 0x0" | |
1646 [(set_attr "type" "load_multiple") | |
1647 (set_attr "combo" "12") | |
1648 (set_attr "length" "4")] | |
1649 ) | |
1650 | |
1651 (define_insn "*lmwsi11" | |
1652 [(match_parallel 0 "nds32_load_multiple_operation" | |
1653 [(set (match_operand:SI 2 "register_operand" "") | |
1654 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1655 (set (match_operand:SI 3 "register_operand" "") | |
1656 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1657 (set (match_operand:SI 4 "register_operand" "") | |
1658 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1659 (set (match_operand:SI 5 "register_operand" "") | |
1660 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1661 (set (match_operand:SI 6 "register_operand" "") | |
1662 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1663 (set (match_operand:SI 7 "register_operand" "") | |
1664 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1665 (set (match_operand:SI 8 "register_operand" "") | |
1666 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1667 (set (match_operand:SI 9 "register_operand" "") | |
1668 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1669 (set (match_operand:SI 10 "register_operand" "") | |
1670 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1671 (set (match_operand:SI 11 "register_operand" "") | |
1672 (mem:SI (plus:SI (match_dup 1) (const_int 36)))) | |
1673 (set (match_operand:SI 12 "register_operand" "") | |
1674 (mem:SI (plus:SI (match_dup 1) (const_int 40))))])] | |
1675 "(XVECLEN (operands[0], 0) == 11)" | |
1676 "lmw.bi\t%2, [%1], %12, 0x0" | |
1677 [(set_attr "type" "load_multiple") | |
1678 (set_attr "combo" "11") | |
1679 (set_attr "length" "4")] | |
1680 ) | |
1681 | |
1682 (define_insn "*lmwsi10" | |
1683 [(match_parallel 0 "nds32_load_multiple_operation" | |
1684 [(set (match_operand:SI 2 "register_operand" "") | |
1685 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1686 (set (match_operand:SI 3 "register_operand" "") | |
1687 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1688 (set (match_operand:SI 4 "register_operand" "") | |
1689 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1690 (set (match_operand:SI 5 "register_operand" "") | |
1691 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1692 (set (match_operand:SI 6 "register_operand" "") | |
1693 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1694 (set (match_operand:SI 7 "register_operand" "") | |
1695 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1696 (set (match_operand:SI 8 "register_operand" "") | |
1697 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1698 (set (match_operand:SI 9 "register_operand" "") | |
1699 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1700 (set (match_operand:SI 10 "register_operand" "") | |
1701 (mem:SI (plus:SI (match_dup 1) (const_int 32)))) | |
1702 (set (match_operand:SI 11 "register_operand" "") | |
1703 (mem:SI (plus:SI (match_dup 1) (const_int 36))))])] | |
1704 "(XVECLEN (operands[0], 0) == 10)" | |
1705 "lmw.bi\t%2, [%1], %11, 0x0" | |
1706 [(set_attr "type" "load_multiple") | |
1707 (set_attr "combo" "10") | |
1708 (set_attr "length" "4")] | |
1709 ) | |
1710 | |
1711 (define_insn "*lmwsi9" | |
1712 [(match_parallel 0 "nds32_load_multiple_operation" | |
1713 [(set (match_operand:SI 2 "register_operand" "") | |
1714 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | |
1715 (set (match_operand:SI 3 "register_operand" "") | |
1716 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
1717 (set (match_operand:SI 4 "register_operand" "") | |
1718 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
1719 (set (match_operand:SI 5 "register_operand" "") | |
1720 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
1721 (set (match_operand:SI 6 "register_operand" "") | |
1722 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
1723 (set (match_operand:SI 7 "register_operand" "") | |
1724 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
1725 (set (match_operand:SI 8 "register_operand" "") | |
1726 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
1727 (set (match_operand:SI 9 "register_operand" "") | |
1728 (mem:SI (plus:SI (match_dup 1) (const_int 28)))) | |
1729 (set (match_operand:SI 10 "register_operand" "") | |
1730 (mem:SI (plus:SI (match_dup 1) (const_int 32))))])] | |
1731 "(XVECLEN (operands[0], 0) == 9)" | |
1732 "lmw.bi\t%2, [%1], %10, 0x0" | |
1733 [(set_attr "type" "load_multiple") | |
1734 (set_attr "combo" "9") | |
1735 (set_attr "length" "4")] | |
1736 ) | |
76 | 1737 |
77 (define_insn "*lmwsi8" | 1738 (define_insn "*lmwsi8" |
78 [(match_parallel 0 "nds32_load_multiple_operation" | 1739 [(match_parallel 0 "nds32_load_multiple_operation" |
79 [(set (match_operand:SI 2 "register_operand" "") | 1740 [(set (match_operand:SI 2 "register_operand" "") |
80 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | 1741 (mem:SI (match_operand:SI 1 "register_operand" "r"))) |
92 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | 1753 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) |
93 (set (match_operand:SI 9 "register_operand" "") | 1754 (set (match_operand:SI 9 "register_operand" "") |
94 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | 1755 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] |
95 "(XVECLEN (operands[0], 0) == 8)" | 1756 "(XVECLEN (operands[0], 0) == 8)" |
96 "lmw.bi\t%2, [%1], %9, 0x0" | 1757 "lmw.bi\t%2, [%1], %9, 0x0" |
97 [(set_attr "type" "load") | 1758 [(set_attr "type" "load_multiple") |
98 (set_attr "length" "4")] | 1759 (set_attr "combo" "8") |
1760 (set_attr "length" "4")] | |
99 ) | 1761 ) |
100 | 1762 |
101 (define_insn "*lmwsi7" | 1763 (define_insn "*lmwsi7" |
102 [(match_parallel 0 "nds32_load_multiple_operation" | 1764 [(match_parallel 0 "nds32_load_multiple_operation" |
103 [(set (match_operand:SI 2 "register_operand" "") | 1765 [(set (match_operand:SI 2 "register_operand" "") |
114 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | 1776 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) |
115 (set (match_operand:SI 8 "register_operand" "") | 1777 (set (match_operand:SI 8 "register_operand" "") |
116 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | 1778 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] |
117 "(XVECLEN (operands[0], 0) == 7)" | 1779 "(XVECLEN (operands[0], 0) == 7)" |
118 "lmw.bi\t%2, [%1], %8, 0x0" | 1780 "lmw.bi\t%2, [%1], %8, 0x0" |
119 [(set_attr "type" "load") | 1781 [(set_attr "type" "load_multiple") |
120 (set_attr "length" "4")] | 1782 (set_attr "combo" "7") |
1783 (set_attr "length" "4")] | |
121 ) | 1784 ) |
122 | 1785 |
123 (define_insn "*lmwsi6" | 1786 (define_insn "*lmwsi6" |
124 [(match_parallel 0 "nds32_load_multiple_operation" | 1787 [(match_parallel 0 "nds32_load_multiple_operation" |
125 [(set (match_operand:SI 2 "register_operand" "") | 1788 [(set (match_operand:SI 2 "register_operand" "") |
134 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | 1797 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) |
135 (set (match_operand:SI 7 "register_operand" "") | 1798 (set (match_operand:SI 7 "register_operand" "") |
136 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | 1799 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] |
137 "(XVECLEN (operands[0], 0) == 6)" | 1800 "(XVECLEN (operands[0], 0) == 6)" |
138 "lmw.bi\t%2, [%1], %7, 0x0" | 1801 "lmw.bi\t%2, [%1], %7, 0x0" |
139 [(set_attr "type" "load") | 1802 [(set_attr "type" "load_multiple") |
140 (set_attr "length" "4")] | 1803 (set_attr "combo" "6") |
1804 (set_attr "length" "4")] | |
141 ) | 1805 ) |
142 | 1806 |
143 (define_insn "*lmwsi5" | 1807 (define_insn "*lmwsi5" |
144 [(match_parallel 0 "nds32_load_multiple_operation" | 1808 [(match_parallel 0 "nds32_load_multiple_operation" |
145 [(set (match_operand:SI 2 "register_operand" "") | 1809 [(set (match_operand:SI 2 "register_operand" "") |
152 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | 1816 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) |
153 (set (match_operand:SI 6 "register_operand" "") | 1817 (set (match_operand:SI 6 "register_operand" "") |
154 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | 1818 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] |
155 "(XVECLEN (operands[0], 0) == 5)" | 1819 "(XVECLEN (operands[0], 0) == 5)" |
156 "lmw.bi\t%2, [%1], %6, 0x0" | 1820 "lmw.bi\t%2, [%1], %6, 0x0" |
157 [(set_attr "type" "load") | 1821 [(set_attr "type" "load_multiple") |
158 (set_attr "length" "4")] | 1822 (set_attr "combo" "5") |
1823 (set_attr "length" "4")] | |
159 ) | 1824 ) |
160 | 1825 |
161 (define_insn "*lmwsi4" | 1826 (define_insn "*lmwsi4" |
162 [(match_parallel 0 "nds32_load_multiple_operation" | 1827 [(match_parallel 0 "nds32_load_multiple_operation" |
163 [(set (match_operand:SI 2 "register_operand" "") | 1828 [(set (match_operand:SI 2 "register_operand" "") |
168 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | 1833 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) |
169 (set (match_operand:SI 5 "register_operand" "") | 1834 (set (match_operand:SI 5 "register_operand" "") |
170 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | 1835 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] |
171 "(XVECLEN (operands[0], 0) == 4)" | 1836 "(XVECLEN (operands[0], 0) == 4)" |
172 "lmw.bi\t%2, [%1], %5, 0x0" | 1837 "lmw.bi\t%2, [%1], %5, 0x0" |
173 [(set_attr "type" "load") | 1838 [(set_attr "type" "load_multiple") |
174 (set_attr "length" "4")] | 1839 (set_attr "combo" "4") |
1840 (set_attr "length" "4")] | |
175 ) | 1841 ) |
176 | 1842 |
177 (define_insn "*lmwsi3" | 1843 (define_insn "*lmwsi3" |
178 [(match_parallel 0 "nds32_load_multiple_operation" | 1844 [(match_parallel 0 "nds32_load_multiple_operation" |
179 [(set (match_operand:SI 2 "register_operand" "") | 1845 [(set (match_operand:SI 2 "register_operand" "") |
182 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | 1848 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) |
183 (set (match_operand:SI 4 "register_operand" "") | 1849 (set (match_operand:SI 4 "register_operand" "") |
184 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | 1850 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] |
185 "(XVECLEN (operands[0], 0) == 3)" | 1851 "(XVECLEN (operands[0], 0) == 3)" |
186 "lmw.bi\t%2, [%1], %4, 0x0" | 1852 "lmw.bi\t%2, [%1], %4, 0x0" |
187 [(set_attr "type" "load") | 1853 [(set_attr "type" "load_multiple") |
188 (set_attr "length" "4")] | 1854 (set_attr "combo" "3") |
1855 (set_attr "length" "4")] | |
189 ) | 1856 ) |
190 | 1857 |
191 (define_insn "*lmwsi2" | 1858 (define_insn "*lmwsi2" |
192 [(match_parallel 0 "nds32_load_multiple_operation" | 1859 [(match_parallel 0 "nds32_load_multiple_operation" |
193 [(set (match_operand:SI 2 "register_operand" "") | 1860 [(set (match_operand:SI 2 "register_operand" "") |
194 (mem:SI (match_operand:SI 1 "register_operand" "r"))) | 1861 (mem:SI (match_operand:SI 1 "register_operand" "r"))) |
195 (set (match_operand:SI 3 "register_operand" "") | 1862 (set (match_operand:SI 3 "register_operand" "") |
196 (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] | 1863 (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] |
197 "(XVECLEN (operands[0], 0) == 2)" | 1864 "(XVECLEN (operands[0], 0) == 2)" |
198 "lmw.bi\t%2, [%1], %3, 0x0" | 1865 "lmw.bi\t%2, [%1], %3, 0x0" |
199 [(set_attr "type" "load") | 1866 [(set_attr "type" "load_multiple") |
200 (set_attr "length" "4")] | 1867 (set_attr "combo" "2") |
201 ) | 1868 (set_attr "length" "4")] |
202 | 1869 ) |
203 | 1870 |
204 ;; Store Multiple Insns. | 1871 ;; Store Multiple Insns. |
205 ;; | 1872 ;; |
206 ;; operands[0] is the first memory location. | 1873 ;; operands[0] is the first memory location. |
207 ;; opernads[1] is the first of the consecutive registers. | 1874 ;; opernads[1] is the first of the consecutive registers. |
234 (based on this nds32-multiple.md design). | 1901 (based on this nds32-multiple.md design). |
235 3. Minimum 2 registers for smw.bi instruction | 1902 3. Minimum 2 registers for smw.bi instruction |
236 (based on this nds32-multiple.md design). | 1903 (based on this nds32-multiple.md design). |
237 4. operands[0] must be memory for sure. | 1904 4. operands[0] must be memory for sure. |
238 5. operands[1] must be register for sure. | 1905 5. operands[1] must be register for sure. |
239 6. Do not cross $r15 register because it is not allocatable. */ | 1906 6. operands[0] is not volatile memory access. |
1907 7. Do not cross $r15 register because it is not allocatable. */ | |
240 if (GET_CODE (operands[2]) != CONST_INT | 1908 if (GET_CODE (operands[2]) != CONST_INT |
241 || INTVAL (operands[2]) > maximum | 1909 || INTVAL (operands[2]) > maximum |
242 || INTVAL (operands[2]) < 2 | 1910 || INTVAL (operands[2]) < 2 |
243 || GET_CODE (operands[0]) != MEM | 1911 || GET_CODE (operands[0]) != MEM |
244 || GET_CODE (operands[1]) != REG | 1912 || GET_CODE (operands[1]) != REG |
1913 || MEM_VOLATILE_P (operands[0]) | |
245 || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM) | 1914 || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM) |
246 FAIL; | 1915 FAIL; |
247 | 1916 |
248 /* For (mem addr), we force_reg on addr here, | 1917 /* For (mem addr), we force_reg on addr here, |
249 so that nds32_expand_store_multiple can easily use it. */ | 1918 so that nds32_expand_store_multiple can easily use it. */ |
250 operands[3] = nds32_expand_store_multiple (REGNO (operands[1]), | 1919 operands[3] = nds32_expand_store_multiple (REGNO (operands[1]), |
251 INTVAL (operands[2]), | 1920 INTVAL (operands[2]), |
252 force_reg (SImode, | 1921 force_reg (SImode, |
253 XEXP (operands[0], 0)), | 1922 XEXP (operands[0], 0)), |
254 operands[0]); | 1923 operands[0], |
1924 false, NULL); | |
255 }) | 1925 }) |
256 | 1926 |
257 ;; Ordinary Store Multiple. | 1927 ;; Ordinary Store Multiple. |
1928 (define_insn "*stm_bim_si25" | |
1929 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
1930 [(set (match_operand:SI 1 "register_operand" "=r") | |
1931 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 100))) | |
1932 (set (mem:SI (match_dup 2)) | |
1933 (match_operand:SI 3 "register_operand" "")) | |
1934 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
1935 (match_operand:SI 4 "register_operand" "")) | |
1936 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
1937 (match_operand:SI 5 "register_operand" "")) | |
1938 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
1939 (match_operand:SI 6 "register_operand" "")) | |
1940 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
1941 (match_operand:SI 7 "register_operand" "")) | |
1942 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
1943 (match_operand:SI 8 "register_operand" "")) | |
1944 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
1945 (match_operand:SI 9 "register_operand" "")) | |
1946 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
1947 (match_operand:SI 10 "register_operand" "")) | |
1948 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
1949 (match_operand:SI 11 "register_operand" "")) | |
1950 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
1951 (match_operand:SI 12 "register_operand" "")) | |
1952 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
1953 (match_operand:SI 13 "register_operand" "")) | |
1954 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
1955 (match_operand:SI 14 "register_operand" "")) | |
1956 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
1957 (match_operand:SI 15 "register_operand" "")) | |
1958 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
1959 (match_operand:SI 16 "register_operand" "")) | |
1960 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
1961 (match_operand:SI 17 "register_operand" "")) | |
1962 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
1963 (match_operand:SI 18 "register_operand" "")) | |
1964 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
1965 (match_operand:SI 19 "register_operand" "")) | |
1966 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
1967 (match_operand:SI 20 "register_operand" "")) | |
1968 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
1969 (match_operand:SI 21 "register_operand" "")) | |
1970 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
1971 (match_operand:SI 22 "register_operand" "")) | |
1972 (set (mem:SI (plus:SI (match_dup 2) (const_int 80))) | |
1973 (match_operand:SI 23 "register_operand" "")) | |
1974 (set (mem:SI (plus:SI (match_dup 2) (const_int 84))) | |
1975 (match_operand:SI 24 "register_operand" "")) | |
1976 (set (mem:SI (plus:SI (match_dup 2) (const_int 88))) | |
1977 (match_operand:SI 25 "register_operand" "")) | |
1978 (set (mem:SI (plus:SI (match_dup 2) (const_int 92))) | |
1979 (match_operand:SI 26 "register_operand" "")) | |
1980 (set (mem:SI (plus:SI (match_dup 2) (const_int 96))) | |
1981 (match_operand:SI 27 "register_operand" ""))])] | |
1982 "(XVECLEN (operands[0], 0) == 26)" | |
1983 "smw.bim\t%3, [%1], %27, 0x0" | |
1984 [(set_attr "type" "store_multiple") | |
1985 (set_attr "combo" "25") | |
1986 (set_attr "length" "4")] | |
1987 ) | |
1988 | |
1989 (define_insn "*stm_bim_si24" | |
1990 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
1991 [(set (match_operand:SI 1 "register_operand" "=r") | |
1992 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 96))) | |
1993 (set (mem:SI (match_dup 2)) | |
1994 (match_operand:SI 3 "register_operand" "")) | |
1995 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
1996 (match_operand:SI 4 "register_operand" "")) | |
1997 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
1998 (match_operand:SI 5 "register_operand" "")) | |
1999 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2000 (match_operand:SI 6 "register_operand" "")) | |
2001 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2002 (match_operand:SI 7 "register_operand" "")) | |
2003 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2004 (match_operand:SI 8 "register_operand" "")) | |
2005 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2006 (match_operand:SI 9 "register_operand" "")) | |
2007 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2008 (match_operand:SI 10 "register_operand" "")) | |
2009 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2010 (match_operand:SI 11 "register_operand" "")) | |
2011 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2012 (match_operand:SI 12 "register_operand" "")) | |
2013 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2014 (match_operand:SI 13 "register_operand" "")) | |
2015 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2016 (match_operand:SI 14 "register_operand" "")) | |
2017 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2018 (match_operand:SI 15 "register_operand" "")) | |
2019 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2020 (match_operand:SI 16 "register_operand" "")) | |
2021 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2022 (match_operand:SI 17 "register_operand" "")) | |
2023 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2024 (match_operand:SI 18 "register_operand" "")) | |
2025 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2026 (match_operand:SI 19 "register_operand" "")) | |
2027 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2028 (match_operand:SI 20 "register_operand" "")) | |
2029 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2030 (match_operand:SI 21 "register_operand" "")) | |
2031 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
2032 (match_operand:SI 22 "register_operand" "")) | |
2033 (set (mem:SI (plus:SI (match_dup 2) (const_int 80))) | |
2034 (match_operand:SI 23 "register_operand" "")) | |
2035 (set (mem:SI (plus:SI (match_dup 2) (const_int 84))) | |
2036 (match_operand:SI 24 "register_operand" "")) | |
2037 (set (mem:SI (plus:SI (match_dup 2) (const_int 88))) | |
2038 (match_operand:SI 25 "register_operand" "")) | |
2039 (set (mem:SI (plus:SI (match_dup 2) (const_int 92))) | |
2040 (match_operand:SI 26 "register_operand" ""))])] | |
2041 "(XVECLEN (operands[0], 0) == 25)" | |
2042 "smw.bim\t%3, [%1], %26, 0x0" | |
2043 [(set_attr "type" "store_multiple") | |
2044 (set_attr "combo" "24") | |
2045 (set_attr "length" "4")] | |
2046 ) | |
2047 | |
2048 (define_insn "*stm_bim_si23" | |
2049 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2050 [(set (match_operand:SI 1 "register_operand" "=r") | |
2051 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 92))) | |
2052 (set (mem:SI (match_dup 2)) | |
2053 (match_operand:SI 3 "register_operand" "")) | |
2054 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2055 (match_operand:SI 4 "register_operand" "")) | |
2056 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2057 (match_operand:SI 5 "register_operand" "")) | |
2058 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2059 (match_operand:SI 6 "register_operand" "")) | |
2060 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2061 (match_operand:SI 7 "register_operand" "")) | |
2062 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2063 (match_operand:SI 8 "register_operand" "")) | |
2064 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2065 (match_operand:SI 9 "register_operand" "")) | |
2066 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2067 (match_operand:SI 10 "register_operand" "")) | |
2068 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2069 (match_operand:SI 11 "register_operand" "")) | |
2070 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2071 (match_operand:SI 12 "register_operand" "")) | |
2072 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2073 (match_operand:SI 13 "register_operand" "")) | |
2074 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2075 (match_operand:SI 14 "register_operand" "")) | |
2076 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2077 (match_operand:SI 15 "register_operand" "")) | |
2078 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2079 (match_operand:SI 16 "register_operand" "")) | |
2080 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2081 (match_operand:SI 17 "register_operand" "")) | |
2082 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2083 (match_operand:SI 18 "register_operand" "")) | |
2084 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2085 (match_operand:SI 19 "register_operand" "")) | |
2086 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2087 (match_operand:SI 20 "register_operand" "")) | |
2088 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2089 (match_operand:SI 21 "register_operand" "")) | |
2090 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
2091 (match_operand:SI 22 "register_operand" "")) | |
2092 (set (mem:SI (plus:SI (match_dup 2) (const_int 80))) | |
2093 (match_operand:SI 23 "register_operand" "")) | |
2094 (set (mem:SI (plus:SI (match_dup 2) (const_int 84))) | |
2095 (match_operand:SI 24 "register_operand" "")) | |
2096 (set (mem:SI (plus:SI (match_dup 2) (const_int 88))) | |
2097 (match_operand:SI 25 "register_operand" ""))])] | |
2098 "(XVECLEN (operands[0], 0) == 24)" | |
2099 "smw.bim\t%3, [%1], %25, 0x0" | |
2100 [(set_attr "type" "store_multiple") | |
2101 (set_attr "combo" "23") | |
2102 (set_attr "length" "4")] | |
2103 ) | |
2104 | |
2105 (define_insn "*stm_bim_si22" | |
2106 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2107 [(set (match_operand:SI 1 "register_operand" "=r") | |
2108 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 88))) | |
2109 (set (mem:SI (match_dup 2)) | |
2110 (match_operand:SI 3 "register_operand" "")) | |
2111 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2112 (match_operand:SI 4 "register_operand" "")) | |
2113 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2114 (match_operand:SI 5 "register_operand" "")) | |
2115 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2116 (match_operand:SI 6 "register_operand" "")) | |
2117 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2118 (match_operand:SI 7 "register_operand" "")) | |
2119 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2120 (match_operand:SI 8 "register_operand" "")) | |
2121 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2122 (match_operand:SI 9 "register_operand" "")) | |
2123 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2124 (match_operand:SI 10 "register_operand" "")) | |
2125 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2126 (match_operand:SI 11 "register_operand" "")) | |
2127 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2128 (match_operand:SI 12 "register_operand" "")) | |
2129 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2130 (match_operand:SI 13 "register_operand" "")) | |
2131 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2132 (match_operand:SI 14 "register_operand" "")) | |
2133 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2134 (match_operand:SI 15 "register_operand" "")) | |
2135 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2136 (match_operand:SI 16 "register_operand" "")) | |
2137 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2138 (match_operand:SI 17 "register_operand" "")) | |
2139 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2140 (match_operand:SI 18 "register_operand" "")) | |
2141 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2142 (match_operand:SI 19 "register_operand" "")) | |
2143 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2144 (match_operand:SI 20 "register_operand" "")) | |
2145 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2146 (match_operand:SI 21 "register_operand" "")) | |
2147 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
2148 (match_operand:SI 22 "register_operand" "")) | |
2149 (set (mem:SI (plus:SI (match_dup 2) (const_int 80))) | |
2150 (match_operand:SI 23 "register_operand" "")) | |
2151 (set (mem:SI (plus:SI (match_dup 2) (const_int 84))) | |
2152 (match_operand:SI 24 "register_operand" ""))])] | |
2153 "(XVECLEN (operands[0], 0) == 23)" | |
2154 "smw.bim\t%3, [%1], %24, 0x0" | |
2155 [(set_attr "type" "store_multiple") | |
2156 (set_attr "combo" "22") | |
2157 (set_attr "length" "4")] | |
2158 ) | |
2159 | |
2160 (define_insn "*stm_bim_si21" | |
2161 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2162 [(set (match_operand:SI 1 "register_operand" "=r") | |
2163 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 84))) | |
2164 (set (mem:SI (match_dup 2)) | |
2165 (match_operand:SI 3 "register_operand" "")) | |
2166 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2167 (match_operand:SI 4 "register_operand" "")) | |
2168 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2169 (match_operand:SI 5 "register_operand" "")) | |
2170 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2171 (match_operand:SI 6 "register_operand" "")) | |
2172 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2173 (match_operand:SI 7 "register_operand" "")) | |
2174 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2175 (match_operand:SI 8 "register_operand" "")) | |
2176 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2177 (match_operand:SI 9 "register_operand" "")) | |
2178 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2179 (match_operand:SI 10 "register_operand" "")) | |
2180 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2181 (match_operand:SI 11 "register_operand" "")) | |
2182 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2183 (match_operand:SI 12 "register_operand" "")) | |
2184 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2185 (match_operand:SI 13 "register_operand" "")) | |
2186 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2187 (match_operand:SI 14 "register_operand" "")) | |
2188 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2189 (match_operand:SI 15 "register_operand" "")) | |
2190 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2191 (match_operand:SI 16 "register_operand" "")) | |
2192 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2193 (match_operand:SI 17 "register_operand" "")) | |
2194 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2195 (match_operand:SI 18 "register_operand" "")) | |
2196 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2197 (match_operand:SI 19 "register_operand" "")) | |
2198 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2199 (match_operand:SI 20 "register_operand" "")) | |
2200 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2201 (match_operand:SI 21 "register_operand" "")) | |
2202 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
2203 (match_operand:SI 22 "register_operand" "")) | |
2204 (set (mem:SI (plus:SI (match_dup 2) (const_int 80))) | |
2205 (match_operand:SI 23 "register_operand" ""))])] | |
2206 "(XVECLEN (operands[0], 0) == 22)" | |
2207 "smw.bim\t%3, [%1], %23, 0x0" | |
2208 [(set_attr "type" "store_multiple") | |
2209 (set_attr "combo" "21") | |
2210 (set_attr "length" "4")] | |
2211 ) | |
2212 | |
2213 (define_insn "*stm_bim_si20" | |
2214 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2215 [(set (match_operand:SI 1 "register_operand" "=r") | |
2216 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 80))) | |
2217 (set (mem:SI (match_dup 2)) | |
2218 (match_operand:SI 3 "register_operand" "")) | |
2219 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2220 (match_operand:SI 4 "register_operand" "")) | |
2221 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2222 (match_operand:SI 5 "register_operand" "")) | |
2223 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2224 (match_operand:SI 6 "register_operand" "")) | |
2225 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2226 (match_operand:SI 7 "register_operand" "")) | |
2227 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2228 (match_operand:SI 8 "register_operand" "")) | |
2229 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2230 (match_operand:SI 9 "register_operand" "")) | |
2231 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2232 (match_operand:SI 10 "register_operand" "")) | |
2233 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2234 (match_operand:SI 11 "register_operand" "")) | |
2235 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2236 (match_operand:SI 12 "register_operand" "")) | |
2237 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2238 (match_operand:SI 13 "register_operand" "")) | |
2239 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2240 (match_operand:SI 14 "register_operand" "")) | |
2241 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2242 (match_operand:SI 15 "register_operand" "")) | |
2243 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2244 (match_operand:SI 16 "register_operand" "")) | |
2245 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2246 (match_operand:SI 17 "register_operand" "")) | |
2247 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2248 (match_operand:SI 18 "register_operand" "")) | |
2249 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2250 (match_operand:SI 19 "register_operand" "")) | |
2251 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2252 (match_operand:SI 20 "register_operand" "")) | |
2253 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2254 (match_operand:SI 21 "register_operand" "")) | |
2255 (set (mem:SI (plus:SI (match_dup 2) (const_int 76))) | |
2256 (match_operand:SI 22 "register_operand" ""))])] | |
2257 "(XVECLEN (operands[0], 0) == 21)" | |
2258 "smw.bim\t%3, [%1], %22, 0x0" | |
2259 [(set_attr "type" "store_multiple") | |
2260 (set_attr "combo" "20") | |
2261 (set_attr "length" "4")] | |
2262 ) | |
2263 | |
2264 (define_insn "*stm_bim_si19" | |
2265 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2266 [(set (match_operand:SI 1 "register_operand" "=r") | |
2267 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 76))) | |
2268 (set (mem:SI (match_dup 2)) | |
2269 (match_operand:SI 3 "register_operand" "")) | |
2270 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2271 (match_operand:SI 4 "register_operand" "")) | |
2272 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2273 (match_operand:SI 5 "register_operand" "")) | |
2274 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2275 (match_operand:SI 6 "register_operand" "")) | |
2276 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2277 (match_operand:SI 7 "register_operand" "")) | |
2278 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2279 (match_operand:SI 8 "register_operand" "")) | |
2280 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2281 (match_operand:SI 9 "register_operand" "")) | |
2282 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2283 (match_operand:SI 10 "register_operand" "")) | |
2284 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2285 (match_operand:SI 11 "register_operand" "")) | |
2286 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2287 (match_operand:SI 12 "register_operand" "")) | |
2288 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2289 (match_operand:SI 13 "register_operand" "")) | |
2290 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2291 (match_operand:SI 14 "register_operand" "")) | |
2292 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2293 (match_operand:SI 15 "register_operand" "")) | |
2294 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2295 (match_operand:SI 16 "register_operand" "")) | |
2296 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2297 (match_operand:SI 17 "register_operand" "")) | |
2298 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2299 (match_operand:SI 18 "register_operand" "")) | |
2300 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2301 (match_operand:SI 19 "register_operand" "")) | |
2302 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2303 (match_operand:SI 20 "register_operand" "")) | |
2304 (set (mem:SI (plus:SI (match_dup 2) (const_int 72))) | |
2305 (match_operand:SI 21 "register_operand" ""))])] | |
2306 "(XVECLEN (operands[0], 0) == 20)" | |
2307 "smw.bim\t%3, [%1], %21, 0x0" | |
2308 [(set_attr "type" "store_multiple") | |
2309 (set_attr "combo" "19") | |
2310 (set_attr "length" "4")] | |
2311 ) | |
2312 | |
2313 (define_insn "*stm_bim_si18" | |
2314 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2315 [(set (match_operand:SI 1 "register_operand" "=r") | |
2316 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 72))) | |
2317 (set (mem:SI (match_dup 2)) | |
2318 (match_operand:SI 3 "register_operand" "")) | |
2319 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2320 (match_operand:SI 4 "register_operand" "")) | |
2321 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2322 (match_operand:SI 5 "register_operand" "")) | |
2323 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2324 (match_operand:SI 6 "register_operand" "")) | |
2325 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2326 (match_operand:SI 7 "register_operand" "")) | |
2327 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2328 (match_operand:SI 8 "register_operand" "")) | |
2329 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2330 (match_operand:SI 9 "register_operand" "")) | |
2331 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2332 (match_operand:SI 10 "register_operand" "")) | |
2333 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2334 (match_operand:SI 11 "register_operand" "")) | |
2335 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2336 (match_operand:SI 12 "register_operand" "")) | |
2337 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2338 (match_operand:SI 13 "register_operand" "")) | |
2339 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2340 (match_operand:SI 14 "register_operand" "")) | |
2341 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2342 (match_operand:SI 15 "register_operand" "")) | |
2343 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2344 (match_operand:SI 16 "register_operand" "")) | |
2345 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2346 (match_operand:SI 17 "register_operand" "")) | |
2347 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2348 (match_operand:SI 18 "register_operand" "")) | |
2349 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2350 (match_operand:SI 19 "register_operand" "")) | |
2351 (set (mem:SI (plus:SI (match_dup 2) (const_int 68))) | |
2352 (match_operand:SI 20 "register_operand" ""))])] | |
2353 "(XVECLEN (operands[0], 0) == 19)" | |
2354 "smw.bim\t%3, [%1], %20, 0x0" | |
2355 [(set_attr "type" "store_multiple") | |
2356 (set_attr "combo" "18") | |
2357 (set_attr "length" "4")] | |
2358 ) | |
2359 | |
2360 (define_insn "*stm_bim_si17" | |
2361 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2362 [(set (match_operand:SI 1 "register_operand" "=r") | |
2363 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 68))) | |
2364 (set (mem:SI (match_dup 2)) | |
2365 (match_operand:SI 3 "register_operand" "")) | |
2366 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2367 (match_operand:SI 4 "register_operand" "")) | |
2368 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2369 (match_operand:SI 5 "register_operand" "")) | |
2370 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2371 (match_operand:SI 6 "register_operand" "")) | |
2372 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2373 (match_operand:SI 7 "register_operand" "")) | |
2374 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2375 (match_operand:SI 8 "register_operand" "")) | |
2376 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2377 (match_operand:SI 9 "register_operand" "")) | |
2378 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2379 (match_operand:SI 10 "register_operand" "")) | |
2380 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2381 (match_operand:SI 11 "register_operand" "")) | |
2382 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2383 (match_operand:SI 12 "register_operand" "")) | |
2384 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2385 (match_operand:SI 13 "register_operand" "")) | |
2386 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2387 (match_operand:SI 14 "register_operand" "")) | |
2388 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2389 (match_operand:SI 15 "register_operand" "")) | |
2390 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2391 (match_operand:SI 16 "register_operand" "")) | |
2392 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2393 (match_operand:SI 17 "register_operand" "")) | |
2394 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2395 (match_operand:SI 18 "register_operand" "")) | |
2396 (set (mem:SI (plus:SI (match_dup 2) (const_int 64))) | |
2397 (match_operand:SI 19 "register_operand" ""))])] | |
2398 "(XVECLEN (operands[0], 0) == 18)" | |
2399 "smw.bim\t%3, [%1], %19, 0x0" | |
2400 [(set_attr "type" "store_multiple") | |
2401 (set_attr "combo" "17") | |
2402 (set_attr "length" "4")] | |
2403 ) | |
2404 | |
2405 (define_insn "*stm_bim_si16" | |
2406 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2407 [(set (match_operand:SI 1 "register_operand" "=r") | |
2408 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 64))) | |
2409 (set (mem:SI (match_dup 2)) | |
2410 (match_operand:SI 3 "register_operand" "")) | |
2411 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2412 (match_operand:SI 4 "register_operand" "")) | |
2413 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2414 (match_operand:SI 5 "register_operand" "")) | |
2415 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2416 (match_operand:SI 6 "register_operand" "")) | |
2417 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2418 (match_operand:SI 7 "register_operand" "")) | |
2419 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2420 (match_operand:SI 8 "register_operand" "")) | |
2421 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2422 (match_operand:SI 9 "register_operand" "")) | |
2423 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2424 (match_operand:SI 10 "register_operand" "")) | |
2425 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2426 (match_operand:SI 11 "register_operand" "")) | |
2427 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2428 (match_operand:SI 12 "register_operand" "")) | |
2429 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2430 (match_operand:SI 13 "register_operand" "")) | |
2431 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2432 (match_operand:SI 14 "register_operand" "")) | |
2433 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2434 (match_operand:SI 15 "register_operand" "")) | |
2435 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2436 (match_operand:SI 16 "register_operand" "")) | |
2437 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2438 (match_operand:SI 17 "register_operand" "")) | |
2439 (set (mem:SI (plus:SI (match_dup 2) (const_int 60))) | |
2440 (match_operand:SI 18 "register_operand" ""))])] | |
2441 "(XVECLEN (operands[0], 0) == 17)" | |
2442 "smw.bim\t%3, [%1], %18, 0x0" | |
2443 [(set_attr "type" "store_multiple") | |
2444 (set_attr "combo" "16") | |
2445 (set_attr "length" "4")] | |
2446 ) | |
2447 | |
2448 (define_insn "*stm_bim_si15" | |
2449 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2450 [(set (match_operand:SI 1 "register_operand" "=r") | |
2451 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 60))) | |
2452 (set (mem:SI (match_dup 2)) | |
2453 (match_operand:SI 3 "register_operand" "")) | |
2454 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2455 (match_operand:SI 4 "register_operand" "")) | |
2456 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2457 (match_operand:SI 5 "register_operand" "")) | |
2458 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2459 (match_operand:SI 6 "register_operand" "")) | |
2460 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2461 (match_operand:SI 7 "register_operand" "")) | |
2462 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2463 (match_operand:SI 8 "register_operand" "")) | |
2464 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2465 (match_operand:SI 9 "register_operand" "")) | |
2466 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2467 (match_operand:SI 10 "register_operand" "")) | |
2468 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2469 (match_operand:SI 11 "register_operand" "")) | |
2470 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2471 (match_operand:SI 12 "register_operand" "")) | |
2472 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2473 (match_operand:SI 13 "register_operand" "")) | |
2474 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2475 (match_operand:SI 14 "register_operand" "")) | |
2476 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2477 (match_operand:SI 15 "register_operand" "")) | |
2478 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2479 (match_operand:SI 16 "register_operand" "")) | |
2480 (set (mem:SI (plus:SI (match_dup 2) (const_int 56))) | |
2481 (match_operand:SI 17 "register_operand" ""))])] | |
2482 "(XVECLEN (operands[0], 0) == 16)" | |
2483 "smw.bim\t%3, [%1], %17, 0x0" | |
2484 [(set_attr "type" "store_multiple") | |
2485 (set_attr "combo" "15") | |
2486 (set_attr "length" "4")] | |
2487 ) | |
2488 | |
2489 (define_insn "*stm_bim_si14" | |
2490 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2491 [(set (match_operand:SI 1 "register_operand" "=r") | |
2492 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 56))) | |
2493 (set (mem:SI (match_dup 2)) | |
2494 (match_operand:SI 3 "register_operand" "")) | |
2495 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2496 (match_operand:SI 4 "register_operand" "")) | |
2497 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2498 (match_operand:SI 5 "register_operand" "")) | |
2499 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2500 (match_operand:SI 6 "register_operand" "")) | |
2501 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2502 (match_operand:SI 7 "register_operand" "")) | |
2503 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2504 (match_operand:SI 8 "register_operand" "")) | |
2505 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2506 (match_operand:SI 9 "register_operand" "")) | |
2507 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2508 (match_operand:SI 10 "register_operand" "")) | |
2509 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2510 (match_operand:SI 11 "register_operand" "")) | |
2511 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2512 (match_operand:SI 12 "register_operand" "")) | |
2513 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2514 (match_operand:SI 13 "register_operand" "")) | |
2515 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2516 (match_operand:SI 14 "register_operand" "")) | |
2517 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2518 (match_operand:SI 15 "register_operand" "")) | |
2519 (set (mem:SI (plus:SI (match_dup 2) (const_int 52))) | |
2520 (match_operand:SI 16 "register_operand" ""))])] | |
2521 "(XVECLEN (operands[0], 0) == 15)" | |
2522 "smw.bim\t%3, [%1], %16, 0x0" | |
2523 [(set_attr "type" "store_multiple") | |
2524 (set_attr "combo" "14") | |
2525 (set_attr "length" "4")] | |
2526 ) | |
2527 | |
2528 (define_insn "*stm_bim_si13" | |
2529 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2530 [(set (match_operand:SI 1 "register_operand" "=r") | |
2531 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 52))) | |
2532 (set (mem:SI (match_dup 2)) | |
2533 (match_operand:SI 3 "register_operand" "")) | |
2534 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2535 (match_operand:SI 4 "register_operand" "")) | |
2536 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2537 (match_operand:SI 5 "register_operand" "")) | |
2538 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2539 (match_operand:SI 6 "register_operand" "")) | |
2540 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2541 (match_operand:SI 7 "register_operand" "")) | |
2542 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2543 (match_operand:SI 8 "register_operand" "")) | |
2544 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2545 (match_operand:SI 9 "register_operand" "")) | |
2546 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2547 (match_operand:SI 10 "register_operand" "")) | |
2548 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2549 (match_operand:SI 11 "register_operand" "")) | |
2550 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2551 (match_operand:SI 12 "register_operand" "")) | |
2552 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2553 (match_operand:SI 13 "register_operand" "")) | |
2554 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2555 (match_operand:SI 14 "register_operand" "")) | |
2556 (set (mem:SI (plus:SI (match_dup 2) (const_int 48))) | |
2557 (match_operand:SI 15 "register_operand" ""))])] | |
2558 "(XVECLEN (operands[0], 0) == 14)" | |
2559 "smw.bim\t%3, [%1], %15, 0x0" | |
2560 [(set_attr "type" "store_multiple") | |
2561 (set_attr "combo" "13") | |
2562 (set_attr "length" "4")] | |
2563 ) | |
2564 | |
2565 (define_insn "*stm_bim_si12" | |
2566 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2567 [(set (match_operand:SI 1 "register_operand" "=r") | |
2568 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 48))) | |
2569 (set (mem:SI (match_dup 2)) | |
2570 (match_operand:SI 3 "register_operand" "")) | |
2571 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2572 (match_operand:SI 4 "register_operand" "")) | |
2573 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2574 (match_operand:SI 5 "register_operand" "")) | |
2575 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2576 (match_operand:SI 6 "register_operand" "")) | |
2577 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2578 (match_operand:SI 7 "register_operand" "")) | |
2579 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2580 (match_operand:SI 8 "register_operand" "")) | |
2581 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2582 (match_operand:SI 9 "register_operand" "")) | |
2583 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2584 (match_operand:SI 10 "register_operand" "")) | |
2585 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2586 (match_operand:SI 11 "register_operand" "")) | |
2587 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2588 (match_operand:SI 12 "register_operand" "")) | |
2589 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2590 (match_operand:SI 13 "register_operand" "")) | |
2591 (set (mem:SI (plus:SI (match_dup 2) (const_int 44))) | |
2592 (match_operand:SI 14 "register_operand" ""))])] | |
2593 "(XVECLEN (operands[0], 0) == 13)" | |
2594 "smw.bim\t%3, [%1], %14, 0x0" | |
2595 [(set_attr "type" "store_multiple") | |
2596 (set_attr "combo" "12") | |
2597 (set_attr "length" "4")] | |
2598 ) | |
2599 | |
2600 (define_insn "*stm_bim_si11" | |
2601 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2602 [(set (match_operand:SI 1 "register_operand" "=r") | |
2603 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 44))) | |
2604 (set (mem:SI (match_dup 2)) | |
2605 (match_operand:SI 3 "register_operand" "")) | |
2606 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2607 (match_operand:SI 4 "register_operand" "")) | |
2608 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2609 (match_operand:SI 5 "register_operand" "")) | |
2610 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2611 (match_operand:SI 6 "register_operand" "")) | |
2612 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2613 (match_operand:SI 7 "register_operand" "")) | |
2614 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2615 (match_operand:SI 8 "register_operand" "")) | |
2616 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2617 (match_operand:SI 9 "register_operand" "")) | |
2618 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2619 (match_operand:SI 10 "register_operand" "")) | |
2620 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2621 (match_operand:SI 11 "register_operand" "")) | |
2622 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2623 (match_operand:SI 12 "register_operand" "")) | |
2624 (set (mem:SI (plus:SI (match_dup 2) (const_int 40))) | |
2625 (match_operand:SI 13 "register_operand" ""))])] | |
2626 "(XVECLEN (operands[0], 0) == 12)" | |
2627 "smw.bim\t%3, [%1], %13, 0x0" | |
2628 [(set_attr "type" "store_multiple") | |
2629 (set_attr "combo" "11") | |
2630 (set_attr "length" "4")] | |
2631 ) | |
2632 | |
2633 (define_insn "*stm_bim_si10" | |
2634 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2635 [(set (match_operand:SI 1 "register_operand" "=r") | |
2636 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40))) | |
2637 (set (mem:SI (match_dup 2)) | |
2638 (match_operand:SI 3 "register_operand" "")) | |
2639 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2640 (match_operand:SI 4 "register_operand" "")) | |
2641 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2642 (match_operand:SI 5 "register_operand" "")) | |
2643 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2644 (match_operand:SI 6 "register_operand" "")) | |
2645 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2646 (match_operand:SI 7 "register_operand" "")) | |
2647 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2648 (match_operand:SI 8 "register_operand" "")) | |
2649 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2650 (match_operand:SI 9 "register_operand" "")) | |
2651 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2652 (match_operand:SI 10 "register_operand" "")) | |
2653 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2654 (match_operand:SI 11 "register_operand" "")) | |
2655 (set (mem:SI (plus:SI (match_dup 2) (const_int 36))) | |
2656 (match_operand:SI 12 "register_operand" ""))])] | |
2657 "(XVECLEN (operands[0], 0) == 11)" | |
2658 "smw.bim\t%3, [%1], %12, 0x0" | |
2659 [(set_attr "type" "store_multiple") | |
2660 (set_attr "combo" "10") | |
2661 (set_attr "length" "4")] | |
2662 ) | |
2663 | |
2664 (define_insn "*stm_bim_si9" | |
2665 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2666 [(set (match_operand:SI 1 "register_operand" "=r") | |
2667 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36))) | |
2668 (set (mem:SI (match_dup 2)) | |
2669 (match_operand:SI 3 "register_operand" "")) | |
2670 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2671 (match_operand:SI 4 "register_operand" "")) | |
2672 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2673 (match_operand:SI 5 "register_operand" "")) | |
2674 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2675 (match_operand:SI 6 "register_operand" "")) | |
2676 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2677 (match_operand:SI 7 "register_operand" "")) | |
2678 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2679 (match_operand:SI 8 "register_operand" "")) | |
2680 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2681 (match_operand:SI 9 "register_operand" "")) | |
2682 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2683 (match_operand:SI 10 "register_operand" "")) | |
2684 (set (mem:SI (plus:SI (match_dup 2) (const_int 32))) | |
2685 (match_operand:SI 11 "register_operand" ""))])] | |
2686 "(XVECLEN (operands[0], 0) == 10)" | |
2687 "smw.bim\t%3, [%1], %11, 0x0" | |
2688 [(set_attr "type" "store_multiple") | |
2689 (set_attr "combo" "9") | |
2690 (set_attr "length" "4")] | |
2691 ) | |
2692 | |
2693 | |
2694 (define_insn "*stm_bim_si8" | |
2695 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2696 [(set (match_operand:SI 1 "register_operand" "=r") | |
2697 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32))) | |
2698 (set (mem:SI (match_dup 2)) | |
2699 (match_operand:SI 3 "register_operand" "")) | |
2700 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2701 (match_operand:SI 4 "register_operand" "")) | |
2702 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2703 (match_operand:SI 5 "register_operand" "")) | |
2704 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2705 (match_operand:SI 6 "register_operand" "")) | |
2706 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2707 (match_operand:SI 7 "register_operand" "")) | |
2708 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2709 (match_operand:SI 8 "register_operand" "")) | |
2710 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2711 (match_operand:SI 9 "register_operand" "")) | |
2712 (set (mem:SI (plus:SI (match_dup 2) (const_int 28))) | |
2713 (match_operand:SI 10 "register_operand" ""))])] | |
2714 "(XVECLEN (operands[0], 0) == 9)" | |
2715 "smw.bim\t%3, [%1], %10, 0x0" | |
2716 [(set_attr "type" "store_multiple") | |
2717 (set_attr "combo" "8") | |
2718 (set_attr "length" "4")] | |
2719 ) | |
2720 | |
2721 (define_insn "*stm_bim_si7" | |
2722 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2723 [(set (match_operand:SI 1 "register_operand" "=r") | |
2724 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28))) | |
2725 (set (mem:SI (match_dup 2)) | |
2726 (match_operand:SI 3 "register_operand" "")) | |
2727 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2728 (match_operand:SI 4 "register_operand" "")) | |
2729 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2730 (match_operand:SI 5 "register_operand" "")) | |
2731 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2732 (match_operand:SI 6 "register_operand" "")) | |
2733 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2734 (match_operand:SI 7 "register_operand" "")) | |
2735 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2736 (match_operand:SI 8 "register_operand" "")) | |
2737 (set (mem:SI (plus:SI (match_dup 2) (const_int 24))) | |
2738 (match_operand:SI 9 "register_operand" ""))])] | |
2739 "(XVECLEN (operands[0], 0) == 8)" | |
2740 "smw.bim\t%3, [%1], %9, 0x0" | |
2741 [(set_attr "type" "store_multiple") | |
2742 (set_attr "combo" "7") | |
2743 (set_attr "length" "4")] | |
2744 ) | |
2745 | |
2746 (define_insn "*stm_bim_si6" | |
2747 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2748 [(set (match_operand:SI 1 "register_operand" "=r") | |
2749 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24))) | |
2750 (set (mem:SI (match_dup 2)) | |
2751 (match_operand:SI 3 "register_operand" "")) | |
2752 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2753 (match_operand:SI 4 "register_operand" "")) | |
2754 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2755 (match_operand:SI 5 "register_operand" "")) | |
2756 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2757 (match_operand:SI 6 "register_operand" "")) | |
2758 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2759 (match_operand:SI 7 "register_operand" "")) | |
2760 (set (mem:SI (plus:SI (match_dup 2) (const_int 20))) | |
2761 (match_operand:SI 8 "register_operand" ""))])] | |
2762 "(XVECLEN (operands[0], 0) == 7)" | |
2763 "smw.bim\t%3, [%1], %8, 0x0" | |
2764 [(set_attr "type" "store_multiple") | |
2765 (set_attr "combo" "6") | |
2766 (set_attr "length" "4")] | |
2767 ) | |
2768 | |
2769 (define_insn "*stm_bim_si5" | |
2770 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2771 [(set (match_operand:SI 1 "register_operand" "=r") | |
2772 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20))) | |
2773 (set (mem:SI (match_dup 2)) | |
2774 (match_operand:SI 3 "register_operand" "")) | |
2775 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2776 (match_operand:SI 4 "register_operand" "")) | |
2777 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2778 (match_operand:SI 5 "register_operand" "")) | |
2779 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2780 (match_operand:SI 6 "register_operand" "")) | |
2781 (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | |
2782 (match_operand:SI 7 "register_operand" ""))])] | |
2783 "(XVECLEN (operands[0], 0) == 6)" | |
2784 "smw.bim\t%3, [%1], %7, 0x0" | |
2785 [(set_attr "type" "store_multiple") | |
2786 (set_attr "combo" "5") | |
2787 (set_attr "length" "4")] | |
2788 ) | |
2789 | |
2790 (define_insn "*stm_bim_si4" | |
2791 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2792 [(set (match_operand:SI 1 "register_operand" "=r") | |
2793 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16))) | |
2794 (set (mem:SI (match_dup 2)) | |
2795 (match_operand:SI 3 "register_operand" "")) | |
2796 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2797 (match_operand:SI 4 "register_operand" "")) | |
2798 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2799 (match_operand:SI 5 "register_operand" "")) | |
2800 (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | |
2801 (match_operand:SI 6 "register_operand" ""))])] | |
2802 "(XVECLEN (operands[0], 0) == 5)" | |
2803 "smw.bim\t%3, [%1], %6, 0x0" | |
2804 [(set_attr "type" "store_multiple") | |
2805 (set_attr "combo" "4") | |
2806 (set_attr "length" "4")] | |
2807 ) | |
2808 | |
2809 (define_insn "*stm_bim_si3" | |
2810 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2811 [(set (match_operand:SI 1 "register_operand" "=r") | |
2812 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12))) | |
2813 (set (mem:SI (match_dup 2)) | |
2814 (match_operand:SI 3 "register_operand" "")) | |
2815 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2816 (match_operand:SI 4 "register_operand" "")) | |
2817 (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | |
2818 (match_operand:SI 5 "register_operand" ""))])] | |
2819 "(XVECLEN (operands[0], 0) == 4)" | |
2820 "smw.bim\t%3, [%1], %5, 0x0" | |
2821 [(set_attr "type" "store_multiple") | |
2822 (set_attr "combo" "3") | |
2823 (set_attr "length" "4")] | |
2824 ) | |
2825 | |
2826 (define_insn "*stm_bim_si2" | |
2827 [(match_parallel 0 "nds32_store_multiple_and_update_address_operation" | |
2828 [(set (match_operand:SI 1 "register_operand" "=r") | |
2829 (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8))) | |
2830 (set (mem:SI (match_dup 2)) | |
2831 (match_operand:SI 3 "register_operand" "")) | |
2832 (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | |
2833 (match_operand:SI 4 "register_operand" ""))])] | |
2834 "(XVECLEN (operands[0], 0) == 3)" | |
2835 "smw.bim\t%3, [%1], %4, 0x0" | |
2836 [(set_attr "type" "store_multiple") | |
2837 (set_attr "combo" "2") | |
2838 (set_attr "length" "4")] | |
2839 ) | |
2840 | |
2841 (define_expand "unaligned_store_update_base_w" | |
2842 [(parallel [(set (match_operand:SI 0 "register_operand" "=r") | |
2843 (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 4))) | |
2844 (set (mem:SI (match_dup 1)) | |
2845 (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_UASTORE_W))])] | |
2846 "" | |
2847 { | |
2848 emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[1]), operands[2])); | |
2849 emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (4, Pmode))); | |
2850 DONE; | |
2851 } | |
2852 [(set_attr "type" "store_multiple") | |
2853 (set_attr "combo" "1") | |
2854 (set_attr "length" "4")] | |
2855 ) | |
2856 | |
2857 (define_expand "unaligned_store_update_base_dw" | |
2858 [(parallel [(set (match_operand:SI 0 "register_operand" "=r") | |
2859 (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 8))) | |
2860 (set (mem:DI (match_dup 1)) | |
2861 (unspec:DI [(match_operand:DI 2 "register_operand" "r")] UNSPEC_UASTORE_DW))])] | |
2862 "" | |
2863 { | |
2864 /* DO NOT emit unaligned_store_w_m immediately since web pass don't | |
2865 recognize post_inc, try it again after GCC 5.0. | |
2866 REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */ | |
2867 emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[1]), operands[2])); | |
2868 emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (8, Pmode))); | |
2869 DONE; | |
2870 } | |
2871 [(set_attr "type" "store_multiple") | |
2872 (set_attr "combo" "2") | |
2873 (set_attr "length" "4")] | |
2874 ) | |
2875 | |
2876 (define_insn "*stmsi25" | |
2877 [(match_parallel 0 "nds32_store_multiple_operation" | |
2878 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
2879 (match_operand:SI 2 "register_operand" "")) | |
2880 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
2881 (match_operand:SI 3 "register_operand" "")) | |
2882 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
2883 (match_operand:SI 4 "register_operand" "")) | |
2884 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
2885 (match_operand:SI 5 "register_operand" "")) | |
2886 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
2887 (match_operand:SI 6 "register_operand" "")) | |
2888 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
2889 (match_operand:SI 7 "register_operand" "")) | |
2890 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
2891 (match_operand:SI 8 "register_operand" "")) | |
2892 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
2893 (match_operand:SI 9 "register_operand" "")) | |
2894 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
2895 (match_operand:SI 10 "register_operand" "")) | |
2896 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
2897 (match_operand:SI 11 "register_operand" "")) | |
2898 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
2899 (match_operand:SI 12 "register_operand" "")) | |
2900 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
2901 (match_operand:SI 13 "register_operand" "")) | |
2902 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
2903 (match_operand:SI 14 "register_operand" "")) | |
2904 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
2905 (match_operand:SI 15 "register_operand" "")) | |
2906 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
2907 (match_operand:SI 16 "register_operand" "")) | |
2908 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
2909 (match_operand:SI 17 "register_operand" "")) | |
2910 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
2911 (match_operand:SI 18 "register_operand" "")) | |
2912 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
2913 (match_operand:SI 19 "register_operand" "")) | |
2914 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
2915 (match_operand:SI 20 "register_operand" "")) | |
2916 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
2917 (match_operand:SI 21 "register_operand" "")) | |
2918 (set (mem:SI (plus:SI (match_dup 1) (const_int 80))) | |
2919 (match_operand:SI 22 "register_operand" "")) | |
2920 (set (mem:SI (plus:SI (match_dup 1) (const_int 84))) | |
2921 (match_operand:SI 23 "register_operand" "")) | |
2922 (set (mem:SI (plus:SI (match_dup 1) (const_int 88))) | |
2923 (match_operand:SI 24 "register_operand" "")) | |
2924 (set (mem:SI (plus:SI (match_dup 1) (const_int 92))) | |
2925 (match_operand:SI 25 "register_operand" "")) | |
2926 (set (mem:SI (plus:SI (match_dup 1) (const_int 96))) | |
2927 (match_operand:SI 26 "register_operand" ""))])] | |
2928 "(XVECLEN (operands[0], 0) == 25)" | |
2929 "smw.bi\t%2, [%1], %26, 0x0" | |
2930 [(set_attr "type" "store_multiple") | |
2931 (set_attr "combo" "25") | |
2932 (set_attr "length" "4")] | |
2933 ) | |
2934 | |
2935 (define_insn "*stmsi24" | |
2936 [(match_parallel 0 "nds32_store_multiple_operation" | |
2937 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
2938 (match_operand:SI 2 "register_operand" "")) | |
2939 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
2940 (match_operand:SI 3 "register_operand" "")) | |
2941 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
2942 (match_operand:SI 4 "register_operand" "")) | |
2943 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
2944 (match_operand:SI 5 "register_operand" "")) | |
2945 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
2946 (match_operand:SI 6 "register_operand" "")) | |
2947 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
2948 (match_operand:SI 7 "register_operand" "")) | |
2949 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
2950 (match_operand:SI 8 "register_operand" "")) | |
2951 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
2952 (match_operand:SI 9 "register_operand" "")) | |
2953 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
2954 (match_operand:SI 10 "register_operand" "")) | |
2955 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
2956 (match_operand:SI 11 "register_operand" "")) | |
2957 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
2958 (match_operand:SI 12 "register_operand" "")) | |
2959 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
2960 (match_operand:SI 13 "register_operand" "")) | |
2961 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
2962 (match_operand:SI 14 "register_operand" "")) | |
2963 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
2964 (match_operand:SI 15 "register_operand" "")) | |
2965 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
2966 (match_operand:SI 16 "register_operand" "")) | |
2967 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
2968 (match_operand:SI 17 "register_operand" "")) | |
2969 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
2970 (match_operand:SI 18 "register_operand" "")) | |
2971 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
2972 (match_operand:SI 19 "register_operand" "")) | |
2973 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
2974 (match_operand:SI 20 "register_operand" "")) | |
2975 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
2976 (match_operand:SI 21 "register_operand" "")) | |
2977 (set (mem:SI (plus:SI (match_dup 1) (const_int 80))) | |
2978 (match_operand:SI 22 "register_operand" "")) | |
2979 (set (mem:SI (plus:SI (match_dup 1) (const_int 84))) | |
2980 (match_operand:SI 23 "register_operand" "")) | |
2981 (set (mem:SI (plus:SI (match_dup 1) (const_int 88))) | |
2982 (match_operand:SI 24 "register_operand" "")) | |
2983 (set (mem:SI (plus:SI (match_dup 1) (const_int 92))) | |
2984 (match_operand:SI 25 "register_operand" "")) | |
2985 ])] | |
2986 "(XVECLEN (operands[0], 0) == 24)" | |
2987 "smw.bi\t%2, [%1], %25, 0x0" | |
2988 [(set_attr "type" "store_multiple") | |
2989 (set_attr "combo" "24") | |
2990 (set_attr "length" "4")] | |
2991 ) | |
2992 | |
2993 (define_insn "*stmsi23" | |
2994 [(match_parallel 0 "nds32_store_multiple_operation" | |
2995 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
2996 (match_operand:SI 2 "register_operand" "")) | |
2997 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
2998 (match_operand:SI 3 "register_operand" "")) | |
2999 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3000 (match_operand:SI 4 "register_operand" "")) | |
3001 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3002 (match_operand:SI 5 "register_operand" "")) | |
3003 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3004 (match_operand:SI 6 "register_operand" "")) | |
3005 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3006 (match_operand:SI 7 "register_operand" "")) | |
3007 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3008 (match_operand:SI 8 "register_operand" "")) | |
3009 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3010 (match_operand:SI 9 "register_operand" "")) | |
3011 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3012 (match_operand:SI 10 "register_operand" "")) | |
3013 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3014 (match_operand:SI 11 "register_operand" "")) | |
3015 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3016 (match_operand:SI 12 "register_operand" "")) | |
3017 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3018 (match_operand:SI 13 "register_operand" "")) | |
3019 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3020 (match_operand:SI 14 "register_operand" "")) | |
3021 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3022 (match_operand:SI 15 "register_operand" "")) | |
3023 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3024 (match_operand:SI 16 "register_operand" "")) | |
3025 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3026 (match_operand:SI 17 "register_operand" "")) | |
3027 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3028 (match_operand:SI 18 "register_operand" "")) | |
3029 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3030 (match_operand:SI 19 "register_operand" "")) | |
3031 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
3032 (match_operand:SI 20 "register_operand" "")) | |
3033 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
3034 (match_operand:SI 21 "register_operand" "")) | |
3035 (set (mem:SI (plus:SI (match_dup 1) (const_int 80))) | |
3036 (match_operand:SI 22 "register_operand" "")) | |
3037 (set (mem:SI (plus:SI (match_dup 1) (const_int 84))) | |
3038 (match_operand:SI 23 "register_operand" "")) | |
3039 (set (mem:SI (plus:SI (match_dup 1) (const_int 88))) | |
3040 (match_operand:SI 24 "register_operand" "")) | |
3041 ])] | |
3042 "(XVECLEN (operands[0], 0) == 23)" | |
3043 "smw.bi\t%2, [%1], %24, 0x0" | |
3044 [(set_attr "type" "store_multiple") | |
3045 (set_attr "combo" "23") | |
3046 (set_attr "length" "4")] | |
3047 ) | |
3048 | |
3049 (define_insn "*stmsi22" | |
3050 [(match_parallel 0 "nds32_store_multiple_operation" | |
3051 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3052 (match_operand:SI 2 "register_operand" "")) | |
3053 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3054 (match_operand:SI 3 "register_operand" "")) | |
3055 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3056 (match_operand:SI 4 "register_operand" "")) | |
3057 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3058 (match_operand:SI 5 "register_operand" "")) | |
3059 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3060 (match_operand:SI 6 "register_operand" "")) | |
3061 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3062 (match_operand:SI 7 "register_operand" "")) | |
3063 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3064 (match_operand:SI 8 "register_operand" "")) | |
3065 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3066 (match_operand:SI 9 "register_operand" "")) | |
3067 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3068 (match_operand:SI 10 "register_operand" "")) | |
3069 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3070 (match_operand:SI 11 "register_operand" "")) | |
3071 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3072 (match_operand:SI 12 "register_operand" "")) | |
3073 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3074 (match_operand:SI 13 "register_operand" "")) | |
3075 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3076 (match_operand:SI 14 "register_operand" "")) | |
3077 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3078 (match_operand:SI 15 "register_operand" "")) | |
3079 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3080 (match_operand:SI 16 "register_operand" "")) | |
3081 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3082 (match_operand:SI 17 "register_operand" "")) | |
3083 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3084 (match_operand:SI 18 "register_operand" "")) | |
3085 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3086 (match_operand:SI 19 "register_operand" "")) | |
3087 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
3088 (match_operand:SI 20 "register_operand" "")) | |
3089 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
3090 (match_operand:SI 21 "register_operand" "")) | |
3091 (set (mem:SI (plus:SI (match_dup 1) (const_int 80))) | |
3092 (match_operand:SI 22 "register_operand" "")) | |
3093 (set (mem:SI (plus:SI (match_dup 1) (const_int 84))) | |
3094 (match_operand:SI 23 "register_operand" "")) | |
3095 ])] | |
3096 "(XVECLEN (operands[0], 0) == 22)" | |
3097 "smw.bi\t%2, [%1], %23, 0x0" | |
3098 [(set_attr "type" "store_multiple") | |
3099 (set_attr "combo" "22") | |
3100 (set_attr "length" "4")] | |
3101 ) | |
3102 | |
3103 (define_insn "*stmsi21" | |
3104 [(match_parallel 0 "nds32_store_multiple_operation" | |
3105 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3106 (match_operand:SI 2 "register_operand" "")) | |
3107 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3108 (match_operand:SI 3 "register_operand" "")) | |
3109 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3110 (match_operand:SI 4 "register_operand" "")) | |
3111 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3112 (match_operand:SI 5 "register_operand" "")) | |
3113 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3114 (match_operand:SI 6 "register_operand" "")) | |
3115 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3116 (match_operand:SI 7 "register_operand" "")) | |
3117 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3118 (match_operand:SI 8 "register_operand" "")) | |
3119 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3120 (match_operand:SI 9 "register_operand" "")) | |
3121 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3122 (match_operand:SI 10 "register_operand" "")) | |
3123 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3124 (match_operand:SI 11 "register_operand" "")) | |
3125 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3126 (match_operand:SI 12 "register_operand" "")) | |
3127 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3128 (match_operand:SI 13 "register_operand" "")) | |
3129 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3130 (match_operand:SI 14 "register_operand" "")) | |
3131 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3132 (match_operand:SI 15 "register_operand" "")) | |
3133 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3134 (match_operand:SI 16 "register_operand" "")) | |
3135 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3136 (match_operand:SI 17 "register_operand" "")) | |
3137 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3138 (match_operand:SI 18 "register_operand" "")) | |
3139 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3140 (match_operand:SI 19 "register_operand" "")) | |
3141 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
3142 (match_operand:SI 20 "register_operand" "")) | |
3143 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
3144 (match_operand:SI 21 "register_operand" "")) | |
3145 (set (mem:SI (plus:SI (match_dup 1) (const_int 80))) | |
3146 (match_operand:SI 22 "register_operand" "")) | |
3147 ])] | |
3148 "(XVECLEN (operands[0], 0) == 21)" | |
3149 "smw.bi\t%2, [%1], %22, 0x0" | |
3150 [(set_attr "type" "store_multiple") | |
3151 (set_attr "combo" "21") | |
3152 (set_attr "length" "4")] | |
3153 ) | |
3154 | |
3155 (define_insn "*stmsi20" | |
3156 [(match_parallel 0 "nds32_store_multiple_operation" | |
3157 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3158 (match_operand:SI 2 "register_operand" "")) | |
3159 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3160 (match_operand:SI 3 "register_operand" "")) | |
3161 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3162 (match_operand:SI 4 "register_operand" "")) | |
3163 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3164 (match_operand:SI 5 "register_operand" "")) | |
3165 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3166 (match_operand:SI 6 "register_operand" "")) | |
3167 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3168 (match_operand:SI 7 "register_operand" "")) | |
3169 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3170 (match_operand:SI 8 "register_operand" "")) | |
3171 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3172 (match_operand:SI 9 "register_operand" "")) | |
3173 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3174 (match_operand:SI 10 "register_operand" "")) | |
3175 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3176 (match_operand:SI 11 "register_operand" "")) | |
3177 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3178 (match_operand:SI 12 "register_operand" "")) | |
3179 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3180 (match_operand:SI 13 "register_operand" "")) | |
3181 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3182 (match_operand:SI 14 "register_operand" "")) | |
3183 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3184 (match_operand:SI 15 "register_operand" "")) | |
3185 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3186 (match_operand:SI 16 "register_operand" "")) | |
3187 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3188 (match_operand:SI 17 "register_operand" "")) | |
3189 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3190 (match_operand:SI 18 "register_operand" "")) | |
3191 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3192 (match_operand:SI 19 "register_operand" "")) | |
3193 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
3194 (match_operand:SI 20 "register_operand" "")) | |
3195 (set (mem:SI (plus:SI (match_dup 1) (const_int 76))) | |
3196 (match_operand:SI 21 "register_operand" ""))])] | |
3197 "(XVECLEN (operands[0], 0) == 20)" | |
3198 "smw.bi\t%2, [%1], %21, 0x0" | |
3199 [(set_attr "type" "store_multiple") | |
3200 (set_attr "combo" "20") | |
3201 (set_attr "length" "4")] | |
3202 ) | |
3203 | |
3204 (define_insn "*stmsi19" | |
3205 [(match_parallel 0 "nds32_store_multiple_operation" | |
3206 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3207 (match_operand:SI 2 "register_operand" "")) | |
3208 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3209 (match_operand:SI 3 "register_operand" "")) | |
3210 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3211 (match_operand:SI 4 "register_operand" "")) | |
3212 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3213 (match_operand:SI 5 "register_operand" "")) | |
3214 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3215 (match_operand:SI 6 "register_operand" "")) | |
3216 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3217 (match_operand:SI 7 "register_operand" "")) | |
3218 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3219 (match_operand:SI 8 "register_operand" "")) | |
3220 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3221 (match_operand:SI 9 "register_operand" "")) | |
3222 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3223 (match_operand:SI 10 "register_operand" "")) | |
3224 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3225 (match_operand:SI 11 "register_operand" "")) | |
3226 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3227 (match_operand:SI 12 "register_operand" "")) | |
3228 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3229 (match_operand:SI 13 "register_operand" "")) | |
3230 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3231 (match_operand:SI 14 "register_operand" "")) | |
3232 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3233 (match_operand:SI 15 "register_operand" "")) | |
3234 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3235 (match_operand:SI 16 "register_operand" "")) | |
3236 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3237 (match_operand:SI 17 "register_operand" "")) | |
3238 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3239 (match_operand:SI 18 "register_operand" "")) | |
3240 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3241 (match_operand:SI 19 "register_operand" "")) | |
3242 (set (mem:SI (plus:SI (match_dup 1) (const_int 72))) | |
3243 (match_operand:SI 20 "register_operand" ""))])] | |
3244 "(XVECLEN (operands[0], 0) == 19)" | |
3245 "smw.bi\t%2, [%1], %20, 0x0" | |
3246 [(set_attr "type" "store_multiple") | |
3247 (set_attr "combo" "19") | |
3248 (set_attr "length" "4")] | |
3249 ) | |
3250 | |
3251 (define_insn "*stmsi18" | |
3252 [(match_parallel 0 "nds32_store_multiple_operation" | |
3253 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3254 (match_operand:SI 2 "register_operand" "")) | |
3255 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3256 (match_operand:SI 3 "register_operand" "")) | |
3257 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3258 (match_operand:SI 4 "register_operand" "")) | |
3259 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3260 (match_operand:SI 5 "register_operand" "")) | |
3261 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3262 (match_operand:SI 6 "register_operand" "")) | |
3263 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3264 (match_operand:SI 7 "register_operand" "")) | |
3265 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3266 (match_operand:SI 8 "register_operand" "")) | |
3267 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3268 (match_operand:SI 9 "register_operand" "")) | |
3269 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3270 (match_operand:SI 10 "register_operand" "")) | |
3271 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3272 (match_operand:SI 11 "register_operand" "")) | |
3273 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3274 (match_operand:SI 12 "register_operand" "")) | |
3275 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3276 (match_operand:SI 13 "register_operand" "")) | |
3277 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3278 (match_operand:SI 14 "register_operand" "")) | |
3279 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3280 (match_operand:SI 15 "register_operand" "")) | |
3281 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3282 (match_operand:SI 16 "register_operand" "")) | |
3283 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3284 (match_operand:SI 17 "register_operand" "")) | |
3285 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3286 (match_operand:SI 18 "register_operand" "")) | |
3287 (set (mem:SI (plus:SI (match_dup 1) (const_int 68))) | |
3288 (match_operand:SI 19 "register_operand" ""))])] | |
3289 "(XVECLEN (operands[0], 0) == 18)" | |
3290 "smw.bi\t%2, [%1], %19, 0x0" | |
3291 [(set_attr "type" "store_multiple") | |
3292 (set_attr "combo" "18") | |
3293 (set_attr "length" "4")] | |
3294 ) | |
3295 | |
3296 (define_insn "*stmsi17" | |
3297 [(match_parallel 0 "nds32_store_multiple_operation" | |
3298 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3299 (match_operand:SI 2 "register_operand" "")) | |
3300 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3301 (match_operand:SI 3 "register_operand" "")) | |
3302 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3303 (match_operand:SI 4 "register_operand" "")) | |
3304 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3305 (match_operand:SI 5 "register_operand" "")) | |
3306 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3307 (match_operand:SI 6 "register_operand" "")) | |
3308 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3309 (match_operand:SI 7 "register_operand" "")) | |
3310 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3311 (match_operand:SI 8 "register_operand" "")) | |
3312 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3313 (match_operand:SI 9 "register_operand" "")) | |
3314 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3315 (match_operand:SI 10 "register_operand" "")) | |
3316 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3317 (match_operand:SI 11 "register_operand" "")) | |
3318 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3319 (match_operand:SI 12 "register_operand" "")) | |
3320 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3321 (match_operand:SI 13 "register_operand" "")) | |
3322 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3323 (match_operand:SI 14 "register_operand" "")) | |
3324 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3325 (match_operand:SI 15 "register_operand" "")) | |
3326 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3327 (match_operand:SI 16 "register_operand" "")) | |
3328 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3329 (match_operand:SI 17 "register_operand" "")) | |
3330 (set (mem:SI (plus:SI (match_dup 1) (const_int 64))) | |
3331 (match_operand:SI 18 "register_operand" ""))])] | |
3332 "(XVECLEN (operands[0], 0) == 17)" | |
3333 "smw.bi\t%2, [%1], %18, 0x0" | |
3334 [(set_attr "type" "store_multiple") | |
3335 (set_attr "combo" "17") | |
3336 (set_attr "length" "4")] | |
3337 ) | |
3338 | |
3339 (define_insn "*stmsi16" | |
3340 [(match_parallel 0 "nds32_store_multiple_operation" | |
3341 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3342 (match_operand:SI 2 "register_operand" "")) | |
3343 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3344 (match_operand:SI 3 "register_operand" "")) | |
3345 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3346 (match_operand:SI 4 "register_operand" "")) | |
3347 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3348 (match_operand:SI 5 "register_operand" "")) | |
3349 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3350 (match_operand:SI 6 "register_operand" "")) | |
3351 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3352 (match_operand:SI 7 "register_operand" "")) | |
3353 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3354 (match_operand:SI 8 "register_operand" "")) | |
3355 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3356 (match_operand:SI 9 "register_operand" "")) | |
3357 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3358 (match_operand:SI 10 "register_operand" "")) | |
3359 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3360 (match_operand:SI 11 "register_operand" "")) | |
3361 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3362 (match_operand:SI 12 "register_operand" "")) | |
3363 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3364 (match_operand:SI 13 "register_operand" "")) | |
3365 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3366 (match_operand:SI 14 "register_operand" "")) | |
3367 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3368 (match_operand:SI 15 "register_operand" "")) | |
3369 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3370 (match_operand:SI 16 "register_operand" "")) | |
3371 (set (mem:SI (plus:SI (match_dup 1) (const_int 60))) | |
3372 (match_operand:SI 17 "register_operand" ""))])] | |
3373 "(XVECLEN (operands[0], 0) == 16)" | |
3374 "smw.bi\t%2, [%1], %17, 0x0" | |
3375 [(set_attr "type" "store_multiple") | |
3376 (set_attr "combo" "16") | |
3377 (set_attr "length" "4")] | |
3378 ) | |
3379 | |
3380 (define_insn "*stmsi15" | |
3381 [(match_parallel 0 "nds32_store_multiple_operation" | |
3382 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3383 (match_operand:SI 2 "register_operand" "")) | |
3384 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3385 (match_operand:SI 3 "register_operand" "")) | |
3386 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3387 (match_operand:SI 4 "register_operand" "")) | |
3388 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3389 (match_operand:SI 5 "register_operand" "")) | |
3390 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3391 (match_operand:SI 6 "register_operand" "")) | |
3392 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3393 (match_operand:SI 7 "register_operand" "")) | |
3394 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3395 (match_operand:SI 8 "register_operand" "")) | |
3396 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3397 (match_operand:SI 9 "register_operand" "")) | |
3398 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3399 (match_operand:SI 10 "register_operand" "")) | |
3400 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3401 (match_operand:SI 11 "register_operand" "")) | |
3402 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3403 (match_operand:SI 12 "register_operand" "")) | |
3404 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3405 (match_operand:SI 13 "register_operand" "")) | |
3406 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3407 (match_operand:SI 14 "register_operand" "")) | |
3408 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3409 (match_operand:SI 15 "register_operand" "")) | |
3410 (set (mem:SI (plus:SI (match_dup 1) (const_int 56))) | |
3411 (match_operand:SI 16 "register_operand" ""))])] | |
3412 "(XVECLEN (operands[0], 0) == 15)" | |
3413 "smw.bi\t%2, [%1], %16, 0x0" | |
3414 [(set_attr "type" "store_multiple") | |
3415 (set_attr "combo" "15") | |
3416 (set_attr "length" "4")] | |
3417 ) | |
3418 | |
3419 (define_insn "*stmsi14" | |
3420 [(match_parallel 0 "nds32_store_multiple_operation" | |
3421 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3422 (match_operand:SI 2 "register_operand" "")) | |
3423 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3424 (match_operand:SI 3 "register_operand" "")) | |
3425 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3426 (match_operand:SI 4 "register_operand" "")) | |
3427 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3428 (match_operand:SI 5 "register_operand" "")) | |
3429 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3430 (match_operand:SI 6 "register_operand" "")) | |
3431 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3432 (match_operand:SI 7 "register_operand" "")) | |
3433 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3434 (match_operand:SI 8 "register_operand" "")) | |
3435 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3436 (match_operand:SI 9 "register_operand" "")) | |
3437 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3438 (match_operand:SI 10 "register_operand" "")) | |
3439 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3440 (match_operand:SI 11 "register_operand" "")) | |
3441 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3442 (match_operand:SI 12 "register_operand" "")) | |
3443 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3444 (match_operand:SI 13 "register_operand" "")) | |
3445 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3446 (match_operand:SI 14 "register_operand" "")) | |
3447 (set (mem:SI (plus:SI (match_dup 1) (const_int 52))) | |
3448 (match_operand:SI 15 "register_operand" ""))])] | |
3449 "(XVECLEN (operands[0], 0) == 14)" | |
3450 "smw.bi\t%2, [%1], %15, 0x0" | |
3451 [(set_attr "type" "store_multiple") | |
3452 (set_attr "combo" "14") | |
3453 (set_attr "length" "4")] | |
3454 ) | |
3455 | |
3456 (define_insn "*stmsi13" | |
3457 [(match_parallel 0 "nds32_store_multiple_operation" | |
3458 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3459 (match_operand:SI 2 "register_operand" "")) | |
3460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3461 (match_operand:SI 3 "register_operand" "")) | |
3462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3463 (match_operand:SI 4 "register_operand" "")) | |
3464 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3465 (match_operand:SI 5 "register_operand" "")) | |
3466 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3467 (match_operand:SI 6 "register_operand" "")) | |
3468 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3469 (match_operand:SI 7 "register_operand" "")) | |
3470 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3471 (match_operand:SI 8 "register_operand" "")) | |
3472 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3473 (match_operand:SI 9 "register_operand" "")) | |
3474 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3475 (match_operand:SI 10 "register_operand" "")) | |
3476 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3477 (match_operand:SI 11 "register_operand" "")) | |
3478 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3479 (match_operand:SI 12 "register_operand" "")) | |
3480 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3481 (match_operand:SI 13 "register_operand" "")) | |
3482 (set (mem:SI (plus:SI (match_dup 1) (const_int 48))) | |
3483 (match_operand:SI 14 "register_operand" ""))])] | |
3484 "(XVECLEN (operands[0], 0) == 13)" | |
3485 "smw.bi\t%2, [%1], %14, 0x0" | |
3486 [(set_attr "type" "store_multiple") | |
3487 (set_attr "combo" "13") | |
3488 (set_attr "length" "4")] | |
3489 ) | |
3490 | |
3491 (define_insn "*stmsi12" | |
3492 [(match_parallel 0 "nds32_store_multiple_operation" | |
3493 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3494 (match_operand:SI 2 "register_operand" "")) | |
3495 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3496 (match_operand:SI 3 "register_operand" "")) | |
3497 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3498 (match_operand:SI 4 "register_operand" "")) | |
3499 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3500 (match_operand:SI 5 "register_operand" "")) | |
3501 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3502 (match_operand:SI 6 "register_operand" "")) | |
3503 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3504 (match_operand:SI 7 "register_operand" "")) | |
3505 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3506 (match_operand:SI 8 "register_operand" "")) | |
3507 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3508 (match_operand:SI 9 "register_operand" "")) | |
3509 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3510 (match_operand:SI 10 "register_operand" "")) | |
3511 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3512 (match_operand:SI 11 "register_operand" "")) | |
3513 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3514 (match_operand:SI 12 "register_operand" "")) | |
3515 (set (mem:SI (plus:SI (match_dup 1) (const_int 44))) | |
3516 (match_operand:SI 13 "register_operand" ""))])] | |
3517 "(XVECLEN (operands[0], 0) == 12)" | |
3518 "smw.bi\t%2, [%1], %13, 0x0" | |
3519 [(set_attr "type" "store_multiple") | |
3520 (set_attr "combo" "12") | |
3521 (set_attr "length" "4")] | |
3522 ) | |
3523 | |
3524 (define_insn "*stmsi11" | |
3525 [(match_parallel 0 "nds32_store_multiple_operation" | |
3526 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3527 (match_operand:SI 2 "register_operand" "")) | |
3528 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3529 (match_operand:SI 3 "register_operand" "")) | |
3530 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3531 (match_operand:SI 4 "register_operand" "")) | |
3532 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3533 (match_operand:SI 5 "register_operand" "")) | |
3534 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3535 (match_operand:SI 6 "register_operand" "")) | |
3536 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3537 (match_operand:SI 7 "register_operand" "")) | |
3538 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3539 (match_operand:SI 8 "register_operand" "")) | |
3540 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3541 (match_operand:SI 9 "register_operand" "")) | |
3542 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3543 (match_operand:SI 10 "register_operand" "")) | |
3544 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3545 (match_operand:SI 11 "register_operand" "")) | |
3546 (set (mem:SI (plus:SI (match_dup 1) (const_int 40))) | |
3547 (match_operand:SI 12 "register_operand" ""))])] | |
3548 "(XVECLEN (operands[0], 0) == 11)" | |
3549 "smw.bi\t%2, [%1], %12, 0x0" | |
3550 [(set_attr "type" "store_multiple") | |
3551 (set_attr "combo" "11") | |
3552 (set_attr "length" "4")] | |
3553 ) | |
3554 | |
3555 (define_insn "*stmsi10" | |
3556 [(match_parallel 0 "nds32_store_multiple_operation" | |
3557 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3558 (match_operand:SI 2 "register_operand" "")) | |
3559 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3560 (match_operand:SI 3 "register_operand" "")) | |
3561 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3562 (match_operand:SI 4 "register_operand" "")) | |
3563 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3564 (match_operand:SI 5 "register_operand" "")) | |
3565 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3566 (match_operand:SI 6 "register_operand" "")) | |
3567 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3568 (match_operand:SI 7 "register_operand" "")) | |
3569 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3570 (match_operand:SI 8 "register_operand" "")) | |
3571 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3572 (match_operand:SI 9 "register_operand" "")) | |
3573 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3574 (match_operand:SI 10 "register_operand" "")) | |
3575 (set (mem:SI (plus:SI (match_dup 1) (const_int 36))) | |
3576 (match_operand:SI 11 "register_operand" ""))])] | |
3577 "(XVECLEN (operands[0], 0) == 10)" | |
3578 "smw.bi\t%2, [%1], %11, 0x0" | |
3579 [(set_attr "type" "store_multiple") | |
3580 (set_attr "combo" "10") | |
3581 (set_attr "length" "4")] | |
3582 ) | |
3583 | |
3584 (define_insn "*stmsi9" | |
3585 [(match_parallel 0 "nds32_store_multiple_operation" | |
3586 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
3587 (match_operand:SI 2 "register_operand" "")) | |
3588 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
3589 (match_operand:SI 3 "register_operand" "")) | |
3590 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
3591 (match_operand:SI 4 "register_operand" "")) | |
3592 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
3593 (match_operand:SI 5 "register_operand" "")) | |
3594 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
3595 (match_operand:SI 6 "register_operand" "")) | |
3596 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
3597 (match_operand:SI 7 "register_operand" "")) | |
3598 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
3599 (match_operand:SI 8 "register_operand" "")) | |
3600 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
3601 (match_operand:SI 9 "register_operand" "")) | |
3602 (set (mem:SI (plus:SI (match_dup 1) (const_int 32))) | |
3603 (match_operand:SI 10 "register_operand" ""))])] | |
3604 "(XVECLEN (operands[0], 0) == 9)" | |
3605 "smw.bi\t%2, [%1], %10, 0x0" | |
3606 [(set_attr "type" "store_multiple") | |
3607 (set_attr "combo" "9") | |
3608 (set_attr "length" "4")] | |
3609 ) | |
258 | 3610 |
259 (define_insn "*stmsi8" | 3611 (define_insn "*stmsi8" |
260 [(match_parallel 0 "nds32_store_multiple_operation" | 3612 [(match_parallel 0 "nds32_store_multiple_operation" |
261 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3613 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
262 (match_operand:SI 2 "register_operand" "")) | 3614 (match_operand:SI 2 "register_operand" "")) |
274 (match_operand:SI 8 "register_operand" "")) | 3626 (match_operand:SI 8 "register_operand" "")) |
275 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | 3627 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) |
276 (match_operand:SI 9 "register_operand" ""))])] | 3628 (match_operand:SI 9 "register_operand" ""))])] |
277 "(XVECLEN (operands[0], 0) == 8)" | 3629 "(XVECLEN (operands[0], 0) == 8)" |
278 "smw.bi\t%2, [%1], %9, 0x0" | 3630 "smw.bi\t%2, [%1], %9, 0x0" |
279 [(set_attr "type" "store") | 3631 [(set_attr "type" "store_multiple") |
280 (set_attr "length" "4")] | 3632 (set_attr "combo" "8") |
3633 (set_attr "length" "4")] | |
281 ) | 3634 ) |
282 | 3635 |
283 (define_insn "*stmsi7" | 3636 (define_insn "*stmsi7" |
284 [(match_parallel 0 "nds32_store_multiple_operation" | 3637 [(match_parallel 0 "nds32_store_multiple_operation" |
285 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3638 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
296 (match_operand:SI 7 "register_operand" "")) | 3649 (match_operand:SI 7 "register_operand" "")) |
297 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | 3650 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) |
298 (match_operand:SI 8 "register_operand" ""))])] | 3651 (match_operand:SI 8 "register_operand" ""))])] |
299 "(XVECLEN (operands[0], 0) == 7)" | 3652 "(XVECLEN (operands[0], 0) == 7)" |
300 "smw.bi\t%2, [%1], %8, 0x0" | 3653 "smw.bi\t%2, [%1], %8, 0x0" |
301 [(set_attr "type" "store") | 3654 [(set_attr "type" "store_multiple") |
302 (set_attr "length" "4")] | 3655 (set_attr "combo" "7") |
3656 (set_attr "length" "4")] | |
303 ) | 3657 ) |
304 | 3658 |
305 (define_insn "*stmsi6" | 3659 (define_insn "*stmsi6" |
306 [(match_parallel 0 "nds32_store_multiple_operation" | 3660 [(match_parallel 0 "nds32_store_multiple_operation" |
307 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3661 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
316 (match_operand:SI 6 "register_operand" "")) | 3670 (match_operand:SI 6 "register_operand" "")) |
317 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | 3671 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) |
318 (match_operand:SI 7 "register_operand" ""))])] | 3672 (match_operand:SI 7 "register_operand" ""))])] |
319 "(XVECLEN (operands[0], 0) == 6)" | 3673 "(XVECLEN (operands[0], 0) == 6)" |
320 "smw.bi\t%2, [%1], %7, 0x0" | 3674 "smw.bi\t%2, [%1], %7, 0x0" |
321 [(set_attr "type" "store") | 3675 [(set_attr "type" "store_multiple") |
322 (set_attr "length" "4")] | 3676 (set_attr "combo" "6") |
3677 (set_attr "length" "4")] | |
323 ) | 3678 ) |
324 | 3679 |
325 (define_insn "*stmsi5" | 3680 (define_insn "*stmsi5" |
326 [(match_parallel 0 "nds32_store_multiple_operation" | 3681 [(match_parallel 0 "nds32_store_multiple_operation" |
327 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3682 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
334 (match_operand:SI 5 "register_operand" "")) | 3689 (match_operand:SI 5 "register_operand" "")) |
335 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | 3690 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) |
336 (match_operand:SI 6 "register_operand" ""))])] | 3691 (match_operand:SI 6 "register_operand" ""))])] |
337 "(XVECLEN (operands[0], 0) == 5)" | 3692 "(XVECLEN (operands[0], 0) == 5)" |
338 "smw.bi\t%2, [%1], %6, 0x0" | 3693 "smw.bi\t%2, [%1], %6, 0x0" |
339 [(set_attr "type" "store") | 3694 [(set_attr "type" "store_multiple") |
340 (set_attr "length" "4")] | 3695 (set_attr "combo" "5") |
3696 (set_attr "length" "4")] | |
341 ) | 3697 ) |
342 | 3698 |
343 (define_insn "*stmsi4" | 3699 (define_insn "*stmsi4" |
344 [(match_parallel 0 "nds32_store_multiple_operation" | 3700 [(match_parallel 0 "nds32_store_multiple_operation" |
345 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3701 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
350 (match_operand:SI 4 "register_operand" "")) | 3706 (match_operand:SI 4 "register_operand" "")) |
351 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | 3707 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) |
352 (match_operand:SI 5 "register_operand" ""))])] | 3708 (match_operand:SI 5 "register_operand" ""))])] |
353 "(XVECLEN (operands[0], 0) == 4)" | 3709 "(XVECLEN (operands[0], 0) == 4)" |
354 "smw.bi\t%2, [%1], %5, 0x0" | 3710 "smw.bi\t%2, [%1], %5, 0x0" |
355 [(set_attr "type" "store") | 3711 [(set_attr "type" "store_multiple") |
356 (set_attr "length" "4")] | 3712 (set_attr "combo" "4") |
3713 (set_attr "length" "4")] | |
357 ) | 3714 ) |
358 | 3715 |
359 (define_insn "*stmsi3" | 3716 (define_insn "*stmsi3" |
360 [(match_parallel 0 "nds32_store_multiple_operation" | 3717 [(match_parallel 0 "nds32_store_multiple_operation" |
361 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3718 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
364 (match_operand:SI 3 "register_operand" "")) | 3721 (match_operand:SI 3 "register_operand" "")) |
365 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | 3722 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) |
366 (match_operand:SI 4 "register_operand" ""))])] | 3723 (match_operand:SI 4 "register_operand" ""))])] |
367 "(XVECLEN (operands[0], 0) == 3)" | 3724 "(XVECLEN (operands[0], 0) == 3)" |
368 "smw.bi\t%2, [%1], %4, 0x0" | 3725 "smw.bi\t%2, [%1], %4, 0x0" |
369 [(set_attr "type" "store") | 3726 [(set_attr "type" "store_multiple") |
370 (set_attr "length" "4")] | 3727 (set_attr "combo" "3") |
3728 (set_attr "length" "4")] | |
371 ) | 3729 ) |
372 | 3730 |
373 (define_insn "*stmsi2" | 3731 (define_insn "*stmsi2" |
374 [(match_parallel 0 "nds32_store_multiple_operation" | 3732 [(match_parallel 0 "nds32_store_multiple_operation" |
375 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) | 3733 [(set (mem:SI (match_operand:SI 1 "register_operand" "r")) |
376 (match_operand:SI 2 "register_operand" "")) | 3734 (match_operand:SI 2 "register_operand" "")) |
377 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | 3735 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) |
378 (match_operand:SI 3 "register_operand" ""))])] | 3736 (match_operand:SI 3 "register_operand" ""))])] |
379 "(XVECLEN (operands[0], 0) == 2)" | 3737 "(XVECLEN (operands[0], 0) == 2)" |
380 "smw.bi\t%2, [%1], %3, 0x0" | 3738 "smw.bi\t%2, [%1], %3, 0x0" |
381 [(set_attr "type" "store") | 3739 [(set_attr "type" "store_multiple") |
382 (set_attr "length" "4")] | 3740 (set_attr "combo" "2") |
3741 (set_attr "length" "4")] | |
383 ) | 3742 ) |
384 | 3743 |
385 ;; Move a block of memory if it is word aligned and MORE than 2 words long. | 3744 ;; Move a block of memory if it is word aligned and MORE than 2 words long. |
386 ;; We could let this apply for blocks of less than this, but it clobbers so | 3745 ;; We could let this apply for blocks of less than this, but it clobbers so |
387 ;; many registers that there is then probably a better way. | 3746 ;; many registers that there is then probably a better way. |
389 ;; operands[0] is the destination block of memory. | 3748 ;; operands[0] is the destination block of memory. |
390 ;; operands[1] is the source block of memory. | 3749 ;; operands[1] is the source block of memory. |
391 ;; operands[2] is the number of bytes to move. | 3750 ;; operands[2] is the number of bytes to move. |
392 ;; operands[3] is the known shared alignment. | 3751 ;; operands[3] is the known shared alignment. |
393 | 3752 |
394 (define_expand "movmemqi" | 3753 |
3754 (define_expand "movmemsi" | |
395 [(match_operand:BLK 0 "general_operand" "") | 3755 [(match_operand:BLK 0 "general_operand" "") |
396 (match_operand:BLK 1 "general_operand" "") | 3756 (match_operand:BLK 1 "general_operand" "") |
397 (match_operand:SI 2 "const_int_operand" "") | 3757 (match_operand:SI 2 "nds32_reg_constant_operand" "") |
398 (match_operand:SI 3 "const_int_operand" "")] | 3758 (match_operand:SI 3 "const_int_operand" "")] |
399 "" | 3759 "" |
400 { | 3760 { |
401 if (nds32_expand_movmemqi (operands[0], | 3761 if (nds32_expand_movmemsi (operands[0], |
402 operands[1], | 3762 operands[1], |
403 operands[2], | 3763 operands[2], |
404 operands[3])) | 3764 operands[3])) |
405 DONE; | 3765 DONE; |
406 | 3766 |
407 FAIL; | 3767 FAIL; |
408 }) | 3768 }) |
409 | 3769 |
410 ;; ------------------------------------------------------------------------ | 3770 ;; ------------------------------------------------------------------------ |
3771 | |
3772 (define_expand "strlensi" | |
3773 [(match_operand:SI 0 "register_operand") | |
3774 (match_operand:BLK 1 "memory_operand") | |
3775 (match_operand:QI 2 "nds32_reg_constant_operand") | |
3776 (match_operand 3 "const_int_operand")] | |
3777 "TARGET_EXT_STRING" | |
3778 { | |
3779 if (nds32_expand_strlen (operands[0], operands[1], operands[2], operands[3])) | |
3780 DONE; | |
3781 | |
3782 FAIL; | |
3783 }) | |
3784 | |
3785 (define_expand "setmemsi" | |
3786 [(use (match_operand:BLK 0 "memory_operand")) | |
3787 (use (match_operand:SI 1 "nds32_reg_constant_operand")) | |
3788 (use (match_operand:QI 2 "nonmemory_operand")) | |
3789 (use (match_operand 3 "const_int_operand")) | |
3790 (use (match_operand:SI 4 "const_int_operand")) | |
3791 (use (match_operand:SI 5 "const_int_operand"))] | |
3792 "" | |
3793 { | |
3794 if (nds32_expand_setmem (operands[0], operands[1], | |
3795 operands[2], operands[3], | |
3796 operands[4], operands[5])) | |
3797 DONE; | |
3798 | |
3799 FAIL; | |
3800 }) | |
3801 | |
3802 ;; ------------------------------------------------------------------------ |