Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/nds32/nds32.opt @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
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date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
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111:04ced10e8804 | 131:84e7813d76e9 |
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1 ; Options of Andes NDS32 cpu for GNU compiler | 1 ; Options of Andes NDS32 cpu for GNU compiler |
2 ; Copyright (C) 2012-2017 Free Software Foundation, Inc. | 2 ; Copyright (C) 2012-2018 Free Software Foundation, Inc. |
3 ; Contributed by Andes Technology Corporation. | 3 ; Contributed by Andes Technology Corporation. |
4 ; | 4 ; |
5 ; This file is part of GCC. | 5 ; This file is part of GCC. |
6 ; | 6 ; |
7 ; GCC is free software; you can redistribute it and/or modify it | 7 ; GCC is free software; you can redistribute it and/or modify it |
19 ; <http://www.gnu.org/licenses/>. | 19 ; <http://www.gnu.org/licenses/>. |
20 | 20 |
21 HeaderInclude | 21 HeaderInclude |
22 config/nds32/nds32-opts.h | 22 config/nds32/nds32-opts.h |
23 | 23 |
24 mbig-endian | 24 ; --------------------------------------------------------------- |
25 Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN) | 25 ; The following options are designed for aliasing and compatibility options. |
26 | |
27 EB | |
28 Target RejectNegative Alias(mbig-endian) | |
26 Generate code in big-endian mode. | 29 Generate code in big-endian mode. |
27 | 30 |
28 mlittle-endian | 31 EL |
29 Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN) | 32 Target RejectNegative Alias(mlittle-endian) |
30 Generate code in little-endian mode. | 33 Generate code in little-endian mode. |
34 | |
35 mfp-as-gp | |
36 Target RejectNegative Alias(mforce-fp-as-gp) | |
37 Force performing fp-as-gp optimization. | |
38 | |
39 mno-fp-as-gp | |
40 Target RejectNegative Alias(mforbid-fp-as-gp) | |
41 Forbid performing fp-as-gp optimization. | |
42 | |
43 ; --------------------------------------------------------------- | |
44 | |
45 mabi= | |
46 Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI) | |
47 Specify which ABI type to generate code for: 2, 2fp+. | |
48 | |
49 Enum | |
50 Name(abi_type) Type(enum abi_type) | |
51 Known ABIs (for use with the -mabi= option): | |
52 | |
53 EnumValue | |
54 Enum(abi_type) String(2) Value(NDS32_ABI_V2) | |
55 | |
56 EnumValue | |
57 Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS) | |
58 | |
59 mfloat-abi=soft | |
60 Target RejectNegative Alias(mabi=, 2) | |
61 Specify use soft floating point ABI which mean alias to -mabi=2. | |
62 | |
63 mfloat-abi=hard | |
64 Target RejectNegative Alias(mabi=, 2fp+) | |
65 Specify use soft floating point ABI which mean alias to -mabi=2fp+. | |
66 | |
67 ; --------------------------------------------------------------- | |
31 | 68 |
32 mreduced-regs | 69 mreduced-regs |
33 Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) | 70 Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) |
34 Use reduced-set registers for register allocation. | 71 Use reduced-set registers for register allocation. |
35 | 72 |
36 mfull-regs | 73 mfull-regs |
37 Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) | 74 Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) |
38 Use full-set registers for register allocation. | 75 Use full-set registers for register allocation. |
39 | 76 |
77 ; --------------------------------------------------------------- | |
78 | |
79 malways-align | |
80 Target Mask(ALWAYS_ALIGN) | |
81 Always align function entry, jump target and return address. | |
82 | |
83 malign-functions | |
84 Target Mask(ALIGN_FUNCTION) | |
85 Align function entry to 4 byte. | |
86 | |
87 mbig-endian | |
88 Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN) | |
89 Generate code in big-endian mode. | |
90 | |
91 mlittle-endian | |
92 Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN) | |
93 Generate code in little-endian mode. | |
94 | |
95 mforce-fp-as-gp | |
96 Target Undocumented Mask(FORCE_FP_AS_GP) | |
97 Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization. | |
98 | |
99 mforbid-fp-as-gp | |
100 Target Undocumented Mask(FORBID_FP_AS_GP) | |
101 Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'. | |
102 | |
103 mict-model= | |
104 Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL) | |
105 Specify the address generation strategy for ICT call's code model. | |
106 | |
107 Enum | |
108 Name(nds32_ict_model_type) Type(enum nds32_ict_model_type) | |
109 Known cmodel types (for use with the -mict-model= option): | |
110 | |
111 EnumValue | |
112 Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL) | |
113 | |
114 EnumValue | |
115 Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE) | |
116 | |
40 mcmov | 117 mcmov |
41 Target Report Mask(CMOV) | 118 Target Report Mask(CMOV) |
42 Generate conditional move instructions. | 119 Generate conditional move instructions. |
43 | 120 |
44 mperf-ext | 121 mhw-abs |
45 Target Report Mask(PERF_EXT) | 122 Target Report Mask(HW_ABS) |
123 Generate hardware abs instructions. | |
124 | |
125 mext-perf | |
126 Target Report Mask(EXT_PERF) | |
46 Generate performance extension instructions. | 127 Generate performance extension instructions. |
128 | |
129 mext-perf2 | |
130 Target Report Mask(EXT_PERF2) | |
131 Generate performance extension version 2 instructions. | |
132 | |
133 mext-string | |
134 Target Report Mask(EXT_STRING) | |
135 Generate string extension instructions. | |
136 | |
137 mext-dsp | |
138 Target Report Mask(EXT_DSP) | |
139 Generate DSP extension instructions. | |
47 | 140 |
48 mv3push | 141 mv3push |
49 Target Report Mask(V3PUSH) | 142 Target Report Mask(V3PUSH) |
50 Generate v3 push25/pop25 instructions. | 143 Generate v3 push25/pop25 instructions. |
51 | 144 |
52 m16-bit | 145 m16-bit |
53 Target Report Mask(16_BIT) | 146 Target Report Mask(16_BIT) |
54 Generate 16-bit instructions. | 147 Generate 16-bit instructions. |
55 | 148 |
149 mrelax-hint | |
150 Target Report Mask(RELAX_HINT) | |
151 Insert relax hint for linker to do relaxation. | |
152 | |
153 mvh | |
154 Target Report Mask(VH) Condition(!TARGET_LINUX_ABI) | |
155 Enable Virtual Hosting support. | |
156 | |
56 misr-vector-size= | 157 misr-vector-size= |
57 Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) | 158 Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) |
58 Specify the size of each interrupt vector, which must be 4 or 16. | 159 Specify the size of each interrupt vector, which must be 4 or 16. |
59 | 160 |
161 misr-secure= | |
162 Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0) | |
163 Specify the security level of c-isr for the whole file. | |
164 | |
60 mcache-block-size= | 165 mcache-block-size= |
61 Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) | 166 Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) |
62 Specify the size of each cache block, which must be a power of 2 between 4 and 512. | 167 Specify the size of each cache block, which must be a power of 2 between 4 and 512. |
63 | 168 |
64 march= | 169 march= |
74 | 179 |
75 EnumValue | 180 EnumValue |
76 Enum(nds32_arch_type) String(v3) Value(ARCH_V3) | 181 Enum(nds32_arch_type) String(v3) Value(ARCH_V3) |
77 | 182 |
78 EnumValue | 183 EnumValue |
184 Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J) | |
185 | |
186 EnumValue | |
79 Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M) | 187 Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M) |
80 | 188 |
81 mcmodel= | 189 EnumValue |
82 Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_MEDIUM) | 190 Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F) |
83 Specify the address generation strategy for code model. | 191 |
84 | 192 EnumValue |
85 Enum | 193 Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S) |
86 Name(nds32_cmodel_type) Type(enum nds32_cmodel_type) | 194 |
87 Known cmodel types (for use with the -mcmodel= option): | 195 mcpu= |
88 | 196 Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9) |
89 EnumValue | 197 Specify the cpu for pipeline model. |
90 Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL) | 198 |
91 | 199 Enum |
92 EnumValue | 200 Name(nds32_cpu_type) Type(enum nds32_cpu_type) |
93 Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM) | 201 Known cpu types (for use with the -mcpu= option): |
94 | 202 |
95 EnumValue | 203 EnumValue |
96 Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE) | 204 Enum(nds32_cpu_type) String(n6) Value(CPU_N6) |
205 | |
206 EnumValue | |
207 Enum(nds32_cpu_type) String(n650) Value(CPU_N6) | |
208 | |
209 EnumValue | |
210 Enum(nds32_cpu_type) String(n7) Value(CPU_N7) | |
211 | |
212 EnumValue | |
213 Enum(nds32_cpu_type) String(n705) Value(CPU_N7) | |
214 | |
215 EnumValue | |
216 Enum(nds32_cpu_type) String(n8) Value(CPU_N8) | |
217 | |
218 EnumValue | |
219 Enum(nds32_cpu_type) String(n801) Value(CPU_N8) | |
220 | |
221 EnumValue | |
222 Enum(nds32_cpu_type) String(sn8) Value(CPU_N8) | |
223 | |
224 EnumValue | |
225 Enum(nds32_cpu_type) String(sn801) Value(CPU_N8) | |
226 | |
227 EnumValue | |
228 Enum(nds32_cpu_type) String(s8) Value(CPU_N8) | |
229 | |
230 EnumValue | |
231 Enum(nds32_cpu_type) String(s801) Value(CPU_N8) | |
232 | |
233 EnumValue | |
234 Enum(nds32_cpu_type) String(e8) Value(CPU_E8) | |
235 | |
236 EnumValue | |
237 Enum(nds32_cpu_type) String(e801) Value(CPU_E8) | |
238 | |
239 EnumValue | |
240 Enum(nds32_cpu_type) String(n820) Value(CPU_E8) | |
241 | |
242 EnumValue | |
243 Enum(nds32_cpu_type) String(s830) Value(CPU_E8) | |
244 | |
245 EnumValue | |
246 Enum(nds32_cpu_type) String(e830) Value(CPU_E8) | |
247 | |
248 EnumValue | |
249 Enum(nds32_cpu_type) String(n9) Value(CPU_N9) | |
250 | |
251 EnumValue | |
252 Enum(nds32_cpu_type) String(n903) Value(CPU_N9) | |
253 | |
254 EnumValue | |
255 Enum(nds32_cpu_type) String(n903a) Value(CPU_N9) | |
256 | |
257 EnumValue | |
258 Enum(nds32_cpu_type) String(n968) Value(CPU_N9) | |
259 | |
260 EnumValue | |
261 Enum(nds32_cpu_type) String(n968a) Value(CPU_N9) | |
262 | |
263 EnumValue | |
264 Enum(nds32_cpu_type) String(n10) Value(CPU_N10) | |
265 | |
266 EnumValue | |
267 Enum(nds32_cpu_type) String(n1033) Value(CPU_N10) | |
268 | |
269 EnumValue | |
270 Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10) | |
271 | |
272 EnumValue | |
273 Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10) | |
274 | |
275 EnumValue | |
276 Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10) | |
277 | |
278 EnumValue | |
279 Enum(nds32_cpu_type) String(n1068) Value(CPU_N10) | |
280 | |
281 EnumValue | |
282 Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10) | |
283 | |
284 EnumValue | |
285 Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10) | |
286 | |
287 EnumValue | |
288 Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10) | |
289 | |
290 EnumValue | |
291 Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10) | |
292 | |
293 EnumValue | |
294 Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10) | |
295 | |
296 EnumValue | |
297 Enum(nds32_cpu_type) String(d10) Value(CPU_N10) | |
298 | |
299 EnumValue | |
300 Enum(nds32_cpu_type) String(d1088) Value(CPU_N10) | |
301 | |
302 EnumValue | |
303 Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10) | |
304 | |
305 EnumValue | |
306 Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10) | |
307 | |
308 EnumValue | |
309 Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF) | |
310 | |
311 EnumValue | |
312 Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF) | |
313 | |
314 EnumValue | |
315 Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF) | |
316 | |
317 EnumValue | |
318 Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF) | |
319 | |
320 EnumValue | |
321 Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF) | |
322 | |
323 EnumValue | |
324 Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF) | |
325 | |
326 EnumValue | |
327 Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF) | |
328 | |
329 EnumValue | |
330 Enum(nds32_cpu_type) String(n12) Value(CPU_N12) | |
331 | |
332 EnumValue | |
333 Enum(nds32_cpu_type) String(n1213) Value(CPU_N12) | |
334 | |
335 EnumValue | |
336 Enum(nds32_cpu_type) String(n1233) Value(CPU_N12) | |
337 | |
338 EnumValue | |
339 Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12) | |
340 | |
341 EnumValue | |
342 Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12) | |
343 | |
344 EnumValue | |
345 Enum(nds32_cpu_type) String(n13) Value(CPU_N13) | |
346 | |
347 EnumValue | |
348 Enum(nds32_cpu_type) String(n1337) Value(CPU_N13) | |
349 | |
350 EnumValue | |
351 Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13) | |
352 | |
353 EnumValue | |
354 Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13) | |
355 | |
356 EnumValue | |
357 Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE) | |
358 | |
359 mconfig-fpu= | |
360 Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT) | |
361 Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3. | |
362 | |
363 Enum | |
364 Name(float_reg_number) Type(enum float_reg_number) | |
365 Known floating-point number of registers (for use with the -mconfig-fpu= option): | |
366 | |
367 EnumValue | |
368 Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0) | |
369 | |
370 EnumValue | |
371 Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1) | |
372 | |
373 EnumValue | |
374 Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2) | |
375 | |
376 EnumValue | |
377 Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3) | |
378 | |
379 EnumValue | |
380 Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4) | |
381 | |
382 EnumValue | |
383 Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5) | |
384 | |
385 EnumValue | |
386 Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6) | |
387 | |
388 EnumValue | |
389 Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7) | |
390 | |
391 mconfig-mul= | |
392 Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1) | |
393 Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1. | |
394 | |
395 Enum | |
396 Name(nds32_mul_type) Type(enum nds32_mul_type) | |
397 | |
398 EnumValue | |
399 Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1) | |
400 | |
401 EnumValue | |
402 Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1) | |
403 | |
404 EnumValue | |
405 Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2) | |
406 | |
407 EnumValue | |
408 Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW) | |
409 | |
410 mconfig-register-ports= | |
411 Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W) | |
412 Specify how many read/write ports for n9/n10 cores. The value should be 3r2w or 2r1w. | |
413 | |
414 Enum | |
415 Name(nds32_register_ports) Type(enum nds32_register_ports) | |
416 | |
417 EnumValue | |
418 Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W) | |
419 | |
420 EnumValue | |
421 Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W) | |
97 | 422 |
98 mctor-dtor | 423 mctor-dtor |
99 Target Report | 424 Target Report |
100 Enable constructor/destructor feature. | 425 Enable constructor/destructor feature. |
101 | 426 |
102 mrelax | 427 mrelax |
103 Target Report | 428 Target Report |
104 Guide linker to relax instructions. | 429 Guide linker to relax instructions. |
430 | |
431 mext-fpu-fma | |
432 Target Report Mask(EXT_FPU_FMA) | |
433 Generate floating-point multiply-accumulation instructions. | |
434 | |
435 mext-fpu-sp | |
436 Target Report Mask(FPU_SINGLE) | |
437 Generate single-precision floating-point instructions. | |
438 | |
439 mext-fpu-dp | |
440 Target Report Mask(FPU_DOUBLE) | |
441 Generate double-precision floating-point instructions. | |
442 | |
443 mforce-no-ext-dsp | |
444 Target Undocumented Report Mask(FORCE_NO_EXT_DSP) | |
445 Force disable hardware loop, even use -mext-dsp. | |
446 | |
447 msched-prolog-epilog | |
448 Target Var(flag_sched_prolog_epilog) Init(0) | |
449 Permit scheduling of a function's prologue and epilogue sequence. | |
450 | |
451 mret-in-naked-func | |
452 Target Var(flag_ret_in_naked_func) Init(1) | |
453 Generate return instruction in naked function. | |
454 | |
455 malways-save-lp | |
456 Target Var(flag_always_save_lp) Init(0) | |
457 Always save $lp in the stack. | |
458 | |
459 munaligned-access | |
460 Target Report Var(flag_unaligned_access) Init(0) | |
461 Enable unaligned word and halfword accesses to packed data. | |
462 | |
463 minline-asm-r15 | |
464 Target Report Var(flag_inline_asm_r15) Init(0) | |
465 Allow use r15 for inline ASM. |