CbC/CbC_gcc: gcc/config/riscv/riscv.c comparison

comparison gcc/config/riscv/riscv.c @ 131:84e7813d76e9

gcc-8.2

author	mir3636
date	Thu, 25 Oct 2018 07:37:49 +0900
parents	04ced10e8804
children	1830386684a0

comparison

equal deleted inserted replaced

-:04ced10e8804
+:84e7813d76e9
 /* Subroutines used for code generation for RISC-V.
-Copyright (C) 2011-2017 Free Software Foundation, Inc.
+Copyright (C) 2011-2018 Free Software Foundation, Inc.
 Contributed by Andrew Waterman (andrew@sifive.com).
 Based on MIPS target for GNU compiler.
 This file is part of GCC.
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
+#define IN_TARGET_CODE 1
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
 #include "optabs.h"
 #include "bitmap.h"
 #include "df.h"
 #include "diagnostic.h"
 #include "builtins.h"
+#include "predict.h"
 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */
 #define UNSPEC_ADDRESS_P(X)					\
 (GET_CODE (X) == UNSPEC					\
 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST			\
 /* The offset of arg_pointer_rtx from the bottom of the frame.  */
 HOST_WIDE_INT arg_pointer_offset;
 };
+enum riscv_privilege_levels {
+UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE
+};
 struct GTY(())  machine_function {
 /* The number of extra stack bytes taken up by register varargs.
 This area is allocated by the callee at the very top of the frame.  */
 int varargs_size;
-/* Memoized return value of leaf_function_p.  <0 if false, >0 if true.  */
+/* True if current function is a naked function.  */
-int is_leaf;
+bool naked_p;
+/* True if current function is an interrupt function.  */
+bool interrupt_handler_p;
+/* For an interrupt handler, indicates the privilege level.  */
+enum riscv_privilege_levels interrupt_mode;
+/* True if attributes on current function have been checked.  */
+bool attributes_checked_p;
 /* The current frame information, calculated by riscv_compute_frame_info.  */
 struct riscv_frame_info frame;
 };
 };
 /* Global variables for machine-dependent things.  */
 /* Whether unaligned accesses execute very slowly.  */
-static bool riscv_slow_unaligned_access_p;
+bool riscv_slow_unaligned_access_p;
+/* Stack alignment to assume/maintain.  */
+unsigned riscv_stack_boundary;
 /* Which tuning parameters to use.  */
 static const struct riscv_tune_info *tune_info;
 /* Index R is the smallest register class that contains register R.  */
 1,						/* branch_cost */
 2,						/* memory_cost */
 false,					/* slow_unaligned_access */
 };
+static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
+static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
+/* Defining target-specific uses of __attribute__.  */
+static const struct attribute_spec riscv_attribute_table[] =
+{
+/* Syntax: { name, min_len, max_len, decl_required, type_required,
+	       function_type_required, affects_type_identity, handler,
+	       exclude } */
+/* The attribute telling no prologue/epilogue.  */
+{ "naked",	0,  0, true, false, false, false,
+riscv_handle_fndecl_attribute, NULL },
+/* This attribute generates prologue/epilogue for interrupt handlers.  */
+{ "interrupt", 0, 1, false, true, true, false,
+riscv_handle_type_attribute, NULL },
+/* The last attribute spec is set to be NULL.  */
+{ NULL,	0,  0, false, false, false, false, NULL, NULL }
+};
 /* A table describing all the processors GCC knows about.  */
 static const struct riscv_cpu_info riscv_cpu_info_table[] = {
 { "rocket", &rocket_tune_info },
 { "size", &optimize_size_tune_info },
 };
 {
 struct riscv_address_info addr;
 int n = 1;
 if (!riscv_classify_address (&addr, x, mode, false))
-return 0;
+{
+/* This could be a pattern from the pic.md file.  In which case we want
+	 this address to always have a cost of 3 to make it as expensive as the
+	 most expensive symbol.  This prevents constant propagation from
+	 preferring symbols over register plus offset.  */
+return 3;
+}
 /* BLKmode is used for single unaligned loads and stores and should
 not count as a multiword mode. */
 if (mode != BLKmode && might_split_p)
 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
 	  ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno);
 	  gcc_assert ((size_t) bytes < sizeof (buf));
 	  label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
 	  SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL;
+	  /* ??? Ugly hack to make weak symbols work.  May need to change the
+	     RTL for the auipc and/or low patterns to get a better fix for
+	     this.  */
+	  if (! nonzero_address_p (addr))
+	    SYMBOL_REF_WEAK (label) = 1;
 	  if (temp == NULL)
 	    temp = gen_reg_rtx (Pmode);
 	  if (Pmode == DImode)
 riscv_legitimize_const_move (mode, dest, src);
 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
 return true;
 }
+/* RISC-V GCC may generate non-legitimate address due to we provide some
+pattern for optimize access PIC local symbol and it's make GCC generate
+unrecognizable instruction during optmizing.  */
+if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0),
+						   reload_completed))
+{
+XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode);
+}
+if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0),
+						  reload_completed))
+{
+XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode);
+}
 return false;
 }
 /* Return true if there is an instruction that implements CODE and accepts
 X as an immediate operand. */
 /* We need to use a shift left and a shift right.  */
 return COSTS_N_INSNS (2);
 }
 /* Implement TARGET_RTX_COSTS.  */
+#define SINGLE_SHIFT_COST 1
 static bool
 riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED,
 		 int *total, bool speed)
 {
 case XOR:
 /* Double-word operations use two single-word operations.  */
 *total = riscv_binary_cost (x, 1, 2);
 return false;
+case ZERO_EXTRACT:
+/* This is an SImode shift.  */
+if (outer_code == SET && (INTVAL (XEXP (x, 2)) > 0)
+	  && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32))
+	{
+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+	  return true;
+	}
+return false;
 case ASHIFT:
 case ASHIFTRT:
 case LSHIFTRT:
-*total = riscv_binary_cost (x, 1, CONSTANT_P (XEXP (x, 1)) ? 4 : 9);
+*total = riscv_binary_cost (x, SINGLE_SHIFT_COST,
+				  CONSTANT_P (XEXP (x, 1)) ? 4 : 9);
 return false;
 case ABS:
 *total = COSTS_N_INSNS (float_mode_p ? 1 : 3);
 return false;
 case LO_SUM:
 *total = set_src_cost (XEXP (x, 0), mode, speed);
 return true;
 case LT:
+/* This is an SImode shift.  */
+if (outer_code == SET && GET_MODE (x) == DImode
+	  && GET_MODE (XEXP (x, 0)) == SImode)
+	{
+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+	  return true;
+	}
+/* Fall through.  */
 case LTU:
 case LE:
 case LEU:
 case GT:
 case GTU:
 return false;
 case MULT:
 if (float_mode_p)
 	*total = tune_info->fp_mul[mode == DFmode];
+else if (!TARGET_MUL)
+	/* Estimate the cost of a library call.  */
+	*total = COSTS_N_INSNS (speed ? 32 : 6);
 else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
 	*total = 3 * tune_info->int_mul[0] + COSTS_N_INSNS (2);
 else if (!speed)
 	*total = COSTS_N_INSNS (1);
 else
 	}
 /* Fall through.  */
 case UDIV:
 case UMOD:
-if (speed)
+if (!TARGET_DIV)
+	/* Estimate the cost of a library call.  */
+	*total = COSTS_N_INSNS (speed ? 32 : 6);
+else if (speed)
 	*total = tune_info->int_div[mode == DImode];
 else
 	*total = COSTS_N_INSNS (1);
 return false;
+case ZERO_EXTEND:
+/* This is an SImode shift.  */
+if (GET_CODE (XEXP (x, 0)) == LSHIFTRT)
+	{
+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+	  return true;
+	}
+/* Fall through.  */
 case SIGN_EXTEND:
-case ZERO_EXTEND:
 *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
 return false;
 case FLOAT:
 case UNSIGNED_FLOAT:
 if (src_code == MEM)
 	return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1";
 }
 gcc_unreachable ();
 }
+const char *
+riscv_output_return ()
+{
+if (cfun->machine->naked_p)
+return "";
+return "ret";
+}
 /* Return true if CMP1 is a suitable second operand for integer ordering
 test CODE.  See also the *sCC patterns in riscv.md.  */
 static bool
 riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
 {
 /* Comparisons consider all XLEN bits, so extend sub-XLEN values.  */
 if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0)))
 {
-/* It is more profitable to zero-extend QImode values.  */
+/* It is more profitable to zero-extend QImode values.  But not if the
-if (unsigned_condition (code) == code && GET_MODE (*op0) == QImode)
+	 first operand has already been sign-extended, and the second one is
+	 is a constant or has already been sign-extended also.  */
+if (unsigned_condition (code) == code
+	  && (GET_MODE (*op0) == QImode
+	      && ! (GET_CODE (*op0) == SUBREG
+		    && SUBREG_PROMOTED_VAR_P (*op0)
+		    && SUBREG_PROMOTED_SIGNED_P (*op0)
+		    && (CONST_INT_P (*op1)
+			|| (GET_CODE (*op1) == SUBREG
+			    && SUBREG_PROMOTED_VAR_P (*op1)
+			    && SUBREG_PROMOTED_SIGNED_P (*op1))))))
 	{
 	  *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0);
 	  if (CONST_INT_P (*op1))
 	    *op1 = GEN_INT ((uint8_t) INTVAL (*op1));
 	  else
 emit_jump_insn (gen_condjump (condition, label));
 }
 /* Implement TARGET_FUNCTION_ARG_BOUNDARY.  Every parameter gets at
 least PARM_BOUNDARY bits of alignment, but will be given anything up
-to STACK_BOUNDARY bits if the type requires it.  */
+to PREFERRED_STACK_BOUNDARY bits if the type requires it.  */
 static unsigned int
 riscv_function_arg_boundary (machine_mode mode, const_tree type)
 {
 unsigned int alignment;
 if (type && !AGGREGATE_TYPE_P (type))
 alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type));
 else
 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
-return MIN (STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment));
+return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment));
 }
 /* If MODE represents an argument that can be passed or returned in
 floating-point registers, return the number of registers, else 0.  */
 }
 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD;
 }
+/* Handle an attribute requiring a FUNCTION_DECL;
+arguments as in struct attribute_spec.handler.  */
+static tree
+riscv_handle_fndecl_attribute (tree *node, tree name,
+			       tree args ATTRIBUTE_UNUSED,
+			       int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
+{
+if (TREE_CODE (*node) != FUNCTION_DECL)
+{
+warning (OPT_Wattributes, "%qE attribute only applies to functions",
+	       name);
+*no_add_attrs = true;
+}
+return NULL_TREE;
+}
+/* Verify type based attributes.  NODE is the what the attribute is being
+applied to.  NAME is the attribute name.  ARGS are the attribute args.
+FLAGS gives info about the context.  NO_ADD_ATTRS should be set to true if
+the attribute should be ignored.  */
+static tree
+riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
+			     int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
+{
+/* Check for an argument.  */
+if (is_attribute_p ("interrupt", name))
+{
+if (args)
+	{
+	  tree cst = TREE_VALUE (args);
+	  const char *string;
+	  if (TREE_CODE (cst) != STRING_CST)
+	    {
+	      warning (OPT_Wattributes,
+		       "%qE attribute requires a string argument",
+		       name);
+	      *no_add_attrs = true;
+	      return NULL_TREE;
+	    }
+	  string = TREE_STRING_POINTER (cst);
+	  if (strcmp (string, "user") && strcmp (string, "supervisor")
+	      && strcmp (string, "machine"))
+	    {
+	      warning (OPT_Wattributes,
+		       "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
+		       name);
+	      *no_add_attrs = true;
+	    }
+	}
+}
+return NULL_TREE;
+}
+/* Return true if function TYPE is an interrupt function.  */
+static bool
+riscv_interrupt_type_p (tree type)
+{
+return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
+}
+/* Return true if FUNC is a naked function.  */
+static bool
+riscv_naked_function_p (tree func)
+{
+tree func_decl = func;
+if (func == NULL_TREE)
+func_decl = current_function_decl;
+return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl));
+}
+/* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS.  */
+static bool
+riscv_allocate_stack_slots_for_args ()
+{
+/* Naked functions should not allocate stack slots for arguments.  */
+return !riscv_naked_function_p (current_function_decl);
+}
+/* Implement TARGET_WARN_FUNC_RETURN.  */
+static bool
+riscv_warn_func_return (tree decl)
+{
+/* Naked functions are implemented entirely in assembly, including the
+return sequence, so suppress warnings about this.  */
+return !riscv_naked_function_p (decl);
+}
 /* Implement TARGET_EXPAND_BUILTIN_VA_START.  */
 static void
 riscv_va_start (tree valist, rtx nextarg)
 {
 rtx reg = RISCV_PROLOGUE_TEMP (Pmode);
 riscv_emit_move (reg, addr);
 return reg;
 }
 return addr;
+}
+/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
+Assume that the areas do not overlap.  */
+static void
+riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
+{
+HOST_WIDE_INT offset, delta;
+unsigned HOST_WIDE_INT bits;
+int i;
+enum machine_mode mode;
+rtx *regs;
+bits = MAX (BITS_PER_UNIT,
+	      MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest))));
+mode = mode_for_size (bits, MODE_INT, 0).require ();
+delta = bits / BITS_PER_UNIT;
+/* Allocate a buffer for the temporary registers.  */
+regs = XALLOCAVEC (rtx, length / delta);
+/* Load as many BITS-sized chunks as possible.  Use a normal load if
+the source has enough alignment, otherwise use left/right pairs.  */
+for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
+{
+regs[i] = gen_reg_rtx (mode);
+riscv_emit_move (regs[i], adjust_address (src, mode, offset));
+}
+/* Copy the chunks to the destination.  */
+for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
+riscv_emit_move (adjust_address (dest, mode, offset), regs[i]);
+/* Mop up any left-over bytes.  */
+if (offset < length)
+{
+src = adjust_address (src, BLKmode, offset);
+dest = adjust_address (dest, BLKmode, offset);
+move_by_pieces (dest, src, length - offset,
+		      MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
+}
+}
+/* Helper function for doing a loop-based block operation on memory
+reference MEM.  Each iteration of the loop will operate on LENGTH
+bytes of MEM.
+Create a new base register for use within the loop and point it to
+the start of MEM.  Create a new memory reference that uses this
+register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
+static void
+riscv_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
+		       rtx *loop_reg, rtx *loop_mem)
+{
+*loop_reg = copy_addr_to_reg (XEXP (mem, 0));
+/* Although the new mem does not refer to a known location,
+it does keep up to LENGTH bytes of alignment.  */
+*loop_mem = change_address (mem, BLKmode, *loop_reg);
+set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
+}
+/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
+bytes at a time.  LENGTH must be at least BYTES_PER_ITER.  Assume that
+the memory regions do not overlap.  */
+static void
+riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
+		      HOST_WIDE_INT bytes_per_iter)
+{
+rtx label, src_reg, dest_reg, final_src, test;
+HOST_WIDE_INT leftover;
+leftover = length % bytes_per_iter;
+length -= leftover;
+/* Create registers and memory references for use within the loop.  */
+riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
+riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
+/* Calculate the value that SRC_REG should have after the last iteration
+of the loop.  */
+final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
+				   0, 0, OPTAB_WIDEN);
+/* Emit the start of the loop.  */
+label = gen_label_rtx ();
+emit_label (label);
+/* Emit the loop body.  */
+riscv_block_move_straight (dest, src, bytes_per_iter);
+/* Move on to the next block.  */
+riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
+riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
+/* Emit the loop condition.  */
+test = gen_rtx_NE (VOIDmode, src_reg, final_src);
+if (Pmode == DImode)
+emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
+else
+emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
+/* Mop up any left-over bytes.  */
+if (leftover)
+riscv_block_move_straight (dest, src, leftover);
+else
+emit_insn(gen_nop ());
+}
+/* Expand a movmemsi instruction, which copies LENGTH bytes from
+memory reference SRC to memory reference DEST.  */
+bool
+riscv_expand_block_move (rtx dest, rtx src, rtx length)
+{
+if (CONST_INT_P (length))
+{
+HOST_WIDE_INT factor, align;
+align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
+factor = BITS_PER_WORD / align;
+if (optimize_function_for_size_p (cfun)
+	  && INTVAL (length) * factor * UNITS_PER_WORD > MOVE_RATIO (false))
+	return false;
+if (INTVAL (length) <= RISCV_MAX_MOVE_BYTES_STRAIGHT / factor)
+	{
+	  riscv_block_move_straight (dest, src, INTVAL (length));
+	  return true;
+	}
+else if (optimize && align >= BITS_PER_WORD)
+	{
+	  unsigned min_iter_words
+	    = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD;
+	  unsigned iter_words = min_iter_words;
+	  HOST_WIDE_INT bytes = INTVAL (length), words = bytes / UNITS_PER_WORD;
+	  /* Lengthen the loop body if it shortens the tail.  */
+	  for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++)
+	    {
+	      unsigned cur_cost = iter_words + words % iter_words;
+	      unsigned new_cost = i + words % i;
+	      if (new_cost <= cur_cost)
+		iter_words = i;
+	    }
+	  riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD);
+	  return true;
+	}
+}
+return false;
 }
 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
 in context CONTEXT.  HI_RELOC indicates a high-part reloc.  */
 	  any outermost HIGH.
 'R'	Print the low-part relocation associated with OP.
 'C'	Print the integer branch condition for comparison OP.
 'A'	Print the atomic operation suffix for memory model OP.
 'F'	Print a FENCE if the memory model requires a release.
-'z'	Print x0 if OP is zero, otherwise print OP normally.  */
+'z'	Print x0 if OP is zero, otherwise print OP normally.
+'i'	Print i if the operand is not a register.  */
 static void
 riscv_print_operand (FILE *file, rtx op, int letter)
 {
 machine_mode mode = GET_MODE (op);
 break;
 case 'F':
 if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
 	fputs ("fence iorw,ow; ", file);
+break;
+case 'i':
+if (code != REG)
+fputs ("i", file);
 break;
 default:
 switch (code)
 	{
 }
 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x)));
 }
+/* Switch to the appropriate section for output of DECL.  */
+static section *
+riscv_select_section (tree decl, int reloc,
+		      unsigned HOST_WIDE_INT align)
+{
+switch (categorize_decl_for_section (decl, reloc))
+{
+case SECCAT_SRODATA:
+return get_named_section (decl, ".srodata", reloc);
+default:
+return default_elf_select_section (decl, reloc, align);
+}
+}
 /* Return a section for X, handling small data. */
 static section *
 riscv_elf_select_rtx_section (machine_mode mode, rtx x,
 			      unsigned HOST_WIDE_INT align)
 return true;
 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
 return true;
+/* If this is an interrupt handler, then must save extra registers.  */
+if (cfun->machine->interrupt_handler_p)
+{
+/* zero register is always zero.  */
+if (regno == GP_REG_FIRST)
+	return false;
+/* The function will return the stack pointer to its original value.  */
+if (regno == STACK_POINTER_REGNUM)
+	return false;
+/* By convention, we assume that gp and tp are safe.  */
+if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM)
+	return false;
+/* We must save every register used in this function.  If this is not a
+	 leaf function, then we must save all temporary registers.  */
+if (df_regs_ever_live_p (regno)
+	  || (!crtl->is_leaf && call_used_regs[regno]))
+	return true;
+}
 return false;
 }
 /* Determine whether to call GPR save/restore routines.  */
 static bool
 riscv_use_save_libcall (const struct riscv_frame_info *frame)
 {
-if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed)
+if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed
+|| cfun->machine->interrupt_handler_p)
 return false;
 return frame->save_libcall_adjustment != 0;
 }
 Dynamic stack allocations such as alloca insert data at point P.
 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
 hard_frame_pointer_rtx unchanged.  */
+static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame);
 static void
 riscv_compute_frame_info (void)
 {
 struct riscv_frame_info *frame;
 HOST_WIDE_INT offset;
+bool interrupt_save_t1 = false;
 unsigned int regno, i, num_x_saved = 0, num_f_saved = 0;
 frame = &cfun->machine->frame;
+/* In an interrupt function, if we have a large frame, then we need to
+save/restore t1.  We check for this before clearing the frame struct.  */
+if (cfun->machine->interrupt_handler_p)
+{
+HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
+if (! SMALL_OPERAND (frame->total_size - step1))
+	interrupt_save_t1 = true;
+}
 memset (frame, 0, sizeof (*frame));
-/* Find out which GPRs we need to save.  */
+if (!cfun->machine->naked_p)
-for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+{
-if (riscv_save_reg_p (regno))
+/* Find out which GPRs we need to save.  */
-frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
+for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+	if (riscv_save_reg_p (regno)
-/* If this function calls eh_return, we must also save and restore the
+	    || (interrupt_save_t1 && (regno == T1_REGNUM)))
-EH data registers.  */
+	  frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
-if (crtl->calls_eh_return)
-for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
+/* If this function calls eh_return, we must also save and restore the
-frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
+	 EH data registers.  */
+if (crtl->calls_eh_return)
-/* Find out which FPRs we need to save.  This loop must iterate over
+	for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
-the same space as its companion in riscv_for_each_saved_reg.  */
+	  frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
-if (TARGET_HARD_FLOAT)
-for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
+/* Find out which FPRs we need to save.  This loop must iterate over
-if (riscv_save_reg_p (regno))
+	 the same space as its companion in riscv_for_each_saved_reg.  */
-	frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
+if (TARGET_HARD_FLOAT)
+	for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
+	  if (riscv_save_reg_p (regno))
+	    frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
+}
 /* At the bottom of the frame are any outgoing stack arguments. */
-offset = crtl->outgoing_args_size;
+offset = RISCV_STACK_ALIGN (crtl->outgoing_args_size);
 /* Next are local stack variables. */
 offset += RISCV_STACK_ALIGN (get_frame_size ());
 /* The virtual frame pointer points above the local variables. */
 frame->frame_pointer_offset = offset;
 /* Next are the callee-saved FPRs. */
 unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD);
 unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask);
 /* Only use save/restore routines if they don't alter the stack size.  */
 if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size)
-	frame->save_libcall_adjustment = x_save_size;
+	{
+	  /* Libcall saves/restores 3 registers at once, so we need to
+	     allocate 12 bytes for callee-saved register.  */
+	  if (TARGET_RVE)
+	    x_save_size = 3 * UNITS_PER_WORD;
+	  frame->save_libcall_adjustment = x_save_size;
+	}
 offset += x_save_size;
 }
 frame->gp_sp_offset = offset - UNITS_PER_WORD;
 /* The hard frame pointer points above the callee-saved GPRs. */
 frame->hard_frame_pointer_offset = offset;
 /* Above the hard frame pointer is the callee-allocated varags save area. */
 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size);
-frame->arg_pointer_offset = offset;
 /* Next is the callee-allocated area for pretend stack arguments.  */
-offset += crtl->args.pretend_args_size;
+offset += RISCV_STACK_ALIGN (crtl->args.pretend_args_size);
+/* Arg pointer must be below pretend args, but must be above alignment
+padding.  */
+frame->arg_pointer_offset = offset - crtl->args.pretend_args_size;
 frame->total_size = offset;
 /* Next points the incoming stack pointer and any incoming arguments. */
 /* Only use save/restore routines when the GPRs are atop the frame.  */
 if (frame->hard_frame_pointer_offset != frame->total_size)
 /* Call FN for each register that is saved by the current function.
 SP_OFFSET is the offset of the current stack pointer from the start
 of the frame.  */
 static void
-riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn)
+riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn,
+			  bool epilogue, bool maybe_eh_return)
 {
 HOST_WIDE_INT offset;
 /* Save the link register and s-registers. */
 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
-for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++)
+for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
 {
-	riscv_save_restore_reg (word_mode, regno, offset, fn);
+	bool handle_reg = TRUE;
+	/* If this is a normal return in a function that calls the eh_return
+	   builtin, then do not restore the eh return data registers as that
+	   would clobber the return value.  But we do still need to save them
+	   in the prologue, and restore them for an exception return, so we
+	   need special handling here.  */
+	if (epilogue && !maybe_eh_return && crtl->calls_eh_return)
+	  {
+	    unsigned int i, regnum;
+	    for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM;
+		 i++)
+	      if (regno == regnum)
+		{
+		  handle_reg = FALSE;
+		  break;
+		}
+	  }
+	if (handle_reg)
+	  riscv_save_restore_reg (word_mode, regno, offset, fn);
 	offset -= UNITS_PER_WORD;
 }
 /* This loop must iterate over the same space as its companion in
 riscv_compute_frame_info.  */
 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
-for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
+for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
 {
 	machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
 	riscv_save_restore_reg (mode, regno, offset, fn);
 return s;
 }
 /* For stack frames that can't be allocated with a single ADDI instruction,
 compute the best value to initially allocate.  It must at a minimum
-allocate enough space to spill the callee-saved registers.  */
+allocate enough space to spill the callee-saved registers.  If TARGET_RVC,
+try to pick a value that will allow compression of the register saves
+without adding extra instructions.  */
 static HOST_WIDE_INT
 riscv_first_stack_step (struct riscv_frame_info *frame)
 {
-HOST_WIDE_INT min_first_step = frame->total_size - frame->fp_sp_offset;
-HOST_WIDE_INT max_first_step = IMM_REACH / 2 - STACK_BOUNDARY / 8;
 if (SMALL_OPERAND (frame->total_size))
 return frame->total_size;
+HOST_WIDE_INT min_first_step =
+RISCV_STACK_ALIGN (frame->total_size - frame->fp_sp_offset);
+HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8;
+HOST_WIDE_INT min_second_step = frame->total_size - max_first_step;
+gcc_assert (min_first_step <= max_first_step);
 /* As an optimization, use the least-significant bits of the total frame
 size, so that the second adjustment step is just LUI + ADD.  */
-if (!SMALL_OPERAND (frame->total_size - max_first_step)
+if (!SMALL_OPERAND (min_second_step)
 && frame->total_size % IMM_REACH < IMM_REACH / 2
 && frame->total_size % IMM_REACH >= min_first_step)
 return frame->total_size % IMM_REACH;
-gcc_assert (min_first_step <= max_first_step);
+if (TARGET_RVC)
+{
+/* If we need two subtracts, and one is small enough to allow compressed
+	 loads and stores, then put that one first.  */
+if (IN_RANGE (min_second_step, 0,
+		    (TARGET_64BIT ? SDSP_REACH : SWSP_REACH)))
+	return MAX (min_second_step, min_first_step);
+/* If we need LUI + ADDI + ADD for the second adjustment step, then start
+	 with the minimum first step, so that we can get compressed loads and
+	 stores.  */
+else if (!SMALL_OPERAND (min_second_step))
+	return min_first_step;
+}
 return max_first_step;
 }
 static rtx
 riscv_adjust_libcall_cfi_prologue ()
 rtx dwarf = NULL_RTX;
 rtx adjust_sp_rtx, reg, mem, insn;
 int saved_size = cfun->machine->frame.save_libcall_adjustment;
 int offset;
-for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++)
+for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
 {
 	/* The save order is ra, s0, s1, s2 to s11.  */
 	if (regno == RETURN_ADDR_REGNUM)
 	  offset = saved_size - UNITS_PER_WORD;
 rtx insn;
 if (flag_stack_usage_info)
 current_function_static_stack_size = size;
+if (cfun->machine->naked_p)
+return;
 /* When optimizing for size, call a subroutine to save the registers.  */
 if (riscv_use_save_libcall (frame))
 {
 rtx dwarf = NULL_RTX;
 dwarf = riscv_adjust_libcall_cfi_prologue ();
 insn = gen_add3_insn (stack_pointer_rtx,
 			    stack_pointer_rtx,
 			    GEN_INT (-step1));
 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
 size -= step1;
-riscv_for_each_saved_reg (size, riscv_save_reg);
+riscv_for_each_saved_reg (size, riscv_save_reg, false, false);
 }
 frame->mask = mask; /* Undo the above fib.  */
 /* Set up the frame pointer, if we're using one.  */
 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
 				 stack_pointer_rtx, GEN_INT (saved_size));
 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
 			  dwarf);
-for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++)
+for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
 {
 	reg = gen_rtx_REG (SImode, regno);
 	dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
 }
 return dwarf;
 }
-/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
+/* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
-says which.  */
+style says which.  */
 void
-riscv_expand_epilogue (bool sibcall_p)
+riscv_expand_epilogue (int style)
 {
 /* Split the frame into two.  STEP1 is the amount of stack we should
 deallocate before restoring the registers.  STEP2 is the amount we
 should deallocate afterwards.
 Start off by assuming that no registers need to be restored.  */
 struct riscv_frame_info *frame = &cfun->machine->frame;
 unsigned mask = frame->mask;
 HOST_WIDE_INT step1 = frame->total_size;
 HOST_WIDE_INT step2 = 0;
-bool use_restore_libcall = !sibcall_p && riscv_use_save_libcall (frame);
+bool use_restore_libcall = ((style == NORMAL_RETURN)
+			      && riscv_use_save_libcall (frame));
 rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
 rtx insn;
 /* We need to add memory barrier to prevent read from deallocated stack.  */
 bool need_barrier_p = (get_frame_size ()
 			 + cfun->machine->frame.arg_pointer_offset) != 0;
-if (!sibcall_p && riscv_can_use_return_insn ())
+if (cfun->machine->naked_p)
+{
+gcc_assert (style == NORMAL_RETURN);
+emit_jump_insn (gen_return ());
+return;
+}
+if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ())
 {
 emit_jump_insn (gen_return ());
 return;
 }
 if (use_restore_libcall)
 frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
 /* Restore the registers.  */
-riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg);
+riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg,
+			    true, style == EXCEPTION_RETURN);
 if (use_restore_libcall)
 {
 frame->mask = mask; /* Undo the above fib.  */
 gcc_assert (step2 >= frame->save_libcall_adjustment);
 emit_jump_insn (gen_gpr_restore_return (ra));
 return;
 }
 /* Add in the __builtin_eh_return stack adjustment. */
-if (crtl->calls_eh_return)
+if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return)
 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
 			      EH_RETURN_STACKADJ_RTX));
-if (!sibcall_p)
+/* Return from interrupt.  */
+if (cfun->machine->interrupt_handler_p)
+{
+enum riscv_privilege_levels mode = cfun->machine->interrupt_mode;
+gcc_assert (mode != UNKNOWN_MODE);
+if (mode == MACHINE_MODE)
+	emit_jump_insn (gen_riscv_mret ());
+else if (mode == SUPERVISOR_MODE)
+	emit_jump_insn (gen_riscv_sret ());
+else
+	emit_jump_insn (gen_riscv_uret ());
+}
+else if (style != SIBCALL_RETURN)
 emit_jump_insn (gen_simple_return_internal (ra));
+}
+/* Implement EPILOGUE_USES.  */
+bool
+riscv_epilogue_uses (unsigned int regno)
+{
+if (regno == RETURN_ADDR_REGNUM)
+return true;
+if (epilogue_completed && cfun->machine->interrupt_handler_p)
+{
+/* An interrupt function restores temp regs, so we must indicate that
+	 they are live at function end.  */
+if (df_regs_ever_live_p (regno)
+	    || (!crtl->is_leaf && call_used_regs[regno]))
+	return true;
+}
+return false;
 }
 /* Return nonzero if this function is known to have a null epilogue.
 This allows the optimizer to omit jumps to jumps if no stack
 was created.  */
 bool
 riscv_can_use_return_insn (void)
 {
-return reload_completed && cfun->machine->frame.total_size == 0;
+return (reload_completed && cfun->machine->frame.total_size == 0
+	  && ! cfun->machine->interrupt_handler_p);
 }
 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
 When floating-point registers are wider than integer ones, moves between
 {
 default_file_start ();
 /* Instruct GAS to generate position-[in]dependent code.  */
 fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
+/* If the user specifies "-mno-relax" on the command line then disable linker
+relaxation in the assembler.  */
+if (! riscv_mrelax)
+fprintf (asm_out_file, "\t.option norelax\n");
 }
 /* Implement TARGET_ASM_OUTPUT_MI_THUNK.  Generate rtl rather than asm text
 in order to avoid duplicating too much logic from elsewhere.  */
 			 RISCV_TUNE_STRING_DEFAULT);
 tune_info = optimize_size ? &optimize_size_tune_info : cpu->tune_info;
 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
 for size.  For architectures that trap and emulate unaligned accesses,
-the performance cost is too great, even for -Os.  */
+the performance cost is too great, even for -Os.  Similarly, if
+-m[no-]strict-align is left unspecified, heed -mtune's advice.  */
 riscv_slow_unaligned_access_p = (cpu->tune_info->slow_unaligned_access
 				   || TARGET_STRICT_ALIGN);
+if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
+&& cpu->tune_info->slow_unaligned_access)
+target_flags |= MASK_STRICT_ALIGN;
 /* If the user hasn't specified a branch cost, use the processor's
 default.  */
 if (riscv_branch_cost == 0)
 riscv_branch_cost = tune_info->branch_cost;
 /* Require that the ISA supports the requested floating-point ABI.  */
 if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0))
 error ("requested ABI requires -march to subsume the %qc extension",
 	   UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
+if (TARGET_RVE && riscv_abi != ABI_ILP32E)
+error ("rv32e requires ilp32e ABI");
 /* We do not yet support ILP32 on RV64.  */
 if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires -march=rv%d", POINTER_SIZE);
+/* Validate -mpreferred-stack-boundary= value.  */
+riscv_stack_boundary = ABI_STACK_BOUNDARY;
+if (riscv_preferred_stack_boundary_arg)
+{
+int min = ctz_hwi (STACK_BOUNDARY / 8);
+int max = 8;
+if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max))
+	error ("-mpreferred-stack-boundary=%d must be between %d and %d",
+	       riscv_preferred_stack_boundary_arg, min, max);
+riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg;
+}
 }
 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE.  */
 static void
 riscv_conditional_register_usage (void)
 {
+/* We have only x0~x15 on RV32E.  */
+if (TARGET_RVE)
+{
+for (int r = 16; r <= 31; r++)
+	fixed_regs[r] = 1;
+}
+if (riscv_abi == ABI_ILP32E)
+{
+for (int r = 16; r <= 31; r++)
+	call_used_regs[r] = 1;
+}
 if (!TARGET_HARD_FLOAT)
 {
 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 	fixed_regs[regno] = call_used_regs[regno] = 1;
+}
+/* In the soft-float ABI, there are no callee-saved FP registers.  */
+if (UNITS_PER_FP_ARG == 0)
+{
+for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
+	call_used_regs[regno] = 1;
 }
 }
 /* Return a register priority for hard reg REGNO.  */
 /* Flush the code part of the trampoline.  */
 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
 emit_insn (gen_clear_cache (addr, end_addr));
 }
-/* Return leaf_function_p () and memoize the result.  */
-static bool
-riscv_leaf_function_p (void)
-{
-if (cfun->machine->is_leaf == 0)
-cfun->machine->is_leaf = leaf_function_p () ? 1 : -1;
-return cfun->machine->is_leaf > 0;
-}
 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL.  */
 static bool
 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
 			       tree exp ATTRIBUTE_UNUSED)
 {
-/* When optimzing for size, don't use sibcalls in non-leaf routines */
+/* Don't use sibcalls when use save-restore routine.  */
 if (TARGET_SAVE_RESTORE)
-return riscv_leaf_function_p ();
+return false;
+/* Don't use sibcall for naked functions.  */
+if (cfun->machine->naked_p)
+return false;
+/* Don't use sibcall for interrupt functions.  */
+if (cfun->machine->interrupt_handler_p)
+return false;
 return true;
+}
+/* Get the intterupt type, return UNKNOWN_MODE if it's not
+interrupt function. */
+static enum riscv_privilege_levels
+riscv_get_interrupt_type (tree decl)
+{
+gcc_assert (decl != NULL_TREE);
+if ((TREE_CODE(decl) != FUNCTION_DECL)
+|| (!riscv_interrupt_type_p (TREE_TYPE (decl))))
+return UNKNOWN_MODE;
+tree attr_args
+= TREE_VALUE (lookup_attribute ("interrupt",
+				    TYPE_ATTRIBUTES (TREE_TYPE (decl))));
+if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE)
+{
+const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args));
+if (!strcmp (string, "user"))
+	return USER_MODE;
+else if (!strcmp (string, "supervisor"))
+	return SUPERVISOR_MODE;
+else /* Must be "machine".  */
+	return MACHINE_MODE;
+}
+else
+/* Interrupt attributes are machine mode by default.  */
+return MACHINE_MODE;
+}
+/* Implement `TARGET_SET_CURRENT_FUNCTION'.  */
+/* Sanity cheching for above function attributes.  */
+static void
+riscv_set_current_function (tree decl)
+{
+if (decl == NULL_TREE
+|| current_function_decl == NULL_TREE
+|| current_function_decl == error_mark_node
+|| ! cfun->machine
+|| cfun->machine->attributes_checked_p)
+return;
+cfun->machine->naked_p = riscv_naked_function_p (decl);
+cfun->machine->interrupt_handler_p
+= riscv_interrupt_type_p (TREE_TYPE (decl));
+if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p)
+error ("function attributes %qs and %qs are mutually exclusive",
+	   "interrupt", "naked");
+if (cfun->machine->interrupt_handler_p)
+{
+tree ret = TREE_TYPE (TREE_TYPE (decl));
+tree args = TYPE_ARG_TYPES (TREE_TYPE (decl));
+if (TREE_CODE (ret) != VOID_TYPE)
+	error ("%qs function cannot return a value", "interrupt");
+if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
+	error ("%qs function cannot have arguments", "interrupt");
+cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl);
+gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE);
+}
+/* Don't print the above diagnostics more than once.  */
+cfun->machine->attributes_checked_p = 1;
+}
+/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
+static tree
+riscv_merge_decl_attributes (tree olddecl, tree newdecl)
+{
+tree combined_attrs;
+enum riscv_privilege_levels old_interrupt_type
+= riscv_get_interrupt_type (olddecl);
+enum riscv_privilege_levels new_interrupt_type
+= riscv_get_interrupt_type (newdecl);
+/* Check old and new has same interrupt type. */
+if ((old_interrupt_type != UNKNOWN_MODE)
+&& (new_interrupt_type != UNKNOWN_MODE)
+&& (old_interrupt_type != new_interrupt_type))
+error ("%qs function cannot have different intterupt type.", "interrupt");
+/* Create combined attributes.  */
+combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl),
+DECL_ATTRIBUTES (newdecl));
+return combined_attrs;
 }
 /* Implement TARGET_CANNOT_COPY_INSN_P.  */
 static bool
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
+#undef  TARGET_SET_CURRENT_FUNCTION
+#define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
 #undef TARGET_REGISTER_MOVE_COST
 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
 #undef TARGET_MEMORY_MOVE_COST
 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
 #undef TARGET_PRINT_OPERAND_ADDRESS
 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
 #undef TARGET_SETUP_INCOMING_VARARGS
 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
+#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
+#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
 #undef TARGET_STRICT_ARGUMENT_NAMING
 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
 #undef TARGET_MUST_PASS_IN_STACK
 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
 #undef TARGET_PASS_BY_REFERENCE
 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
 #undef TARGET_IN_SMALL_DATA_P
 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
+#undef TARGET_HAVE_SRODATA_SECTION
+#define TARGET_HAVE_SRODATA_SECTION true
+#undef TARGET_ASM_SELECT_SECTION
+#define TARGET_ASM_SELECT_SECTION riscv_select_section
 #undef TARGET_ASM_SELECT_RTX_SECTION
 #define TARGET_ASM_SELECT_RTX_SECTION  riscv_elf_select_rtx_section
 #undef TARGET_MIN_ANCHOR_OFFSET
 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
 #undef TARGET_CONSTANT_ALIGNMENT
 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
+#undef TARGET_MERGE_DECL_ATTRIBUTES
+#define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
+#undef TARGET_WARN_FUNC_RETURN
+#define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
+/* The low bit is ignored by jump instructions so is safe to use.  */
+#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
+#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
 struct gcc_target targetm = TARGET_INITIALIZER;
 #include "gt-riscv.h"

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/riscv/riscv.c @ 131:84e7813d76e9