Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/rs6000/e6500.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
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111:04ced10e8804 131:84e7813d76e9
1 ;; Pipeline description for Freescale PowerPC e6500 core. 1 ;; Pipeline description for Freescale PowerPC e6500 core.
2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com) 3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
197 (eq_attr "cpu" "ppce6500")) 197 (eq_attr "cpu" "ppce6500"))
198 "e6500_decode,e6500_bu") 198 "e6500_decode,e6500_bu")
199 199
200 ;; BU - CR logical. 200 ;; BU - CR logical.
201 (define_insn_reservation "e6500_cr_logical" 1 201 (define_insn_reservation "e6500_cr_logical" 1
202 (and (eq_attr "type" "cr_logical,delayed_cr") 202 (and (eq_attr "type" "cr_logical")
203 (eq_attr "cpu" "ppce6500")) 203 (eq_attr "cpu" "ppce6500"))
204 "e6500_decode,e6500_bu") 204 "e6500_decode,e6500_bu")
205 205
206 ;; VSFX. 206 ;; VSFX.
207 (define_insn_reservation "e6500_vecsimple" 1 207 (define_insn_reservation "e6500_vecsimple" 1