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comparison gcc/config/rs6000/predicates.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 ;; Predicate definitions for POWER and PowerPC. 1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2005-2018 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
404 return 1; 404 return 1;
405 405
406 return FP_REGNO_P (r); 406 return FP_REGNO_P (r);
407 }) 407 })
408 408
409 ;; Return true if this is a register that can has D-form addressing (GPR and 409 ;; Return true if this is a register that can has D-form addressing (GPR,
410 ;; traditional FPR registers for scalars). ISA 3.0 (power9) adds D-form 410 ;; traditional FPR registers, and Altivec registers for scalars). Unlike
411 ;; addressing for scalars in Altivec registers. 411 ;; power8 fusion, this fusion does not depend on putting the ADDIS instruction
412 ;; 412 ;; into the GPR register being loaded.
413 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the 413 (define_predicate "p9_fusion_reg_operand"
414 ;; power9 fusion allow the floating point types.
415 (define_predicate "toc_fusion_or_p9_reg_operand"
416 (match_code "reg,subreg") 414 (match_code "reg,subreg")
417 { 415 {
418 HOST_WIDE_INT r; 416 HOST_WIDE_INT r;
419 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode 417 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
420 || mode == SFmode 418 || mode == SFmode
609 if (GET_MODE (op) != mode 607 if (GET_MODE (op) != mode
610 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) 608 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
611 return 0; 609 return 0;
612 610
613 /* Consider all constants with -msoft-float to be easy. */ 611 /* Consider all constants with -msoft-float to be easy. */
614 if ((TARGET_SOFT_FLOAT 612 if (TARGET_SOFT_FLOAT && mode != DImode)
615 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
616 && mode != DImode)
617 return 1; 613 return 1;
618 614
619 /* 0.0D is not all zero bits. */ 615 /* 0.0D is not all zero bits. */
620 if (DECIMAL_FLOAT_MODE_P (mode)) 616 if (DECIMAL_FLOAT_MODE_P (mode))
621 return 0; 617 return 0;
688 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 684 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
689 ;; vector register without using memory. 685 ;; vector register without using memory.
690 (define_predicate "easy_vector_constant" 686 (define_predicate "easy_vector_constant"
691 (match_code "const_vector") 687 (match_code "const_vector")
692 { 688 {
693 /* As the paired vectors are actually FPRs it seems that there is
694 no easy way to load a CONST_VECTOR without using memory. */
695 if (TARGET_PAIRED_FLOAT)
696 return false;
697
698 /* Because IEEE 128-bit floating point is considered a vector type 689 /* Because IEEE 128-bit floating point is considered a vector type
699 in order to pass it in VSX registers, it might use this function 690 in order to pass it in VSX registers, it might use this function
700 instead of easy_fp_constant. */ 691 instead of easy_fp_constant. */
701 if (FLOAT128_VECTOR_P (mode)) 692 if (FLOAT128_VECTOR_P (mode))
702 return easy_fp_constant (op, mode); 693 return easy_fp_constant (op, mode);
1218 ;; insn, which is true if the corresponding bit in the CC register is set. 1209 ;; insn, which is true if the corresponding bit in the CC register is set.
1219 (define_predicate "branch_positive_comparison_operator" 1210 (define_predicate "branch_positive_comparison_operator"
1220 (and (match_operand 0 "branch_comparison_operator") 1211 (and (match_operand 0 "branch_comparison_operator")
1221 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1212 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1222 1213
1223 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1224 (define_predicate "load_multiple_operation"
1225 (match_code "parallel")
1226 {
1227 int count = XVECLEN (op, 0);
1228 unsigned int dest_regno;
1229 rtx src_addr;
1230 int i;
1231
1232 /* Perform a quick check so we don't blow up below. */
1233 if (count <= 1
1234 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1235 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1236 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1237 return 0;
1238
1239 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1240 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1241
1242 for (i = 1; i < count; i++)
1243 {
1244 rtx elt = XVECEXP (op, 0, i);
1245
1246 if (GET_CODE (elt) != SET
1247 || GET_CODE (SET_DEST (elt)) != REG
1248 || GET_MODE (SET_DEST (elt)) != SImode
1249 || REGNO (SET_DEST (elt)) != dest_regno + i
1250 || GET_CODE (SET_SRC (elt)) != MEM
1251 || GET_MODE (SET_SRC (elt)) != SImode
1252 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1253 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1254 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1255 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1256 return 0;
1257 }
1258
1259 return 1;
1260 })
1261
1262 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1263 ;; The second vector element is a CLOBBER.
1264 (define_predicate "store_multiple_operation"
1265 (match_code "parallel")
1266 {
1267 int count = XVECLEN (op, 0) - 1;
1268 unsigned int src_regno;
1269 rtx dest_addr;
1270 int i;
1271
1272 /* Perform a quick check so we don't blow up below. */
1273 if (count <= 1
1274 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1275 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1276 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1277 return 0;
1278
1279 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1280 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1281
1282 for (i = 1; i < count; i++)
1283 {
1284 rtx elt = XVECEXP (op, 0, i + 1);
1285
1286 if (GET_CODE (elt) != SET
1287 || GET_CODE (SET_SRC (elt)) != REG
1288 || GET_MODE (SET_SRC (elt)) != SImode
1289 || REGNO (SET_SRC (elt)) != src_regno + i
1290 || GET_CODE (SET_DEST (elt)) != MEM
1291 || GET_MODE (SET_DEST (elt)) != SImode
1292 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1293 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1294 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1295 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1296 return 0;
1297 }
1298
1299 return 1;
1300 })
1301
1302 ;; Return 1 if OP is valid for a save_world call in prologue, known to be 1214 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1303 ;; a PARLLEL. 1215 ;; a PARLLEL.
1304 (define_predicate "save_world_operation" 1216 (define_predicate "save_world_operation"
1305 (match_code "parallel") 1217 (match_code "parallel")
1306 { 1218 {
1372 int index; 1284 int index;
1373 int i; 1285 int i;
1374 rtx elt; 1286 rtx elt;
1375 int count = XVECLEN (op, 0); 1287 int count = XVECLEN (op, 0);
1376 1288
1377 if (count != 59) 1289 if (count != 58)
1378 return 0; 1290 return 0;
1379 1291
1380 index = 0; 1292 index = 0;
1381 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 1293 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1382 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1383 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1294 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1384 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 1295 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1385 return 0; 1296 return 0;
1386 1297
1387 elt = XVECEXP (op, 0, index++); 1298 elt = XVECEXP (op, 0, index++);
1749 op = XEXP (op, 0); 1660 op = XEXP (op, 0);
1750 1661
1751 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; 1662 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1752 }) 1663 })
1753 1664
1754 ;; Match the TOC memory operand that can be fused with an addis instruction.
1755 ;; This is used in matching a potential fused address before register
1756 ;; allocation.
1757 (define_predicate "toc_fusion_mem_raw"
1758 (match_code "mem")
1759 {
1760 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1761 return false;
1762
1763 return small_toc_ref (XEXP (op, 0), Pmode);
1764 })
1765
1766 ;; Match the memory operand that has been fused with an addis instruction and
1767 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1768 (define_predicate "toc_fusion_mem_wrapped"
1769 (match_code "mem")
1770 {
1771 rtx addr;
1772
1773 if (!TARGET_TOC_FUSION_INT)
1774 return false;
1775
1776 if (!MEM_P (op))
1777 return false;
1778
1779 addr = XEXP (op, 0);
1780 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1781 })
1782
1783 ;; Match the first insn (addis) in fusing the combination of addis and loads to 1665 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1784 ;; GPR registers on power8. 1666 ;; GPR registers on power8.
1785 (define_predicate "fusion_gpr_addis" 1667 (define_predicate "fusion_gpr_addis"
1786 (match_code "const_int,high,plus") 1668 (match_code "const_int,high,plus")
1787 { 1669 {
1918 1800
1919 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit 1801 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
1920 DFmode in 32-bit if -msoft-float since it splits into two separate 1802 DFmode in 32-bit if -msoft-float since it splits into two separate
1921 instructions. */ 1803 instructions. */
1922 case E_DFmode: 1804 case E_DFmode:
1923 if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION) 1805 if ((!TARGET_POWERPC64 && !TARGET_HARD_FLOAT) || !TARGET_P9_FUSION)
1924 return 0; 1806 return 0;
1925 break; 1807 break;
1926 1808
1927 default: 1809 default:
1928 return 0; 1810 return 0;
1978 1860
1979 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits 1861 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
1980 into two separate instructions. Do allow fusion if we have hardware 1862 into two separate instructions. Do allow fusion if we have hardware
1981 floating point. */ 1863 floating point. */
1982 case E_DFmode: 1864 case E_DFmode:
1983 if (!TARGET_POWERPC64 && !TARGET_DF_FPR) 1865 if (!TARGET_POWERPC64 && !TARGET_HARD_FLOAT)
1984 return 0; 1866 return 0;
1985 break; 1867 break;
1986 1868
1987 default: 1869 default:
1988 return 0; 1870 return 0;