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comparison gcc/config/rs6000/rs6000-c.c @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 /* Subroutines for the C front end on the PowerPC architecture. 1 /* Subroutines for the C front end on the PowerPC architecture.
2 Copyright (C) 2002-2017 Free Software Foundation, Inc. 2 Copyright (C) 2002-2018 Free Software Foundation, Inc.
3 3
4 Contributed by Zack Weinberg <zack@codesourcery.com> 4 Contributed by Zack Weinberg <zack@codesourcery.com>
5 and Paolo Bonzini <bonzini@gnu.org> 5 and Paolo Bonzini <bonzini@gnu.org>
6 6
7 This file is part of GCC. 7 This file is part of GCC.
17 License for more details. 17 License for more details.
18 18
19 You should have received a copy of the GNU General Public License 19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see 20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */ 21 <http://www.gnu.org/licenses/>. */
22
23 #define IN_TARGET_CODE 1
22 24
23 #include "config.h" 25 #include "config.h"
24 #include "system.h" 26 #include "system.h"
25 #include "coretypes.h" 27 #include "coretypes.h"
26 #include "target.h" 28 #include "target.h"
216 we allow the normal handling, this module will be called recursively, 218 we allow the normal handling, this module will be called recursively,
217 and the vector will be skipped.; */ 219 and the vector will be skipped.; */
218 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword))) 220 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
219 { 221 {
220 enum rid rid_code = (enum rid)(ident->rid_code); 222 enum rid rid_code = (enum rid)(ident->rid_code);
221 enum node_type itype = ident->type; 223 bool is_macro = cpp_macro_p (ident);
224
222 /* If there is a function-like macro, check if it is going to be 225 /* If there is a function-like macro, check if it is going to be
223 invoked with or without arguments. Without following ( treat 226 invoked with or without arguments. Without following ( treat
224 it like non-macro, otherwise the following cpp_get_token eats 227 it like non-macro, otherwise the following cpp_get_token eats
225 what should be preserved. */ 228 what should be preserved. */
226 if (itype == NT_MACRO && cpp_fun_like_macro_p (ident)) 229 if (is_macro && cpp_fun_like_macro_p (ident))
227 { 230 {
228 int idx2 = idx; 231 int idx2 = idx;
229 do 232 do
230 tok = cpp_peek_token (pfile, idx2++); 233 tok = cpp_peek_token (pfile, idx2++);
231 while (tok->type == CPP_PADDING); 234 while (tok->type == CPP_PADDING);
232 if (tok->type != CPP_OPEN_PAREN) 235 if (tok->type != CPP_OPEN_PAREN)
233 itype = NT_VOID; 236 is_macro = false;
234 } 237 }
235 if (itype == NT_MACRO) 238
239 if (is_macro)
236 { 240 {
237 do 241 do
238 (void) cpp_get_token (pfile); 242 (void) cpp_get_token (pfile);
239 while (--idx > 0); 243 while (--idx > 0);
240 do 244 do
448 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); 452 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
449 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) 453 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
450 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); 454 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
451 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on 455 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
452 in any of the following conditions: 456 in any of the following conditions:
453 1. The command line specifies either -maltivec=le or -maltivec=be. 457 1. The operating system is Darwin and it is configured for 64
454 2. The operating system is Darwin and it is configured for 64
455 bit. (See darwin_rs6000_override_options.) 458 bit. (See darwin_rs6000_override_options.)
456 3. The operating system is Darwin and the operating system 459 2. The operating system is Darwin and the operating system
457 version is 10.5 or higher and the user has not explicitly 460 version is 10.5 or higher and the user has not explicitly
458 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and 461 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
459 the compiler is not producing code for integration within the 462 the compiler is not producing code for integration within the
460 kernel. (See darwin_rs6000_override_options.) 463 kernel. (See darwin_rs6000_override_options.)
461 Note that the OPTION_MASK_ALTIVEC flag is automatically turned 464 Note that the OPTION_MASK_ALTIVEC flag is automatically turned
486 flag is considered to have been explicitly turned on. 489 flag is considered to have been explicitly turned on.
487 Note that the OPTION_MASK_VSX flag is automatically turned off in 490 Note that the OPTION_MASK_VSX flag is automatically turned off in
488 the following conditions: 491 the following conditions:
489 1. The operating system does not support saving of AltiVec 492 1. The operating system does not support saving of AltiVec
490 registers (OS_MISSING_ALTIVEC). 493 registers (OS_MISSING_ALTIVEC).
491 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT, 494 2. If the option TARGET_HARD_FLOAT is turned off. Hereafter, the
492 or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
493 OPTION_MASK_VSX flag is considered to have been turned off 495 OPTION_MASK_VSX flag is considered to have been turned off
494 explicitly. 496 explicitly.
495 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the 497 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
496 OPTION_MASK_VSX flag is considered to have been turned off
497 explicitly.
498 4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
499 compilation context, or if it is turned on by any means in an 498 compilation context, or if it is turned on by any means in an
500 inner compilation context. Hereafter, the OPTION_MASK_VSX 499 inner compilation context. Hereafter, the OPTION_MASK_VSX
501 flag is considered to have been turned off explicitly. 500 flag is considered to have been turned off explicitly.
502 5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the 501 4. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
503 OPTION_MASK_VSX flag is considered to have been turned off 502 OPTION_MASK_VSX flag is considered to have been turned off
504 explicitly. 503 explicitly.
505 6. If an inner context (as introduced by 504 5. If an inner context (as introduced by
506 __attribute__((__target__())) or #pragma GCC target() 505 __attribute__((__target__())) or #pragma GCC target()
507 requests a target that normally enables the 506 requests a target that normally enables the
508 OPTION_MASK_VSX flag but the outer-most "main target" 507 OPTION_MASK_VSX flag but the outer-most "main target"
509 does not support the rs6000_altivec_abi, this flag is 508 does not support the rs6000_altivec_abi, this flag is
510 turned off for the inner context unless OPTION_MASK_VSX 509 turned off for the inner context unless OPTION_MASK_VSX
586 via the target attribute/pragma. */ 585 via the target attribute/pragma. */
587 if ((flags & OPTION_MASK_FLOAT128_HW) != 0) 586 if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
588 rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); 587 rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
589 588
590 /* options from the builtin masks. */ 589 /* options from the builtin masks. */
591 /* Note that RS6000_BTM_PAIRED is enabled only if
592 TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
593 if ((bu_mask & RS6000_BTM_PAIRED) != 0)
594 rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
595 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu == 590 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
596 PROCESSOR_CELL) (e.g. -mcpu=cell). */ 591 PROCESSOR_CELL) (e.g. -mcpu=cell). */
597 if ((bu_mask & RS6000_BTM_CELL) != 0) 592 if ((bu_mask & RS6000_BTM_CELL) != 0)
598 rs6000_define_or_undefine_macro (define_p, "__PPU__"); 593 rs6000_define_or_undefine_macro (define_p, "__PPU__");
599 } 594 }
613 builtin_define ("__RSQRTE__"); 608 builtin_define ("__RSQRTE__");
614 if (TARGET_FRSQRTES) 609 if (TARGET_FRSQRTES)
615 builtin_define ("__RSQRTEF__"); 610 builtin_define ("__RSQRTEF__");
616 if (TARGET_FLOAT128_TYPE) 611 if (TARGET_FLOAT128_TYPE)
617 builtin_define ("__FLOAT128_TYPE__"); 612 builtin_define ("__FLOAT128_TYPE__");
618 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
619 builtin_define ("__ibm128=long double");
620 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB 613 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
621 builtin_define ("__BUILTIN_CPU_SUPPORTS__"); 614 builtin_define ("__BUILTIN_CPU_SUPPORTS__");
622 #endif 615 #endif
623 616
624 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM) 617 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
638 631
639 /* Enable context-sensitive macros. */ 632 /* Enable context-sensitive macros. */
640 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; 633 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
641 } 634 }
642 } 635 }
643 if (!TARGET_HARD_FLOAT 636 if (!TARGET_HARD_FLOAT)
644 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
645 builtin_define ("_SOFT_DOUBLE"); 637 builtin_define ("_SOFT_DOUBLE");
646 /* Used by lwarx/stwcx. errata work-around. */ 638 /* Used by lwarx/stwcx. errata work-around. */
647 if (rs6000_cpu == PROCESSOR_PPC405) 639 if (rs6000_cpu == PROCESSOR_PPC405)
648 builtin_define ("__PPC405__"); 640 builtin_define ("__PPC405__");
649 /* Used by libstdc++. */ 641 /* Used by libstdc++. */
681 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp"); 673 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
682 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); 674 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
683 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); 675 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
684 } 676 }
685 677
678 /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */
679 if (TARGET_FLOAT128_TYPE)
680 {
681 builtin_define ("__builtin_fabsq=__builtin_fabsf128");
682 builtin_define ("__builtin_copysignq=__builtin_copysignf128");
683 builtin_define ("__builtin_nanq=__builtin_nanf128");
684 builtin_define ("__builtin_nansq=__builtin_nansf128");
685 builtin_define ("__builtin_infq=__builtin_inff128");
686 builtin_define ("__builtin_huge_valq=__builtin_huge_valf128");
687 }
688
686 /* Tell users they can use __builtin_bswap{16,64}. */ 689 /* Tell users they can use __builtin_bswap{16,64}. */
687 builtin_define ("__HAVE_BSWAP__"); 690 builtin_define ("__HAVE_BSWAP__");
688 691
689 /* May be overridden by target configuration. */ 692 /* May be overridden by target configuration. */
690 RS6000_CPU_CPP_ENDIAN_BUILTINS(); 693 RS6000_CPU_CPP_ENDIAN_BUILTINS();
693 { 696 {
694 builtin_define ("__LONG_DOUBLE_128__"); 697 builtin_define ("__LONG_DOUBLE_128__");
695 builtin_define ("__LONGDOUBLE128"); 698 builtin_define ("__LONGDOUBLE128");
696 699
697 if (TARGET_IEEEQUAD) 700 if (TARGET_IEEEQUAD)
698 builtin_define ("__LONG_DOUBLE_IEEE128__"); 701 {
702 /* Older versions of GLIBC used __attribute__((__KC__)) to create the
703 IEEE 128-bit floating point complex type for C++ (which does not
704 support _Float128 _Complex). If the default for long double is
705 IEEE 128-bit mode, the library would need to use
706 __attribute__((__TC__)) instead. Defining __KF__ and __KC__
707 is a stop-gap to build with the older libraries, until we
708 get an updated library. */
709 builtin_define ("__LONG_DOUBLE_IEEE128__");
710 builtin_define ("__KF__=__TF__");
711 builtin_define ("__KC__=__TC__");
712 }
699 else 713 else
700 builtin_define ("__LONG_DOUBLE_IBM128__"); 714 builtin_define ("__LONG_DOUBLE_IBM128__");
701 } 715 }
702 716
703 switch (TARGET_CMODEL) 717 switch (TARGET_CMODEL)
733 default: 747 default:
734 break; 748 break;
735 } 749 }
736 750
737 /* Vector element order. */ 751 /* Vector element order. */
738 if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) 752 if (BYTES_BIG_ENDIAN)
739 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); 753 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
740 else 754 else
741 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); 755 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
742 756
743 /* Let the compiled code know if 'f' class registers will not be available. */ 757 /* Let the compiled code know if 'f' class registers will not be available. */
748 if their alignment is 16 bytes or larger. */ 762 if their alignment is 16 bytes or larger. */
749 if ((TARGET_MACHO && rs6000_darwin64_abi) 763 if ((TARGET_MACHO && rs6000_darwin64_abi)
750 || DEFAULT_ABI == ABI_ELFv2 764 || DEFAULT_ABI == ABI_ELFv2
751 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) 765 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
752 builtin_define ("__STRUCT_PARM_ALIGN__=16"); 766 builtin_define ("__STRUCT_PARM_ALIGN__=16");
753
754 /* Generate defines for Xilinx FPU. */
755 if (rs6000_xilinx_fpu)
756 {
757 builtin_define ("_XFPU");
758 if (rs6000_single_float && ! rs6000_double_float)
759 {
760 if (rs6000_simple_fpu)
761 builtin_define ("_XFPU_SP_LITE");
762 else
763 builtin_define ("_XFPU_SP_FULL");
764 }
765 if (rs6000_double_float)
766 {
767 if (rs6000_simple_fpu)
768 builtin_define ("_XFPU_DP_LITE");
769 else
770 builtin_define ("_XFPU_DP_FULL");
771 }
772 }
773 } 767 }
774 768
775 769
776 struct altivec_builtin_types 770 struct altivec_builtin_types
777 { 771 {
871 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 865 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
872 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 866 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
873 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 867 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
874 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, 868 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
875 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 869 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
870 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
871 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
876 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 872 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
877 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 873 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
878 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 874 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
879 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 875 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
880 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 876 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
901 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 897 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
902 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 898 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
903 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 899 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
904 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 900 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
905 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 901 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
902 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
903 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
906 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 904 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
907 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
908 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 906 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
909 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 907 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
910 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 908 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
1146 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1144 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1145 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1148 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1146 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1149 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1150 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1148 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1149 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1150 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1151 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1151 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1152 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1152 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1153 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1153 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1154 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1154 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1375 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1375 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1376 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, 1376 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1377 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1377 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1378 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, 1378 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1379 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1379 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1380 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1381 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1382 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1383 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1384 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, 1380 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1385 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1381 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1386 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, 1382 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1387 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1383 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1388 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1389 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1390 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1391 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1392 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, 1384 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1393 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1385 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1394 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, 1386 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1395 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1387 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1396 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1397 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1398 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1399 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1400 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, 1388 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1401 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1389 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1402 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, 1390 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1403 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1391 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1404 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, 1392 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1510 1498
1511 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, 1499 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1512 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, 1500 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1513 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, 1501 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1514 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1502 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1515 { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI, 1503 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1504 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1505 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1516 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1506 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1517 { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI, 1507 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1518 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 1508 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1519 RS6000_BTI_unsigned_V2DI, 0 }, 1509 RS6000_BTI_unsigned_V2DI, 0 },
1520 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, 1510 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1521 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1511 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1522 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, 1512 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1527 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1517 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1528 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, 1518 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1529 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, 1519 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1530 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, 1520 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1531 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1521 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1522
1523 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1524 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1525 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1526 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1527 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1528 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1529 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1530 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1532 1531
1533 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1532 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1534 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1533 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1535 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1534 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1536 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1535 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1613 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1612 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1614 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1613 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1615 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1614 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1616 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1615 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1617 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1616 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1617
1618 /* vector float vec_ldl (int, vector float *);
1619 vector float vec_ldl (int, float *); */
1618 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1620 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1619 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1621 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1620 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1622 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1621 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1623 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1624
1625 /* vector bool int vec_ldl (int, vector bool int *);
1626 vector bool int vec_ldl (int, bool int *);
1627 vector int vec_ldl (int, vector int *);
1628 vector int vec_ldl (int, int *);
1629 vector unsigned int vec_ldl (int, vector unsigned int *);
1630 vector unsigned int vec_ldl (int, unsigned int *); */
1622 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1631 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1623 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1632 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1633 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1634 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1624 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1635 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1625 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1636 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1626 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1637 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1627 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1638 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1628 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1639 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1629 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1630 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1631 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1640 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1632 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1641 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1633 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1642 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1634 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1643
1635 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1644 /* vector bool short vec_ldl (int, vector bool short *);
1645 vector bool short vec_ldl (int, bool short *);
1646 vector pixel vec_ldl (int, vector pixel *);
1647 vector short vec_ldl (int, vector short *);
1648 vector short vec_ldl (int, short *);
1649 vector unsigned short vec_ldl (int, vector unsigned short *);
1650 vector unsigned short vec_ldl (int, unsigned short *); */
1636 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1651 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1637 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1652 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1653 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1654 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1638 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1655 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1639 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1656 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1640 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1657 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1641 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1658 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1642 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1659 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1643 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1660 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1644 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1661 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1645 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1662 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1646 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1663 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1647 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1664 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1665
1666 /* vector bool char vec_ldl (int, vector bool char *);
1667 vector bool char vec_ldl (int, bool char *);
1668 vector char vec_ldl (int, vector char *);
1669 vector char vec_ldl (int, char *);
1670 vector unsigned char vec_ldl (int, vector unsigned char *);
1671 vector unsigned char vec_ldl (int, unsigned char *); */
1648 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1672 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1649 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1673 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1674 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1675 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1650 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1676 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1651 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1677 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1652 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1678 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1653 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1679 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1654 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1680 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1655 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1681 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1656 ~RS6000_BTI_unsigned_V16QI, 0 }, 1682 ~RS6000_BTI_unsigned_V16QI, 0 },
1657 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1683 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1658 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1685
1686 /* vector double vec_ldl (int, vector double *);
1687 vector double vec_ldl (int, double *); */
1659 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1688 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1660 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1689 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1690 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1691 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1692
1693 /* vector long long vec_ldl (int, vector long long *);
1694 vector long long vec_ldl (int, long long *);
1695 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1696 vector unsigned long long vec_ldl (int, unsigned long long *);
1697 vector bool long long vec_ldl (int, vector bool long long *);
1698 vector bool long long vec_ldl (int, bool long long *); */
1661 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1699 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1662 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1700 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1701 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1702 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1663 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1703 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1664 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1704 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1665 ~RS6000_BTI_unsigned_V2DI, 0 }, 1705 ~RS6000_BTI_unsigned_V2DI, 0 },
1666 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1706 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1707 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1708 ~RS6000_BTI_unsigned_long_long, 0 },
1709 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1667 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1710 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1711 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1712 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1713
1668 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1714 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1669 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1715 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1670 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1716 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1671 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1672 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1718 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
2197 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2243 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2198 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, 2244 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2199 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2200 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, 2246 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2201 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2247 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2202 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW, 2248 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
2203 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2249 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2204 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW, 2250 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
2205 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 2251 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2206 RS6000_BTI_unsigned_V4SI, 0 }, 2252 RS6000_BTI_unsigned_V4SI, 0 },
2207 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, 2253 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2208 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2254 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2209 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, 2255 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2210 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2256 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2211 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, 2257 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2212 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2258 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2213 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, 2259 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2214 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2260 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2215 { ALTIVEC_BUILTIN_VEC_VMULEUW, ALTIVEC_BUILTIN_VMULEUW, 2261 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
2216 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2262 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2217 { ALTIVEC_BUILTIN_VEC_VMULESW, ALTIVEC_BUILTIN_VMULESW, 2263 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
2218 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2264 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2219 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, 2265 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2220 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2266 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2221 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, 2267 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2222 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2268 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2223 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, 2269 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2224 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2270 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2225 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW, 2271 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
2226 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2272 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2227 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW, 2273 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
2228 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 2274 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2229 RS6000_BTI_unsigned_V4SI, 0 }, 2275 RS6000_BTI_unsigned_V4SI, 0 },
2230 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, 2276 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2231 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2277 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2232 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, 2278 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2235 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2281 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2236 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, 2282 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2237 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2283 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2238 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, 2284 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2239 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2285 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2240 { ALTIVEC_BUILTIN_VEC_VMULOUW, ALTIVEC_BUILTIN_VMULOUW, 2286 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
2241 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2287 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2242 { ALTIVEC_BUILTIN_VEC_VMULOSW, ALTIVEC_BUILTIN_VMULOSW, 2288 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
2243 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2289 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2244 2290
2245 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI, 2291 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2246 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 2292 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2247 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI, 2293 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2256 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2302 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2257 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, 2303 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2258 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2304 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2259 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, 2305 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2260 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2306 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2261
2262 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
2263 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2264 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
2265 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2266 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
2267 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2268 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
2269 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2270 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
2271 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2272 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
2273 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2274 2307
2275 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2308 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2276 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2309 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2277 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2310 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2278 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2311 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2392 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2425 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2393 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2426 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2394 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2427 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2395 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2428 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2396 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2429 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2397 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2430 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
2398 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2431 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2432
2433 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2434 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2435 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2436 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2437 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2438 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2439 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2440 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2441 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2442 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2443 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2444 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2399 2445
2400 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, 2446 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2401 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2447 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2448
2449 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2450 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2451 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2452 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2453 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2454 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2455 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2456 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2457 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2458 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2459 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2460 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2461 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2462 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2463 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2464 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2465 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2466 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2467 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2468 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2469 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2470 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2471 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2472 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2473 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2474 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2475 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2476 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2477 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2478 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2479 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2480 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2481 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2482 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2483 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2484 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2485
2486 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2487 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2488 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2489 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2490 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2492 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2493 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2494 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2495 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2496 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2497 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2498 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2499 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2500 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2501 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2502 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2503 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2402 2504
2403 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2505 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2404 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2506 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2405 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2507 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2406 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2508 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2442 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2544 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2443 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, 2545 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2444 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2546 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2445 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2547 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2446 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2548 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2447 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2549 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2448 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2550 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2449 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, 2551 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2450 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2552 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2451 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, 2553 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2452 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2554 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2584 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2686 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2687 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2586 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2688 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2689 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2588 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2690 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2691
2692 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2693 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2694 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2695 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2696 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2697 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2698 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2699 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2700 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2701 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2702
2589 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2703 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2590 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2704 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2705 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2592 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2706 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2707 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2792 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2906 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2793 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2907 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2794 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2908 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2795 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2909 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2796 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2910 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2911 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2912 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2913 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2914 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2797 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2915 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2798 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2916 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2799 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2917 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2800 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2918 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2801 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2919 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2824 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2942 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2825 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2943 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2826 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2944 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2827 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2945 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2828 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2946 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2947 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2948 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2949 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2950 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2951 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2952 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2953 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2954 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2955
2829 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2956 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2830 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2957 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2831 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2958 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2832 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2959 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2833 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2960 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3042 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 3169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3043 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS, 3170 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3044 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3171 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3045 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, 3172 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3046 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3173 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3047 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF, 3174
3175 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3048 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 3176 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3049 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF, 3177 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3050 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 3178 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3051 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, 3179 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3180 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3181 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3182 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
3183 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3184 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3185 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3052 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 3186 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3053 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, 3187 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3054 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 3188 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3055 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, 3189 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3190 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
3191 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3056 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3192 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3057 ~RS6000_BTI_unsigned_V2DI, 0 }, 3193 ~RS6000_BTI_unsigned_V2DI, 0 },
3058 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, 3194 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3059 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3195 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3060 ~RS6000_BTI_unsigned_long_long, 0 }, 3196 ~RS6000_BTI_unsigned_long_long, 0 },
3061 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF, 3197 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3198 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
3199
3200 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3062 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 3201 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3063 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF, 3202 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3064 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 3203 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3065 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, 3204 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3066 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 3205 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3067 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, 3206 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3068 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 3207 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3069 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, 3208 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3070 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 3209 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3071 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, 3210 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3072 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 3211 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3073 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, 3212 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3074 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 3213 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3075 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, 3214 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3076 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 3215 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3077 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, 3216 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3078 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 3217 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3079 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, 3218 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3080 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 3219 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3081 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, 3220 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3082 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 3221 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3083 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, 3222 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3084 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 3223 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3085 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, 3224 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3086 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3225 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3087 ~RS6000_BTI_unsigned_V16QI, 0 }, 3226 ~RS6000_BTI_unsigned_V16QI, 0 },
3088 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, 3227 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3089 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3228 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3090 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V16QI, 3229
3230 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3231 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3232 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3233 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3234 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3235 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3236 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3237 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3238 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3239 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3240 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3241 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3242 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3243 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3244 ~RS6000_BTI_unsigned_V2DI, 0 },
3245 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3246 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3247 ~RS6000_BTI_unsigned_long_long, 0 },
3248 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3249 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3250 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3251 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3252 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3253 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3254 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3255 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3256 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3257 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3258 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3259 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3260 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3261 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3262 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3263 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3264 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3266 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3267 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3268 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3269 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3270 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3271 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3272 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3274 ~RS6000_BTI_unsigned_V16QI, 0 },
3275 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3091 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3276 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3092 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V16QI,
3093 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3094 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V8HI,
3095 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3096 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V8HI,
3097 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3098 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SI,
3099 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3100 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SI,
3101 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3102 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DI,
3103 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3104 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DI,
3105 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3106 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SF,
3107 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3108 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DF,
3109 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3110 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3277 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3111 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3278 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3112 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3279 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3113 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 3280 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3114 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3281 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3430 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3597 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3431 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3598 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3432 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3599 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3433 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3600 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3434 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3601 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3602
3603 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3604 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3605 RS6000_BTI_bool_V16QI },
3606 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3607 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3608 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3609 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3610 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3611
3435 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3612 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3436 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, 3613 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3437 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3614 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3438 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, 3615 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3439 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3616 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3501 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3678 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3502 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3679 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3503 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3680 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3504 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3681 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3505 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, 3682 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3506 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 3683 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3507 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3684 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3508 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 3685 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3509 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3686 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3510 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE }, 3687 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3511 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3688 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, 3689 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3513 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3690 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3514 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 3691 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3515 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3692 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3516 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, 3693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3517 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3694 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3518 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE }, 3695 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3519 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3696 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3520 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE }, 3697 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3521 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3698 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3522 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 3699 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3523 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3700 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3524 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, 3701 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3525 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3702 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3526 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, 3703 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3527 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, 3704 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3528 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, 3705 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3706 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3707 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3708 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3709 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3710 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3711 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3712
3529 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3713 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3530 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 3714 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3531 RS6000_BTI_NOT_OPAQUE }, 3715 RS6000_BTI_INTSI },
3532 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3716 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3533 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3717 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3534 RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, 3718 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3535 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3719 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3536 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 3720 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3537 RS6000_BTI_NOT_OPAQUE }, 3721 RS6000_BTI_INTSI },
3538 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3722 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3723 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3540 RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, 3724 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3541 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3725 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3542 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 3726 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3543 RS6000_BTI_NOT_OPAQUE }, 3727 RS6000_BTI_INTSI },
3544 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3728 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3545 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3729 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3546 RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, 3730 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3547 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3731 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3548 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 3732 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3549 RS6000_BTI_NOT_OPAQUE }, 3733 RS6000_BTI_INTSI },
3550 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3734 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3551 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3735 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3552 RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, 3736 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3737
3553 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3738 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3554 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3739 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3555 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3740 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3556 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3741 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3557 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3742 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3880 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4065 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3881 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4066 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3882 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 4067 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3883 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4068 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3884 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4069 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3885 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF, 4070 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3886 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 4071 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3887 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF, 4072 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3888 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 4073 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3889 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, 4074 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3890 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 4075 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3891 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, 4076 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4077 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
4078 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
4079 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
4080 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4081 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4082 ~RS6000_BTI_unsigned_V2DI },
4083 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4084 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4085 ~RS6000_BTI_bool_V2DI },
4086 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4087 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4088 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4089 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4090 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4091 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4092 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4093 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4094 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4095 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4096 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4097 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4098 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4099 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4100 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4101 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4102 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4103 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4104 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4105 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4106 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4107 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4108 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4109 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4110 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4111 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4112 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4113 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4114 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4115 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4116 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4117 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4118 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4119 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4120 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4121 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4122 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4123 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4124 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4125 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4126 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4127 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4128 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4129 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4130 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4131 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4132 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4133 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4134 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4135 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4136 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4137 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4138 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4139 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
4140 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4141 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
4142 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4143 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4144 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3892 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 4145 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3893 ~RS6000_BTI_long_long }, 4146 ~RS6000_BTI_long_long },
3894 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, 4147 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3895 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4148 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3896 ~RS6000_BTI_unsigned_V2DI }, 4149 ~RS6000_BTI_unsigned_V2DI },
3897 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, 4150 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3898 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4151 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3899 ~RS6000_BTI_unsigned_long_long }, 4152 ~RS6000_BTI_unsigned_long_long },
3900 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF, 4153 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3901 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4154 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3902 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF, 4155 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3903 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4156 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3904 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, 4157 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3905 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4158 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3906 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, 4159 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3907 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4160 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3908 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, 4161 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3909 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4162 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3910 ~RS6000_BTI_unsigned_V4SI }, 4163 ~RS6000_BTI_unsigned_V4SI },
3911 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, 4164 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3912 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4165 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3913 ~RS6000_BTI_UINTSI }, 4166 ~RS6000_BTI_UINTSI },
3914 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, 4167 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3915 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4168 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3916 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, 4169 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3917 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4170 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3918 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, 4171 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3919 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4172 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3920 ~RS6000_BTI_unsigned_V8HI }, 4173 ~RS6000_BTI_unsigned_V8HI },
3921 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, 4174 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
3922 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4175 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3923 ~RS6000_BTI_UINTHI }, 4176 ~RS6000_BTI_UINTHI },
3924 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, 4177 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3925 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4178 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3926 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, 4179 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3927 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4180 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3928 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, 4181 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3929 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4182 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3930 ~RS6000_BTI_unsigned_V16QI }, 4183 ~RS6000_BTI_unsigned_V16QI },
3931 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, 4184 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
3932 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4185 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3933 ~RS6000_BTI_UINTQI }, 4186 ~RS6000_BTI_UINTQI },
3934 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 4187 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3935 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 4188 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3936 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 4189 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3937 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4190 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3938 RS6000_BTI_NOT_OPAQUE }, 4191 RS6000_BTI_INTSI },
3939 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 4192 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3940 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 4193 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3941 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 4194 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3942 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4195 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3943 RS6000_BTI_NOT_OPAQUE }, 4196 RS6000_BTI_INTSI },
3944 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 4197 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3945 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 4198 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3946 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 4199 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3947 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4200 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3948 RS6000_BTI_NOT_OPAQUE }, 4201 RS6000_BTI_INTSI },
3949 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 4202 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3950 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, 4203 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3951 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 4204 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3952 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4205 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3953 RS6000_BTI_NOT_OPAQUE }, 4206 RS6000_BTI_INTSI },
3954 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, 4207 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3955 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 4208 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3956 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, 4209 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3957 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, 4210 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4211
3958 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, 4212 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3959 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, 4213 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3960 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 4214 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3961 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, 4215 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3962 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 4216 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3963 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4217 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3964 RS6000_BTI_NOT_OPAQUE }, 4218 RS6000_BTI_INTSI },
3965 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, 4219 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3966 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 4220 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3967 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 4221 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3968 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 4222 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3969 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 4223 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3970 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4224 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3971 RS6000_BTI_NOT_OPAQUE }, 4225 RS6000_BTI_INTSI },
3972 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 4226 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3973 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 4227 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3974 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 4228 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4229 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3976 RS6000_BTI_NOT_OPAQUE }, 4230 RS6000_BTI_INTSI },
3977 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 4231 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3978 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 4232 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3979 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 4233 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3980 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4234 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3981 RS6000_BTI_NOT_OPAQUE }, 4235 RS6000_BTI_INTSI },
3982 4236
3983 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 4237 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3984 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 4238 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3985 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 4239 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3986 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 4240 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3987 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4241 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3988 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 4242 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3989 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4243 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4244 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
4245 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4246 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4247 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4248 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
4249 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4250 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3991 ~RS6000_BTI_unsigned_V2DI, 0 }, 4251 ~RS6000_BTI_unsigned_V2DI, 0 },
4252 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4253 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3992 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4254 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3993 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 4255 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3994 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 4256 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3995 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 4257 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3996 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 4258 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4038 4300
4039 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 4301 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4040 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 4302 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4041 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 4303 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4042 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 4304 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4305 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4306 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4307 ~RS6000_BTI_long_long },
4308 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4309 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4310 ~RS6000_BTI_unsigned_long_long },
4311 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4312 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4313 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4314 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
4043 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4315 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4044 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 4316 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4045 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4317 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4046 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4318 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4047 ~RS6000_BTI_unsigned_V2DI }, 4319 ~RS6000_BTI_unsigned_V2DI },
5171 RS6000_BTI_V4SI, 0 }, 5443 RS6000_BTI_V4SI, 0 },
5172 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, 5444 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5173 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 5445 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5174 RS6000_BTI_unsigned_V4SI, 0 }, 5446 RS6000_BTI_unsigned_V4SI, 0 },
5175 5447
5176 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB, 5448 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5177 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5449 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5178 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB, 5450 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5179 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5451 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5180 5452
5181 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB, 5453 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5182 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5454 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5183 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB, 5455 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5184 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5456 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5185 5457 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5186 { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, 5458 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5187 RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 }, 5459 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5188 { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, 5460 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5189 RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 }, 5461
5462 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5463 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5190 5464
5191 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH, 5465 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5192 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5466 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5193 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL, 5467 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5194 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5468 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5244 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5518 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5245 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5519 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5246 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5520 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5247 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5521 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5248 5522
5249 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, 5523 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5250 RS6000_BTI_V16QI, RS6000_BTI_V4SI, 5524 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5251 RS6000_BTI_V16QI, RS6000_BTI_UINTSI }, 5525 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5252 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, 5526 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5253 RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
5254 RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5255 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5256 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 5527 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI }, 5528 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5258 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5259 RS6000_BTI_V16QI, RS6000_BTI_INTDI,
5260 RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5261 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5262 RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
5263 RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5264 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5265 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
5266 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5267 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5268 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
5269 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5270 5529
5271 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5530 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5272 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5531 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5273 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5532 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5274 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5533 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5324 RS6000_BTI_bool_V2DI, 0 }, 5583 RS6000_BTI_bool_V2DI, 0 },
5325 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5584 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5326 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5585 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5327 RS6000_BTI_unsigned_V2DI, 0 }, 5586 RS6000_BTI_unsigned_V2DI, 0 },
5328 5587
5588 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5589 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5590 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5591 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5592 RS6000_BTI_unsigned_V2DI, 0 },
5593 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5594 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5595 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5596 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5597 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5598 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5329 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5599 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5330 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5600 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5331 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5601 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5332 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5602 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5333 RS6000_BTI_unsigned_V4SI, 0 }, 5603 RS6000_BTI_unsigned_V4SI, 0 },
5334 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5604 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5335 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5605 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5336 5606
5337 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 5607 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5338 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5608 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5339 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 5609 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5340 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5341 RS6000_BTI_unsigned_V4SI, 0 }, 5611 RS6000_BTI_unsigned_V4SI, 0 },
5342 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 5612 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5343 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5613 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5614 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5615 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5616 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5617 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5618 RS6000_BTI_unsigned_V2DI, 0 },
5619 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5620 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5621 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5622 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5623 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5624 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5344 5625
5345 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB, 5626 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5346 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 5627 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5347 RS6000_BTI_unsigned_V16QI, 0 }, 5628 RS6000_BTI_unsigned_V16QI, 0 },
5348 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH, 5629 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5549 RS6000_BTI_unsigned_V16QI, 0 }, 5830 RS6000_BTI_unsigned_V16QI, 0 },
5550 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV, 5831 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5832 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5552 RS6000_BTI_unsigned_V16QI, 0 }, 5833 RS6000_BTI_unsigned_V16QI, 0 },
5553 5834
5554 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI, 5835 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5836 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5837 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5838 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5839 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5840 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5841 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5842 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5843 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5844 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5845 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5846 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5847 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5848 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5849 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5850 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5851 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5852 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5853 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5854 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5855 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5856 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5857 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5858 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5859 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5555 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5860 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5556 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI, 5861 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5557 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5558 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5559 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5862 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5560 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI, 5863 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5561 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5562 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5563 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5564 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5565 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5566 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5567 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5568 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
5569 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 5864 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5570 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI, 5865 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5571 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5572 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5573 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5574 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5575 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5576 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
5577 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 5866 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5578 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5579 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5580 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5581 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5582 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5583 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5584 5867
5585 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5868 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5586 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5869 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5587 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5870 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5588 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5871 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5617 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5900 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5618 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF, 5901 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5619 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5902 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5620 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, 5903 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5621 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5904 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5622 { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF, 5905 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5623 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5906 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5624 5907
5625 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, 5908 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5626 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5909 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5627 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF, 5910 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5628 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5911 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5629 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF, 5912 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5630 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5913 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5631 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, 5914 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5632 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5915 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5633 { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF, 5916 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5634 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 5917 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5635 RS6000_BTI_V2DF, 0 }, 5918 RS6000_BTI_V2DF, 0 },
5636 5919
5637 /* Crypto builtins. */ 5920 /* Crypto builtins. */
5638 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, 5921 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5684 tree t; 5967 tree t;
5685 t = rs6000_builtin_types[id < 0 ? ~id : id]; 5968 t = rs6000_builtin_types[id < 0 ? ~id : id];
5686 return id < 0 ? build_pointer_type (t) : t; 5969 return id < 0 ? build_pointer_type (t) : t;
5687 } 5970 }
5688 5971
5689 /* Check whether the type of an argument, T, is compatible with a 5972 /* Check whether the type of an argument, T, is compatible with a type ID
5690 type ID stored into a struct altivec_builtin_types. Integer 5973 stored into a struct altivec_builtin_types. Integer types are considered
5691 types are considered compatible; otherwise, the language hook 5974 compatible; otherwise, the language hook lang_hooks.types_compatible_p makes
5692 lang_hooks.types_compatible_p makes the decision. */ 5975 the decision. Also allow long double and _Float128 to be compatible if
5693 5976 -mabi=ieeelongdouble. */
5977
5978 static inline bool
5979 is_float128_p (tree t)
5980 {
5981 return (t == float128_type_node
5982 || (TARGET_IEEEQUAD
5983 && TARGET_LONG_DOUBLE_128
5984 && t == long_double_type_node));
5985 }
5986
5694 static inline bool 5987 static inline bool
5695 rs6000_builtin_type_compatible (tree t, int id) 5988 rs6000_builtin_type_compatible (tree t, int id)
5696 { 5989 {
5697 tree builtin_type; 5990 tree builtin_type;
5698 builtin_type = rs6000_builtin_type (id); 5991 builtin_type = rs6000_builtin_type (id);
5699 if (t == error_mark_node) 5992 if (t == error_mark_node)
5700 return false; 5993 return false;
5701 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type)) 5994 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
5995 return true;
5996 else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
5997 && is_float128_p (t) && is_float128_p (builtin_type))
5702 return true; 5998 return true;
5703 else 5999 else
5704 return lang_hooks.types_compatible_p (t, builtin_type); 6000 return lang_hooks.types_compatible_p (t, builtin_type);
5705 } 6001 }
5706 6002
5812 if (TARGET_DEBUG_BUILTIN) 6108 if (TARGET_DEBUG_BUILTIN)
5813 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", 6109 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
5814 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); 6110 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
5815 6111
5816 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ 6112 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */
5817 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG) 6113 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !BYTES_BIG_ENDIAN)
5818 warning (OPT_Wdeprecated, 6114 warning (OPT_Wdeprecated,
5819 "vec_lvsl is deprecated for little endian; use " 6115 "vec_lvsl is deprecated for little endian; use "
5820 "assignment for unaligned loads and stores"); 6116 "assignment for unaligned loads and stores");
5821 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG) 6117 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !BYTES_BIG_ENDIAN)
5822 warning (OPT_Wdeprecated, 6118 warning (OPT_Wdeprecated,
5823 "vec_lvsr is deprecated for little endian; use " 6119 "vec_lvsr is deprecated for little endian; use "
5824 "assignment for unaligned loads and stores"); 6120 "assignment for unaligned loads and stores");
5825 6121
5826 if (fcode == ALTIVEC_BUILTIN_VEC_MUL) 6122 if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
6228 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 6524 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6229 goto bad; 6525 goto bad;
6230 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 6526 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6231 goto bad; 6527 goto bad;
6232 6528
6233 /* If we are targeting little-endian, but -maltivec=be has been
6234 specified to override the element order, adjust the element
6235 number accordingly. */
6236 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6237 {
6238 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6239 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6240 build_int_cstu (TREE_TYPE (arg2), last_elem),
6241 arg2);
6242 }
6243
6244 /* See if we can optimize vec_extracts with the current VSX instruction 6529 /* See if we can optimize vec_extracts with the current VSX instruction
6245 set. */ 6530 set. */
6246 mode = TYPE_MODE (arg1_type); 6531 mode = TYPE_MODE (arg1_type);
6247 if (VECTOR_MEM_VSX_P (mode)) 6532 if (VECTOR_MEM_VSX_P (mode))
6248 6533
6249 { 6534 {
6250 tree call = NULL_TREE; 6535 tree call = NULL_TREE;
6251 int nunits = GET_MODE_NUNITS (mode); 6536 int nunits = GET_MODE_NUNITS (mode);
6537
6538 arg2 = fold_for_warn (arg2);
6252 6539
6253 /* If the second argument is an integer constant, if the value is in 6540 /* If the second argument is an integer constant, if the value is in
6254 the expected range, generate the built-in code if we can. We need 6541 the expected range, generate the built-in code if we can. We need
6255 64-bit and direct move to extract the small integer vectors. */ 6542 64-bit and direct move to extract the small integer vectors. */
6256 if (TREE_CODE (arg2) == INTEGER_CST 6543 if (TREE_CODE (arg2) == INTEGER_CST
6366 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); 6653 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6367 stmt = convert (innerptrtype, stmt); 6654 stmt = convert (innerptrtype, stmt);
6368 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); 6655 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6369 stmt = build_indirect_ref (loc, stmt, RO_NULL); 6656 stmt = build_indirect_ref (loc, stmt, RO_NULL);
6370 6657
6658 /* PR83660: We mark this as having side effects so that
6659 downstream in fold_build_cleanup_point_expr () it will get a
6660 CLEANUP_POINT_EXPR. If it does not we can run into an ICE
6661 later in gimplify_cleanup_point_expr (). Potentially this
6662 causes missed optimization because the actually is no side
6663 effect. */
6664 if (c_dialect_cxx ())
6665 TREE_SIDE_EFFECTS (stmt) = 1;
6666
6371 return stmt; 6667 return stmt;
6372 } 6668 }
6373 6669
6374 /* For now use pointer tricks to do the insertion, unless we are on VSX 6670 /* For now use pointer tricks to do the insertion, unless we are on VSX
6375 inserting a double to a constant offset.. */ 6671 inserting a double to a constant offset.. */
6392 } 6688 }
6393 6689
6394 arg0 = (*arglist)[0]; 6690 arg0 = (*arglist)[0];
6395 arg1 = (*arglist)[1]; 6691 arg1 = (*arglist)[1];
6396 arg1_type = TREE_TYPE (arg1); 6692 arg1_type = TREE_TYPE (arg1);
6397 arg2 = (*arglist)[2]; 6693 arg2 = fold_for_warn ((*arglist)[2]);
6398 6694
6399 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 6695 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6400 goto bad; 6696 goto bad;
6401 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 6697 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6402 goto bad; 6698 goto bad;
6403
6404 /* If we are targeting little-endian, but -maltivec=be has been
6405 specified to override the element order, adjust the element
6406 number accordingly. */
6407 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6408 {
6409 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6410 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6411 build_int_cstu (TREE_TYPE (arg2), last_elem),
6412 arg2);
6413 }
6414 6699
6415 /* If we can use the VSX xxpermdi instruction, use that for insert. */ 6700 /* If we can use the VSX xxpermdi instruction, use that for insert. */
6416 mode = TYPE_MODE (arg1_type); 6701 mode = TYPE_MODE (arg1_type);
6417 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) 6702 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6418 && TREE_CODE (arg2) == INTEGER_CST 6703 && TREE_CODE (arg2) == INTEGER_CST
6546 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0])); 6831 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6547 } 6832 }
6548 6833
6549 { 6834 {
6550 bool unsupported_builtin = false; 6835 bool unsupported_builtin = false;
6836 enum rs6000_builtins overloaded_code;
6837 tree result = NULL;
6551 for (desc = altivec_overloaded_builtins; 6838 for (desc = altivec_overloaded_builtins;
6552 desc->code && desc->code != fcode; desc++) 6839 desc->code && desc->code != fcode; desc++)
6553 continue; 6840 continue;
6554 6841
6555 /* Need to special case __builtin_cmp because the overloaded forms 6842 /* Need to special case __builtin_cmp because the overloaded forms
6558 allow the respective argument types to be implicitly coerced into 6845 allow the respective argument types to be implicitly coerced into
6559 each other, the default handling does not provide adequate 6846 each other, the default handling does not provide adequate
6560 discrimination between the desired forms of the function. */ 6847 discrimination between the desired forms of the function. */
6561 if (fcode == P6_OV_BUILTIN_CMPB) 6848 if (fcode == P6_OV_BUILTIN_CMPB)
6562 { 6849 {
6563 int overloaded_code;
6564 machine_mode arg1_mode = TYPE_MODE (types[0]); 6850 machine_mode arg1_mode = TYPE_MODE (types[0]);
6565 machine_mode arg2_mode = TYPE_MODE (types[1]); 6851 machine_mode arg2_mode = TYPE_MODE (types[1]);
6566 6852
6567 if (nargs != 2) 6853 if (nargs != 2)
6568 { 6854 {
6593 if (desc->code && (desc->code == fcode) 6879 if (desc->code && (desc->code == fcode)
6594 && rs6000_builtin_type_compatible (types[0], desc->op1) 6880 && rs6000_builtin_type_compatible (types[0], desc->op1)
6595 && rs6000_builtin_type_compatible (types[1], desc->op2)) 6881 && rs6000_builtin_type_compatible (types[1], desc->op2))
6596 { 6882 {
6597 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 6883 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6598 return altivec_build_resolved_builtin (args, n, desc); 6884 {
6885 result = altivec_build_resolved_builtin (args, n, desc);
6886 /* overloaded_code is set above */
6887 if (!rs6000_builtin_is_supported_p (overloaded_code))
6888 unsupported_builtin = true;
6889 else
6890 return result;
6891 }
6599 else 6892 else
6600 unsupported_builtin = true; 6893 unsupported_builtin = true;
6601 } 6894 }
6602 } 6895 }
6603 else if (fcode == P9V_BUILTIN_VEC_VSIEDP) 6896 else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6604 { 6897 {
6605 int overloaded_code;
6606 machine_mode arg1_mode = TYPE_MODE (types[0]); 6898 machine_mode arg1_mode = TYPE_MODE (types[0]);
6607 6899
6608 if (nargs != 2) 6900 if (nargs != 2)
6609 { 6901 {
6610 error ("builtin %qs only accepts 2 arguments", 6902 error ("builtin %qs only accepts 2 arguments",
6635 overloaded_code = P9V_BUILTIN_VSIEDP; 6927 overloaded_code = P9V_BUILTIN_VSIEDP;
6636 } 6928 }
6637 while (desc->code && desc->code == fcode 6929 while (desc->code && desc->code == fcode
6638 && desc->overloaded_code != overloaded_code) 6930 && desc->overloaded_code != overloaded_code)
6639 desc++; 6931 desc++;
6932
6640 if (desc->code && (desc->code == fcode) 6933 if (desc->code && (desc->code == fcode)
6641 && rs6000_builtin_type_compatible (types[0], desc->op1) 6934 && rs6000_builtin_type_compatible (types[0], desc->op1)
6642 && rs6000_builtin_type_compatible (types[1], desc->op2)) 6935 && rs6000_builtin_type_compatible (types[1], desc->op2))
6643 { 6936 {
6644 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 6937 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6645 return altivec_build_resolved_builtin (args, n, desc); 6938 {
6939 result = altivec_build_resolved_builtin (args, n, desc);
6940 /* overloaded_code is set above. */
6941 if (!rs6000_builtin_is_supported_p (overloaded_code))
6942 unsupported_builtin = true;
6943 else
6944 return result;
6945 }
6646 else 6946 else
6647 unsupported_builtin = true; 6947 unsupported_builtin = true;
6648 } 6948 }
6649 } 6949 }
6650 else 6950 else
6659 || rs6000_builtin_type_compatible (types[1], desc->op2)) 6959 || rs6000_builtin_type_compatible (types[1], desc->op2))
6660 && (desc->op3 == RS6000_BTI_NOT_OPAQUE 6960 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6661 || rs6000_builtin_type_compatible (types[2], desc->op3))) 6961 || rs6000_builtin_type_compatible (types[2], desc->op3)))
6662 { 6962 {
6663 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 6963 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6664 return altivec_build_resolved_builtin (args, n, desc); 6964 {
6965 result = altivec_build_resolved_builtin (args, n, desc);
6966 if (!rs6000_builtin_is_supported_p (desc->overloaded_code))
6967 {
6968 /* Allow loop to continue in case a different
6969 definition is supported. */
6970 overloaded_code = desc->overloaded_code;
6971 unsupported_builtin = true;
6972 }
6973 else
6974 return result;
6975 }
6665 else 6976 else
6666 unsupported_builtin = true; 6977 unsupported_builtin = true;
6667 } 6978 }
6668 } 6979 }
6669 } 6980 }
6670 6981
6671 if (unsupported_builtin) 6982 if (unsupported_builtin)
6672 { 6983 {
6673 const char *name = rs6000_overloaded_builtin_name (fcode); 6984 const char *name = rs6000_overloaded_builtin_name (fcode);
6674 error ("builtin function %qs not supported in this compiler " 6985 if (result != NULL)
6675 "configuration", name); 6986 {
6676 return error_mark_node; 6987 const char *internal_name
6988 = rs6000_overloaded_builtin_name (overloaded_code);
6989 /* An error message making reference to the name of the
6990 non-overloaded function has already been issued. Add
6991 clarification of the previous message. */
6992 rich_location richloc (line_table, input_location);
6993 inform (&richloc, "builtin %qs requires builtin %qs",
6994 name, internal_name);
6995 }
6996 else
6997 error ("builtin function %qs not supported in this compiler "
6998 "configuration", name);
6999 /* If an error-representing result tree was returned from
7000 altivec_build_resolved_builtin above, use it. */
7001 return (result != NULL) ? result : error_mark_node;
6677 } 7002 }
6678 } 7003 }
6679 bad: 7004 bad:
6680 { 7005 {
6681 const char *name = rs6000_overloaded_builtin_name (fcode); 7006 const char *name = rs6000_overloaded_builtin_name (fcode);