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comparison gcc/config/rs6000/rs6000-modes.def @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
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111:04ced10e8804 131:84e7813d76e9
1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 2002-2017 Free Software Foundation, Inc. 2 Copyright (C) 2002-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify it 7 GCC is free software; you can redistribute it and/or modify it
16 16
17 You should have received a copy of the GNU General Public License 17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see 18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */ 19 <http://www.gnu.org/licenses/>. */
20 20
21 /* IBM 128-bit floating point. IFmode and KFmode use the fractional float 21 /* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
22 support in order to declare 3 128-bit floating point types. */ 22 floating point) is the 128-bit floating point type with the highest
23 FRACTIONAL_FLOAT_MODE (IF, 106, 16, ibm_extended_format); 23 precision (128 bits). This so that machine independent parts of the
24 compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
25 hardware support for IEEE 128-bit. We set TFmode (long double mode) in
26 between, and KFmode (explicit __float128) below it.
27
28 Previously, IFmode and KFmode were defined to be fractional modes and TFmode
29 was the standard mode. Since IFmode does not define the normal arithmetic
30 insns (other than neg/abs), on a ISA 3.0 system, the machine independent
31 parts of the compiler would see that TFmode has the necessary hardware
32 support, and widen the operation from IFmode to TFmode. However, IEEE
33 128-bit is not strictly a super-set of IBM extended double and the
34 conversion to/from IEEE 128-bit was a function call.
35
36 We now make IFmode the highest fractional mode, which means its values are
37 not considered for widening. Since we don't define insns for IFmode, the
38 IEEE 128-bit modes would not widen to IFmode. */
39
40 #ifndef RS6000_MODES_H
41 #include "config/rs6000/rs6000-modes.h"
42 #endif
43
44 /* IBM 128-bit floating point. */
45 FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format);
24 46
25 /* Explicit IEEE 128-bit floating point. */ 47 /* Explicit IEEE 128-bit floating point. */
26 FRACTIONAL_FLOAT_MODE (KF, 113, 16, ieee_quad_format); 48 FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format);
27 49
28 /* 128-bit floating point. ABI_V4 uses IEEE quad, AIX/Darwin 50 /* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is
29 adjust this in rs6000_option_override_internal. */ 51 adjusted in rs6000_option_override_internal to be the appropriate floating
30 FLOAT_MODE (TF, 16, ieee_quad_format); 52 point type. */
53 FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
31 54
32 /* Add any extra modes needed to represent the condition code. 55 /* Add any extra modes needed to represent the condition code.
33 56
34 For the RS/6000, we need separate modes when unsigned (logical) comparisons 57 For the RS/6000, we need separate modes when unsigned (logical) comparisons
35 are being done and we need a separate mode for floating-point. We also 58 are being done and we need a separate mode for floating-point. We also
49 72
50 /* Two VMX/VSX vectors (for permute, select, concat, etc.) */ 73 /* Two VMX/VSX vectors (for permute, select, concat, etc.) */
51 VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ 74 VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
52 VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ 75 VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
53 76
54 /* Paired single. */
55 VECTOR_MODE (FLOAT, SF, 2); /* The only valid paired-single mode. */
56 VECTOR_MODE (INT, SI, 2); /* For paired-single permutes. */
57
58 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode 77 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
59 for quad memory atomic operations to force getting an even/odd register 78 for quad memory atomic operations to force getting an even/odd register
60 combination. */ 79 combination. */
61 PARTIAL_INT_MODE (TI, 128, PTI); 80 PARTIAL_INT_MODE (TI, 128, PTI);