CbC/CbC_gcc: gcc/config/rs6000/rs6000.c comparison

comparison gcc/config/rs6000/rs6000.c @ 131:84e7813d76e9

gcc-8.2

author	mir3636
date	Thu, 25 Oct 2018 07:37:49 +0900
parents	04ced10e8804
children	1830386684a0

comparison

equal deleted inserted replaced

-:04ced10e8804
+:84e7813d76e9
 /* Subroutines used for code generation on IBM RS/6000.
-Copyright (C) 1991-2017 Free Software Foundation, Inc.
+Copyright (C) 1991-2018 Free Software Foundation, Inc.
 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify it
 License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
+#define IN_TARGET_CODE 1
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
 #include "backend.h"
 #include "params.h"
 #include "tm-constrs.h"
 #include "tree-vectorizer.h"
 #include "target-globals.h"
 #include "builtins.h"
+#include "tree-vector-builder.h"
 #include "context.h"
 #include "tree-pass.h"
 #include "except.h"
 #if TARGET_XCOFF
 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
 #define TARGET_IEEEQUAD_DEFAULT 1
 #else
 #define TARGET_IEEEQUAD_DEFAULT 0
 #endif
 #endif
-#define min(A,B)	((A) < (B) ? (A) : (B))
-#define max(A,B)	((A) > (B) ? (A) : (B))
 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
 /* Structure used to define the rs6000 stack */
 typedef struct rs6000_stack {
 /* The components already handled by separate shrink-wrapping, which should
 not be considered by the prologue and epilogue.  */
 bool gpr_is_wrapped_separately[32];
 bool fpr_is_wrapped_separately[32];
 bool lr_is_wrapped_separately;
+bool toc_is_wrapped_separately;
 } machine_function;
 /* Support targetm.vectorize.builtin_mask_for_load.  */
 static GTY(()) tree altivec_builtin_mask_for_load;
 /* Specify the machine mode that pointers have.  After generation of rtl, the
 compiler makes no further distinction between pointers and any other objects
 of this machine mode.  */
 scalar_int_mode rs6000_pmode;
+#if TARGET_ELF
+/* Note whether IEEE 128-bit floating point was passed or returned, either as
+the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
+floating point.  We changed the default C++ mangling for these types and we
+may want to generate a weak alias of the old mangling (U10__float128) to the
+new mangling (u9__ieee128).  */
+static bool rs6000_passes_ieee128;
+#endif
+/* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
+name used in current releases (i.e. u9__ieee128).  */
+static bool ieee128_mangling_gcc_8_1;
 /* Width in bits of a pointer.  */
 unsigned rs6000_pointer_size;
 #ifdef HAVE_AS_GNU_ATTRIBUTE
 { "arch_2_07",	PPC_FEATURE2_ARCH_2_07,		1 },
 { "dscr",		PPC_FEATURE2_HAS_DSCR,		1 },
 { "ebb",		PPC_FEATURE2_HAS_EBB,		1 },
 { "htm",		PPC_FEATURE2_HAS_HTM,		1 },
 { "htm-nosc",		PPC_FEATURE2_HTM_NOSC,		1 },
+{ "htm-no-suspend",	PPC_FEATURE2_HTM_NO_SUSPEND,	1 },
 { "isel",		PPC_FEATURE2_HAS_ISEL,		1 },
 { "tar",		PPC_FEATURE2_HAS_TAR,		1 },
 { "vcrypto",		PPC_FEATURE2_HAS_VEC_CRYPTO,	1 },
 { "arch_3_00",	PPC_FEATURE2_ARCH_3_00,		1 },
 { "ieee128",		PPC_FEATURE2_HAS_IEEE128,	1 },
 enum insn_code reload_load;		/* INSN to reload for loading. */
 enum insn_code reload_store;		/* INSN to reload for storing.  */
 enum insn_code reload_fpr_gpr;	/* INSN to move from FPR to GPR.  */
 enum insn_code reload_gpr_vsx;	/* INSN to move from GPR to VSX.  */
 enum insn_code reload_vsx_gpr;	/* INSN to move from VSX to GPR.  */
-enum insn_code fusion_gpr_ld;		/* INSN for fusing gpr ADDIS/loads.  */
-					/* INSNs for fusing addi with loads
-					   or stores for each reg. class.  */
-enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
-enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
-					/* INSNs for fusing addis with loads
-					   or stores for each reg. class.  */
-enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
-enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks.  */
 bool scalar_in_vmx_p;			/* Scalar value can go in VMX.  */
-bool fused_toc;			/* Mode supports TOC fusion.  */
 };
 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC.  */
 /* Helper function to say whether a mode supports PRE_MODIFY.  */
 static inline bool
 mode_supports_pre_modify_p (machine_mode mode)
 {
 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
+	  != 0);
+}
+/* Return true if we have D-form addressing in altivec registers.  */
+static inline bool
+mode_supports_vmx_dform (machine_mode mode)
+{
+return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
+}
+/* Return true if we have D-form addressing in VSX registers.  This addressing
+is more limited than normal d-form addressing in that the offset must be
+aligned on a 16-byte boundary.  */
+static inline bool
+mode_supports_dq_form (machine_mode mode)
+{
+return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
 	  != 0);
 }
 /* Given that there exists at least one variable that is set (produced)
 by OUT_INSN and read (consumed) by IN_INSN, return true iff
 		}
 	    }
 	}
 }
 return store_data_bypass_p (out_insn, in_insn);
-}
-/* Return true if we have D-form addressing in altivec registers.  */
-static inline bool
-mode_supports_vmx_dform (machine_mode mode)
-{
-return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
-}
-/* Return true if we have D-form addressing in VSX registers.  This addressing
-is more limited than normal d-form addressing in that the offset must be
-aligned on a 16-byte boundary.  */
-static inline bool
-mode_supports_vsx_dform_quad (machine_mode mode)
-{
-return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
-	  != 0);
 }
 /* Processor costs (relative to an add) */
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
 { NAME, ICODE, MASK, ATTR },
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)  \
 { NAME, ICODE, MASK, ATTR },
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)  \
-{ NAME, ICODE, MASK, ATTR },
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)  \
 { NAME, ICODE, MASK, ATTR },
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)  \
 { NAME, ICODE, MASK, ATTR },
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 /* Support for -mveclibabi=<xxx> to control which vector library to use.  */
 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
 static void altivec_init_builtins (void);
 static tree builtin_function_type (machine_mode, machine_mode,
 				   machine_mode, machine_mode,
 				   enum rs6000_builtins, const char *name);
 static void rs6000_common_init_builtins (void);
-static void paired_init_builtins (void);
-static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
 static void htm_init_builtins (void);
-static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
 static rs6000_stack_t *rs6000_stack_info (void);
 static void is_altivec_return_reg (rtx, void *);
 int easy_vector_constant (rtx, machine_mode);
 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
 					     int, int *);
 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
 						   int, int, int *);
 static bool rs6000_mode_dependent_address (const_rtx);
 static bool rs6000_debug_mode_dependent_address (const_rtx);
+static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
 						     machine_mode, rtx);
 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
 							   machine_mode,
 							   rtx);
 /* Table of valid machine attributes.  */
 static const struct attribute_spec rs6000_attribute_table[] =
 {
-/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
+/* { name, min_len, max_len, decl_req, type_req, fn_type_req,
-affects_type_identity } */
+affects_type_identity, handler, exclude } */
-{ "altivec",   1, 1, false, true,  false, rs6000_handle_altivec_attribute,
+{ "altivec",   1, 1, false, true,  false, false,
-false },
+rs6000_handle_altivec_attribute, NULL },
-{ "longcall",  0, 0, false, true,  true,  rs6000_handle_longcall_attribute,
+{ "longcall",  0, 0, false, true,  true,  false,
-false },
+rs6000_handle_longcall_attribute, NULL },
-{ "shortcall", 0, 0, false, true,  true,  rs6000_handle_longcall_attribute,
+{ "shortcall", 0, 0, false, true,  true,  false,
-false },
+rs6000_handle_longcall_attribute, NULL },
-{ "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
+{ "ms_struct", 0, 0, false, false, false, false,
-false },
+rs6000_handle_struct_attribute, NULL },
-{ "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
+{ "gcc_struct", 0, 0, false, false, false, false,
-false },
+rs6000_handle_struct_attribute, NULL },
 #ifdef SUBTARGET_ATTRIBUTE_TABLE
 SUBTARGET_ATTRIBUTE_TABLE,
 #endif
-{ NULL,        0, 0, false, false, false, NULL, false }
+{ NULL,        0, 0, false, false, false, false, NULL, NULL }
 };
 #ifndef TARGET_PROFILE_KERNEL
 #define TARGET_PROFILE_KERNEL 0
 #endif
 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
 #undef TARGET_EH_RETURN_FILTER_MODE
 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
+#undef TARGET_TRANSLATE_MODE_ATTRIBUTE
+#define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
 #undef TARGET_SCALAR_MODE_SUPPORTED_P
 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
 #undef TARGET_VECTOR_MODE_SUPPORTED_P
 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
 #undef TARGET_FLOATN_MODE
 #define TARGET_FLOATN_MODE rs6000_floatn_mode
 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
-#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
-#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
 #undef TARGET_MD_ASM_ADJUST
 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
 #undef TARGET_OPTION_OVERRIDE
 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
 #undef TARGET_LEGITIMATE_CONSTANT_P
 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
-#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
+#undef TARGET_VECTORIZE_VEC_PERM_CONST
-#define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
+#define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
 #undef TARGET_CAN_USE_DOLOOP_P
 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
 #undef TARGET_CONSTANT_ALIGNMENT
 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
 #undef TARGET_STARTING_FRAME_OFFSET
 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
+#if TARGET_ELF && RS6000_WEAK
+#undef TARGET_ASM_GLOBALIZE_DECL_NAME
+#define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
+#endif
+#undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
+#define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
+#undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
+#define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
 /* Processor table.  */
 struct rs6000_ptt
 {
 	  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
 	    return 1;
 	}
-if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
-	  && PAIRED_VECTOR_MODE (mode))
-	return 1;
 return 0;
 }
 /* The CR register can only hold CC modes.  */
 if (CR_REGNO_P (regno))
 return false;
 if (GET_MODE_CLASS (mode1) == MODE_CC)
 return GET_MODE_CLASS (mode2) == MODE_CC;
 if (GET_MODE_CLASS (mode2) == MODE_CC)
-return false;
-if (PAIRED_VECTOR_MODE (mode1))
-return PAIRED_VECTOR_MODE (mode2);
-if (PAIRED_VECTOR_MODE (mode2))
 return false;
 return true;
 }
 {
 case VECTOR_NONE:	   ret = "none";      break;
 case VECTOR_ALTIVEC:   ret = "altivec";   break;
 case VECTOR_VSX:	   ret = "vsx";       break;
 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
-case VECTOR_PAIRED:	   ret = "paired";    break;
-case VECTOR_OTHER:	   ret = "other";     break;
 default:		   ret = "unknown";   break;
 }
 return ret;
 }
 DEBUG_FUNCTION void
 rs6000_debug_print_mode (ssize_t m)
 {
 ssize_t rc;
 int spaces = 0;
-bool fuse_extra_p;
 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
 for (rc = 0; rc < N_RELOAD_REG; rc++)
 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
 	     rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
 || (reg_addr[m].reload_load != CODE_FOR_nothing))
-fprintf (stderr, "  Reload=%c%c",
+{
-	     (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
+fprintf (stderr, "%*s  Reload=%c%c", spaces, "",
-	     (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
+	       (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
+	       (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
+spaces = 0;
+}
 else
 spaces += sizeof ("  Reload=sl") - 1;
 if (reg_addr[m].scalar_in_vmx_p)
 {
 fprintf (stderr, "%*s  Upper=y", spaces, "");
 spaces = 0;
 }
 else
 spaces += sizeof ("  Upper=y") - 1;
-fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
-		  || reg_addr[m].fused_toc);
-if (!fuse_extra_p)
-{
-for (rc = 0; rc < N_RELOAD_REG; rc++)
-	{
-	  if (rc != RELOAD_REG_ANY)
-	    {
-	      if (reg_addr[m].fusion_addi_ld[rc]     != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addi_ld[rc]  != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addi_st[rc]  != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
-		{
-		  fuse_extra_p = true;
-		  break;
-		}
-	    }
-	}
-}
-if (fuse_extra_p)
-{
-fprintf (stderr, "%*s  Fuse:", spaces, "");
-spaces = 0;
-for (rc = 0; rc < N_RELOAD_REG; rc++)
-	{
-	  if (rc != RELOAD_REG_ANY)
-	    {
-	      char load, store;
-	      if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
-		load = 'l';
-	      else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
-		load = 'L';
-	      else
-		load = '-';
-	      if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
-		store = 's';
-	      else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
-		store = 'S';
-	      else
-		store = '-';
-	      if (load == '-' && store == '-')
-		spaces += 5;
-	      else
-		{
-		  fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
-			   reload_reg_map[rc].name[0], load, store);
-		  spaces = 0;
-		}
-	    }
-	}
-if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
-	{
-	  fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
-	  spaces = 0;
-	}
-else
-	spaces += sizeof (" P8gpr") - 1;
-if (reg_addr[m].fused_toc)
-	{
-	  fprintf (stderr, "%*sToc", (spaces + 1), "");
-	  spaces = 0;
-	}
-else
-	spaces += sizeof (" Toc") - 1;
-}
-else
-spaces += sizeof ("  Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
 if (rs6000_vector_unit[m] != VECTOR_NONE
 || rs6000_vector_mem[m] != VECTOR_NONE)
 {
 fprintf (stderr, "%*s  vector: arith=%-10s mem=%s",
 IFmode,
 KFmode,
 SDmode,
 DDmode,
 TDmode,
-V2SImode,
 V16QImode,
 V8HImode,
 V4SImode,
 V2DImode,
 V1TImode,
 V32QImode,
 V16HImode,
 V8SImode,
 V4DImode,
 V2TImode,
-V2SFmode,
 V4SFmode,
 V2DFmode,
 V8SFmode,
 V4DFmode,
 CCmode,
 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
 if (rs6000_darwin64_abi)
 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
-fprintf (stderr, DEBUG_FMT_S, "single_float",
-	   (TARGET_SINGLE_FLOAT ? "true" : "false"));
-fprintf (stderr, DEBUG_FMT_S, "double_float",
-	   (TARGET_DOUBLE_FLOAT ? "true" : "false"));
 fprintf (stderr, DEBUG_FMT_S, "soft_float",
 	   (TARGET_SOFT_FLOAT ? "true" : "false"));
 if (TARGET_LINK_STACK)
 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
 if (TARGET_P8_FUSION)
 {
 char options[80];
 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
-if (TARGET_TOC_FUSION)
-	strcat (options, ", toc");
 if (TARGET_P8_FUSION_SIGN)
 	strcat (options, ", sign");
 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
 }
 fprintf (stderr, DEBUG_FMT_S, "align_branch",
 	   tf[!!rs6000_align_branch_targets]);
 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
 	   rs6000_long_double_type_size);
-if (rs6000_long_double_type_size == 128)
+if (rs6000_long_double_type_size > 64)
 {
 fprintf (stderr, DEBUG_FMT_S, "long double type",
 	       TARGET_IEEEQUAD ? "IEEE" : "IBM");
 fprintf (stderr, DEBUG_FMT_S, "default long double type",
 	       TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
 	      else
 		addr_mask |= RELOAD_REG_INDEXED;
 	      /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
 		 addressing.  If we allow scalars into Altivec registers,
-		 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.  */
+		 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
+		 For VSX systems, we don't allow update addressing for
+		 DFmode/SFmode if those registers can go in both the
+		 traditional floating point registers and Altivec registers.
+		 The load/store instructions for the Altivec registers do not
+		 have update forms.  If we allowed update addressing, it seems
+		 to break IV-OPT code using floating point if the index type is
+		 int instead of long (PR target/81550 and target/84042).  */
 	      if (TARGET_UPDATE
 		  && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
 		  && msize <= 8
 		  && !VECTOR_MODE_P (m2)
 		  && !FLOAT128_VECTOR_P (m2)
 		  && !complex_p
+		  && (m != E_DFmode || !TARGET_VSX)
+		  && (m != E_SFmode || !TARGET_P8_VECTOR)
 		  && !small_int_vsx_p)
 		{
 		  addr_mask |= RELOAD_REG_PRE_INCDEC;
 		  /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
 			addr_mask |= RELOAD_REG_PRE_MODIFY;
 		      break;
 		    case E_DFmode:
 		    case E_DDmode:
-		      if (TARGET_DF_INSN)
+		      if (TARGET_HARD_FLOAT)
 			addr_mask |= RELOAD_REG_PRE_MODIFY;
 		      break;
 		    }
 		}
 	    }
 if (TARGET_VSX)
 {
 rs6000_vector_mem[TImode] = VECTOR_VSX;
 rs6000_vector_align[TImode] = align64;
 }
-/* TODO add paired floating point vector support.  */
 /* Register class constraints for the constraints that depend on compile
 switches. When the VSX code was added, different constraints were added
 based on the type (DFmode, V2DFmode, V4SFmode).  For the vector types, all
 of the VSX registers are used.  The register classes for scalar floating
 	wI - VSX register if SImode is allowed in VSX registers.
 	wJ - VSX register if QImode/HImode are allowed in VSX registers.
 	wK - Altivec register if QImode/HImode are allowed in VSX registers.  */
 if (TARGET_HARD_FLOAT)
-rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;	/* SFmode  */
+{
+rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;	/* SFmode  */
-if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;	/* DFmode  */
-rs6000_constraints[RS6000_CONSTRAINT_d]  = FLOAT_REGS;	/* DFmode  */
+}
 if (TARGET_VSX)
 {
 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;	/* V2DFmode  */
 	  if (TARGET_P9_VECTOR)
 	    {
 	      reg_addr[HImode].scalar_in_vmx_p = true;
 	      reg_addr[QImode].scalar_in_vmx_p = true;
 	    }
-	}
-}
-/* Setup the fusion operations.  */
-if (TARGET_P8_FUSION)
-{
-reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
-reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
-reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
-if (TARGET_64BIT)
-	reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
-}
-if (TARGET_P9_FUSION)
-{
-struct fuse_insns {
-	enum machine_mode mode;			/* mode of the fused type.  */
-	enum machine_mode pmode;		/* pointer mode.  */
-	enum rs6000_reload_reg_type rtype;	/* register type.  */
-	enum insn_code load;			/* load insn.  */
-	enum insn_code store;			/* store insn.  */
-};
-static const struct fuse_insns addis_insns[] = {
-	{ E_SFmode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_sf_load,
-	  CODE_FOR_fusion_vsx_di_sf_store },
-	{ E_SFmode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_sf_load,
-	  CODE_FOR_fusion_vsx_si_sf_store },
-	{ E_DFmode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_df_load,
-	  CODE_FOR_fusion_vsx_di_df_store },
-	{ E_DFmode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_df_load,
-	  CODE_FOR_fusion_vsx_si_df_store },
-	{ E_DImode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_di_load,
-	  CODE_FOR_fusion_vsx_di_di_store },
-	{ E_DImode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_di_load,
-	  CODE_FOR_fusion_vsx_si_di_store },
-	{ E_QImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_qi_load,
-	  CODE_FOR_fusion_gpr_di_qi_store },
-	{ E_QImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_qi_load,
-	  CODE_FOR_fusion_gpr_si_qi_store },
-	{ E_HImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_hi_load,
-	  CODE_FOR_fusion_gpr_di_hi_store },
-	{ E_HImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_hi_load,
-	  CODE_FOR_fusion_gpr_si_hi_store },
-	{ E_SImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_si_load,
-	  CODE_FOR_fusion_gpr_di_si_store },
-	{ E_SImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_si_load,
-	  CODE_FOR_fusion_gpr_si_si_store },
-	{ E_SFmode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_sf_load,
-	  CODE_FOR_fusion_gpr_di_sf_store },
-	{ E_SFmode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_sf_load,
-	  CODE_FOR_fusion_gpr_si_sf_store },
-	{ E_DImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_di_load,
-	  CODE_FOR_fusion_gpr_di_di_store },
-	{ E_DFmode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_df_load,
-	  CODE_FOR_fusion_gpr_di_df_store },
-};
-machine_mode cur_pmode = Pmode;
-size_t i;
-for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
-	{
-	  machine_mode xmode = addis_insns[i].mode;
-	  enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
-	  if (addis_insns[i].pmode != cur_pmode)
-	    continue;
-	  if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
-	    continue;
-	  reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
-	  reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
-	  if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
-	    {
-	      reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
-		= addis_insns[i].load;
-	      reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
-		= addis_insns[i].store;
-	    }
-	}
-}
-/* Note which types we support fusing TOC setup plus memory insn.  We only do
-fused TOCs for medium/large code models.  */
-if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
-&& (TARGET_CMODEL != CMODEL_SMALL))
-{
-reg_addr[QImode].fused_toc = true;
-reg_addr[HImode].fused_toc = true;
-reg_addr[SImode].fused_toc = true;
-reg_addr[DImode].fused_toc = true;
-if (TARGET_HARD_FLOAT)
-	{
-	  if (TARGET_SINGLE_FLOAT)
-	    reg_addr[SFmode].fused_toc = true;
-	  if (TARGET_DOUBLE_FLOAT)
-	    reg_addr[DFmode].fused_toc = true;
 	}
 }
 /* Precalculate HARD_REGNO_NREGS.  */
 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
 #endif
 /* Return the builtin mask of the various options used that could affect which
 builtins were used.  In the past we used target_flags, but we've run out of
-bits, and some options like PAIRED are no longer in target_flags.  */
+bits, and some options are no longer in target_flags.  */
 HOST_WIDE_INT
 rs6000_builtin_mask_calculate (void)
 {
 return (((TARGET_ALTIVEC)		    ? RS6000_BTM_ALTIVEC   : 0)
 	  | ((TARGET_CMPB)		    ? RS6000_BTM_CMPB	   : 0)
 	  | ((TARGET_VSX)		    ? RS6000_BTM_VSX	   : 0)
-	  | ((TARGET_PAIRED_FLOAT)	    ? RS6000_BTM_PAIRED	   : 0)
 	  | ((TARGET_FRE)		    ? RS6000_BTM_FRE	   : 0)
 	  | ((TARGET_FRES)		    ? RS6000_BTM_FRES	   : 0)
 	  | ((TARGET_FRSQRTE)		    ? RS6000_BTM_FRSQRTE   : 0)
 	  | ((TARGET_FRSQRTES)		    ? RS6000_BTM_FRSQRTES  : 0)
 	  | ((TARGET_POPCNTD)		    ? RS6000_BTM_POPCNTD   : 0)
 	  | ((TARGET_P8_VECTOR)		    ? RS6000_BTM_P8_VECTOR : 0)
 	  | ((TARGET_P9_VECTOR)		    ? RS6000_BTM_P9_VECTOR : 0)
 	  | ((TARGET_P9_MISC)		    ? RS6000_BTM_P9_MISC   : 0)
 	  | ((TARGET_MODULO)		    ? RS6000_BTM_MODULO    : 0)
 	  | ((TARGET_64BIT)		    ? RS6000_BTM_64BIT     : 0)
+	  | ((TARGET_POWERPC64)		    ? RS6000_BTM_POWERPC64 : 0)
 	  | ((TARGET_CRYPTO)		    ? RS6000_BTM_CRYPTO	   : 0)
 	  | ((TARGET_HTM)		    ? RS6000_BTM_HTM	   : 0)
 	  | ((TARGET_DFP)		    ? RS6000_BTM_DFP	   : 0)
 	  | ((TARGET_HARD_FLOAT)	    ? RS6000_BTM_HARD_FLOAT : 0)
-	  | ((TARGET_LONG_DOUBLE_128)	    ? RS6000_BTM_LDBL128   : 0)
+	  | ((TARGET_LONG_DOUBLE_128
+	      && TARGET_HARD_FLOAT
+	      && !TARGET_IEEEQUAD)	    ? RS6000_BTM_LDBL128   : 0)
 	  | ((TARGET_FLOAT128_TYPE)	    ? RS6000_BTM_FLOAT128  : 0)
 	  | ((TARGET_FLOAT128_HW)	    ? RS6000_BTM_FLOAT128_HW : 0));
 }
 /* Implement TARGET_MD_ASM_ADJUST.  All asm statements are considered
 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
 cpu_index = main_target_opt->x_rs6000_cpu_index;
 else if (OPTION_TARGET_CPU_DEFAULT)
 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
-if (cpu_index >= 0)
-{
-const char *unavailable_cpu = NULL;
-switch (processor_target_table[cpu_index].processor)
-	{
-#ifndef HAVE_AS_POWER9
-	case PROCESSOR_POWER9:
-	  unavailable_cpu = "power9";
-	  break;
-#endif
-#ifndef HAVE_AS_POWER8
-	case PROCESSOR_POWER8:
-	  unavailable_cpu = "power8";
-	  break;
-#endif
-#ifndef HAVE_AS_POPCNTD
-	case PROCESSOR_POWER7:
-	  unavailable_cpu = "power7";
-	  break;
-#endif
-#ifndef HAVE_AS_DFP
-	case PROCESSOR_POWER6:
-	  unavailable_cpu = "power6";
-	  break;
-#endif
-#ifndef HAVE_AS_POPCNTB
-	case PROCESSOR_POWER5:
-	  unavailable_cpu = "power5";
-	  break;
-#endif
-	default:
-	  break;
-	}
-if (unavailable_cpu)
-	{
-	  cpu_index = -1;
-	  warning (0, "will not generate %qs instructions because "
-		   "assembler lacks %qs support", unavailable_cpu,
-		   unavailable_cpu);
-	}
-}
 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
 with those from the cpu, except for options that were explicitly set.  If
 we don't have a cpu, do not override the target bits set in
 TARGET_DEFAULT.  */
 	    tune_index = i;
 	    break;
 	  }
 }
+if (cpu_index >= 0)
+rs6000_cpu = processor_target_table[cpu_index].processor;
+else
+rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
 gcc_assert (tune_index >= 0);
-rs6000_cpu = processor_target_table[tune_index].processor;
+rs6000_tune = processor_target_table[tune_index].processor;
 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
 || rs6000_cpu == PROCESSOR_PPCE5500)
 {
 if (TARGET_ALTIVEC)
 	error ("AltiVec not supported in this target");
 }
 /* If we are optimizing big endian systems for space, use the load/store
-multiple and string instructions.  */
+multiple instructions.  */
 if (BYTES_BIG_ENDIAN && optimize_size)
-rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
+rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
-						      | OPTION_MASK_STRING);
+/* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
-/* Don't allow -mmultiple or -mstring on little endian systems
+because the hardware doesn't support the instructions used in little
-unless the cpu is a 750, because the hardware doesn't support the
+endian mode, and causes an alignment trap.  The 750 does not cause an
-instructions used in little endian mode, and causes an alignment
+alignment trap (except when the target is unaligned).  */
-trap.  The 750 does not cause an alignment trap (except when the
-target is unaligned).  */
+if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
+{
-if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
+rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
-{
+if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
-if (TARGET_MULTIPLE)
+	warning (0, "%qs is not supported on little endian systems",
-	{
+		 "-mmultiple");
-	  rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
-	  if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
-	    warning (0, "%qs is not supported on little endian systems",
-		     "-mmultiple");
-	}
-if (TARGET_STRING)
-	{
-	  rs6000_isa_flags &= ~OPTION_MASK_STRING;
-	  if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
-	    warning (0, "%qs is not supported on little endian systems",
-		     "-mstring");
-	}
 }
 /* If little-endian, default to -mstrict-align on older processors.
 Testing for htm matches power8 and later.  */
 if (!BYTES_BIG_ENDIAN
 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
-/* -maltivec={le,be} implies -maltivec.  */
-if (rs6000_altivec_element_order != 0)
-rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
-/* Disallow -maltivec=le in big endian mode for now.  This is not
-known to be useful for anyone.  */
-if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
-{
-warning (0, N_("-maltivec=le not allowed for big-endian targets"));
-rs6000_altivec_element_order = 0;
-}
 if (!rs6000_fold_gimple)
 fprintf (stderr,
 	      "gimple folding of rs6000 builtins has been disabled.\n");
 /* Add some warnings for VSX.  */
 if (TARGET_VSX)
 {
 const char *msg = NULL;
-if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
+if (!TARGET_HARD_FLOAT)
 	{
 	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
 	    msg = N_("-mvsx requires hardware floating point");
 	  else
 	    {
 	      rs6000_isa_flags &= ~ OPTION_MASK_VSX;
 	      rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
 	    }
 	}
-else if (TARGET_PAIRED_FLOAT)
-	msg = N_("-mvsx and -mpaired are incompatible");
 else if (TARGET_AVOID_XFORM > 0)
 	msg = N_("-mvsx needs indexed addressing");
 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
 				   & OPTION_MASK_ALTIVEC))
 {
 if (TARGET_QUAD_MEMORY
 && !TARGET_QUAD_MEMORY_ATOMIC
 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
+/* If we can shrink-wrap the TOC register save separately, then use
+-msave-toc-indirect unless explicitly disabled.  */
+if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
+&& flag_shrink_wrap_separate
+&& optimize_function_for_speed_p (cfun))
+rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
 /* Enable power8 fusion if we are tuning for power8, even if we aren't
 generating power8 instructions.  */
 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
 			 & OPTION_MASK_P8_FUSION);
 /* Setting additional fusion flags turns on base fusion.  */
-if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
+if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
 {
 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
 	{
 	  if (TARGET_P8_FUSION_SIGN)
 	    error ("%qs requires %qs", "-mpower8-fusion-sign",
 		   "-mpower8-fusion");
-	  if (TARGET_TOC_FUSION)
-	    error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
 	  rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
 	}
 else
 	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
 && optimize_function_for_speed_p (cfun)
 && optimize >= 3)
 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
-/* TOC fusion requires 64-bit and medium/large code model.  */
-if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
-{
-rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires 64-bit"));
-}
-if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
-{
-rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires medium/large code model"));
-}
-/* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
-model.  */
-if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
-&& (TARGET_CMODEL != CMODEL_SMALL)
-&& !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
-rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
 /* ISA 3.0 vector instructions include ISA 2.07.  */
 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
 {
 /* We prefer to not mention undocumented options in
 	 error messages.  However, if users have managed to select
 	  rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
 	}
 }
+/* Use long double size to select the appropriate long double.  We use
+TYPE_PRECISION to differentiate the 3 different long double types.  We map
+128 into the precision used for TFmode.  */
+int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
+				  ? 64
+				  : FLOAT_PRECISION_TFmode);
 /* Set long double size before the IEEE 128-bit tests.  */
 if (!global_options_set.x_rs6000_long_double_type_size)
 {
 if (main_target_opt != NULL
 	  && (main_target_opt->x_rs6000_long_double_type_size
-	      != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
+	      != default_long_double_size))
 	error ("target attribute or pragma changes long double size");
 else
-	rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
+	rs6000_long_double_type_size = default_long_double_size;
 }
+else if (rs6000_long_double_type_size == 128)
+rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
 /* Set -mabi=ieeelongdouble on some old targets.  In the future, power server
 systems will also set long double to be IEEE 128-bit.  AIX and Darwin
 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
 those systems will not pick up this default.  Warn if the user changes the
 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
 /* E500mc does "better" if we inline more aggressively.  Respect the
 user's opinion, though.  */
 if (rs6000_block_move_inline_limit == 0
-&& (rs6000_cpu == PROCESSOR_PPCE500MC
+&& (rs6000_tune == PROCESSOR_PPCE500MC
-	  || rs6000_cpu == PROCESSOR_PPCE500MC64
+	  || rs6000_tune == PROCESSOR_PPCE500MC64
-	  || rs6000_cpu == PROCESSOR_PPCE5500
+	  || rs6000_tune == PROCESSOR_PPCE5500
-	  || rs6000_cpu == PROCESSOR_PPCE6500))
+	  || rs6000_tune == PROCESSOR_PPCE6500))
 rs6000_block_move_inline_limit = 128;
 /* store_one_arg depends on expand_block_move to handle at least the
 size of reg_parm_stack_space.  */
 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
 #endif
 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
-/* For the E500 family of cores, reset the single/double FP flags to let us
+rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
-check that they remain constant across attributes or pragmas.  Also,
+			&& rs6000_tune != PROCESSOR_POWER5
-clear a possible request for string instructions, not supported and which
+			&& rs6000_tune != PROCESSOR_POWER6
-we might have silently queried above for -Os.
+			&& rs6000_tune != PROCESSOR_POWER7
+			&& rs6000_tune != PROCESSOR_POWER8
-For other families, clear ISEL in case it was set implicitly.
+			&& rs6000_tune != PROCESSOR_POWER9
-*/
+			&& rs6000_tune != PROCESSOR_PPCA2
+			&& rs6000_tune != PROCESSOR_CELL
-switch (rs6000_cpu)
+			&& rs6000_tune != PROCESSOR_PPC476);
-{
+rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
-case PROCESSOR_PPC8540:
+			 || rs6000_tune == PROCESSOR_POWER5
-case PROCESSOR_PPC8548:
+			 || rs6000_tune == PROCESSOR_POWER7
-case PROCESSOR_PPCE500MC:
+			 || rs6000_tune == PROCESSOR_POWER8);
-case PROCESSOR_PPCE500MC64:
+rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
-case PROCESSOR_PPCE5500:
+				 || rs6000_tune == PROCESSOR_POWER5
-case PROCESSOR_PPCE6500:
+				 || rs6000_tune == PROCESSOR_POWER6
+				 || rs6000_tune == PROCESSOR_POWER7
-rs6000_single_float = 0;
+				 || rs6000_tune == PROCESSOR_POWER8
-rs6000_double_float = 0;
+				 || rs6000_tune == PROCESSOR_POWER9
+				 || rs6000_tune == PROCESSOR_PPCE500MC
-rs6000_isa_flags &= ~OPTION_MASK_STRING;
+				 || rs6000_tune == PROCESSOR_PPCE500MC64
+				 || rs6000_tune == PROCESSOR_PPCE5500
-break;
+				 || rs6000_tune == PROCESSOR_PPCE6500);
-default:
-if (cpu_index >= 0 && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
-	rs6000_isa_flags &= ~OPTION_MASK_ISEL;
-break;
-}
-if (main_target_opt)
-{
-if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
-	error ("target attribute or pragma changes single precision floating "
-	       "point");
-if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
-	error ("target attribute or pragma changes double precision floating "
-	       "point");
-}
-rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
-			&& rs6000_cpu != PROCESSOR_POWER5
-			&& rs6000_cpu != PROCESSOR_POWER6
-			&& rs6000_cpu != PROCESSOR_POWER7
-			&& rs6000_cpu != PROCESSOR_POWER8
-			&& rs6000_cpu != PROCESSOR_POWER9
-			&& rs6000_cpu != PROCESSOR_PPCA2
-			&& rs6000_cpu != PROCESSOR_CELL
-			&& rs6000_cpu != PROCESSOR_PPC476);
-rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
-			 || rs6000_cpu == PROCESSOR_POWER5
-			 || rs6000_cpu == PROCESSOR_POWER7
-			 || rs6000_cpu == PROCESSOR_POWER8);
-rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
-				 || rs6000_cpu == PROCESSOR_POWER5
-				 || rs6000_cpu == PROCESSOR_POWER6
-				 || rs6000_cpu == PROCESSOR_POWER7
-				 || rs6000_cpu == PROCESSOR_POWER8
-				 || rs6000_cpu == PROCESSOR_POWER9
-				 || rs6000_cpu == PROCESSOR_PPCE500MC
-				 || rs6000_cpu == PROCESSOR_PPCE500MC64
-				 || rs6000_cpu == PROCESSOR_PPCE5500
-				 || rs6000_cpu == PROCESSOR_PPCE6500);
 /* Allow debug switches to override the above settings.  These are set to -1
 in rs6000.opt to indicate the user hasn't directly set the switch.  */
 if (TARGET_ALWAYS_HINT >= 0)
 rs6000_always_hint = TARGET_ALWAYS_HINT;
 /* Set branch target alignment, if not optimizing for size.  */
 if (!optimize_size)
 	{
 	  /* Cell wants to be aligned 8byte for dual issue.  Titan wants to be
 	     aligned 8byte to avoid misprediction by the branch predictor.  */
-	  if (rs6000_cpu == PROCESSOR_TITAN
+	  if (rs6000_tune == PROCESSOR_TITAN
-	      || rs6000_cpu == PROCESSOR_CELL)
+	      || rs6000_tune == PROCESSOR_CELL)
 	    {
-	      if (align_functions <= 0)
+	      if (flag_align_functions && !str_align_functions)
-		align_functions = 8;
+		str_align_functions = "8";
-	      if (align_jumps <= 0)
+	      if (flag_align_jumps && !str_align_jumps)
-		align_jumps = 8;
+		str_align_jumps = "8";
-	      if (align_loops <= 0)
+	      if (flag_align_loops && !str_align_loops)
-		align_loops = 8;
+		str_align_loops = "8";
 	    }
 	  if (rs6000_align_branch_targets)
 	    {
-	      if (align_functions <= 0)
+	      if (flag_align_functions && !str_align_functions)
-		align_functions = 16;
+		str_align_functions = "16";
-	      if (align_jumps <= 0)
+	      if (flag_align_jumps && !str_align_jumps)
-		align_jumps = 16;
+		str_align_jumps = "16";
-	      if (align_loops <= 0)
+	      if (flag_align_loops && !str_align_loops)
 		{
 		  can_override_loop_align = 1;
-		  align_loops = 16;
+		  str_align_loops = "16";
 		}
 	    }
-	  if (align_jumps_max_skip <= 0)
-	    align_jumps_max_skip = 15;
+	  if (flag_align_jumps && !str_align_jumps)
-	  if (align_loops_max_skip <= 0)
+	    str_align_jumps = "16";
-	    align_loops_max_skip = 15;
+	  if (flag_align_loops && !str_align_loops)
+	    str_align_loops = "16";
 	}
 /* Arrange to save and restore machine status around nested functions.  */
 init_machine_status = rs6000_init_machine_status;
 /* Initialize rs6000_cost with the appropriate target costs.  */
 if (optimize_size)
 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
 else
-switch (rs6000_cpu)
+switch (rs6000_tune)
 {
 case PROCESSOR_RS64A:
 	rs6000_cost = &rs64a_cost;
 	break;
 	 ap = __builtin_next_arg (0).  */
 if (DEFAULT_ABI != ABI_V4)
 	targetm.expand_builtin_va_start = NULL;
 }
-/* Set up single/double float flags.
-If TARGET_HARD_FLOAT is set, but neither single or double is set,
-then set both flags. */
-if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
-rs6000_single_float = rs6000_double_float = 1;
 /* If not explicitly specified via option, decide whether to generate indexed
 load/store instructions.  A value of -1 indicates that the
 initial value of this variable has not been overwritten. During
 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
 if (TARGET_AVOID_XFORM == -1)
 /* Avoid indexed addressing when targeting Power6 in order to avoid the
 DERAT mispredict penalty.  However the LVE and STVE altivec instructions
 need indexed accesses and the type used is the scalar type of the element
 being loaded or stored.  */
-TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
 			  && !TARGET_ALTIVEC);
 /* Set the -mrecip options.  */
 if (rs6000_recip_name)
 {
 	}
 }
 /* Set the builtin mask of the various options used that could affect which
 builtins were used.  In the past we used target_flags, but we've run out
-of bits, and some options like PAIRED are no longer in target_flags.  */
+of bits, and some options are no longer in target_flags.  */
 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 rs6000_print_builtin_options (stderr, 0, "builtin mask",
 				  rs6000_builtin_mask);
 = build_target_option_node (&global_options);
 /* If not explicitly specified via option, decide whether to generate the
 extra blr's required to preserve the link stack on some cpus (eg, 476).  */
 if (TARGET_LINK_STACK == -1)
-SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
+SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
+/* Deprecate use of -mno-speculate-indirect-jumps.  */
+if (!rs6000_speculate_indirect_jumps)
+warning (0, "%qs is deprecated and not recommended in any circumstances",
+	     "-mno-speculate-indirect-jumps");
 return ret;
 }
 /* Implement TARGET_OPTION_OVERRIDE.  On the RS/6000 this is used to
 else
 return 0;
 }
 /* Implement LOOP_ALIGN. */
-int
+align_flags
 rs6000_loop_align (rtx label)
 {
 basic_block bb;
 int ninsns;
 /* Don't override loop alignment if -falign-loops was specified. */
 if (!can_override_loop_align)
-return align_loops_log;
+return align_loops;
 bb = BLOCK_FOR_INSN (label);
 ninsns = num_loop_insns(bb->loop_father);
 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
 if (ninsns > 4 && ninsns <= 8
-&& (rs6000_cpu == PROCESSOR_POWER4
+&& (rs6000_tune == PROCESSOR_POWER4
-	  || rs6000_cpu == PROCESSOR_POWER5
+	  || rs6000_tune == PROCESSOR_POWER5
-	  || rs6000_cpu == PROCESSOR_POWER6
+	  || rs6000_tune == PROCESSOR_POWER6
-	  || rs6000_cpu == PROCESSOR_POWER7
+	  || rs6000_tune == PROCESSOR_POWER7
-	  || rs6000_cpu == PROCESSOR_POWER8
+	  || rs6000_tune == PROCESSOR_POWER8))
-	  || rs6000_cpu == PROCESSOR_POWER9))
+return align_flags (5);
-return 5;
 else
-return align_loops_log;
+return align_loops;
-}
-/* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
-static int
-rs6000_loop_align_max_skip (rtx_insn *label)
-{
-return (1 << rs6000_loop_align (label)) - 1;
 }
 /* Return true iff, data reference of TYPE can reach vector alignment (16)
 after applying N number of iterations.  This routine does not determine
 how may iterations are required to reach desired alignment.  */
 	return V8HImode;
 case E_QImode:
 	return V16QImode;
 default:;
 }
-if (TARGET_PAIRED_FLOAT
-&& mode == SFmode)
-return V2SFmode;
 return word_mode;
 }
 typedef struct _rs6000_cost_data
 {
 const int DENSITY_SIZE_THRESHOLD = 70;
 const int DENSITY_PENALTY = 10;
 struct loop *loop = data->loop_info;
 basic_block *bbs = get_loop_body (loop);
 int nbbs = loop->num_nodes;
+loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
 int i, density_pct;
 for (i = 0; i < nbbs; i++)
 {
 gimple_stmt_iterator gsi;
 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
 	{
 	  gimple *stmt = gsi_stmt (gsi);
-	  stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
+	  stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
 	  if (!STMT_VINFO_RELEVANT_P (stmt_info)
 	      && !STMT_VINFO_IN_PATTERN_P (stmt_info))
 	    not_vec_cost++;
 	}
 }
 }
 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
 If the mode of OP is MODE_VECTOR_INT, this simply returns the
-corresponding element of the vector, but for V4SFmode and V2SFmode,
+corresponding element of the vector, but for V4SFmode, the
-the corresponding "float" is interpreted as an SImode integer.  */
+corresponding "float" is interpreted as an SImode integer.  */
 HOST_WIDE_INT
 const_vector_elt_as_int (rtx op, unsigned int elt)
 {
 rtx tmp;
 /* We can't handle V2DImode and V2DFmode vector constants here yet.  */
 gcc_assert (GET_MODE (op) != V2DImode
 	      && GET_MODE (op) != V2DFmode);
 tmp = CONST_VECTOR_ELT (op, elt);
-if (GET_MODE (op) == V4SFmode
+if (GET_MODE (op) == V4SFmode)
-|| GET_MODE (op) == V2SFmode)
 tmp = gen_lowpart (SImode, tmp);
 return INTVAL (tmp);
 }
 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
 	  gcc_unreachable ();
 	}
 }
 gcc_unreachable ();
-}
-/* Initialize TARGET of vector PAIRED to VALS.  */
-void
-paired_expand_vector_init (rtx target, rtx vals)
-{
-machine_mode mode = GET_MODE (target);
-int n_elts = GET_MODE_NUNITS (mode);
-int n_var = 0;
-rtx x, new_rtx, tmp, constant_op, op1, op2;
-int i;
-for (i = 0; i < n_elts; ++i)
-{
-x = XVECEXP (vals, 0, i);
-if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
-	++n_var;
-}
-if (n_var == 0)
-{
-/* Load from constant pool.  */
-emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
-return;
-}
-if (n_var == 2)
-{
-/* The vector is initialized only with non-constants.  */
-new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
-				XVECEXP (vals, 0, 1));
-emit_move_insn (target, new_rtx);
-return;
-}
-/* One field is non-constant and the other one is a constant.  Load the
-constant from the constant pool and use ps_merge instruction to
-construct the whole vector.  */
-op1 = XVECEXP (vals, 0, 0);
-op2 = XVECEXP (vals, 0, 1);
-constant_op = (CONSTANT_P (op1)) ? op1 : op2;
-tmp = gen_reg_rtx (GET_MODE (constant_op));
-emit_move_insn (tmp, constant_op);
-if (CONSTANT_P (op1))
-new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
-else
-new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
-emit_move_insn (target, new_rtx);
-}
-void
-paired_expand_vector_move (rtx operands[])
-{
-rtx op0 = operands[0], op1 = operands[1];
-emit_move_insn (op0, op1);
-}
-/* Emit vector compare for code RCODE.  DEST is destination, OP1 and
-OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
-operands for the relation operation COND.  This is a recursive
-function.  */
-static void
-paired_emit_vector_compare (enum rtx_code rcode,
-rtx dest, rtx op0, rtx op1,
-rtx cc_op0, rtx cc_op1)
-{
-rtx tmp = gen_reg_rtx (V2SFmode);
-rtx tmp1, max, min;
-gcc_assert (TARGET_PAIRED_FLOAT);
-gcc_assert (GET_MODE (op0) == GET_MODE (op1));
-switch (rcode)
-{
-case LT:
-case LTU:
-paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
-return;
-case GE:
-case GEU:
-emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
-emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
-return;
-case LE:
-case LEU:
-paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
-return;
-case GT:
-paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
-return;
-case EQ:
-tmp1 = gen_reg_rtx (V2SFmode);
-max = gen_reg_rtx (V2SFmode);
-min = gen_reg_rtx (V2SFmode);
-gen_reg_rtx (V2SFmode);
-emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
-emit_insn (gen_selv2sf4
-(max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
-emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
-emit_insn (gen_selv2sf4
-(min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
-emit_insn (gen_subv2sf3 (tmp1, min, max));
-emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
-return;
-case NE:
-paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
-return;
-case UNLE:
-paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
-return;
-case UNLT:
-paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
-return;
-case UNGE:
-paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
-return;
-case UNGT:
-paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
-return;
-default:
-gcc_unreachable ();
-}
-return;
-}
-/* Emit vector conditional expression.
-DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
-CC_OP0 and CC_OP1 are the two operands for the relation operation COND.  */
-int
-paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
-			      rtx cond, rtx cc_op0, rtx cc_op1)
-{
-enum rtx_code rcode = GET_CODE (cond);
-if (!TARGET_PAIRED_FLOAT)
-return 0;
-paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
-return 1;
 }
 /* Initialize vector TARGET to VALS.  */
 void
 	{
 	  rtx elements[4];
 	  size_t i;
 	  for (i = 0; i < 4; i++)
-	    {
+	    elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
-	      elements[i] = XVECEXP (vals, 0, i);
-	      if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
-		elements[i] = copy_to_mode_reg (SImode, elements[i]);
-	    }
 	  emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
 					elements[2], elements[3]));
 	  return;
 	}
 			UNSPEC_VPERM);
 else
 {
 if (TARGET_P9_VECTOR)
 	x = gen_rtx_UNSPEC (mode,
-			    gen_rtvec (3, target, reg,
+			    gen_rtvec (3, reg, target,
 				       force_reg (V16QImode, x)),
 			    UNSPEC_VPERMR);
 else
 	{
 	  /* Invert selector.  We prefer to generate VNAND on P8 so
 	{
 	  rtx dest_si = gen_rtx_REG (SImode, dest_regno);
 	  rtx element_si = gen_rtx_REG (SImode, element_regno);
 	  if (mode == V16QImode)
-	    emit_insn (VECTOR_ELT_ORDER_BIG
+	    emit_insn (BYTES_BIG_ENDIAN
 		       ? gen_vextublx (dest_si, element_si, src)
 		       : gen_vextubrx (dest_si, element_si, src));
 	  else if (mode == V8HImode)
 	    {
 	      rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
 	      emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
-	      emit_insn (VECTOR_ELT_ORDER_BIG
+	      emit_insn (BYTES_BIG_ENDIAN
 			 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
 			 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
 	    }
 	  else
 	    {
 	      rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
 	      emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
-	      emit_insn (VECTOR_ELT_ORDER_BIG
+	      emit_insn (BYTES_BIG_ENDIAN
 			 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
 			 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
 	    }
 	  return;
 	 an XOR, otherwise we need to subtract.  The shift amount is so VSLO
 	 will shift the element into the upper position (adding 3 to convert a
 	 byte shift into a bit shift).  */
 if (scalar_size == 8)
 	{
-	  if (!VECTOR_ELT_ORDER_BIG)
+	  if (!BYTES_BIG_ENDIAN)
 	    {
 	      emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
 	      element2 = tmp_gpr;
 	    }
 	  else
 							       GEN_INT (6)),
 					       GEN_INT (64))));
 	}
 else
 	{
-	  if (!VECTOR_ELT_ORDER_BIG)
+	  if (!BYTES_BIG_ENDIAN)
 	    {
 	      rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
 	      emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
 	      emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
 }
 else
 gcc_unreachable ();
 }
-/* Helper function for rs6000_split_v4si_init to build up a DImode value from
-two SImode values.  */
-static void
-rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
-{
-const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
-if (CONST_INT_P (si1) && CONST_INT_P (si2))
-{
-unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
-unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
-emit_move_insn (dest, GEN_INT (const1 | const2));
-return;
-}
-/* Put si1 into upper 32-bits of dest.  */
-if (CONST_INT_P (si1))
-emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
-else
-{
-/* Generate RLDIC.  */
-rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
-rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
-rtx mask_rtx = GEN_INT (mask_32bit << 32);
-rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
-gcc_assert (!reg_overlap_mentioned_p (dest, si1));
-emit_insn (gen_rtx_SET (dest, and_rtx));
-}
-/* Put si2 into the temporary.  */
-gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
-if (CONST_INT_P (si2))
-emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
-else
-emit_insn (gen_zero_extendsidi2 (tmp, si2));
-/* Combine the two parts.  */
-emit_insn (gen_iordi3 (dest, dest, tmp));
-return;
-}
-/* Split a V4SI initialization.  */
-void
-rs6000_split_v4si_init (rtx operands[])
-{
-rtx dest = operands[0];
-/* Destination is a GPR, build up the two DImode parts in place.  */
-if (REG_P (dest) || SUBREG_P (dest))
-{
-int d_regno = regno_or_subregno (dest);
-rtx scalar1 = operands[1];
-rtx scalar2 = operands[2];
-rtx scalar3 = operands[3];
-rtx scalar4 = operands[4];
-rtx tmp1 = operands[5];
-rtx tmp2 = operands[6];
-/* Even though we only need one temporary (plus the destination, which
-	 has an early clobber constraint, try to use two temporaries, one for
-	 each double word created.  That way the 2nd insn scheduling pass can
-	 rearrange things so the two parts are done in parallel.  */
-if (BYTES_BIG_ENDIAN)
-	{
-	  rtx di_lo = gen_rtx_REG (DImode, d_regno);
-	  rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
-	  rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
-	  rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
-	}
-else
-	{
-	  rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
-	  rtx di_hi = gen_rtx_REG (DImode, d_regno);
-	  gcc_assert (!VECTOR_ELT_ORDER_BIG);
-	  rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
-	  rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
-	}
-return;
-}
-else
-gcc_unreachable ();
-}
 /* Return alignment of TYPE.  Existing alignment is ALIGN.  HOW
 selects whether the alignment is abi mandated, optional, or
 both abi and optional alignment.  */
 unsigned int
 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
 {
 if (how != align_opt)
 {
-if (TREE_CODE (type) == VECTOR_TYPE)
+if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
-	{
+	align = 128;
-	  if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
-	    {
-	      if (align < 64)
-		align = 64;
-	    }
-	  else if (align < 128)
-	    align = 128;
-	}
 }
 if (how != align_abi)
 {
 if (TREE_CODE (type) == ARRAY_TYPE
 return false;
 if (legitimate_indirect_address_p (addr, strict))
 return true;
-if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
+if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
 return false;
 if (GET_CODE (addr) != PLUS)
 return false;
 mem_operand_gpr (rtx op, machine_mode mode)
 {
 unsigned HOST_WIDE_INT offset;
 int extra;
 rtx addr = XEXP (op, 0);
+/* PR85755: Allow PRE_INC and PRE_DEC addresses.  */
+if (TARGET_UPDATE
+&& (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
+&& mode_supports_pre_incdec_p (mode)
+&& legitimate_indirect_address_p (XEXP (addr, 0), false))
+return true;
+/* Don't allow non-offsettable addresses.  See PRs 83969 and 84279.  */
+if (!rs6000_offsettable_memref_p (op, mode, false))
+return false;
 op = address_offset (addr);
 if (op == NULL_RTX)
 return true;
 	 a vector mode, if we want to use the VSX registers to move it around,
 	 we need to restrict ourselves to reg+reg addressing.  Similarly for
 	 IEEE 128-bit floating point that is passed in a single vector
 	 register.  */
 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
-	return mode_supports_vsx_dform_quad (mode);
+	return mode_supports_dq_form (mode);
-break;
-case E_V2SImode:
-case E_V2SFmode:
-/* Paired vector modes.  Only reg+reg addressing is valid.  */
-if (TARGET_PAIRED_FLOAT)
-return false;
 break;
 case E_SDmode:
 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
 	 addressing for the LFIWZX and STFIWX instructions.  */
 if (GET_CODE (op) != SYMBOL_REF)
 return false;
 /* ISA 3.0 vector d-form addressing is restricted, don't allow
 SYMBOL_REF.  */
-if (mode_supports_vsx_dform_quad (mode))
+if (mode_supports_dq_form (mode))
 return false;
 dsize = GET_MODE_SIZE (mode);
 decl = SYMBOL_REF_DECL (op);
 if (!decl)
 *tocrel_base_ret = tocrel_base;
 if (tocrel_offset_ret)
 *tocrel_offset_ret = tocrel_offset;
 return (GET_CODE (tocrel_base) == UNSPEC
-	  && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
+	  && XINT (tocrel_base, 1) == UNSPEC_TOCREL
+	  && REG_P (XVECEXP (tocrel_base, 0, 1))
+	  && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
 }
 /* Return true if X is a constant pool address, and also for cmodel=medium
 if X is a toc-relative address known to be offsettable within MODE.  */
 return false;
 if (!REG_P (XEXP (x, 0)))
 return false;
 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
 return false;
-if (mode_supports_vsx_dform_quad (mode))
+if (mode_supports_dq_form (mode))
 return quad_address_p (x, mode, strict);
 if (!reg_offset_addressing_ok_p (mode))
 return virtual_stack_registers_memory_p (x);
 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
 return true;
 offset = INTVAL (XEXP (x, 1));
 extra = 0;
 switch (mode)
 {
-case E_V2SImode:
-case E_V2SFmode:
-/* Paired single modes: offset addressing isn't valid.  */
-return false;
 case E_DFmode:
 case E_DDmode:
 case E_DImode:
 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
 	 addressing.  */
 if (GET_CODE (XEXP (x, 0)) != REG)
 return false;
 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
 return false;
 /* quad word addresses are restricted, and we can't use LO_SUM.  */
-if (mode_supports_vsx_dform_quad (mode))
+if (mode_supports_dq_form (mode))
 return false;
 x = XEXP (x, 1);
 if (TARGET_ELF || TARGET_MACHO)
 {
 	return false;
 if (GET_MODE_NUNITS (mode) != 1)
 	return false;
 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
 	  && !(/* ??? Assume floating point reg based on mode?  */
-	       TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+	       TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
-	       && (mode == DFmode || mode == DDmode)))
 	return false;
 return CONSTANT_P (x) || large_toc_ok;
 }
 			   machine_mode mode)
 {
 unsigned int extra;
 if (!reg_offset_addressing_ok_p (mode)
-|| mode_supports_vsx_dform_quad (mode))
+|| mode_supports_dq_form (mode))
 {
 if (virtual_stack_registers_memory_p (x))
 	return x;
 /* In theory we should not be seeing addresses of the form reg+0,
 if (GET_CODE (x) == PLUS
 && GET_CODE (XEXP (x, 0)) == REG
 && GET_CODE (XEXP (x, 1)) == CONST_INT
 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
-	  >= 0x10000 - extra)
+	  >= 0x10000 - extra))
-&& !PAIRED_VECTOR_MODE (mode))
 {
 HOST_WIDE_INT high_int, low_int;
 rtx sum;
 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
 if (low_int >= 0x8000 - extra)
 	   && GET_CODE (XEXP (x, 0)) == REG
 	   && GET_CODE (XEXP (x, 1)) != CONST_INT
 	   && GET_MODE_NUNITS (mode) == 1
 	   && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
 	       || (/* ??? Assume floating point reg based on mode?  */
-		   (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+		   TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
-		   && (mode == DFmode || mode == DDmode)))
 	   && !avoiding_indexed_address_p (mode))
 {
 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
 			   force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
-}
-else if (PAIRED_VECTOR_MODE (mode))
-{
-if (mode == DImode)
-	return x;
-/* We accept [reg + reg].  */
-if (GET_CODE (x) == PLUS)
-{
-rtx op1 = XEXP (x, 0);
-rtx op2 = XEXP (x, 1);
-rtx y;
-op1 = force_reg (Pmode, op1);
-op2 = force_reg (Pmode, op2);
-/* We can't always do [reg + reg] for these, because [reg +
-reg + offset] is not a legitimate addressing mode.  */
-y = gen_rtx_PLUS (Pmode, op1, op2);
-if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
-return force_reg (Pmode, y);
-else
-return y;
-}
-return force_reg (Pmode, x);
 }
 else if ((TARGET_ELF
 #if TARGET_MACHO
 	    || !MACHO_DYNAMIC_NO_PIC_P
 #endif
 	   && GET_CODE (x) != CONST_DOUBLE
 	   && CONSTANT_P (x)
 	   && GET_MODE_NUNITS (mode) == 1
 	   && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
 	       || (/* ??? Assume floating point reg based on mode?  */
-		   (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+		   TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
-		   && (mode == DFmode || mode == DDmode))))
 {
 rtx reg = gen_reg_rtx (Pmode);
 if (TARGET_ELF)
 	emit_insn (gen_elf_high (reg, x));
 else
 splitter that runs after reload needs memory to transfer from
 a gpr to fpr.  See PR70098 and PR71763 which are not fixed
 for the difficult case.  It's better to not create problems
 in the first place.  */
 if (icode != CODE_FOR_nothing
-&& (icode == CODE_FOR_ctrsi_internal1
+&& (icode == CODE_FOR_bdz_si
-	  || icode == CODE_FOR_ctrdi_internal1
+	  || icode == CODE_FOR_bdz_di
-	  || icode == CODE_FOR_ctrsi_internal2
+	  || icode == CODE_FOR_bdnz_si
-	  || icode == CODE_FOR_ctrdi_internal2))
+	  || icode == CODE_FOR_bdnz_di
+	  || icode == CODE_FOR_bdztf_si
+	  || icode == CODE_FOR_bdztf_di
+	  || icode == CODE_FOR_bdnztf_si
+	  || icode == CODE_FOR_bdnztf_di))
 return false;
 return true;
 }
 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
 				  int opnum, int type,
 				  int ind_levels ATTRIBUTE_UNUSED, int *win)
 {
 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
-bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+bool quad_offset_p = mode_supports_dq_form (mode);
 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
 DFmode/DImode MEM.  Ditto for ISA 3.0 vsx_splat_v4sf/v4si.  */
 if (reg_offset_p
 && opnum == 1
 && REG_P (XEXP (x, 0))
 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
 && CONST_INT_P (XEXP (x, 1))
 && reg_offset_p
-&& !PAIRED_VECTOR_MODE (mode)
 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
 {
 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
 HOST_WIDE_INT high
 if (GET_CODE (x) == SYMBOL_REF
 && reg_offset_p
 && !quad_offset_p
 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
-&& !PAIRED_VECTOR_MODE (mode)
 #if TARGET_MACHO
 && DEFAULT_ABI == ABI_DARWIN
 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
 && machopic_symbol_defined_p (x)
 #else
 && mode != KFmode
 && (mode != TImode || !TARGET_VSX)
 && mode != PTImode
 && (mode != DImode || TARGET_POWERPC64)
 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
-	  || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
+	  || TARGET_HARD_FLOAT))
 {
 #if TARGET_MACHO
 if (flag_pic)
 	{
 	  rtx offset = machopic_gen_offset (x);
 during assembly output.  */
 static bool
 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
 {
 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
-bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+bool quad_offset_p = mode_supports_dq_form (mode);
 /* If this is an unaligned stvx/ldvx type address, discard the outer AND.  */
 if (VECTOR_MEM_ALTIVEC_P (mode)
 && GET_CODE (x) == AND
 && GET_CODE (XEXP (x, 1)) == CONST_INT
 {
 if (legitimate_small_data_p (mode, x))
 	return 1;
 if (legitimate_constant_pool_address_p (x, mode,
 					     reg_ok_strict || lra_in_progress))
-	return 1;
-if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
-	  && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
 	return 1;
 }
 /* For TImode, if we have TImode in VSX registers, only allow register
 indirect addresses.  This will allow the values to go in either GPRs
 && GET_CODE (XEXP (x, 1)) == CONST_INT)
 return 1;
 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
 return 1;
 if (!FLOAT128_2REG_P (mode)
-&& ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+&& (TARGET_HARD_FLOAT
 	  || TARGET_POWERPC64
 	  || (mode != DFmode && mode != DDmode))
 && (TARGET_POWERPC64 || mode != DImode)
 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
 && mode != PTImode
 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
 in 32-bit mode, that the recog predicate rejects.  */
 static bool
-rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
+rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
 {
 bool worst_case;
 if (!MEM_P (op))
 return false;
 /* First mimic offsettable_memref_p.  */
-if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
+if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
 return true;
 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
 the latter predicate knows nothing about the mode of the memory
 reference and, therefore, assumes that it is the largest supported
 at least with a little bit of help here given that we know the
 actual registers used.  */
 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
 		|| GET_MODE_SIZE (reg_mode) == 4);
 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
-					     true, worst_case);
+					     strict, worst_case);
 }
 /* Determine the reassociation width to be used in reassociate_bb.
 This takes into account how many parallel operations we
 can actually do of a given type, and also the latency.
 static int
 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
 machine_mode mode)
 {
-switch (rs6000_cpu)
+switch (rs6000_tune)
 {
 case PROCESSOR_POWER8:
 case PROCESSOR_POWER9:
 if (DECIMAL_FLOAT_MODE_P (mode))
 	return 1;
 if (VECTOR_MODE_P (mode))
 	return 4;
 if (INTEGRAL_MODE_P (mode))
-	return opc == MULT_EXPR ? 4 : 6;
+	return 1;
 if (FLOAT_MODE_P (mode))
 	return 4;
 break;
 default:
 break;
 {
 /* This should be fixed with the introduction of CONST_WIDE_INT.  */
 gcc_unreachable ();
 }
+#ifdef HAVE_AS_GNU_ATTRIBUTE
+/* If we use a long double type, set the flags in .gnu_attribute that say
+what the long double type is.  This is to allow the linker's warning
+message for the wrong long double to be useful, even if the function does
+not do a call (for example, doing a 128-bit add on power9 if the long
+double type is IEEE 128-bit.  Do not set this if __ibm128 or __floa128 are
+used if they aren't the default long dobule type.  */
+if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
+{
+if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
+	rs6000_passes_float = rs6000_passes_long_double = true;
+else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
+	rs6000_passes_float = rs6000_passes_long_double = true;
+}
+#endif
 /* See if we need to special case SImode/SFmode SUBREG moves.  */
 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
 return;
 int regno = REGNO (SUBREG_REG (operands[1]));
 if (regno >= FIRST_PSEUDO_REGISTER)
 	{
 	  cl = reg_preferred_class (regno);
-	  regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
+	  regno = reg_renumber[regno];
+	  if (regno < 0)
+	    regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
 	}
 if (regno >= 0 && ! FP_REGNO_P (regno))
 	{
 	  mode = SDmode;
 	  operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
 if (regno >= FIRST_PSEUDO_REGISTER)
 	{
 	  cl = reg_preferred_class (regno);
 	  gcc_assert (cl != NO_REGS);
-	  regno = ira_class_hard_regs[cl][0];
+	  regno = reg_renumber[regno];
+	  if (regno < 0)
+	    regno = ira_class_hard_regs[cl][0];
 	}
 if (FP_REGNO_P (regno))
 	{
 	  if (GET_MODE (operands[0]) != DDmode)
 	    operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
 int regno = REGNO (SUBREG_REG (operands[0]));
 if (regno >= FIRST_PSEUDO_REGISTER)
 	{
 	  cl = reg_preferred_class (regno);
-	  regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
+	  regno = reg_renumber[regno];
+	  if (regno < 0)
+	    regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
 	}
 if (regno >= 0 && ! FP_REGNO_P (regno))
 	{
 	  mode = SDmode;
 	  operands[0] = SUBREG_REG (operands[0]);
 if (regno >= FIRST_PSEUDO_REGISTER)
 	{
 	  cl = reg_preferred_class (regno);
 	  gcc_assert (cl != NO_REGS);
-	  regno = ira_class_hard_regs[cl][0];
+	  regno = reg_renumber[regno];
+	  if (regno < 0)
+	    regno = ira_class_hard_regs[cl][0];
 	}
 if (FP_REGNO_P (regno))
 	{
 	  if (GET_MODE (operands[1]) != DDmode)
 	    operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
 case E_V16QImode:
 case E_V8HImode:
 case E_V4SFmode:
 case E_V4SImode:
-case E_V2SFmode:
-case E_V2SImode:
 case E_V2DFmode:
 case E_V2DImode:
 case E_V1TImode:
 if (CONSTANT_P (operands[1])
 	  && !easy_vector_constant (operands[1], mode))
 {
 /* Note that we do not accept complex types at the top level as
 homogeneous aggregates; these types are handled via the
 targetm.calls.split_complex_arg mechanism.  Complex types
 can be elements of homogeneous aggregates, however.  */
-if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))
+if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
+&& AGGREGATE_TYPE_P (type))
 {
 machine_mode field_mode = VOIDmode;
 int field_count = rs6000_aggregate_candidate (type, &field_mode);
 if (field_count > 0)
 	{
-	  int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
+	  int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
-			(GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
+	  int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
 	  /* The ELFv2 ABI allows homogeneous aggregates to occupy
 	     up to AGGR_ARG_NUM_REG registers.  */
-	  if (field_count * n_regs <= AGGR_ARG_NUM_REG)
+	  if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
 	    {
 	      if (elt_mode)
 		*elt_mode = field_mode;
 	      if (n_elts)
 		*n_elts = field_count;
 		      || FLOAT128_IEEE_P (return_mode)
 		      || (return_type != NULL
 			  && (TYPE_MAIN_VARIANT (return_type)
 			      == long_double_type_node))))
 		rs6000_passes_long_double = true;
+	      /* Note if we passed or return a IEEE 128-bit type.  We changed
+		 the mangling for these types, and we may need to make an alias
+		 with the old mangling.  */
+	      if (FLOAT128_IEEE_P (return_mode))
+		rs6000_passes_ieee128 = true;
 	    }
-	  if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
+	  if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
-	      || PAIRED_VECTOR_MODE (return_mode))
 	    rs6000_passes_vector = true;
 	}
 }
 #endif
 }
 static inline bool
 is_complex_IBM_long_double (machine_mode mode)
 {
-return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode);
+return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
 }
 /* Whether ABI_V4 passes MODE args to a function in floating point
 registers.  */
 static bool
-abi_v4_pass_in_fpr (machine_mode mode)
+abi_v4_pass_in_fpr (machine_mode mode, bool named)
 {
 if (!TARGET_HARD_FLOAT)
 return false;
-if (TARGET_SINGLE_FLOAT && mode == SFmode)
+if (mode == DFmode)
 return true;
-if (TARGET_DOUBLE_FLOAT && mode == DFmode)
+if (mode == SFmode && named)
 return true;
 /* ABI_V4 passes complex IBM long double in 8 gprs.
 Stupid, but we can't change the ABI now.  */
 if (is_complex_IBM_long_double (mode))
 return false;
 	      && !is_complex_IBM_long_double (mode)
 	      && FLOAT128_2REG_P (mode))))
 return 64;
 else if (FLOAT128_VECTOR_P (mode))
 return 128;
-else if (PAIRED_VECTOR_MODE (mode)
+else if (type && TREE_CODE (type) == VECTOR_TYPE
-	   || (type && TREE_CODE (type) == VECTOR_TYPE
+	   && int_size_in_bytes (type) >= 8
-	       && int_size_in_bytes (type) >= 8
+	   && int_size_in_bytes (type) < 16)
-	       && int_size_in_bytes (type) < 16))
 return 64;
 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
 	   || (type && TREE_CODE (type) == VECTOR_TYPE
 	       && int_size_in_bytes (type) >= 16))
 return 128;
 	      && (FLOAT128_IBM_P (mode)
 		  || FLOAT128_IEEE_P (mode)
 		  || (type != NULL
 		      && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
 	    rs6000_passes_long_double = true;
-	}
-if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
+	  /* Note if we passed or return a IEEE 128-bit type.  We changed the
-	  || (PAIRED_VECTOR_MODE (mode)
+	     mangling for these types, and we may need to make an alias with
-	      && !cum->stdarg
+	     the old mangling.  */
-	      && cum->sysv_gregno <= GP_ARG_MAX_REG))
+	  if (FLOAT128_IEEE_P (mode))
+	    rs6000_passes_ieee128 = true;
+	}
+if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
 	rs6000_passes_vector = true;
 }
 #endif
 if (TARGET_ALTIVEC_ABI
 		       GET_MODE_NAME (mode));
 	    }
 }
 else if (DEFAULT_ABI == ABI_V4)
 {
-if (abi_v4_pass_in_fpr (mode))
+if (abi_v4_pass_in_fpr (mode, named))
 	{
 	  /* _Decimal128 must use an even/odd register pair.  This assumes
 	     that the register number is odd when fregno is odd.  */
 	  if (mode == TDmode && (cum->fregno % 2) == 1)
 	    cum->fregno++;
 	}
 }
 else if (abi == ABI_V4)
 {
-if (abi_v4_pass_in_fpr (mode))
+if (abi_v4_pass_in_fpr (mode, named))
 	{
 	  /* _Decimal128 must use an even/odd register pair.  This assumes
 	     that the register number is odd when fregno is odd.  */
 	  if (mode == TDmode && (cum->fregno % 2) == 1)
 	    cum->fregno++;
 for (nregs = 0;
 	   fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
 	   fregno++, off += UNITS_PER_FP_WORD, nregs++)
 	{
-	  mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+	  mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
-			      ? DFmode : SFmode,
 plus_constant (Pmode, save_area, off));
 	  MEM_NOTRAP_P (mem) = 1;
 	  set_mem_alias_set (mem, set);
 	  set_mem_align (mem, GET_MODE_ALIGNMENT (
-			 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+			 TARGET_HARD_FLOAT ? DFmode : SFmode));
-			  ? DFmode : SFmode));
 	  emit_move_insn (mem, gen_rtx_REG (
-(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
-			   ? DFmode : SFmode, fregno));
 	}
 emit_label (lab);
 }
 }
 rsize = (size + 3) / 4;
 int pad = 4 * rsize - size;
 align = 1;
 machine_mode mode = TYPE_MODE (type);
-if (abi_v4_pass_in_fpr (mode))
+if (abi_v4_pass_in_fpr (mode, false))
 {
 /* FP args go in FP registers, if present.  */
 reg = fpr;
 n_reg = (size + 7) / 8;
-sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
+sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
-sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
+sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
 if (mode != SFmode && mode != SDmode)
 	align = 8;
 }
 else
 {
 tree tmp = create_tmp_var (type, "va_arg_tmp");
 tree dest_addr = build_fold_addr_expr (tmp);
 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
 				   3, dest_addr, addr, size_int (rsize * 4));
+TREE_ADDRESSABLE (tmp) = 1;
 gimplify_and_add (copy, pre_p);
 addr = dest_addr;
 }
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 static const struct builtin_description bdesc_3arg[] =
 {
 #include "rs6000-builtin.def"
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
 { MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 static const struct builtin_description bdesc_dst[] =
 {
 #include "rs6000-builtin.def"
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 static const struct builtin_description bdesc_2arg[] =
 {
 #include "rs6000-builtin.def"
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
 { MASK, ICODE, NAME, ENUM },
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 /* AltiVec predicates.  */
 static const struct builtin_description bdesc_altivec_preds[] =
 {
 #include "rs6000-builtin.def"
 };
-/* PAIRED predicates.  */
+/* ABS* operations.  */
 #undef RS6000_BUILTIN_0
 #undef RS6000_BUILTIN_1
 #undef RS6000_BUILTIN_2
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
+{ MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
-{ MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-static const struct builtin_description bdesc_paired_preds[] =
+static const struct builtin_description bdesc_abs[] =
 {
 #include "rs6000-builtin.def"
 };
-/* ABS* operations.  */
+/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
+foo (VECa).  */
 #undef RS6000_BUILTIN_0
 #undef RS6000_BUILTIN_1
 #undef RS6000_BUILTIN_2
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
+{ MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-{ MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-static const struct builtin_description bdesc_abs[] =
+static const struct builtin_description bdesc_1arg[] =
 {
 #include "rs6000-builtin.def"
 };
-/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
+/* Simple no-argument operations: result = __builtin_darn_32 () */
-foo (VECa).  */
 #undef RS6000_BUILTIN_0
 #undef RS6000_BUILTIN_1
 #undef RS6000_BUILTIN_2
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_X
-#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
-{ MASK, ICODE, NAME, ENUM },
-#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
-static const struct builtin_description bdesc_1arg[] =
-{
-#include "rs6000-builtin.def"
-};
-/* Simple no-argument operations: result = __builtin_darn_32 () */
-#undef RS6000_BUILTIN_0
-#undef RS6000_BUILTIN_1
-#undef RS6000_BUILTIN_2
-#undef RS6000_BUILTIN_3
-#undef RS6000_BUILTIN_A
-#undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_H
-#undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
 { MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 static const struct builtin_description bdesc_0arg[] =
 {
 #include "rs6000-builtin.def"
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 #undef RS6000_BUILTIN_X
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
 { MASK, ICODE, NAME, ENUM },
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
-#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 static const struct builtin_description bdesc_htm[] =
 {
 #include "rs6000-builtin.def"
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
-#undef RS6000_BUILTIN_Q
 /* Return true if a builtin function is overloaded.  */
 bool
 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
 {
 machine_mode tmode = insn_data[icode].operand[0].mode;
 if (icode == CODE_FOR_nothing)
 /* Builtin not supported on this processor.  */
 return 0;
+if (icode == CODE_FOR_rs6000_mffsl
+&& rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
+{
+error ("__builtin_mffsl() not supported with -msoft-float");
+return const0_rtx;
+}
 if (target == 0
 || GET_MODE (target) != tmode
 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 target = gen_reg_rtx (tmode);
 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
 op1 = copy_to_mode_reg (mode1, op1);
 pat = GEN_FCN (icode) (op0, op1);
+if (!pat)
+return const0_rtx;
+emit_insn (pat);
+return NULL_RTX;
+}
+static rtx
+rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
+{
+rtx pat;
+tree arg0 = CALL_EXPR_ARG (exp, 0);
+rtx op0 = expand_normal (arg0);
+if (icode == CODE_FOR_nothing)
+/* Builtin not supported on this processor.  */
+return 0;
+if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
+{
+error ("__builtin_mtfsb0 and __builtin_mtfsb1 not supported with -msoft-float");
+return const0_rtx;
+}
+/* If we got invalid arguments bail out before generating bad rtl.  */
+if (arg0 == error_mark_node)
+return const0_rtx;
+/* Only allow bit numbers 0 to 31.  */
+if (!u5bit_cint_operand (op0, VOIDmode))
+{
+error ("Argument must be a constant between 0 and 31.");
+return const0_rtx;
+}
+pat = GEN_FCN (icode) (op0);
+if (!pat)
+return const0_rtx;
+emit_insn (pat);
+return NULL_RTX;
+}
+static rtx
+rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
+{
+rtx pat;
+tree arg0 = CALL_EXPR_ARG (exp, 0);
+rtx op0 = expand_normal (arg0);
+machine_mode mode0 = insn_data[icode].operand[0].mode;
+if (icode == CODE_FOR_nothing)
+/* Builtin not supported on this processor.  */
+return 0;
+if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
+{
+error ("__builtin_set_fpscr_rn not supported with -msoft-float");
+return const0_rtx;
+}
+/* If we got invalid arguments bail out before generating bad rtl.  */
+if (arg0 == error_mark_node)
+return const0_rtx;
+/* If the argument is a constant, check the range. Argument can only be a
+2-bit value.  Unfortunately, can't check the range of the value at
+compile time if the argument is a variable.  The least significant two
+bits of the argument, regardless of type, are used to set the rounding
+mode.  All other bits are ignored.  */
+if (GET_CODE (op0) == CONST_INT && !const_0_to_3_operand(op0, VOIDmode))
+{
+error ("Argument must be a value between 0 and 3.");
+return const0_rtx;
+}
+if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+op0 = copy_to_mode_reg (mode0, op0);
+pat = GEN_FCN (icode) (op0);
+if (!pat)
+return const0_rtx;
+emit_insn (pat);
+return NULL_RTX;
+}
+static rtx
+rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
+{
+rtx pat;
+tree arg0 = CALL_EXPR_ARG (exp, 0);
+rtx op0 = expand_normal (arg0);
+machine_mode mode0 = insn_data[icode].operand[0].mode;
+if (TARGET_32BIT)
+/* Builtin not supported in 32-bit mode.  */
+fatal_error (input_location,
+		 "__builtin_set_fpscr_drn is not supported in 32-bit mode.");
+if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
+{
+error ("__builtin_set_fpscr_drn not supported with -msoft-float");
+return const0_rtx;
+}
+if (icode == CODE_FOR_nothing)
+/* Builtin not supported on this processor.  */
+return 0;
+/* If we got invalid arguments bail out before generating bad rtl.  */
+if (arg0 == error_mark_node)
+return const0_rtx;
+/* If the argument is a constant, check the range. Agrument can only be a
+3-bit value.  Unfortunately, can't check the range of the value at
+compile time if the argument is a variable. The least significant two
+bits of the argument, regardless of type, are used to set the rounding
+mode.  All other bits are ignored.  */
+if (GET_CODE (op0) == CONST_INT && !const_0_to_7_operand(op0, VOIDmode))
+{
+error ("Argument must be a value between 0 and 7.");
+return const0_rtx;
+}
+if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+op0 = copy_to_mode_reg (mode0, op0);
+pat = GEN_FCN (icode) (op0);
 if (! pat)
 return const0_rtx;
 emit_insn (pat);
 return NULL_RTX;
 /* If we got invalid arguments bail out before generating bad rtl.  */
 if (arg0 == error_mark_node || arg1 == error_mark_node)
 return const0_rtx;
-if (icode == CODE_FOR_altivec_vcfux
+if (icode == CODE_FOR_unpackv1ti
+	   || icode == CODE_FOR_unpackkf
+	   || icode == CODE_FOR_unpacktf
+	   || icode == CODE_FOR_unpackif
+	   || icode == CODE_FOR_unpacktd)
+{
+/* Only allow 1-bit unsigned literals. */
+STRIP_NOPS (arg1);
+if (TREE_CODE (arg1) != INTEGER_CST
+	  || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
+	{
+	  error ("argument 2 must be a 1-bit unsigned literal");
+	  return CONST0_RTX (tmode);
+	}
+}
+else if (icode == CODE_FOR_altivec_vspltw)
+{
+/* Only allow 2-bit unsigned literals.  */
+STRIP_NOPS (arg1);
+if (TREE_CODE (arg1) != INTEGER_CST
+	  || TREE_INT_CST_LOW (arg1) & ~3)
+	{
+	  error ("argument 2 must be a 2-bit unsigned literal");
+	  return CONST0_RTX (tmode);
+	}
+}
+else if (icode == CODE_FOR_altivec_vsplth)
+{
+/* Only allow 3-bit unsigned literals.  */
+STRIP_NOPS (arg1);
+if (TREE_CODE (arg1) != INTEGER_CST
+	  || TREE_INT_CST_LOW (arg1) & ~7)
+	{
+	  error ("argument 2 must be a 3-bit unsigned literal");
+	  return CONST0_RTX (tmode);
+	}
+}
+else if (icode == CODE_FOR_altivec_vspltb)
+{
+/* Only allow 4-bit unsigned literals.  */
+STRIP_NOPS (arg1);
+if (TREE_CODE (arg1) != INTEGER_CST
+	  || TREE_INT_CST_LOW (arg1) & ~15)
+	{
+	  error ("argument 2 must be a 4-bit unsigned literal");
+	  return CONST0_RTX (tmode);
+	}
+}
+else if (icode == CODE_FOR_altivec_vcfux
 || icode == CODE_FOR_altivec_vcfsx
 || icode == CODE_FOR_altivec_vctsxs
-|| icode == CODE_FOR_altivec_vctuxs
+|| icode == CODE_FOR_altivec_vctuxs)
-|| icode == CODE_FOR_altivec_vspltb
-|| icode == CODE_FOR_altivec_vsplth
-|| icode == CODE_FOR_altivec_vspltw)
 {
 /* Only allow 5-bit unsigned literals.  */
 STRIP_NOPS (arg1);
 if (TREE_CODE (arg1) != INTEGER_CST
 	  || TREE_INT_CST_LOW (arg1) & ~0x1f)
 	{
 	  error ("argument 1 must be a 6-bit unsigned literal");
 	  return CONST0_RTX (tmode);
 	}
 }
-else if (icode == CODE_FOR_xststdcqp
+else if (icode == CODE_FOR_xststdcqp_kf
+	   || icode == CODE_FOR_xststdcqp_tf
 	   || icode == CODE_FOR_xststdcdp
 	   || icode == CODE_FOR_xststdcsp
 	   || icode == CODE_FOR_xvtstdcdp
 	   || icode == CODE_FOR_xvtstdcsp)
 {
 STRIP_NOPS (arg1);
 if (TREE_CODE (arg1) != INTEGER_CST
 	  || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
 	{
 	  error ("argument 2 must be a 7-bit unsigned literal");
-	  return CONST0_RTX (tmode);
-	}
-}
-else if (icode == CODE_FOR_unpackv1ti
-	   || icode == CODE_FOR_unpackkf
-	   || icode == CODE_FOR_unpacktf
-	   || icode == CODE_FOR_unpackif
-	   || icode == CODE_FOR_unpacktd)
-{
-/* Only allow 1-bit unsigned literals. */
-STRIP_NOPS (arg1);
-if (TREE_CODE (arg1) != INTEGER_CST
-	  || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
-	{
-	  error ("argument 2 must be a 1-bit unsigned literal");
 	  return CONST0_RTX (tmode);
 	}
 }
 if (target == 0
 }
 return target;
 }
-static rtx
+rtx
-paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
+swap_endian_selector_for_mode (machine_mode mode)
 {
-rtx pat, addr;
+unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
-tree arg0 = CALL_EXPR_ARG (exp, 0);
-tree arg1 = CALL_EXPR_ARG (exp, 1);
-machine_mode tmode = insn_data[icode].operand[0].mode;
-machine_mode mode0 = Pmode;
-machine_mode mode1 = Pmode;
-rtx op0 = expand_normal (arg0);
-rtx op1 = expand_normal (arg1);
-if (icode == CODE_FOR_nothing)
-/* Builtin not supported on this processor.  */
-return 0;
-/* If we got invalid arguments bail out before generating bad rtl.  */
-if (arg0 == error_mark_node || arg1 == error_mark_node)
-return const0_rtx;
-if (target == 0
-|| GET_MODE (target) != tmode
-|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
-target = gen_reg_rtx (tmode);
-op1 = copy_to_mode_reg (mode1, op1);
-if (op0 == const0_rtx)
-{
-addr = gen_rtx_MEM (tmode, op1);
-}
-else
-{
-op0 = copy_to_mode_reg (mode0, op0);
-addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
-}
-pat = GEN_FCN (icode) (target, addr);
-if (! pat)
-return 0;
-emit_insn (pat);
-return target;
-}
-/* Return a constant vector for use as a little-endian permute control vector
-to reverse the order of elements of the given vector mode.  */
-static rtx
-swap_selector_for_mode (machine_mode mode)
-{
-/* These are little endian vectors, so their elements are reversed
-from what you would normally expect for a permute control vector.  */
 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
-unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
 unsigned int *swaparray, i;
 rtx perm[16];
 switch (mode)
 {
+case E_V1TImode:
+swaparray = swap1;
+break;
 case E_V2DFmode:
 case E_V2DImode:
 swaparray = swap2;
 break;
 case E_V4SFmode:
 swaparray = swap4;
 break;
 case E_V8HImode:
 swaparray = swap8;
 break;
-case E_V16QImode:
-swaparray = swap16;
-break;
 default:
 gcc_unreachable ();
 }
 for (i = 0; i < 16; ++i)
 perm[i] = GEN_INT (swaparray[i]);
-return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
+return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
-}
+						     gen_rtvec_v (16, perm)));
-/* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
-with -maltivec=be specified.  Issue the load followed by an element-
-reversing permute.  */
-void
-altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
-{
-rtx tmp = gen_reg_rtx (mode);
-rtx load = gen_rtx_SET (tmp, op1);
-rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
-rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
-rtx sel = swap_selector_for_mode (mode);
-rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
-gcc_assert (REG_P (op0));
-emit_insn (par);
-emit_insn (gen_rtx_SET (op0, vperm));
-}
-/* Generate code for a "stvxl" built-in for a little endian target with
--maltivec=be specified.  Issue the store preceded by an element-reversing
-permute.  */
-void
-altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
-{
-rtx tmp = gen_reg_rtx (mode);
-rtx store = gen_rtx_SET (op0, tmp);
-rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
-rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
-rtx sel = swap_selector_for_mode (mode);
-rtx vperm;
-gcc_assert (REG_P (op1));
-vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
-emit_insn (gen_rtx_SET (tmp, vperm));
-emit_insn (par);
-}
-/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
-specified.  Issue the store preceded by an element-reversing permute.  */
-void
-altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
-{
-machine_mode inner_mode = GET_MODE_INNER (mode);
-rtx tmp = gen_reg_rtx (mode);
-rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
-rtx sel = swap_selector_for_mode (mode);
-rtx vperm;
-gcc_assert (REG_P (op1));
-vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
-emit_insn (gen_rtx_SET (tmp, vperm));
-emit_insn (gen_rtx_SET (op0, stvx));
 }
 static rtx
 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
 {
 op1 = copy_to_mode_reg (mode1, op1);
 /* For LVX, express the RTL accurately by ANDing the address with -16.
 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
 so the raw address is fine.  */
-if (icode == CODE_FOR_altivec_lvx_v2df_2op
+if (icode == CODE_FOR_altivec_lvx_v1ti
-|| icode == CODE_FOR_altivec_lvx_v2di_2op
+|| icode == CODE_FOR_altivec_lvx_v2df
-|| icode == CODE_FOR_altivec_lvx_v4sf_2op
+|| icode == CODE_FOR_altivec_lvx_v2di
-|| icode == CODE_FOR_altivec_lvx_v4si_2op
+|| icode == CODE_FOR_altivec_lvx_v4sf
-|| icode == CODE_FOR_altivec_lvx_v8hi_2op
+|| icode == CODE_FOR_altivec_lvx_v4si
-|| icode == CODE_FOR_altivec_lvx_v16qi_2op)
+|| icode == CODE_FOR_altivec_lvx_v8hi
+|| icode == CODE_FOR_altivec_lvx_v16qi)
 {
 rtx rawaddr;
 if (op0 == const0_rtx)
 	rawaddr = op1;
 else
 	  rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
 	}
 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
-/* For -maltivec=be, emit the load and follow it up with a
+emit_insn (gen_rtx_SET (target, addr));
-	 permute to swap the elements.  */
-if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-	{
-	  rtx temp = gen_reg_rtx (tmode);
-	  emit_insn (gen_rtx_SET (temp, addr));
-	  rtx sel = swap_selector_for_mode (tmode);
-	  rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
-				      UNSPEC_VPERM);
-	  emit_insn (gen_rtx_SET (target, vperm));
-	}
-else
-	emit_insn (gen_rtx_SET (target, addr));
 }
 else
 {
 if (op0 == const0_rtx)
 	addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
 	return 0;
 emit_insn (pat);
 }
 return target;
-}
-static rtx
-altivec_expand_xl_be_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
-{
-rtx pat, addr;
-tree arg0 = CALL_EXPR_ARG (exp, 0);
-tree arg1 = CALL_EXPR_ARG (exp, 1);
-machine_mode tmode = insn_data[icode].operand[0].mode;
-machine_mode mode0 = Pmode;
-machine_mode mode1 = Pmode;
-rtx op0 = expand_normal (arg0);
-rtx op1 = expand_normal (arg1);
-if (icode == CODE_FOR_nothing)
-/* Builtin not supported on this processor.  */
-return 0;
-/* If we got invalid arguments bail out before generating bad rtl.  */
-if (arg0 == error_mark_node || arg1 == error_mark_node)
-return const0_rtx;
-if (target == 0
-|| GET_MODE (target) != tmode
-|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
-	  target = gen_reg_rtx (tmode);
-op1 = copy_to_mode_reg (mode1, op1);
-if (op0 == const0_rtx)
-addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
-else
-{
-op0 = copy_to_mode_reg (mode0, op0);
-addr = gen_rtx_MEM (blk ? BLKmode : tmode,
-gen_rtx_PLUS (Pmode, op1, op0));
-}
-pat = GEN_FCN (icode) (target, addr);
-if (!pat)
-return 0;
-emit_insn (pat);
-/*  Reverse element order of elements if in LE mode */
-if (!VECTOR_ELT_ORDER_BIG)
-{
-rtx sel = swap_selector_for_mode (tmode);
-rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, target, target, sel),
-				  UNSPEC_VPERM);
-emit_insn (gen_rtx_SET (target, vperm));
-}
-return target;
-}
-static rtx
-paired_expand_stv_builtin (enum insn_code icode, tree exp)
-{
-tree arg0 = CALL_EXPR_ARG (exp, 0);
-tree arg1 = CALL_EXPR_ARG (exp, 1);
-tree arg2 = CALL_EXPR_ARG (exp, 2);
-rtx op0 = expand_normal (arg0);
-rtx op1 = expand_normal (arg1);
-rtx op2 = expand_normal (arg2);
-rtx pat, addr;
-machine_mode tmode = insn_data[icode].operand[0].mode;
-machine_mode mode1 = Pmode;
-machine_mode mode2 = Pmode;
-/* Invalid arguments.  Bail before doing anything stoopid!  */
-if (arg0 == error_mark_node
-|| arg1 == error_mark_node
-|| arg2 == error_mark_node)
-return const0_rtx;
-if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
-op0 = copy_to_mode_reg (tmode, op0);
-op2 = copy_to_mode_reg (mode2, op2);
-if (op1 == const0_rtx)
-{
-addr = gen_rtx_MEM (tmode, op2);
-}
-else
-{
-op1 = copy_to_mode_reg (mode1, op1);
-addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
-}
-pat = GEN_FCN (icode) (addr, op0);
-if (pat)
-emit_insn (pat);
-return NULL_RTX;
 }
 static rtx
 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
 {
 op2 = copy_to_mode_reg (mode2, op2);
 /* For STVX, express the RTL accurately by ANDing the address with -16.
 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
 so the raw address is fine.  */
-if (icode == CODE_FOR_altivec_stvx_v2df_2op
+if (icode == CODE_FOR_altivec_stvx_v2df
-|| icode == CODE_FOR_altivec_stvx_v2di_2op
+|| icode == CODE_FOR_altivec_stvx_v2di
-|| icode == CODE_FOR_altivec_stvx_v4sf_2op
+|| icode == CODE_FOR_altivec_stvx_v4sf
-|| icode == CODE_FOR_altivec_stvx_v4si_2op
+|| icode == CODE_FOR_altivec_stvx_v4si
-|| icode == CODE_FOR_altivec_stvx_v8hi_2op
+|| icode == CODE_FOR_altivec_stvx_v8hi
-|| icode == CODE_FOR_altivec_stvx_v16qi_2op)
+|| icode == CODE_FOR_altivec_stvx_v16qi)
 {
 if (op1 == const0_rtx)
 	rawaddr = op2;
 else
 	{
 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
 addr = gen_rtx_MEM (tmode, addr);
 op0 = copy_to_mode_reg (tmode, op0);
-/* For -maltivec=be, emit a permute to swap the elements, followed
+emit_insn (gen_rtx_SET (addr, op0));
-	by the store.  */
-if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
-	{
-	  rtx temp = gen_reg_rtx (tmode);
-	  rtx sel = swap_selector_for_mode (tmode);
-	  rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
-				      UNSPEC_VPERM);
-	  emit_insn (gen_rtx_SET (temp, vperm));
-	  emit_insn (gen_rtx_SET (addr, temp));
-	}
-else
-	emit_insn (gen_rtx_SET (addr, op0));
 }
 else
 {
 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
 	op0 = copy_to_mode_reg (smode, op0);
 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
 op1 = copy_to_mode_reg (mode1, op1);
 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
 op2 = copy_to_mode_reg (mode2, op2);
-if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
+pat = GEN_FCN (icode) (target, op0, op1, op2);
-pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
-else
-pat = GEN_FCN (icode) (target, op0, op1, op2);
 if (! pat)
 return 0;
 emit_insn (pat);
 return target;
 }
-/* Expand the lvx builtins.  */
-static rtx
-altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
-{
-tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
-tree arg0;
-machine_mode tmode, mode0;
-rtx pat, op0;
-enum insn_code icode;
-switch (fcode)
-{
-case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
-icode = CODE_FOR_vector_altivec_load_v16qi;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
-icode = CODE_FOR_vector_altivec_load_v8hi;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
-icode = CODE_FOR_vector_altivec_load_v4si;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
-icode = CODE_FOR_vector_altivec_load_v4sf;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
-icode = CODE_FOR_vector_altivec_load_v2df;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
-icode = CODE_FOR_vector_altivec_load_v2di;
-break;
-case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
-icode = CODE_FOR_vector_altivec_load_v1ti;
-break;
-default:
-*expandedp = false;
-return NULL_RTX;
-}
-*expandedp = true;
-arg0 = CALL_EXPR_ARG (exp, 0);
-op0 = expand_normal (arg0);
-tmode = insn_data[icode].operand[0].mode;
-mode0 = insn_data[icode].operand[1].mode;
-if (target == 0
-|| GET_MODE (target) != tmode
-|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
-target = gen_reg_rtx (tmode);
-if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
-op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
-pat = GEN_FCN (icode) (target, op0);
-if (! pat)
-return 0;
-emit_insn (pat);
-return target;
-}
-/* Expand the stvx builtins.  */
-static rtx
-altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
-			   bool *expandedp)
-{
-tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
-tree arg0, arg1;
-machine_mode mode0, mode1;
-rtx pat, op0, op1;
-enum insn_code icode;
-switch (fcode)
-{
-case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
-icode = CODE_FOR_vector_altivec_store_v16qi;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
-icode = CODE_FOR_vector_altivec_store_v8hi;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
-icode = CODE_FOR_vector_altivec_store_v4si;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
-icode = CODE_FOR_vector_altivec_store_v4sf;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
-icode = CODE_FOR_vector_altivec_store_v2df;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
-icode = CODE_FOR_vector_altivec_store_v2di;
-break;
-case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
-icode = CODE_FOR_vector_altivec_store_v1ti;
-break;
-default:
-*expandedp = false;
-return NULL_RTX;
-}
-arg0 = CALL_EXPR_ARG (exp, 0);
-arg1 = CALL_EXPR_ARG (exp, 1);
-op0 = expand_normal (arg0);
-op1 = expand_normal (arg1);
-mode0 = insn_data[icode].operand[0].mode;
-mode1 = insn_data[icode].operand[1].mode;
-if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
-op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
-if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
-op1 = copy_to_mode_reg (mode1, op1);
-pat = GEN_FCN (icode) (op0, op1);
-if (pat)
-emit_insn (pat);
-*expandedp = true;
-return NULL_RTX;
-}
 /* Expand the dst builtins.  */
 static rtx
 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
 			    bool *expandedp)
 /* Given it is invalid, just generate a normal call.  */
 return expand_call (exp, target, false);
 }
-target = altivec_expand_ld_builtin (exp, target, expandedp);
-if (*expandedp)
-return target;
-target = altivec_expand_st_builtin (exp, target, expandedp);
-if (*expandedp)
-return target;
 target = altivec_expand_dst_builtin (exp, target, expandedp);
 if (*expandedp)
 return target;
 *expandedp = true;
 switch (fcode)
 {
 case ALTIVEC_BUILTIN_STVX_V2DF:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
 case ALTIVEC_BUILTIN_STVX_V2DI:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
 case ALTIVEC_BUILTIN_STVX_V4SF:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
 case ALTIVEC_BUILTIN_STVX:
 case ALTIVEC_BUILTIN_STVX_V4SI:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
 case ALTIVEC_BUILTIN_STVX_V8HI:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
 case ALTIVEC_BUILTIN_STVX_V16QI:
-return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
+return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
 case ALTIVEC_BUILTIN_STVEBX:
 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
 case ALTIVEC_BUILTIN_STVEHX:
 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
 case ALTIVEC_BUILTIN_STVEWX:
 /* For the following on big endian, it's ok to use any appropriate
 unaligned-supporting store, so use a generic expander.  For
 little-endian, the exact element-reversing instruction must
 be used.  */
+case VSX_BUILTIN_ST_ELEMREV_V1TI:
+{
+enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
+			       : CODE_FOR_vsx_st_elemrev_v1ti);
+return altivec_expand_stv_builtin (code, exp);
+}
 case VSX_BUILTIN_ST_ELEMREV_V2DF:
 {
 	enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
 			       : CODE_FOR_vsx_st_elemrev_v2df);
 	return altivec_expand_stv_builtin (code, exp);
 case VSX_BUILTIN_VEC_EXT_V2DF:
 case VSX_BUILTIN_VEC_EXT_V2DI:
 case VSX_BUILTIN_VEC_EXT_V1TI:
 return altivec_expand_vec_ext_builtin (exp, target);
-case P9V_BUILTIN_VEXTRACT4B:
+case P9V_BUILTIN_VEC_EXTRACT4B:
-case P9V_BUILTIN_VEC_VEXTRACT4B:
 arg1 = CALL_EXPR_ARG (exp, 1);
 STRIP_NOPS (arg1);
 /* Generate a normal call if it is invalid.  */
 if (arg1 == error_mark_node)
 	  error ("second argument to %qs must be 0..12", "vec_vextract4b");
 	  return expand_call (exp, target, false);
 	}
 break;
-case P9V_BUILTIN_VINSERT4B:
+case P9V_BUILTIN_VEC_INSERT4B:
-case P9V_BUILTIN_VINSERT4B_DI:
-case P9V_BUILTIN_VEC_VINSERT4B:
 arg2 = CALL_EXPR_ARG (exp, 2);
 STRIP_NOPS (arg2);
 /* Generate a normal call if it is invalid.  */
 if (arg2 == error_mark_node)
 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVXL_V16QI:
 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
 					exp, target, false);
+case ALTIVEC_BUILTIN_LVX_V1TI:
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
+					exp, target, false);
 case ALTIVEC_BUILTIN_LVX_V2DF:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVX_V2DI:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVX_V4SF:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVX:
 case ALTIVEC_BUILTIN_LVX_V4SI:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVX_V8HI:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVX_V16QI:
-return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
+return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
 					exp, target, false);
 case ALTIVEC_BUILTIN_LVLX:
 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
 					exp, target, true);
 case ALTIVEC_BUILTIN_LVLXL:
 {
 	enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
 			       : CODE_FOR_vsx_ld_elemrev_v2df);
 	return altivec_expand_lv_builtin (code, exp, target, false);
 }
+case VSX_BUILTIN_LD_ELEMREV_V1TI:
+{
+	enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
+			       : CODE_FOR_vsx_ld_elemrev_v1ti);
+	return altivec_expand_lv_builtin (code, exp, target, false);
+}
 case VSX_BUILTIN_LD_ELEMREV_V2DI:
 {
 	enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
 			       : CODE_FOR_vsx_ld_elemrev_v2di);
 	return altivec_expand_lv_builtin (code, exp, target, false);
 default:
 break;
 /* Fall through.  */
 }
-/* XL_BE  We initialized them to always load in big endian order.  */
-switch (fcode)
-{
-case VSX_BUILTIN_XL_BE_V2DI:
-{
-enum insn_code code = CODE_FOR_vsx_load_v2di;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-case VSX_BUILTIN_XL_BE_V4SI:
-{
-enum insn_code code = CODE_FOR_vsx_load_v4si;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-case VSX_BUILTIN_XL_BE_V8HI:
-{
-enum insn_code code = CODE_FOR_vsx_load_v8hi;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-case VSX_BUILTIN_XL_BE_V16QI:
-{
-enum insn_code code = CODE_FOR_vsx_load_v16qi;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-case VSX_BUILTIN_XL_BE_V2DF:
-{
-enum insn_code code = CODE_FOR_vsx_load_v2df;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-case VSX_BUILTIN_XL_BE_V4SF:
-{
-enum insn_code code = CODE_FOR_vsx_load_v4sf;
-return altivec_expand_xl_be_builtin (code, exp, target, false);
-}
-break;
-default:
-break;
-/* Fall through.  */
-}
 *expandedp = false;
 return NULL_RTX;
 }
-/* Expand the builtin in EXP and store the result in TARGET.  Store
+/* Check whether a builtin function is supported in this target
-true in *EXPANDEDP if we found a builtin to expand.  */
+configuration.  */
-static rtx
+bool
-paired_expand_builtin (tree exp, rtx target, bool * expandedp)
+rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
 {
-tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
-enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
+if ((fnmask & rs6000_builtin_mask) != fnmask)
-const struct builtin_description *d;
+return false;
-size_t i;
-*expandedp = true;
-switch (fcode)
-{
-case PAIRED_BUILTIN_STX:
-return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
-case PAIRED_BUILTIN_LX:
-return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
-default:
-break;
-/* Fall through.  */
-}
-/* Expand the paired predicates.  */
-d = bdesc_paired_preds;
-for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
-if (d->code == fcode)
-return paired_expand_predicate_builtin (d->icode, exp, target);
-*expandedp = false;
-return NULL_RTX;
-}
-static rtx
-paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
-{
-rtx pat, scratch, tmp;
-tree form = CALL_EXPR_ARG (exp, 0);
-tree arg0 = CALL_EXPR_ARG (exp, 1);
-tree arg1 = CALL_EXPR_ARG (exp, 2);
-rtx op0 = expand_normal (arg0);
-rtx op1 = expand_normal (arg1);
-machine_mode mode0 = insn_data[icode].operand[1].mode;
-machine_mode mode1 = insn_data[icode].operand[2].mode;
-int form_int;
-enum rtx_code code;
-if (TREE_CODE (form) != INTEGER_CST)
-{
-error ("argument 1 of %s must be a constant",
-	     "__builtin_paired_predicate");
-return const0_rtx;
-}
 else
-form_int = TREE_INT_CST_LOW (form);
+return true;
-gcc_assert (mode0 == mode1);
-if (arg0 == error_mark_node || arg1 == error_mark_node)
-return const0_rtx;
-if (target == 0
-|| GET_MODE (target) != SImode
-|| !(*insn_data[icode].operand[0].predicate) (target, SImode))
-target = gen_reg_rtx (SImode);
-if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
-op0 = copy_to_mode_reg (mode0, op0);
-if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
-op1 = copy_to_mode_reg (mode1, op1);
-scratch = gen_reg_rtx (CCFPmode);
-pat = GEN_FCN (icode) (scratch, op0, op1);
-if (!pat)
-return const0_rtx;
-emit_insn (pat);
-switch (form_int)
-{
-/* LT bit.  */
-case 0:
-code = LT;
-break;
-/* GT bit.  */
-case 1:
-code = GT;
-break;
-/* EQ bit.  */
-case 2:
-code = EQ;
-break;
-/* UN bit.  */
-case 3:
-emit_insn (gen_move_from_CR_ov_bit (target, scratch));
-return target;
-default:
-error ("argument 1 of %qs is out of range",
-	     "__builtin_paired_predicate");
-return const0_rtx;
-}
-tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
-emit_move_insn (target, tmp);
-return target;
 }
 /* Raise an error message for a builtin function that is called without the
 appropriate target options being set.  */
 error ("builtin function %qs requires the %qs option", name, "-mvsx");
 else if ((fnmask & RS6000_BTM_HTM) != 0)
 error ("builtin function %qs requires the %qs option", name, "-mhtm");
 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
 error ("builtin function %qs requires the %qs option", name, "-maltivec");
-else if ((fnmask & RS6000_BTM_PAIRED) != 0)
-error ("builtin function %qs requires the %qs option", name, "-mpaired");
 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
 	   == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
 error ("builtin function %qs requires the %qs and %qs options",
 	   name, "-mhard-dfp", "-mpower8-vector");
 else if ((fnmask & RS6000_BTM_DFP) != 0)
 error ("builtin function %qs requires the %qs and %qs options",
 	   name, "-mcpu=power9", "-m64");
 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
 error ("builtin function %qs requires the %qs option", name,
 	   "-mcpu=power9");
-else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
-	   == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+{
-error ("builtin function %qs requires the %qs and %qs options",
+if (!TARGET_HARD_FLOAT)
-	   name, "-mhard-float", "-mlong-double-128");
+	error ("builtin function %qs requires the %qs option", name,
+	       "-mhard-float");
+else
+	error ("builtin function %qs requires the %qs option", name,
+	       TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
+}
 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
 error ("builtin function %qs requires the %qs option", name,
 	   "-mhard-float");
 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
 	   name);
 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
+else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
+	   == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
+error ("builtin function %qs requires the %qs (or newer), and "
+	   "%qs or %qs options",
+	   name, "-mcpu=power7", "-m64", "-mpowerpc64");
 else
 error ("builtin function %qs is not supported with the current options",
 	   name);
 }
 /* Target hook for early folding of built-ins, shamelessly stolen
 from ia64.c.  */
 static tree
-rs6000_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
+rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
-		     tree *args, bool ignore ATTRIBUTE_UNUSED)
+		     int n_args ATTRIBUTE_UNUSED,
-{
+		     tree *args ATTRIBUTE_UNUSED,
-if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
+		     bool ignore ATTRIBUTE_UNUSED)
 {
-enum rs6000_builtins fn_code
-	= (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
-switch (fn_code)
-	{
-	case RS6000_BUILTIN_NANQ:
-	case RS6000_BUILTIN_NANSQ:
-	  {
-	    tree type = TREE_TYPE (TREE_TYPE (fndecl));
-	    const char *str = c_getstr (*args);
-	    int quiet = fn_code == RS6000_BUILTIN_NANQ;
-	    REAL_VALUE_TYPE real;
-	    if (str && real_nan (&real, str, quiet, TYPE_MODE (type)))
-	      return build_real (type, real);
-	    return NULL_TREE;
-	  }
-	case RS6000_BUILTIN_INFQ:
-	case RS6000_BUILTIN_HUGE_VALQ:
-	  {
-	    tree type = TREE_TYPE (TREE_TYPE (fndecl));
-	    REAL_VALUE_TYPE inf;
-	    real_inf (&inf);
-	    return build_real (type, inf);
-	  }
-	default:
-	  break;
-	}
-}
 #ifdef SUBTARGET_FOLD_BUILTIN
 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
 #else
 return NULL_TREE;
 #endif
 case ALTIVEC_BUILTIN_STVX_V8HI:
 case ALTIVEC_BUILTIN_STVX_V4SI:
 case ALTIVEC_BUILTIN_STVX_V4SF:
 case ALTIVEC_BUILTIN_STVX_V2DI:
 case ALTIVEC_BUILTIN_STVX_V2DF:
+case VSX_BUILTIN_STXVW4X_V16QI:
+case VSX_BUILTIN_STXVW4X_V8HI:
+case VSX_BUILTIN_STXVW4X_V4SF:
+case VSX_BUILTIN_STXVW4X_V4SI:
+case VSX_BUILTIN_STXVD2X_V2DF:
+case VSX_BUILTIN_STXVD2X_V2DI:
 return true;
 default:
 return false;
 }
+}
+/* Helper function to handle the gimple folding of a vector compare
+operation.  This sets up true/false vectors, and uses the
+VEC_COND_EXPR operation.
+CODE indicates which comparison is to be made. (EQ, GT, ...).
+TYPE indicates the type of the result.  */
+static tree
+fold_build_vec_cmp (tree_code code, tree type,
+		    tree arg0, tree arg1)
+{
+tree cmp_type = build_same_sized_truth_vector_type (type);
+tree zero_vec = build_zero_cst (type);
+tree minus_one_vec = build_minus_one_cst (type);
+tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
+return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
+}
+/* Helper function to handle the in-between steps for the
+vector compare built-ins.  */
+static void
+fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
+{
+tree arg0 = gimple_call_arg (stmt, 0);
+tree arg1 = gimple_call_arg (stmt, 1);
+tree lhs = gimple_call_lhs (stmt);
+tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
+gimple *g = gimple_build_assign (lhs, cmp);
+gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
+}
+/* Helper function to map V2DF and V4SF types to their
+integral equivalents (V2DI and V4SI).  */
+tree map_to_integral_tree_type (tree input_tree_type)
+{
+if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
+return input_tree_type;
+else
+{
+if (types_compatible_p (TREE_TYPE (input_tree_type),
+			      TREE_TYPE (V2DF_type_node)))
+	return V2DI_type_node;
+else if (types_compatible_p (TREE_TYPE (input_tree_type),
+				   TREE_TYPE (V4SF_type_node)))
+	return V4SI_type_node;
+else
+	gcc_unreachable ();
+}
+}
+/* Helper function to handle the vector merge[hl] built-ins.  The
+implementation difference between h and l versions for this code are in
+the values used when building of the permute vector for high word versus
+low word merge.  The variance is keyed off the use_high parameter.  */
+static void
+fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
+{
+tree arg0 = gimple_call_arg (stmt, 0);
+tree arg1 = gimple_call_arg (stmt, 1);
+tree lhs = gimple_call_lhs (stmt);
+tree lhs_type = TREE_TYPE (lhs);
+int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
+int midpoint = n_elts / 2;
+int offset = 0;
+if (use_high == 1)
+offset = midpoint;
+/* The permute_type will match the lhs for integral types.  For double and
+float types, the permute type needs to map to the V2 or V4 type that
+matches size.  */
+tree permute_type;
+permute_type = map_to_integral_tree_type (lhs_type);
+tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
+for (int i = 0; i < midpoint; i++)
+{
+elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
+				     offset + i));
+elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
+				     offset + n_elts + i));
+}
+tree permute = elts.build ();
+gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
+gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
+}
+/* Helper function to handle the vector merge[eo] built-ins.  */
+static void
+fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
+{
+tree arg0 = gimple_call_arg (stmt, 0);
+tree arg1 = gimple_call_arg (stmt, 1);
+tree lhs = gimple_call_lhs (stmt);
+tree lhs_type = TREE_TYPE (lhs);
+int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
+/* The permute_type will match the lhs for integral types.  For double and
+float types, the permute type needs to map to the V2 or V4 type that
+matches size.  */
+tree permute_type;
+permute_type = map_to_integral_tree_type (lhs_type);
+tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
+/* Build the permute vector.  */
+for (int i = 0; i < n_elts / 2; i++)
+{
+elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
+				     2*i + use_odd));
+elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
+				     2*i + use_odd + n_elts));
+}
+tree permute = elts.build ();
+gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
+gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
 }
 /* Fold a machine-dependent built-in in GIMPLE.  (For folding into
 a constant, use rs6000_fold_builtin.)  */
 gimple *stmt = gsi_stmt (*gsi);
 tree fndecl = gimple_call_fndecl (stmt);
 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
 enum rs6000_builtins fn_code
 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
-tree arg0, arg1, lhs;
+tree arg0, arg1, lhs, temp;
+gimple *g;
 size_t uns_fncode = (size_t) fn_code;
 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
 const char *fn_name2 = (icode != CODE_FOR_nothing)
 if (!rs6000_fold_gimple)
 return false;
 /* Prevent gimple folding for code that does not have a LHS, unless it is
 allowed per the rs6000_builtin_valid_without_lhs helper function.  */
 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
+return false;
+/* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it.  */
+HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
+bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
+if (!func_valid_p)
 return false;
 switch (fn_code)
 {
 /* Flavors of vec_add.  We deliberately don't expand
 case ALTIVEC_BUILTIN_VADDUHM:
 case ALTIVEC_BUILTIN_VADDUWM:
 case P8V_BUILTIN_VADDUDM:
 case ALTIVEC_BUILTIN_VADDFP:
 case VSX_BUILTIN_XVADDDP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_sub.  We deliberately don't expand
 P8V_BUILTIN_VSUBUQM. */
 case ALTIVEC_BUILTIN_VSUBUBM:
 case ALTIVEC_BUILTIN_VSUBUHM:
 case ALTIVEC_BUILTIN_VSUBUWM:
 case P8V_BUILTIN_VSUBUDM:
 case ALTIVEC_BUILTIN_VSUBFP:
 case VSX_BUILTIN_XVSUBDP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 case VSX_BUILTIN_XVMULSP:
 case VSX_BUILTIN_XVMULDP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Even element flavors of vec_mul (signed). */
 case ALTIVEC_BUILTIN_VMULESB:
 case ALTIVEC_BUILTIN_VMULESH:
-case ALTIVEC_BUILTIN_VMULESW:
+case P8V_BUILTIN_VMULESW:
 /* Even element flavors of vec_mul (unsigned).  */
 case ALTIVEC_BUILTIN_VMULEUB:
 case ALTIVEC_BUILTIN_VMULEUH:
-case ALTIVEC_BUILTIN_VMULEUW:
+case P8V_BUILTIN_VMULEUW:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Odd element flavors of vec_mul (signed).  */
 case ALTIVEC_BUILTIN_VMULOSB:
 case ALTIVEC_BUILTIN_VMULOSH:
-case ALTIVEC_BUILTIN_VMULOSW:
+case P8V_BUILTIN_VMULOSW:
 /* Odd element flavors of vec_mul (unsigned). */
 case ALTIVEC_BUILTIN_VMULOUB:
 case ALTIVEC_BUILTIN_VMULOUH:
-case ALTIVEC_BUILTIN_VMULOUW:
+case P8V_BUILTIN_VMULOUW:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_div (Integer).  */
 case VSX_BUILTIN_DIV_V2DI:
 case VSX_BUILTIN_UDIV_V2DI:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_div (Float).  */
 case VSX_BUILTIN_XVDIVSP:
 case VSX_BUILTIN_XVDIVDP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_and.  */
 case ALTIVEC_BUILTIN_VAND:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_andc.  */
 case ALTIVEC_BUILTIN_VANDC:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
-	tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
+g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
-	gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_insert_before (gsi, g, GSI_SAME_STMT);
-	gsi_insert_before(gsi, g, GSI_SAME_STMT);
+g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
-	g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_nand.  */
 case P8V_BUILTIN_VEC_NAND:
 case P8V_BUILTIN_NAND_V16QI:
 case P8V_BUILTIN_NAND_V8HI:
 case P8V_BUILTIN_NAND_V4SI:
 case P8V_BUILTIN_NAND_V4SF:
 case P8V_BUILTIN_NAND_V2DF:
 case P8V_BUILTIN_NAND_V2DI:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
-	tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
+g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign(temp, BIT_AND_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_insert_before (gsi, g, GSI_SAME_STMT);
-	gsi_insert_before(gsi, g, GSI_SAME_STMT);
+g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
-	g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_or.  */
 case ALTIVEC_BUILTIN_VOR:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* flavors of vec_orc.  */
 case P8V_BUILTIN_ORC_V16QI:
 case P8V_BUILTIN_ORC_V8HI:
 case P8V_BUILTIN_ORC_V4SI:
 case P8V_BUILTIN_ORC_V4SF:
 case P8V_BUILTIN_ORC_V2DF:
 case P8V_BUILTIN_ORC_V2DI:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
-	tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
+g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
-	gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_insert_before (gsi, g, GSI_SAME_STMT);
-	gsi_insert_before(gsi, g, GSI_SAME_STMT);
+g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
-	g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_xor.  */
 case ALTIVEC_BUILTIN_VXOR:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_nor.  */
 case ALTIVEC_BUILTIN_VNOR:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
-	tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
+g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_insert_before (gsi, g, GSI_SAME_STMT);
-	gsi_insert_before(gsi, g, GSI_SAME_STMT);
+g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
-	g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* flavors of vec_abs.  */
 case ALTIVEC_BUILTIN_ABS_V16QI:
 case ALTIVEC_BUILTIN_ABS_V8HI:
 case ALTIVEC_BUILTIN_ABS_V4SI:
 case ALTIVEC_BUILTIN_ABS_V4SF:
 case P8V_BUILTIN_ABS_V2DI:
 case VSX_BUILTIN_XVABSDP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
-	if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
+	  && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
-	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
+	return false;
-	      return false;
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, ABS_EXPR, arg0);
-	gimple *g = gimple_build_assign (lhs, ABS_EXPR, arg0);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* flavors of vec_min.  */
 case VSX_BUILTIN_XVMINDP:
 case P8V_BUILTIN_VMINSD:
 case P8V_BUILTIN_VMINUD:
 case ALTIVEC_BUILTIN_VMINSB:
 case ALTIVEC_BUILTIN_VMINSW:
 case ALTIVEC_BUILTIN_VMINUB:
 case ALTIVEC_BUILTIN_VMINUH:
 case ALTIVEC_BUILTIN_VMINUW:
 case ALTIVEC_BUILTIN_VMINFP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* flavors of vec_max.  */
 case VSX_BUILTIN_XVMAXDP:
 case P8V_BUILTIN_VMAXSD:
 case P8V_BUILTIN_VMAXUD:
 case ALTIVEC_BUILTIN_VMAXSB:
 case ALTIVEC_BUILTIN_VMAXSW:
 case ALTIVEC_BUILTIN_VMAXUB:
 case ALTIVEC_BUILTIN_VMAXUH:
 case ALTIVEC_BUILTIN_VMAXUW:
 case ALTIVEC_BUILTIN_VMAXFP:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_eqv.  */
 case P8V_BUILTIN_EQV_V16QI:
 case P8V_BUILTIN_EQV_V8HI:
 case P8V_BUILTIN_EQV_V4SI:
 case P8V_BUILTIN_EQV_V4SF:
 case P8V_BUILTIN_EQV_V2DF:
 case P8V_BUILTIN_EQV_V2DI:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
-	tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
+g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_insert_before (gsi, g, GSI_SAME_STMT);
-	gsi_insert_before (gsi, g, GSI_SAME_STMT);
+g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
-	g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vec_rotate_left.  */
 case ALTIVEC_BUILTIN_VRLB:
 case ALTIVEC_BUILTIN_VRLH:
 case ALTIVEC_BUILTIN_VRLW:
 case P8V_BUILTIN_VRLD:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vector shift right algebraic.
 vec_sra{b,h,w} -> vsra{b,h,w}.  */
 case ALTIVEC_BUILTIN_VSRAB:
 case ALTIVEC_BUILTIN_VSRAH:
 case ALTIVEC_BUILTIN_VSRAW:
 case P8V_BUILTIN_VSRAD:
-{
+arg0 = gimple_call_arg (stmt, 0);
-	arg0 = gimple_call_arg (stmt, 0);
+arg1 = gimple_call_arg (stmt, 1);
-	arg1 = gimple_call_arg (stmt, 1);
+lhs = gimple_call_lhs (stmt);
-	lhs = gimple_call_lhs (stmt);
+g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
-	gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
+gimple_set_location (g, gimple_location (stmt));
-	gimple_set_location (g, gimple_location (stmt));
+gsi_replace (gsi, g, true);
-	gsi_replace (gsi, g, true);
+return true;
-	return true;
-}
 /* Flavors of vector shift left.
 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}.  */
 case ALTIVEC_BUILTIN_VSLB:
 case ALTIVEC_BUILTIN_VSLH:
 case ALTIVEC_BUILTIN_VSLW:
 case P8V_BUILTIN_VSLD:
 {
+	location_t loc;
+	gimple_seq stmts = NULL;
 	arg0 = gimple_call_arg (stmt, 0);
-	if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
+	tree arg0_type = TREE_TYPE (arg0);
-	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
+	if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
-	      return false;
+	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
+	  return false;
 	arg1 = gimple_call_arg (stmt, 1);
+	tree arg1_type = TREE_TYPE (arg1);
+	tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
+	tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
+	loc = gimple_location (stmt);
 	lhs = gimple_call_lhs (stmt);
-	gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
+	/* Force arg1 into the range valid matching the arg0 type.  */
+	/* Build a vector consisting of the max valid bit-size values.  */
+	int n_elts = VECTOR_CST_NELTS (arg1);
+	int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
+				* BITS_PER_UNIT;
+	tree element_size = build_int_cst (unsigned_element_type,
+					   tree_size_in_bits / n_elts);
+	tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
+	for (int i = 0; i < n_elts; i++)
+	  elts.safe_push (element_size);
+	tree modulo_tree = elts.build ();
+	/* Modulo the provided shift value against that vector.  */
+	tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
+					   unsigned_arg1_type, arg1);
+	tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
+				      unsigned_arg1_type, unsigned_arg1,
+				      modulo_tree);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	/* And finally, do the shift.  */
+	g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
 	gimple_set_location (g, gimple_location (stmt));
 	gsi_replace (gsi, g, true);
 	return true;
 }
 /* Flavors of vector shift right.  */
 	arg1 = gimple_call_arg (stmt, 1);
 	lhs = gimple_call_lhs (stmt);
 	gimple_seq stmts = NULL;
 	/* Convert arg0 to unsigned.  */
 	tree arg0_unsigned
-	   = gimple_build (&stmts, VIEW_CONVERT_EXPR,
+	  = gimple_build (&stmts, VIEW_CONVERT_EXPR,
-			   unsigned_type_for (TREE_TYPE (arg0)), arg0);
+			  unsigned_type_for (TREE_TYPE (arg0)), arg0);
 	tree res
-	   = gimple_build (&stmts, RSHIFT_EXPR,
+	  = gimple_build (&stmts, RSHIFT_EXPR,
-			   TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
+			  TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
 	/* Convert result back to the lhs type.  */
 	res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
 	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
 	update_call_from_tree (gsi, res);
 	return true;
 case ALTIVEC_BUILTIN_LVX_V8HI:
 case ALTIVEC_BUILTIN_LVX_V4SI:
 case ALTIVEC_BUILTIN_LVX_V4SF:
 case ALTIVEC_BUILTIN_LVX_V2DI:
 case ALTIVEC_BUILTIN_LVX_V2DF:
+case ALTIVEC_BUILTIN_LVX_V1TI:
 {
-	 arg0 = gimple_call_arg (stmt, 0);  // offset
+	arg0 = gimple_call_arg (stmt, 0);  // offset
-	 arg1 = gimple_call_arg (stmt, 1);  // address
+	arg1 = gimple_call_arg (stmt, 1);  // address
-	 /* Do not fold for -maltivec=be on LE targets.  */
+	lhs = gimple_call_lhs (stmt);
-	 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
+	location_t loc = gimple_location (stmt);
-	    return false;
+	/* Since arg1 may be cast to a different type, just use ptr_type_node
-	 lhs = gimple_call_lhs (stmt);
+	   here instead of trying to enforce TBAA on pointer types.  */
-	 location_t loc = gimple_location (stmt);
+	tree arg1_type = ptr_type_node;
-	 /* Since arg1 may be cast to a different type, just use ptr_type_node
+	tree lhs_type = TREE_TYPE (lhs);
-	    here instead of trying to enforce TBAA on pointer types.  */
+	/* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
-	 tree arg1_type = ptr_type_node;
+	   the tree using the value from arg0.  The resulting type will match
-	 tree lhs_type = TREE_TYPE (lhs);
+	   the type of arg1.  */
-	 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
+	gimple_seq stmts = NULL;
-	    the tree using the value from arg0.  The resulting type will match
+	tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
-	    the type of arg1.  */
+	tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
-	 gimple_seq stmts = NULL;
-	 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
-	 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
 				       arg1_type, arg1, temp_offset);
-	 /* Mask off any lower bits from the address.  */
+	/* Mask off any lower bits from the address.  */
-	 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
+	tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
 					  arg1_type, temp_addr,
 					  build_int_cst (arg1_type, -16));
-	 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
-	 /* Use the build2 helper to set up the mem_ref.  The MEM_REF could also
+	/* Use the build2 helper to set up the mem_ref.  The MEM_REF could also
-	    take an offset, but since we've already incorporated the offset
+	   take an offset, but since we've already incorporated the offset
-	    above, here we just pass in a zero.  */
+	   above, here we just pass in a zero.  */
-	 gimple *g;
+	gimple *g
-	 g = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
+	  = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
-						build_int_cst (arg1_type, 0)));
+					      build_int_cst (arg1_type, 0)));
-	 gimple_set_location (g, loc);
+	gimple_set_location (g, loc);
-	 gsi_replace (gsi, g, true);
+	gsi_replace (gsi, g, true);
-	 return true;
+	return true;
 }
 /* Vector stores.  */
 case ALTIVEC_BUILTIN_STVX_V16QI:
 case ALTIVEC_BUILTIN_STVX_V8HI:
 case ALTIVEC_BUILTIN_STVX_V4SI:
 case ALTIVEC_BUILTIN_STVX_V4SF:
 case ALTIVEC_BUILTIN_STVX_V2DI:
 case ALTIVEC_BUILTIN_STVX_V2DF:
 {
-	 /* Do not fold for -maltivec=be on LE targets.  */
+	arg0 = gimple_call_arg (stmt, 0); /* Value to be stored.  */
-	 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
+	arg1 = gimple_call_arg (stmt, 1); /* Offset.  */
-	    return false;
+	tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address.  */
-	 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored.  */
+	location_t loc = gimple_location (stmt);
-	 arg1 = gimple_call_arg (stmt, 1); /* Offset.  */
+	tree arg0_type = TREE_TYPE (arg0);
-	 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address.  */
+	/* Use ptr_type_node (no TBAA) for the arg2_type.
-	 location_t loc = gimple_location (stmt);
+	   FIXME: (Richard)  "A proper fix would be to transition this type as
-	 tree arg0_type = TREE_TYPE (arg0);
+	   seen from the frontend to GIMPLE, for example in a similar way we
-	 /* Use ptr_type_node (no TBAA) for the arg2_type.
+	   do for MEM_REFs by piggy-backing that on an extra argument, a
-	  FIXME: (Richard)  "A proper fix would be to transition this type as
+	   constant zero pointer of the alias pointer type to use (which would
-	  seen from the frontend to GIMPLE, for example in a similar way we
+	   also serve as a type indicator of the store itself).  I'd use a
-	  do for MEM_REFs by piggy-backing that on an extra argument, a
+	   target specific internal function for this (not sure if we can have
-	  constant zero pointer of the alias pointer type to use (which would
+	   those target specific, but I guess if it's folded away then that's
-	  also serve as a type indicator of the store itself).  I'd use a
+	   fine) and get away with the overload set."  */
-	  target specific internal function for this (not sure if we can have
+	tree arg2_type = ptr_type_node;
-	  those target specific, but I guess if it's folded away then that's
+	/* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
-	  fine) and get away with the overload set."
+	   the tree using the value from arg0.  The resulting type will match
-	  */
+	   the type of arg2.  */
-	 tree arg2_type = ptr_type_node;
+	gimple_seq stmts = NULL;
-	 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
+	tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
-	    the tree using the value from arg0.  The resulting type will match
+	tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
-	    the type of arg2.  */
-	 gimple_seq stmts = NULL;
-	 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
-	 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
 				       arg2_type, arg2, temp_offset);
-	 /* Mask off any lower bits from the address.  */
+	/* Mask off any lower bits from the address.  */
-	 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
+	tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
 					  arg2_type, temp_addr,
 					  build_int_cst (arg2_type, -16));
-	 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
 	/* The desired gimple result should be similar to:
-	 MEM[(__vector floatD.1407 *)_1] = vf1D.2697;  */
+	   MEM[(__vector floatD.1407 *)_1] = vf1D.2697;  */
-	 gimple *g;
+	gimple *g
-	 g = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
+	  = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
-					   build_int_cst (arg2_type, 0)), arg0);
+					 build_int_cst (arg2_type, 0)), arg0);
-	 gimple_set_location (g, loc);
+	gimple_set_location (g, loc);
-	 gsi_replace (gsi, g, true);
+	gsi_replace (gsi, g, true);
-	 return true;
+	return true;
 }
+/* unaligned Vector loads.  */
+case VSX_BUILTIN_LXVW4X_V16QI:
+case VSX_BUILTIN_LXVW4X_V8HI:
+case VSX_BUILTIN_LXVW4X_V4SF:
+case VSX_BUILTIN_LXVW4X_V4SI:
+case VSX_BUILTIN_LXVD2X_V2DF:
+case VSX_BUILTIN_LXVD2X_V2DI:
+{
+	arg0 = gimple_call_arg (stmt, 0);  // offset
+	arg1 = gimple_call_arg (stmt, 1);  // address
+	lhs = gimple_call_lhs (stmt);
+	location_t loc = gimple_location (stmt);
+	/* Since arg1 may be cast to a different type, just use ptr_type_node
+	   here instead of trying to enforce TBAA on pointer types.  */
+	tree arg1_type = ptr_type_node;
+	tree lhs_type = TREE_TYPE (lhs);
+	/* In GIMPLE the type of the MEM_REF specifies the alignment.  The
+	  required alignment (power) is 4 bytes regardless of data type.  */
+	tree align_ltype = build_aligned_type (lhs_type, 4);
+	/* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
+	   the tree using the value from arg0.  The resulting type will match
+	   the type of arg1.  */
+	gimple_seq stmts = NULL;
+	tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
+	tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
+				       arg1_type, arg1, temp_offset);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	/* Use the build2 helper to set up the mem_ref.  The MEM_REF could also
+	   take an offset, but since we've already incorporated the offset
+	   above, here we just pass in a zero.  */
+	gimple *g;
+	g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
+					      build_int_cst (arg1_type, 0)));
+	gimple_set_location (g, loc);
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* unaligned Vector stores.  */
+case VSX_BUILTIN_STXVW4X_V16QI:
+case VSX_BUILTIN_STXVW4X_V8HI:
+case VSX_BUILTIN_STXVW4X_V4SF:
+case VSX_BUILTIN_STXVW4X_V4SI:
+case VSX_BUILTIN_STXVD2X_V2DF:
+case VSX_BUILTIN_STXVD2X_V2DI:
+{
+	arg0 = gimple_call_arg (stmt, 0); /* Value to be stored.  */
+	arg1 = gimple_call_arg (stmt, 1); /* Offset.  */
+	tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address.  */
+	location_t loc = gimple_location (stmt);
+	tree arg0_type = TREE_TYPE (arg0);
+	/* Use ptr_type_node (no TBAA) for the arg2_type.  */
+	tree arg2_type = ptr_type_node;
+	/* In GIMPLE the type of the MEM_REF specifies the alignment.  The
+	   required alignment (power) is 4 bytes regardless of data type.  */
+	tree align_stype = build_aligned_type (arg0_type, 4);
+	/* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'.  Create
+	   the tree using the value from arg1.  */
+	gimple_seq stmts = NULL;
+	tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
+	tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
+				       arg2_type, arg2, temp_offset);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	gimple *g;
+	g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
+					 build_int_cst (arg2_type, 0)), arg0);
+	gimple_set_location (g, loc);
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* Vector Fused multiply-add (fma).  */
+case ALTIVEC_BUILTIN_VMADDFP:
+case VSX_BUILTIN_XVMADDDP:
+case ALTIVEC_BUILTIN_VMLADDUHM:
+{
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	tree arg2 = gimple_call_arg (stmt, 2);
+	lhs = gimple_call_lhs (stmt);
+	gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
+	gimple_call_set_lhs (g, lhs);
+	gimple_call_set_nothrow (g, true);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* Vector compares; EQ, NE, GE, GT, LE.  */
+case ALTIVEC_BUILTIN_VCMPEQUB:
+case ALTIVEC_BUILTIN_VCMPEQUH:
+case ALTIVEC_BUILTIN_VCMPEQUW:
+case P8V_BUILTIN_VCMPEQUD:
+fold_compare_helper (gsi, EQ_EXPR, stmt);
+return true;
+case P9V_BUILTIN_CMPNEB:
+case P9V_BUILTIN_CMPNEH:
+case P9V_BUILTIN_CMPNEW:
+fold_compare_helper (gsi, NE_EXPR, stmt);
+return true;
+case VSX_BUILTIN_CMPGE_16QI:
+case VSX_BUILTIN_CMPGE_U16QI:
+case VSX_BUILTIN_CMPGE_8HI:
+case VSX_BUILTIN_CMPGE_U8HI:
+case VSX_BUILTIN_CMPGE_4SI:
+case VSX_BUILTIN_CMPGE_U4SI:
+case VSX_BUILTIN_CMPGE_2DI:
+case VSX_BUILTIN_CMPGE_U2DI:
+fold_compare_helper (gsi, GE_EXPR, stmt);
+return true;
+case ALTIVEC_BUILTIN_VCMPGTSB:
+case ALTIVEC_BUILTIN_VCMPGTUB:
+case ALTIVEC_BUILTIN_VCMPGTSH:
+case ALTIVEC_BUILTIN_VCMPGTUH:
+case ALTIVEC_BUILTIN_VCMPGTSW:
+case ALTIVEC_BUILTIN_VCMPGTUW:
+case P8V_BUILTIN_VCMPGTUD:
+case P8V_BUILTIN_VCMPGTSD:
+fold_compare_helper (gsi, GT_EXPR, stmt);
+return true;
+case VSX_BUILTIN_CMPLE_16QI:
+case VSX_BUILTIN_CMPLE_U16QI:
+case VSX_BUILTIN_CMPLE_8HI:
+case VSX_BUILTIN_CMPLE_U8HI:
+case VSX_BUILTIN_CMPLE_4SI:
+case VSX_BUILTIN_CMPLE_U4SI:
+case VSX_BUILTIN_CMPLE_2DI:
+case VSX_BUILTIN_CMPLE_U2DI:
+fold_compare_helper (gsi, LE_EXPR, stmt);
+return true;
+/* flavors of vec_splat_[us]{8,16,32}.  */
+case ALTIVEC_BUILTIN_VSPLTISB:
+case ALTIVEC_BUILTIN_VSPLTISH:
+case ALTIVEC_BUILTIN_VSPLTISW:
+{
+	int size;
+	if (fn_code == ALTIVEC_BUILTIN_VSPLTISB)
+	  size = 8;
+	else if (fn_code == ALTIVEC_BUILTIN_VSPLTISH)
+	  size = 16;
+	else
+	  size = 32;
+	arg0 = gimple_call_arg (stmt, 0);
+	lhs = gimple_call_lhs (stmt);
+	/* Only fold the vec_splat_*() if the lower bits of arg 0 is a
+	   5-bit signed constant in range -16 to +15.  */
+	if (TREE_CODE (arg0) != INTEGER_CST
+	    || !IN_RANGE (sext_hwi (TREE_INT_CST_LOW (arg0), size),
+			  -16, 15))
+	  return false;
+	gimple_seq stmts = NULL;
+	location_t loc = gimple_location (stmt);
+	tree splat_value = gimple_convert (&stmts, loc,
+					   TREE_TYPE (TREE_TYPE (lhs)), arg0);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
+	g = gimple_build_assign (lhs, splat_tree);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* Flavors of vec_splat.  */
+/* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...};  */
+case ALTIVEC_BUILTIN_VSPLTB:
+case ALTIVEC_BUILTIN_VSPLTH:
+case ALTIVEC_BUILTIN_VSPLTW:
+case VSX_BUILTIN_XXSPLTD_V2DI:
+case VSX_BUILTIN_XXSPLTD_V2DF:
+{
+	arg0 = gimple_call_arg (stmt, 0); /* input vector.  */
+	arg1 = gimple_call_arg (stmt, 1); /* index into arg0.  */
+	/* Only fold the vec_splat_*() if arg1 is both a constant value and
+	   is a valid index into the arg0 vector.  */
+	unsigned int n_elts = VECTOR_CST_NELTS (arg0);
+	if (TREE_CODE (arg1) != INTEGER_CST
+	    || TREE_INT_CST_LOW (arg1) > (n_elts -1))
+	  return false;
+	lhs = gimple_call_lhs (stmt);
+	tree lhs_type = TREE_TYPE (lhs);
+	tree arg0_type = TREE_TYPE (arg0);
+	tree splat;
+	if (TREE_CODE (arg0) == VECTOR_CST)
+	  splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
+	else
+	  {
+	    /* Determine (in bits) the length and start location of the
+	       splat value for a call to the tree_vec_extract helper.  */
+	    int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
+				  * BITS_PER_UNIT / n_elts;
+	    int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
+	    tree len = build_int_cst (bitsizetype, splat_elem_size);
+	    tree start = build_int_cst (bitsizetype, splat_start_bit);
+	    splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
+				      len, start);
+	  }
+	/* And finally, build the new vector.  */
+	tree splat_tree = build_vector_from_val (lhs_type, splat);
+	g = gimple_build_assign (lhs, splat_tree);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* vec_mergel (integrals).  */
+case ALTIVEC_BUILTIN_VMRGLH:
+case ALTIVEC_BUILTIN_VMRGLW:
+case VSX_BUILTIN_XXMRGLW_4SI:
+case ALTIVEC_BUILTIN_VMRGLB:
+case VSX_BUILTIN_VEC_MERGEL_V2DI:
+case VSX_BUILTIN_XXMRGLW_4SF:
+case VSX_BUILTIN_VEC_MERGEL_V2DF:
+fold_mergehl_helper (gsi, stmt, 1);
+return true;
+/* vec_mergeh (integrals).  */
+case ALTIVEC_BUILTIN_VMRGHH:
+case ALTIVEC_BUILTIN_VMRGHW:
+case VSX_BUILTIN_XXMRGHW_4SI:
+case ALTIVEC_BUILTIN_VMRGHB:
+case VSX_BUILTIN_VEC_MERGEH_V2DI:
+case VSX_BUILTIN_XXMRGHW_4SF:
+case VSX_BUILTIN_VEC_MERGEH_V2DF:
+fold_mergehl_helper (gsi, stmt, 0);
+return true;
+/* Flavors of vec_mergee.  */
+case P8V_BUILTIN_VMRGEW_V4SI:
+case P8V_BUILTIN_VMRGEW_V2DI:
+case P8V_BUILTIN_VMRGEW_V4SF:
+case P8V_BUILTIN_VMRGEW_V2DF:
+fold_mergeeo_helper (gsi, stmt, 0);
+return true;
+/* Flavors of vec_mergeo.  */
+case P8V_BUILTIN_VMRGOW_V4SI:
+case P8V_BUILTIN_VMRGOW_V2DI:
+case P8V_BUILTIN_VMRGOW_V4SF:
+case P8V_BUILTIN_VMRGOW_V2DF:
+fold_mergeeo_helper (gsi, stmt, 1);
+return true;
+/* d = vec_pack (a, b) */
+case P8V_BUILTIN_VPKUDUM:
+case ALTIVEC_BUILTIN_VPKUHUM:
+case ALTIVEC_BUILTIN_VPKUWUM:
+{
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* d = vec_unpackh (a) */
+/* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
+in this code is sensitive to endian-ness, and needs to be inverted to
+handle both LE and BE targets.  */
+case ALTIVEC_BUILTIN_VUPKHSB:
+case ALTIVEC_BUILTIN_VUPKHSH:
+case P8V_BUILTIN_VUPKHSW:
+{
+	arg0 = gimple_call_arg (stmt, 0);
+	lhs = gimple_call_lhs (stmt);
+	if (BYTES_BIG_ENDIAN)
+	  g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
+	else
+	  g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* d = vec_unpackl (a) */
+case ALTIVEC_BUILTIN_VUPKLSB:
+case ALTIVEC_BUILTIN_VUPKLSH:
+case P8V_BUILTIN_VUPKLSW:
+{
+	arg0 = gimple_call_arg (stmt, 0);
+	lhs = gimple_call_lhs (stmt);
+	if (BYTES_BIG_ENDIAN)
+	  g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
+	else
+	  g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+}
+/* There is no gimple type corresponding with pixel, so just return.  */
+case ALTIVEC_BUILTIN_VUPKHPX:
+case ALTIVEC_BUILTIN_VUPKLPX:
+return false;
+/* vec_perm.  */
+case ALTIVEC_BUILTIN_VPERM_16QI:
+case ALTIVEC_BUILTIN_VPERM_8HI:
+case ALTIVEC_BUILTIN_VPERM_4SI:
+case ALTIVEC_BUILTIN_VPERM_2DI:
+case ALTIVEC_BUILTIN_VPERM_4SF:
+case ALTIVEC_BUILTIN_VPERM_2DF:
+{
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	tree permute = gimple_call_arg (stmt, 2);
+	lhs = gimple_call_lhs (stmt);
+	location_t loc = gimple_location (stmt);
+	gimple_seq stmts = NULL;
+	// convert arg0 and arg1 to match the type of the permute
+	// for the VEC_PERM_EXPR operation.
+	tree permute_type = (TREE_TYPE (permute));
+	tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
+	tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
+	tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
+				      permute_type, arg0_ptype, arg1_ptype,
+				      permute);
+	// Convert the result back to the desired lhs type upon completion.
+	tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	g = gimple_build_assign (lhs, temp);
+	gimple_set_location (g, loc);
+	gsi_replace (gsi, g, true);
+	return true;
+}
 default:
-	if (TARGET_DEBUG_BUILTIN)
+if (TARGET_DEBUG_BUILTIN)
-	   fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
+	fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
-		    fn_code, fn_name1, fn_name2);
+		 fn_code, fn_name1, fn_name2);
 break;
 }
 return false;
 }
 size_t i;
 rtx ret;
 bool success;
 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
+enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
+/* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
+floating point type, depending on whether long double is the IBM extended
+double (KFmode) or long double is IEEE 128-bit (TFmode).  It is simpler if
+we only define one variant of the built-in function, and switch the code
+when defining it, rather than defining two built-ins and using the
+overload table in rs6000-c.c to switch between the two.  If we don't have
+the proper assembler, don't do this switch because CODE_FOR_*kf* and
+CODE_FOR_*tf* will be CODE_FOR_nothing.  */
+if (FLOAT128_IEEE_P (TFmode))
+switch (icode)
+{
+default:
+	break;
+case CODE_FOR_sqrtkf2_odd:	icode = CODE_FOR_sqrttf2_odd;	break;
+case CODE_FOR_trunckfdf2_odd:	icode = CODE_FOR_trunctfdf2_odd; break;
+case CODE_FOR_addkf3_odd:		icode = CODE_FOR_addtf3_odd;	break;
+case CODE_FOR_subkf3_odd:		icode = CODE_FOR_subtf3_odd;	break;
+case CODE_FOR_mulkf3_odd:		icode = CODE_FOR_multf3_odd;	break;
+case CODE_FOR_divkf3_odd:		icode = CODE_FOR_divtf3_odd;	break;
+case CODE_FOR_fmakf4_odd:		icode = CODE_FOR_fmatf4_odd;	break;
+case CODE_FOR_xsxexpqp_kf:	icode = CODE_FOR_xsxexpqp_tf;	break;
+case CODE_FOR_xsxsigqp_kf:	icode = CODE_FOR_xsxsigqp_tf;	break;
+case CODE_FOR_xststdcnegqp_kf:	icode = CODE_FOR_xststdcnegqp_tf; break;
+case CODE_FOR_xsiexpqp_kf:	icode = CODE_FOR_xsiexpqp_tf;	break;
+case CODE_FOR_xsiexpqpf_kf:	icode = CODE_FOR_xsiexpqpf_tf;	break;
+case CODE_FOR_xststdcqp_kf:	icode = CODE_FOR_xststdcqp_tf;	break;
+}
 if (TARGET_DEBUG_BUILTIN)
 {
-enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
 const char *name1 = rs6000_builtin_info[uns_fcode].name;
 const char *name2 = (icode != CODE_FOR_nothing)
 			   ? get_insn_name ((int) icode)
 			   : "nothing";
 const char *name3;
 					   target);
 case RS6000_BUILTIN_MFFS:
 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
+case RS6000_BUILTIN_MTFSB0:
+return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
+case RS6000_BUILTIN_MTFSB1:
+return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
+case RS6000_BUILTIN_SET_FPSCR_RN:
+return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
+						 exp);
+case RS6000_BUILTIN_SET_FPSCR_DRN:
+return
+rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
+					     exp);
+case RS6000_BUILTIN_MFFSL:
+return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
 case RS6000_BUILTIN_MTFSF:
 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
 case RS6000_BUILTIN_CPU_INIT:
 case RS6000_BUILTIN_CPU_IS:
 case RS6000_BUILTIN_CPU_SUPPORTS:
 return cpu_expand_builtin (fcode, exp, target);
+case MISC_BUILTIN_SPEC_BARRIER:
+{
+	emit_insn (gen_speculation_barrier ());
+	return NULL_RTX;
+}
 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
 {
-	int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
+	int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
 		     : (int) CODE_FOR_altivec_lvsl_direct);
-	machine_mode tmode = insn_data[icode].operand[0].mode;
+	machine_mode tmode = insn_data[icode2].operand[0].mode;
-	machine_mode mode = insn_data[icode].operand[1].mode;
+	machine_mode mode = insn_data[icode2].operand[1].mode;
 	tree arg;
 	rtx op, addr, pat;
 	gcc_assert (TARGET_ALTIVEC);
 	  }
 	op = gen_rtx_MEM (mode, op);
 	if (target == 0
 	    || GET_MODE (target) != tmode
-	    || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
+	    || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
 	  target = gen_reg_rtx (tmode);
-	pat = GEN_FCN (icode) (target, op);
+	pat = GEN_FCN (icode2) (target, op);
 	if (!pat)
 	  return 0;
 	emit_insn (pat);
 	return target;
 	  exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
 				 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
 	}
 break;
+/* For the pack and unpack int128 routines, fix up the builtin so it
+	 uses the correct IBM128 type.  */
+case MISC_BUILTIN_PACK_IF:
+if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
+	{
+	  icode = CODE_FOR_packtf;
+	  fcode = MISC_BUILTIN_PACK_TF;
+	  uns_fcode = (size_t)fcode;
+	}
+break;
+case MISC_BUILTIN_UNPACK_IF:
+if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
+	{
+	  icode = CODE_FOR_unpacktf;
+	  fcode = MISC_BUILTIN_UNPACK_TF;
+	  uns_fcode = (size_t)fcode;
+	}
+break;
 default:
 break;
 }
 if (TARGET_ALTIVEC)
 ret = altivec_expand_builtin (exp, target, &success);
 if (success)
 	return ret;
 }
-if (TARGET_PAIRED_FLOAT)
-{
-ret = paired_expand_builtin (exp, target, &success);
-if (success)
-	return ret;
-}
 if (TARGET_HTM)
 {
 ret = htm_expand_builtin (exp, target, &success);
 if (success)
 /* Handle simple unary operations.  */
 d = bdesc_1arg;
 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
 if (d->code == fcode)
-return rs6000_expand_unop_builtin (d->icode, exp, target);
+return rs6000_expand_unop_builtin (icode, exp, target);
 /* Handle simple binary operations.  */
 d = bdesc_2arg;
 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
 if (d->code == fcode)
-return rs6000_expand_binop_builtin (d->icode, exp, target);
+return rs6000_expand_binop_builtin (icode, exp, target);
 /* Handle simple ternary operations.  */
 d = bdesc_3arg;
 for (i = 0; i < ARRAY_SIZE  (bdesc_3arg); i++, d++)
 if (d->code == fcode)
-return rs6000_expand_ternop_builtin (d->icode, exp, target);
+return rs6000_expand_ternop_builtin (icode, exp, target);
 /* Handle simple no-argument operations. */
 d = bdesc_0arg;
 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
 if (d->code == fcode)
-return rs6000_expand_zeroop_builtin (d->icode, target);
+return rs6000_expand_zeroop_builtin (icode, target);
 gcc_unreachable ();
 }
 /* Create a builtin vector type with a name.  Taking care not to give
 tree tdecl;
 tree ftype;
 machine_mode mode;
 if (TARGET_DEBUG_BUILTIN)
-fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
+fprintf (stderr, "rs6000_init_builtins%s%s\n",
-	     (TARGET_PAIRED_FLOAT) ? ", paired"	 : "",
 	     (TARGET_ALTIVEC)	   ? ", altivec" : "",
 	     (TARGET_VSX)	   ? ", vsx"	 : "");
-V2SI_type_node = build_vector_type (intSI_type_node, 2);
-V2SF_type_node = build_vector_type (float_type_node, 2);
 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
 				       : "__vector long long",
 				       intDI_type_node, 2);
 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
 V4SI_type_node = rs6000_vector_type ("__vector signed int",
 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
 				       ? "__vector unsigned long"
 				       : "__vector unsigned long long",
 				       unsigned_intDI_type_node, 2);
-opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
-opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
-opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
 const_str_type_node
 = build_pointer_type (build_qualified_type (char_type_node,
 						TYPE_QUAL_CONST));
 'vector unsigned short'.  */
 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
-bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
+bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
 long_integer_type_internal_node = long_integer_type_node;
 long_unsigned_type_internal_node = long_unsigned_type_node;
 long_long_integer_type_internal_node = long_long_integer_type_node;
 If we don't support for either 128-bit IBM double double or IEEE 128-bit
 floating point, we need make sure the type is non-zero or else self-test
 fails during bootstrap.
-We don't register a built-in type for __ibm128 if the type is the same as
+Always create __ibm128 as a separate type, even if the current long double
-long double.  Instead we add a #define for __ibm128 in
+format is IBM extended double.
-rs6000_cpu_cpp_builtins to long double.
 For IEEE 128-bit floating point, always create the type __ieee128.  If the
 user used -mfloat128, rs6000-c.c will create a define from __float128 to
 __ieee128.  */
-if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
+if (TARGET_FLOAT128_TYPE)
 {
-ibm128_float_type_node = make_node (REAL_TYPE);
+if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
-TYPE_PRECISION (ibm128_float_type_node) = 128;
+	ibm128_float_type_node = long_double_type_node;
-SET_TYPE_MODE (ibm128_float_type_node, IFmode);
+else
-layout_type (ibm128_float_type_node);
+	{
+	  ibm128_float_type_node = make_node (REAL_TYPE);
+	  TYPE_PRECISION (ibm128_float_type_node) = 128;
+	  SET_TYPE_MODE (ibm128_float_type_node, IFmode);
+	  layout_type (ibm128_float_type_node);
+	}
 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
 					      "__ibm128");
-}
-else
+if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
-ibm128_float_type_node = long_double_type_node;
+	ieee128_float_type_node = long_double_type_node;
+else
-if (TARGET_FLOAT128_TYPE)
+	ieee128_float_type_node = float128_type_node;
-{
-ieee128_float_type_node = float128_type_node;
 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
 					      "__ieee128");
 }
 else
-ieee128_float_type_node = long_double_type_node;
+ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
 /* Initialize the modes for builtin_function_type, mapping a machine mode to
 tree type node.  */
 builtin_mode_to_type[QImode][0] = integer_type_node;
 builtin_mode_to_type[HImode][0] = integer_type_node;
 builtin_mode_to_type[TFmode][0] = long_double_type_node;
 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
-builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
-builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
 					    bool_int_type_node, 4);
 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
 					    ? "__vector __bool long"
 					    : "__vector __bool long long",
-					    bool_long_type_node, 2);
+					    bool_long_long_type_node, 2);
 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
 					     pixel_type_node, 8);
-/* Paired builtins are only available if you build a compiler with the
+/* Create Altivec and VSX builtins on machines with at least the
-appropriate options, so only create those builtins with the appropriate
+general purpose extensions (970 and newer) to allow the use of
-compiler option.  Create Altivec and VSX builtins on machines with at
-least the general purpose extensions (970 and newer) to allow the use of
 the target attribute.  */
-if (TARGET_PAIRED_FLOAT)
-paired_init_builtins ();
 if (TARGET_EXTRA_BUILTINS)
 altivec_init_builtins ();
 if (TARGET_HTM)
 htm_init_builtins ();
-if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
+if (TARGET_EXTRA_BUILTINS)
 rs6000_common_init_builtins ();
-ftype = build_function_type_list (ieee128_float_type_node,
-				    const_str_type_node, NULL_TREE);
-def_builtin ("__builtin_nanq", ftype, RS6000_BUILTIN_NANQ);
-def_builtin ("__builtin_nansq", ftype, RS6000_BUILTIN_NANSQ);
-ftype = build_function_type_list (ieee128_float_type_node, NULL_TREE);
-def_builtin ("__builtin_infq", ftype, RS6000_BUILTIN_INFQ);
-def_builtin ("__builtin_huge_valq", ftype, RS6000_BUILTIN_HUGE_VALQ);
 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
 				 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
 ftype = build_function_type_list (double_type_node, NULL_TREE);
 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
+ftype = build_function_type_list (double_type_node, NULL_TREE);
+def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
+ftype = build_function_type_list (void_type_node,
+				    intSI_type_node,
+				    NULL_TREE);
+def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
+ftype = build_function_type_list (void_type_node,
+				    intSI_type_node,
+				    NULL_TREE);
+def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
+ftype = build_function_type_list (void_type_node,
+				    intDI_type_node,
+				    NULL_TREE);
+def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
+ftype = build_function_type_list (void_type_node,
+				    intDI_type_node,
+				    NULL_TREE);
+def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
 ftype = build_function_type_list (void_type_node,
 				    intSI_type_node, double_type_node,
 				    NULL_TREE);
 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
 ftype = build_function_type_list (void_type_node, NULL_TREE);
 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
+def_builtin ("__builtin_ppc_speculation_barrier", ftype,
+	       MISC_BUILTIN_SPEC_BARRIER);
 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
 				    NULL_TREE);
 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
 rs6000_invalid_builtin ((enum rs6000_builtins)code);
 return error_mark_node;
 }
 return rs6000_builtin_decls[code];
-}
-static void
-paired_init_builtins (void)
-{
-const struct builtin_description *d;
-size_t i;
-HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
-tree int_ftype_int_v2sf_v2sf
-= build_function_type_list (integer_type_node,
-integer_type_node,
-V2SF_type_node,
-V2SF_type_node,
-NULL_TREE);
-tree pcfloat_type_node =
-build_pointer_type (build_qualified_type
-			(float_type_node, TYPE_QUAL_CONST));
-tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
-							   long_integer_type_node,
-							   pcfloat_type_node,
-							   NULL_TREE);
-tree void_ftype_v2sf_long_pcfloat =
-build_function_type_list (void_type_node,
-			      V2SF_type_node,
-			      long_integer_type_node,
-			      pcfloat_type_node,
-			      NULL_TREE);
-def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
-	       PAIRED_BUILTIN_LX);
-def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
-	       PAIRED_BUILTIN_STX);
-/* Predicates.  */
-d = bdesc_paired_preds;
-for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
-{
-tree type;
-HOST_WIDE_INT mask = d->mask;
-if ((mask & builtin_mask) != mask)
-	{
-	  if (TARGET_DEBUG_BUILTIN)
-	    fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
-		     d->name);
-	  continue;
-	}
-/* Cannot define builtin if the instruction is disabled.  */
-gcc_assert (d->icode != CODE_FOR_nothing);
-if (TARGET_DEBUG_BUILTIN)
-	fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
-		 (int)i, get_insn_name (d->icode), (int)d->icode,
-		 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
-switch (insn_data[d->icode].operand[1].mode)
-	{
-	case E_V2SFmode:
-	  type = int_ftype_int_v2sf_v2sf;
-	  break;
-	default:
-	  gcc_unreachable ();
-	}
-def_builtin (d->name, type, d->code);
-}
 }
 static void
 altivec_init_builtins (void)
 {
 				NULL_TREE);
 tree v2di_ftype_long_pcvoid
 = build_function_type_list (V2DI_type_node,
 				long_integer_type_node, pcvoid_type_node,
 				NULL_TREE);
+tree v1ti_ftype_long_pcvoid
+= build_function_type_list (V1TI_type_node,
+				long_integer_type_node, pcvoid_type_node,
+				NULL_TREE);
 tree void_ftype_opaque_long_pvoid
 = build_function_type_list (void_type_node,
 				opaque_V4SI_type_node, long_integer_type_node,
 				pvoid_type_node, NULL_TREE);
 				V4SF_type_node, long_integer_type_node,
 				pvoid_type_node, NULL_TREE);
 tree void_ftype_v2df_long_pvoid
 = build_function_type_list (void_type_node,
 				V2DF_type_node, long_integer_type_node,
+				pvoid_type_node, NULL_TREE);
+tree void_ftype_v1ti_long_pvoid
+= build_function_type_list (void_type_node,
+				V1TI_type_node, long_integer_type_node,
 				pvoid_type_node, NULL_TREE);
 tree void_ftype_v2di_long_pvoid
 = build_function_type_list (void_type_node,
 				V2DI_type_node, long_integer_type_node,
 				pvoid_type_node, NULL_TREE);
 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
 	       ALTIVEC_BUILTIN_LVXL_V8HI);
 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
 	       ALTIVEC_BUILTIN_LVXL_V16QI);
 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
+def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
+	       ALTIVEC_BUILTIN_LVX_V1TI);
 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
 	       ALTIVEC_BUILTIN_LVX_V2DF);
 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
 	       ALTIVEC_BUILTIN_LVX_V2DI);
 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
 	       VSX_BUILTIN_LD_ELEMREV_V2DI);
 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
 	       VSX_BUILTIN_LD_ELEMREV_V4SF);
 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
 	       VSX_BUILTIN_LD_ELEMREV_V4SI);
+def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
+	       VSX_BUILTIN_LD_ELEMREV_V8HI);
+def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
+	       VSX_BUILTIN_LD_ELEMREV_V16QI);
 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
 	       VSX_BUILTIN_ST_ELEMREV_V2DF);
+def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
+	       VSX_BUILTIN_ST_ELEMREV_V1TI);
 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
 	       VSX_BUILTIN_ST_ELEMREV_V2DI);
 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
 	       VSX_BUILTIN_ST_ELEMREV_V4SF);
 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
 	       VSX_BUILTIN_ST_ELEMREV_V4SI);
+def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
-def_builtin ("__builtin_vsx_le_be_v8hi", v8hi_ftype_long_pcvoid,
+	       VSX_BUILTIN_ST_ELEMREV_V8HI);
-		   VSX_BUILTIN_XL_BE_V8HI);
+def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
-def_builtin ("__builtin_vsx_le_be_v4si", v4si_ftype_long_pcvoid,
+	       VSX_BUILTIN_ST_ELEMREV_V16QI);
-		   VSX_BUILTIN_XL_BE_V4SI);
-def_builtin ("__builtin_vsx_le_be_v2di", v2di_ftype_long_pcvoid,
-		   VSX_BUILTIN_XL_BE_V2DI);
-def_builtin ("__builtin_vsx_le_be_v4sf", v4sf_ftype_long_pcvoid,
-		   VSX_BUILTIN_XL_BE_V4SF);
-def_builtin ("__builtin_vsx_le_be_v2df", v2df_ftype_long_pcvoid,
-		   VSX_BUILTIN_XL_BE_V2DF);
-def_builtin ("__builtin_vsx_le_be_v16qi", v16qi_ftype_long_pcvoid,
-		   VSX_BUILTIN_XL_BE_V16QI);
-if (TARGET_P9_VECTOR)
-{
-def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
-		   VSX_BUILTIN_LD_ELEMREV_V8HI);
-def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
-		   VSX_BUILTIN_LD_ELEMREV_V16QI);
-def_builtin ("__builtin_vsx_st_elemrev_v8hi",
-		   void_ftype_v8hi_long_pvoid, VSX_BUILTIN_ST_ELEMREV_V8HI);
-def_builtin ("__builtin_vsx_st_elemrev_v16qi",
-		   void_ftype_v16qi_long_pvoid, VSX_BUILTIN_ST_ELEMREV_V16QI);
-}
-else
-{
-rs6000_builtin_decls[(int) VSX_BUILTIN_LD_ELEMREV_V8HI]
-	= rs6000_builtin_decls[(int) VSX_BUILTIN_LXVW4X_V8HI];
-rs6000_builtin_decls[(int) VSX_BUILTIN_LD_ELEMREV_V16QI]
-	= rs6000_builtin_decls[(int) VSX_BUILTIN_LXVW4X_V16QI];
-rs6000_builtin_decls[(int) VSX_BUILTIN_ST_ELEMREV_V8HI]
-	= rs6000_builtin_decls[(int) VSX_BUILTIN_STXVW4X_V8HI];
-rs6000_builtin_decls[(int) VSX_BUILTIN_ST_ELEMREV_V16QI]
-	= rs6000_builtin_decls[(int) VSX_BUILTIN_STXVW4X_V16QI];
-}
 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
 	       VSX_BUILTIN_VEC_LD);
 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
 	       VSX_BUILTIN_VEC_ST);
 	       VSX_BUILTIN_VEC_XL);
 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
 	       VSX_BUILTIN_VEC_XL_BE);
 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
 	       VSX_BUILTIN_VEC_XST);
+def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
+	       VSX_BUILTIN_VEC_XST_BE);
 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
 				    NULL_TREE);
 tree void_ftype_v1ti_long_pvoid
 	= build_function_type_list (void_type_node,
 				    V1TI_type_node, long_integer_type_node,
 				    pvoid_type_node, NULL_TREE);
+def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
+		   VSX_BUILTIN_LD_ELEMREV_V1TI);
 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
 		   VSX_BUILTIN_LXVD2X_V1TI);
 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
 		   VSX_BUILTIN_STXVD2X_V1TI);
 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
 arguments, and it is returned as a decl for the vectorizer (such as
 widening multiplies, permute), make sure the arguments and return value
 are type correct.  */
 switch (builtin)
 {
 /* unsigned 1 argument functions.  */
 case CRYPTO_BUILTIN_VSBOX:
 case P8V_BUILTIN_VGBBD:
 case MISC_BUILTIN_CDTBCD:
 case MISC_BUILTIN_CBCDTD:
 h.uns_p[0] = 1;
 h.uns_p[1] = 1;
 break;
 /* unsigned 2 argument functions.  */
 case ALTIVEC_BUILTIN_VMULEUB:
 case ALTIVEC_BUILTIN_VMULEUH:
-case ALTIVEC_BUILTIN_VMULEUW:
+case P8V_BUILTIN_VMULEUW:
 case ALTIVEC_BUILTIN_VMULOUB:
 case ALTIVEC_BUILTIN_VMULOUH:
-case ALTIVEC_BUILTIN_VMULOUW:
+case P8V_BUILTIN_VMULOUW:
 case CRYPTO_BUILTIN_VCIPHER:
 case CRYPTO_BUILTIN_VCIPHERLAST:
 case CRYPTO_BUILTIN_VNCIPHER:
 case CRYPTO_BUILTIN_VNCIPHERLAST:
 case CRYPTO_BUILTIN_VPMSUMB:
 case CRYPTO_BUILTIN_VPMSUMW:
 case CRYPTO_BUILTIN_VPMSUMD:
 case CRYPTO_BUILTIN_VPMSUM:
 case MISC_BUILTIN_ADDG6S:
 case MISC_BUILTIN_DIVWEU:
-case MISC_BUILTIN_DIVWEUO:
 case MISC_BUILTIN_DIVDEU:
-case MISC_BUILTIN_DIVDEUO:
 case VSX_BUILTIN_UDIV_V2DI:
 case ALTIVEC_BUILTIN_VMAXUB:
 case ALTIVEC_BUILTIN_VMINUB:
 case ALTIVEC_BUILTIN_VMAXUH:
 case ALTIVEC_BUILTIN_VMINUH:
 h.uns_p[0] = 1;
 h.uns_p[1] = 1;
 h.uns_p[2] = 1;
 break;
 /* unsigned 3 argument functions.  */
 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
 h.uns_p[1] = 1;
 h.uns_p[2] = 1;
 h.uns_p[3] = 1;
 break;
 /* signed permute functions with unsigned char mask.  */
 case ALTIVEC_BUILTIN_VPERM_16QI:
 case ALTIVEC_BUILTIN_VPERM_8HI:
 case ALTIVEC_BUILTIN_VPERM_4SI:
 case ALTIVEC_BUILTIN_VPERM_4SF:
 case ALTIVEC_BUILTIN_VPERM_2DI:
 case VSX_BUILTIN_VPERM_2DI:
 case VSX_BUILTIN_VPERM_2DF:
 h.uns_p[3] = 1;
 break;
 /* unsigned args, signed return.  */
 case VSX_BUILTIN_XVCVUXDSP:
 case VSX_BUILTIN_XVCVUXDDP_UNS:
 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
 h.uns_p[1] = 1;
 break;
 /* signed args, unsigned return.  */
 case VSX_BUILTIN_XVCVDPUXDS_UNS:
 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
 case MISC_BUILTIN_UNPACK_TD:
 case MISC_BUILTIN_UNPACK_V1TI:
 h.uns_p[0] = 1;
 break;
-/* unsigned arguments for 128-bit pack instructions.  */
+/* unsigned arguments, bool return (compares).  */
+case ALTIVEC_BUILTIN_VCMPEQUB:
+case ALTIVEC_BUILTIN_VCMPEQUH:
+case ALTIVEC_BUILTIN_VCMPEQUW:
+case P8V_BUILTIN_VCMPEQUD:
+case VSX_BUILTIN_CMPGE_U16QI:
+case VSX_BUILTIN_CMPGE_U8HI:
+case VSX_BUILTIN_CMPGE_U4SI:
+case VSX_BUILTIN_CMPGE_U2DI:
+case ALTIVEC_BUILTIN_VCMPGTUB:
+case ALTIVEC_BUILTIN_VCMPGTUH:
+case ALTIVEC_BUILTIN_VCMPGTUW:
+case P8V_BUILTIN_VCMPGTUD:
+h.uns_p[1] = 1;
+h.uns_p[2] = 1;
+break;
+/* unsigned arguments for 128-bit pack instructions.  */
 case MISC_BUILTIN_PACK_TD:
 case MISC_BUILTIN_PACK_V1TI:
 h.uns_p[1] = 1;
 h.uns_p[2] = 1;
 break;
-	/* unsigned second arguments (vector shift right).  */
+/* unsigned second arguments (vector shift right).  */
 case ALTIVEC_BUILTIN_VSRB:
 case ALTIVEC_BUILTIN_VSRH:
 case ALTIVEC_BUILTIN_VSRW:
 case P8V_BUILTIN_VSRD:
 h.uns_p[2] = 1;
 size_t i;
 tree opaque_ftype_opaque = NULL_TREE;
 tree opaque_ftype_opaque_opaque = NULL_TREE;
 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
-tree v2si_ftype = NULL_TREE;
-tree v2si_ftype_qi = NULL_TREE;
-tree v2si_ftype_v2si_qi = NULL_TREE;
-tree v2si_ftype_int_qi = NULL_TREE;
 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
-if (!TARGET_PAIRED_FLOAT)
+/* Create Altivec and VSX builtins on machines with at least the
-{
+general purpose extensions (970 and newer) to allow the use of
-builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
+the target attribute.  */
-builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
-}
-/* Paired builtins are only available if you build a compiler with the
-appropriate options, so only create those builtins with the appropriate
-compiler option.  Create Altivec and VSX builtins on machines with at
-least the general purpose extensions (970 and newer) to allow the use of
-the target attribute..  */
 if (TARGET_EXTRA_BUILTINS)
 builtin_mask |= RS6000_BTM_COMMON;
 /* Add the ternary operators.  */
 mode0 = insn_data[icode].operand[0].mode;
 mode1 = insn_data[icode].operand[1].mode;
 mode2 = insn_data[icode].operand[2].mode;
-	  if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
+	  type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
-	    {
+					d->code, d->name);
-	      if (! (type = v2si_ftype_v2si_qi))
-		type = v2si_ftype_v2si_qi
-		  = build_function_type_list (opaque_V2SI_type_node,
-					      opaque_V2SI_type_node,
-					      char_type_node,
-					      NULL_TREE);
-	    }
-	  else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
-		   && mode2 == QImode)
-	    {
-	      if (! (type = v2si_ftype_int_qi))
-		type = v2si_ftype_int_qi
-		  = build_function_type_list (opaque_V2SI_type_node,
-					      integer_type_node,
-					      char_type_node,
-					      NULL_TREE);
-	    }
-	  else
-	    type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
-					  d->code, d->name);
 	}
 def_builtin (d->name, type, d->code);
 }
 	    }
 mode0 = insn_data[icode].operand[0].mode;
 mode1 = insn_data[icode].operand[1].mode;
-	  if (mode0 == V2SImode && mode1 == QImode)
+	  type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
-	    {
+					d->code, d->name);
-	      if (! (type = v2si_ftype_qi))
-		type = v2si_ftype_qi
-		  = build_function_type_list (opaque_V2SI_type_node,
-					      char_type_node,
-					      NULL_TREE);
-	    }
-	  else
-	    type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
-					  d->code, d->name);
 	}
 def_builtin (d->name, type, d->code);
 }
 			 "rs6000_builtin, skip no-argument %s (no code)\n",
 			 d->name);
 	      continue;
 	    }
 	  mode0 = insn_data[icode].operand[0].mode;
-	  if (mode0 == V2SImode)
+	  type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
-	    {
+					d->code, d->name);
-	      /* code for paired single */
-	      if (! (type = v2si_ftype))
-		{
-		  v2si_ftype
-		    = build_function_type_list (opaque_V2SI_type_node,
-						NULL_TREE);
-		  type = v2si_ftype;
-		}
-	    }
-	  else
-	    type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
-					  d->code, d->name);
 	}
 def_builtin (d->name, type, d->code);
 }
 }
 /* Add various conversions for IFmode to use the traditional TFmode
 names.  */
 if (mode == IFmode)
 {
-set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
+set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
-set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
+set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
-set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
+set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
-set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
+set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
-set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
+set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
-set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
+set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
 if (TARGET_POWERPC64)
 	{
 	  set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
 	  set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
 	  set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
 	  set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
 	}
 }
+}
+/* Create a decl for either complex long double multiply or complex long double
+divide when long double is IEEE 128-bit floating point.  We can't use
+__multc3 and __divtc3 because the original long double using IBM extended
+double used those names.  The complex multiply/divide functions are encoded
+as builtin functions with a complex result and 4 scalar inputs.  */
+static void
+create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
+{
+tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
+				      name, NULL_TREE);
+set_builtin_decl (fncode, fndecl, true);
+if (TARGET_DEBUG_BUILTIN)
+fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
+return;
 }
 /* Set up IEEE 128-bit floating point routines.  Use different names if the
 arguments can be passed in a vector register.  The historical PowerPC
 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
 static void
 init_float128_ieee (machine_mode mode)
 {
 if (FLOAT128_VECTOR_P (mode))
 {
+static bool complex_muldiv_init_p = false;
+/* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble.  If
+	 we have clone or target attributes, this will be called a second
+	 time.  We want to create the built-in function only once.  */
+if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
+{
+	 complex_muldiv_init_p = true;
+	 built_in_function fncode_mul =
+	   (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
+				- MIN_MODE_COMPLEX_FLOAT);
+	 built_in_function fncode_div =
+	   (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
+				- MIN_MODE_COMPLEX_FLOAT);
+	 tree fntype = build_function_type_list (complex_long_double_type_node,
+						 long_double_type_node,
+						 long_double_type_node,
+						 long_double_type_node,
+						 long_double_type_node,
+						 NULL_TREE);
+	 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
+	 create_complex_muldiv ("__divkc3", fncode_div, fntype);
+}
 set_optab_libfunc (add_optab, mode, "__addkf3");
 set_optab_libfunc (sub_optab, mode, "__subkf3");
 set_optab_libfunc (neg_optab, mode, "__negkf2");
 set_optab_libfunc (smul_optab, mode, "__mulkf3");
 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
-set_optab_libfunc (abs_optab, mode, "__abstkf2");
+set_optab_libfunc (abs_optab, mode, "__abskf2");
+set_optab_libfunc (powi_optab, mode, "__powikf2");
 set_optab_libfunc (eq_optab, mode, "__eqkf2");
 set_optab_libfunc (ne_optab, mode, "__nekf2");
 set_optab_libfunc (gt_optab, mode, "__gtkf2");
 set_optab_libfunc (ge_optab, mode, "__gekf2");
 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
-set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
+set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
-	set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
+	set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
-set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
+set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
-	set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
+	set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
-set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
+set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
-set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
+set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
-set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
+set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
-set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
+set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
-set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
+set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
-set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
+set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
 	      emit_insn (gen_rtx_SET (scratch, addr));
 	      new_addr = scratch;
 	    }
 	}
-else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
+else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
 	{
 	  if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
 	      || !quad_address_p (addr, mode, false))
 	    {
 	      emit_insn (gen_rtx_SET (scratch, addr));
 	      new_addr = scratch;
 	    }
 	}
 /* Quad offsets are restricted and can't handle normal addresses.  */
-else if (mode_supports_vsx_dform_quad (mode))
+else if (mode_supports_dq_form (mode))
 	{
 	  emit_insn (gen_rtx_SET (scratch, addr));
 	  new_addr = scratch;
 	}
 	  return NO_REGS;
 	}
 /* D-form addressing can easily reload the value.  */
 if (mode_supports_vmx_dform (mode)
-	  || mode_supports_vsx_dform_quad (mode))
+	  || mode_supports_dq_form (mode))
 	return rclass;
 /* If this is a scalar floating point value and we don't have D-form
 	 addressing, prefer the traditional floating point registers so that we
 	 can use D-form (register+offset) addressing.  */
 	       && altivec_indexed_or_indirect_operand (src, mode))
 	return "lvx %0,%y1";
 else if (TARGET_VSX && dest_vsx_p)
 	{
-	  if (mode_supports_vsx_dform_quad (mode)
+	  if (mode_supports_dq_form (mode)
 	      && quad_address_p (XEXP (src, 0), mode, true))
 	    return "lxv %x0,%1";
 	  else if (TARGET_P9_VECTOR)
 	    return "lxvx %x0,%y1";
 	  else
 	    return "#";
 	}
 else if (TARGET_ALTIVEC && src_vmx_p
-	       && altivec_indexed_or_indirect_operand (src, mode))
+	       && altivec_indexed_or_indirect_operand (dest, mode))
 	return "stvx %1,%y0";
 else if (TARGET_VSX && src_vsx_p)
 	{
-	  if (mode_supports_vsx_dform_quad (mode)
+	  if (mode_supports_dq_form (mode)
 	      && quad_address_p (XEXP (dest, 0), mode, true))
 	    return "stxv %x1,%0";
 	  else if (TARGET_P9_VECTOR)
 	    return "stxvx %x1,%y0";
 }
 /* Print an operand.  Recognize special options, documented below.  */
 #if TARGET_ELF
+/* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
+only introduced by the linker, when applying the sda21
+relocation.  */
 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
 #else
 #define SMALL_DATA_RELOC "sda21"
 #define SMALL_DATA_REG 0
 	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
 		     reg_names[SMALL_DATA_REG]);
 	}
 return;
-case 'N':
+case 'N': /* Unused */
 /* Write the number of elements in the vector times 4.  */
 if (GET_CODE (x) != PARALLEL)
 	output_operand_lossage ("invalid %%N value");
 else
 	fprintf (file, "%d", XVECLEN (x, 0) * 4);
 return;
-case 'O':
+case 'O': /* Unused */
 /* Similar, but subtract 1 first.  */
 if (GET_CODE (x) != PARALLEL)
 	output_operand_lossage ("invalid %%O value");
 else
 	fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
 	gcc_assert (MEM_P (x));
 	tmp = XEXP (x, 0);
-	if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
+	if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
 	    && GET_CODE (tmp) == AND
 	    && GET_CODE (XEXP (tmp, 1)) == CONST_INT
 	    && INTVAL (XEXP (tmp, 1)) == -16)
 	  tmp = XEXP (tmp, 0);
 	else if (VECTOR_MEM_VSX_P (GET_MODE (x))
 	fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
 else
 	fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
 }
 else
-gcc_unreachable ();
+output_addr_const (file, x);
 }
 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.  */
 static bool
 do_move = true;
 else
 gcc_unreachable ();
-/* Handle conversion between TFmode/KFmode.  */
+/* Handle conversion between TFmode/KFmode/IFmode.  */
 if (do_move)
-emit_move_insn (dest, gen_lowpart (dest_mode, src));
+emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
 /* Handle conversion if we have hardware support.  */
 else if (TARGET_FLOAT128_HW && hw_convert)
 emit_insn ((hw_convert) (dest, src));
 return;
 }
-/* Emit the RTL for an sISEL pattern.  */
-void
-rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
-{
-rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
-}
 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal.  SCRATCH
 can be used as that dest register.  Return the dest register.  */
 rtx
 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
 return 1;
 }
 /* Same as above, but for ints (isel).  */
-static int
+int
 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
 {
 rtx condition_rtx, cr;
 machine_mode mode = GET_MODE (dest);
 enum rtx_code cond_code;
 target = emit_conditional_move (dest, c, op0, op1, mode,
 				    op1, op0, mode, 0);
 gcc_assert (target);
 if (target != dest)
 emit_move_insn (dest, target);
-}
-/* Split a signbit operation on 64-bit machines with direct move.  Also allow
-for the value to come from memory or if it is already loaded into a GPR.  */
-void
-rs6000_split_signbit (rtx dest, rtx src)
-{
-machine_mode d_mode = GET_MODE (dest);
-machine_mode s_mode = GET_MODE (src);
-rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
-rtx shift_reg = dest_di;
-gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
-if (MEM_P (src))
-{
-rtx mem = (WORDS_BIG_ENDIAN
-		 ? adjust_address (src, DImode, 0)
-		 : adjust_address (src, DImode, 8));
-emit_insn (gen_rtx_SET (dest_di, mem));
-}
-else
-{
-unsigned int r = reg_or_subregno (src);
-if (INT_REGNO_P (r))
-	shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
-else
-	{
-	  /* Generate the special mfvsrd instruction to get it in a GPR.  */
-	  gcc_assert (VSX_REGNO_P (r));
-	  if (s_mode == KFmode)
-	    emit_insn (gen_signbitkf2_dm2 (dest_di, src));
-	  else
-	    emit_insn (gen_signbittf2_dm2 (dest_di, src));
-	}
-}
-emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
-return;
 }
 /* A subroutine of the atomic operation splitters.  Jump to LABEL if
 COND is true.  Mark the jump as unlikely to be taken.  */
 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
 mode = GET_MODE (dst);
 nregs = hard_regno_nregs (reg, mode);
 if (FP_REGNO_P (reg))
 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
-	((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
+	(TARGET_HARD_FLOAT ? DFmode : SFmode);
 else if (ALTIVEC_REGNO_P (reg))
 reg_mode = V16QImode;
 else
 reg_mode = word_mode;
 reg_mode_size = GET_MODE_SIZE (reg_mode);
 			   ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
 			   : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
 	      emit_insn (gen_add3_insn (breg, breg, delta_rtx));
 	      src = replace_equiv_address (src, breg);
 	    }
-	  else if (! rs6000_offsettable_memref_p (src, reg_mode))
+	  else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
 	    {
 	      if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
 		{
 		  rtx basereg = XEXP (XEXP (src, 0), 0);
 		  if (TARGET_UPDATE)
 		}
 	      else
 		emit_insn (gen_add3_insn (breg, breg, delta_rtx));
 	      dst = replace_equiv_address (dst, breg);
 	    }
-	  else if (!rs6000_offsettable_memref_p (dst, reg_mode)
+	  else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
 		   && GET_CODE (XEXP (dst, 0)) != LO_SUM)
 	    {
 	      if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
 		{
 		  rtx basereg = XEXP (XEXP (dst, 0), 0);
 		  restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
 		  dst = replace_equiv_address (dst, basereg);
 		}
 	    }
 	  else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
-	    gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
+	    gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
 	}
 for (i = 0; i < nregs; i++)
 	{
 	  /* Calculate index to next subword.  */
 		 | SAVE_INLINE_VRS | REST_INLINE_VRS);
 if (info->first_gp_reg_save == 32)
 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
-if (info->first_fp_reg_save == 64
+if (info->first_fp_reg_save == 64)
-/* The out-of-line FP routines use double-precision stores;
-	 we can't use those routines if we don't have such stores.  */
-|| (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
 static bool
 rs6000_function_ok_for_sibcall (tree decl, tree exp)
 {
 tree fntype;
+/* The sibcall epilogue may clobber the static chain register.
+??? We could work harder and avoid that, but it's probably
+not worth the hassle in practice.  */
+if (CALL_EXPR_STATIC_CHAIN (exp))
+return false;
 if (decl)
 fntype = TREE_TYPE (decl);
 else
 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
 	      && !(info->savres_strategy & REST_MULTIPLE));
 /* Component 0 is the save/restore of LR (done via GPR0).
+Component 2 is the save of the TOC (GPR2).
 Components 13..31 are the save/restore of GPR13..GPR31.
 Components 46..63 are the save/restore of FPR14..FPR31.  */
 cfun->machine->n_components = 64;
 	offset += info->total_size;
 if (IN_RANGE (offset, -0x8000, 0x7fff))
 	bitmap_set_bit (components, 0);
 }
+/* Optimize saving the TOC.  This is component 2.  */
+if (cfun->machine->save_toc_in_prologue)
+bitmap_set_bit (components, 2);
 return components;
 }
 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB.  */
 static sbitmap
 if (bitmap_bit_p (in, LR_REGNO)
 || bitmap_bit_p (gen, LR_REGNO)
 || bitmap_bit_p (kill, LR_REGNO))
 bitmap_set_bit (components, 0);
+/* The TOC save.  */
+if (bitmap_bit_p (in, TOC_REGNUM)
+|| bitmap_bit_p (gen, TOC_REGNUM)
+|| bitmap_bit_p (kill, TOC_REGNUM))
+bitmap_set_bit (components, 2);
 return components;
 }
 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.  */
 static void
 			     ? HARD_FRAME_POINTER_REGNUM
 			     : STACK_POINTER_REGNUM);
 machine_mode reg_mode = Pmode;
 int reg_size = TARGET_32BIT ? 4 : 8;
-machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
-			     ? DFmode : SFmode;
 int fp_reg_size = 8;
 /* Prologue for LR.  */
 if (bitmap_bit_p (components, 0))
 {
+rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
 rtx reg = gen_rtx_REG (reg_mode, 0);
-rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
+rtx_insn *insn = emit_move_insn (reg, lr);
 RTX_FRAME_RELATED_P (insn) = 1;
-add_reg_note (insn, REG_CFA_REGISTER, NULL);
+add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
 int offset = info->lr_save_offset;
 if (info->push_p)
 	offset += info->total_size;
 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
 RTX_FRAME_RELATED_P (insn) = 1;
-rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
+}
+/* Prologue for TOC.  */
+if (bitmap_bit_p (components, 2))
+{
+rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
+rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
+emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
 }
 /* Prologue for the GPRs.  */
 int offset = info->gp_save_offset;
 if (info->push_p)
 			     : STACK_POINTER_REGNUM);
 machine_mode reg_mode = Pmode;
 int reg_size = TARGET_32BIT ? 4 : 8;
-machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
-			     ? DFmode : SFmode;
 int fp_reg_size = 8;
 /* Epilogue for the FPRs.  */
 int offset = info->fp_save_offset;
 if (info->push_p)
 if (bitmap_bit_p (components, i))
 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
 if (bitmap_bit_p (components, 0))
 cfun->machine->lr_is_wrapped_separately = true;
+if (bitmap_bit_p (components, 2))
+cfun->machine->toc_is_wrapped_separately = true;
 }
 /* VRSAVE is a bit vector representing which AltiVec registers
 are used.  The OS uses this to determine which vector
 registers to save on a context switch.  We need to save
 rs6000_emit_prologue (void)
 {
 rs6000_stack_t *info = rs6000_stack_info ();
 machine_mode reg_mode = Pmode;
 int reg_size = TARGET_32BIT ? 4 : 8;
-machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
-			     ? DFmode : SFmode;
 int fp_reg_size = 8;
 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
 rtx frame_reg_rtx = sp_reg_rtx;
 unsigned int cr_save_regno;
 rtx cr_save_rtx = NULL_RTX;
 							    "*save_world"));
 /* We do floats first so that the instruction pattern matches
 	 properly.  */
 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
 	RTVEC_ELT (p, j++)
-	  = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+	  = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
-					  ? DFmode : SFmode,
 					  info->first_fp_reg_save + i),
 			     frame_reg_rtx,
 			     info->fp_save_offset + frame_off + 8 * i);
 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
 	RTVEC_ELT (p, j++)
 a shared library.  This behavior is costly to describe in DWARF,
 both in terms of the size of DWARF info and the time taken in the
 unwinder to interpret it.  R2 changes, apart from the
 calls_eh_return case earlier in this function, are handled by
 linux-unwind.h frob_update_context.  */
-if (rs6000_save_toc_in_prologue_p ())
+if (rs6000_save_toc_in_prologue_p ()
+&& !cfun->machine->toc_is_wrapped_separately)
 {
 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
 }
 rtx cfa_restores = NULL_RTX;
 rtx insn;
 rtx cr_save_reg = NULL_RTX;
 machine_mode reg_mode = Pmode;
 int reg_size = TARGET_32BIT ? 4 : 8;
-machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
-			     ? DFmode : SFmode;
 int fp_reg_size = 8;
 int i;
 bool exit_func;
 unsigned ptr_regno;
 strategy = info->savres_strategy;
 using_load_multiple = strategy & REST_MULTIPLE;
 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
-using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
+using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
-			 || rs6000_cpu == PROCESSOR_PPC603
+			 || rs6000_tune == PROCESSOR_PPC603
-			 || rs6000_cpu == PROCESSOR_PPC750
+			 || rs6000_tune == PROCESSOR_PPC750
 			 || optimize_size);
 /* Restore via the backchain when we have a large frame, since this
 is more efficient than an addis, addi pair.  The second condition
 here will not trigger at the moment;  We don't actually need a
 frame pointer for alloca, but the generic parts of the compiler
 	      && save_reg_p (info->first_altivec_reg_save + i))
 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
 	}
 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
 	{
-	  rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+	  rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
-				  ? DFmode : SFmode),
 				 info->first_fp_reg_save + i);
 	  RTVEC_ELT (p, j++)
 	    = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
 	  if (flag_shrink_wrap
 	      && save_reg_p (info->first_fp_reg_save + i))
 fputs ("\t.byte 0,", file);
 /* Language type.  Unfortunately, there does not seem to be any
 	 official way to discover the language being compiled, so we
 	 use language_string.
-	 C is 0.  Fortran is 1.  Pascal is 2.  Ada is 3.  C++ is 9.
+	 C is 0.  Fortran is 1.  Ada is 3.  C++ is 9.
 	 Java is 13.  Objective-C is 14.  Objective-C++ isn't assigned
 	 a number, so for now use 9.  LTO, Go and JIT aren't assigned numbers
 	 either, so for now use 0.  */
 if (lang_GNU_C ()
 	  || ! strcmp (language_string, "GNU GIMPLE")
 	  || ! strcmp (language_string, "libgccjit"))
 	i = 0;
 else if (! strcmp (language_string, "GNU F77")
 	       || lang_GNU_Fortran ())
 	i = 1;
-else if (! strcmp (language_string, "GNU Pascal"))
-	i = 2;
 else if (! strcmp (language_string, "GNU Ada"))
 	i = 3;
 else if (lang_GNU_CXX ()
 	       || ! strcmp (language_string, "GNU Objective-C++"))
 	i = 9;
 			     gen_rtx_REG (Pmode, 12));
 	  push_topmost_sequence ();
 	  emit_insn_after (pat, get_insns ());
 	  pop_topmost_sequence ();
 	}
-return plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
+rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
-			    FIRST_PARM_OFFSET (current_function_decl));
+			       FIRST_PARM_OFFSET (current_function_decl));
+return copy_to_reg (ret);
 }
 return virtual_incoming_args_rtx;
 }
 /* We may have to tell the dataflow pass that the split stack prologue
 cached_can_issue_more = more - 1;
 return cached_can_issue_more;
 }
-if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
+if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
 return 0;
 cached_can_issue_more = more - 1;
 return cached_can_issue_more;
 }
 {
 /* Data dependency; DEP_INSN writes a register that INSN reads
 	   some cycles later.  */
 	/* Separate a load from a narrower, dependent store.  */
-	if ((rs6000_sched_groups || rs6000_cpu_attr == CPU_POWER9)
+	if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
 	    && GET_CODE (PATTERN (insn)) == SET
 	    && GET_CODE (PATTERN (dep_insn)) == SET
 	    && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
 	    && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
 	    && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
 to it, will be generated by reload.  */
 return 4;
 case TYPE_BRANCH:
 /* Leave some extra cycles between a compare and its
 dependent branch, to inhibit expensive mispredicts.  */
-if ((rs6000_cpu_attr == CPU_PPC603
+if ((rs6000_tune == PROCESSOR_PPC603
-|| rs6000_cpu_attr == CPU_PPC604
+|| rs6000_tune == PROCESSOR_PPC604
-|| rs6000_cpu_attr == CPU_PPC604E
+|| rs6000_tune == PROCESSOR_PPC604e
-|| rs6000_cpu_attr == CPU_PPC620
+|| rs6000_tune == PROCESSOR_PPC620
-|| rs6000_cpu_attr == CPU_PPC630
+|| rs6000_tune == PROCESSOR_PPC630
-|| rs6000_cpu_attr == CPU_PPC750
+|| rs6000_tune == PROCESSOR_PPC750
-|| rs6000_cpu_attr == CPU_PPC7400
+|| rs6000_tune == PROCESSOR_PPC7400
-|| rs6000_cpu_attr == CPU_PPC7450
+|| rs6000_tune == PROCESSOR_PPC7450
-|| rs6000_cpu_attr == CPU_PPCE5500
+|| rs6000_tune == PROCESSOR_PPCE5500
-|| rs6000_cpu_attr == CPU_PPCE6500
+|| rs6000_tune == PROCESSOR_PPCE6500
-|| rs6000_cpu_attr == CPU_POWER4
+|| rs6000_tune == PROCESSOR_POWER4
-|| rs6000_cpu_attr == CPU_POWER5
+|| rs6000_tune == PROCESSOR_POWER5
-		 || rs6000_cpu_attr == CPU_POWER7
+		 || rs6000_tune == PROCESSOR_POWER7
-		 || rs6000_cpu_attr == CPU_POWER8
+		 || rs6000_tune == PROCESSOR_POWER8
-		 || rs6000_cpu_attr == CPU_POWER9
+		 || rs6000_tune == PROCESSOR_POWER9
-|| rs6000_cpu_attr == CPU_CELL)
+|| rs6000_tune == PROCESSOR_CELL)
 && recog_memoized (dep_insn)
 && (INSN_CODE (dep_insn) >= 0))
 switch (get_attr_type (dep_insn))
 {
 case TYPE_CMP:
 case TYPE_FPCOMPARE:
 case TYPE_CR_LOGICAL:
-case TYPE_DELAYED_CR:
 		  return cost + 2;
 case TYPE_EXTS:
 case TYPE_MUL:
 		  if (get_attr_dot (dep_insn) == DOT_YES)
 		    return cost + 2;
 		}
 break;
 case TYPE_STORE:
 case TYPE_FPSTORE:
-if ((rs6000_cpu == PROCESSOR_POWER6)
+if ((rs6000_tune == PROCESSOR_POWER6)
 && recog_memoized (dep_insn)
 && (INSN_CODE (dep_insn) >= 0))
 {
 if (GET_CODE (PATTERN (insn)) != SET)
 }
 }
 	    break;
 case TYPE_LOAD:
-if ((rs6000_cpu == PROCESSOR_POWER6)
+if ((rs6000_tune == PROCESSOR_POWER6)
 && recog_memoized (dep_insn)
 && (INSN_CODE (dep_insn) >= 0))
 {
 /* Adjust the cost for the case where the value written
 }
 }
 break;
 case TYPE_FPLOAD:
-if ((rs6000_cpu == PROCESSOR_POWER6)
+if ((rs6000_tune == PROCESSOR_POWER6)
 && get_attr_update (insn) == UPDATE_NO
 && recog_memoized (dep_insn)
 && (INSN_CODE (dep_insn) >= 0)
 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
 return 2;
 break;
 case REG_DEP_OUTPUT:
 /* Output dependency; DEP_INSN writes a register that INSN writes some
 	 cycles later.  */
-if ((rs6000_cpu == PROCESSOR_POWER6)
+if ((rs6000_tune == PROCESSOR_POWER6)
 && recog_memoized (dep_insn)
 && (INSN_CODE (dep_insn) >= 0))
 {
 attr_type = get_attr_type (insn);
 if (!insn || !NONDEBUG_INSN_P (insn)
 || GET_CODE (PATTERN (insn)) == USE
 || GET_CODE (PATTERN (insn)) == CLOBBER)
 return false;
-if (rs6000_cpu_attr == CPU_CELL)
+if (rs6000_tune == PROCESSOR_CELL)
 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
 if (rs6000_sched_groups
-&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
+&& (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
 {
 enum attr_type type = get_attr_type (insn);
 if ((type == TYPE_LOAD
 	   && get_attr_update (insn) == UPDATE_YES
 	   && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
 || GET_CODE (PATTERN (insn)) == USE
 || GET_CODE (PATTERN (insn)) == CLOBBER)
 return false;
 if (rs6000_sched_groups
-&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
+&& (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
 {
 enum attr_type type = get_attr_type (insn);
 if ((type == TYPE_LOAD
 	   && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
 	   && get_attr_update (insn) == UPDATE_NO)
 	  || (type == TYPE_STORE
 	      && get_attr_update (insn) == UPDATE_YES
 	      && get_attr_indexed (insn) == INDEXED_NO)
 	  || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
 	      && get_attr_update (insn) == UPDATE_YES)
-	  || type == TYPE_DELAYED_CR
+	  || (type == TYPE_CR_LOGICAL
+	      && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
 	  || (type == TYPE_EXTS
 	      && get_attr_dot (insn) == DOT_YES)
 	  || (type == TYPE_SHIFT
 	      && get_attr_dot (insn) == DOT_YES
 	      && get_attr_var_shift (insn) == VAR_SHIFT_NO)
 return priority;
 if (GET_CODE (PATTERN (insn)) == USE)
 return priority;
-switch (rs6000_cpu_attr) {
+switch (rs6000_tune) {
-case CPU_PPC750:
+case PROCESSOR_PPC750:
 switch (get_attr_type (insn))
 {
 default:
 	break;
 	   haifa-sched.c:ready_sort(), only 'priority' (critical path)
 	   considerations precede dispatch-slot restriction considerations.  */
 	return (priority + 1);
 }
-if (rs6000_cpu == PROCESSOR_POWER6
+if (rs6000_tune == PROCESSOR_POWER6
 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
 /* Attach highest priority to insn if the scheduler has just issued two
 stores and this instruction is a load, or two loads and this instruction
 is a store. Power6 wants loads and stores scheduled alternately
 /* Unless scheduling for register pressure, use issue rate of 1 for
 first scheduling pass to decrease degradation.  */
 if (!reload_completed && !flag_sched_pressure)
 return 1;
-switch (rs6000_cpu_attr) {
+switch (rs6000_tune) {
-case CPU_RS64A:
+case PROCESSOR_RS64A:
-case CPU_PPC601: /* ? */
+case PROCESSOR_PPC601: /* ? */
-case CPU_PPC7450:
+case PROCESSOR_PPC7450:
 return 3;
-case CPU_PPC440:
+case PROCESSOR_PPC440:
-case CPU_PPC603:
+case PROCESSOR_PPC603:
-case CPU_PPC750:
+case PROCESSOR_PPC750:
-case CPU_PPC7400:
+case PROCESSOR_PPC7400:
-case CPU_PPC8540:
+case PROCESSOR_PPC8540:
-case CPU_PPC8548:
+case PROCESSOR_PPC8548:
-case CPU_CELL:
+case PROCESSOR_CELL:
-case CPU_PPCE300C2:
+case PROCESSOR_PPCE300C2:
-case CPU_PPCE300C3:
+case PROCESSOR_PPCE300C3:
-case CPU_PPCE500MC:
+case PROCESSOR_PPCE500MC:
-case CPU_PPCE500MC64:
+case PROCESSOR_PPCE500MC64:
-case CPU_PPCE5500:
+case PROCESSOR_PPCE5500:
-case CPU_PPCE6500:
+case PROCESSOR_PPCE6500:
-case CPU_TITAN:
+case PROCESSOR_TITAN:
 return 2;
-case CPU_PPC476:
+case PROCESSOR_PPC476:
-case CPU_PPC604:
+case PROCESSOR_PPC604:
-case CPU_PPC604E:
+case PROCESSOR_PPC604e:
-case CPU_PPC620:
+case PROCESSOR_PPC620:
-case CPU_PPC630:
+case PROCESSOR_PPC630:
 return 4;
-case CPU_POWER4:
+case PROCESSOR_POWER4:
-case CPU_POWER5:
+case PROCESSOR_POWER5:
-case CPU_POWER6:
+case PROCESSOR_POWER6:
-case CPU_POWER7:
+case PROCESSOR_POWER7:
 return 5;
-case CPU_POWER8:
+case PROCESSOR_POWER8:
 return 7;
-case CPU_POWER9:
+case PROCESSOR_POWER9:
 return 6;
 default:
 return 1;
 }
 }
 scheduling.  */
 static int
 rs6000_use_sched_lookahead (void)
 {
-switch (rs6000_cpu_attr)
+switch (rs6000_tune)
 {
-case CPU_PPC8540:
+case PROCESSOR_PPC8540:
-case CPU_PPC8548:
+case PROCESSOR_PPC8548:
 return 4;
-case CPU_CELL:
+case PROCESSOR_CELL:
 return (reload_completed ? 8 : 0);
 default:
 return 0;
 }
 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
 {
 if (ready_index == 0)
 return 0;
-if (rs6000_cpu_attr != CPU_CELL)
+if (rs6000_tune != PROCESSOR_CELL)
 return 0;
 gcc_assert (insn != NULL_RTX && INSN_P (insn));
 if (!reload_completed
 if (sched_verbose)
 fprintf (dump, "// rs6000_sched_reorder :\n");
 /* Reorder the ready list, if the second to last ready insn
 is a nonepipeline insn.  */
-if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
+if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
 {
 if (is_nonpipeline_insn (ready[n_ready - 1])
 && (recog_memoized (ready[n_ready - 2]) > 0))
 /* Simply swap first two insns.  */
 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
 }
-if (rs6000_cpu == PROCESSOR_POWER6)
+if (rs6000_tune == PROCESSOR_POWER6)
 load_store_pendulum = 0;
 return rs6000_issue_rate ();
 }
 load/store instructions which make use of the LSU and which
 would need to be accounted for to strictly model the behavior
 of the machine.  Those instructions are currently unaccounted
 for to help minimize compile time overhead of this code.
 */
-if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
+if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
 {
 int pos;
 int i;
 rtx_insn *tmp;
 rtx load_mem, str_mem;
 }
 }
 }
 /* Do Power9 dependent reordering if necessary.  */
-if (rs6000_cpu == PROCESSOR_POWER9 && last_scheduled_insn
+if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
 && recog_memoized (last_scheduled_insn) >= 0)
 return power9_sched_reorder2 (ready, *pn_ready - 1);
 return cached_can_issue_more;
 }
 || DEBUG_INSN_P (insn)
 || GET_CODE (PATTERN (insn)) == USE
 || GET_CODE (PATTERN (insn)) == CLOBBER)
 return false;
-switch (rs6000_cpu)
+switch (rs6000_tune)
 {
 case PROCESSOR_POWER5:
 if (is_cracked_insn (insn))
 return true;
 /* FALLTHRU */
 switch (type)
 {
 case TYPE_MFCR:
 case TYPE_MFCRF:
 case TYPE_MTCR:
-case TYPE_DELAYED_CR:
 case TYPE_CR_LOGICAL:
 case TYPE_MTJMPR:
 case TYPE_MFJMPR:
 case TYPE_DIV:
 case TYPE_LOAD_L:
 type = get_attr_type (insn);
 switch (type)
 {
 case TYPE_CR_LOGICAL:
-case TYPE_DELAYED_CR:
 case TYPE_MFCR:
 case TYPE_MFCRF:
 case TYPE_MTCR:
 case TYPE_SYNC:
 case TYPE_ISYNC:
 || DEBUG_INSN_P (insn)
 || GET_CODE (PATTERN (insn)) == USE
 || GET_CODE (PATTERN (insn)) == CLOBBER)
 return false;
-switch (rs6000_cpu) {
+switch (rs6000_tune) {
 case PROCESSOR_POWER4:
 case PROCESSOR_POWER5:
 if (is_microcoded_insn (insn))
 return true;
 	 will be forced to the new group.  */
 if (can_issue_more && !is_branch_slot_insn (next_insn))
 	can_issue_more--;
 /* Do we have a special group ending nop? */
-if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
+if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
-	  || rs6000_cpu_attr == CPU_POWER8)
+	  || rs6000_tune == PROCESSOR_POWER8)
 	{
 	  nop = gen_group_ending_nop ();
 	  emit_insn_before (nop, next_insn);
 	  can_issue_more = 0;
 	}
 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
 return NULL_TREE;
 }
-/* AltiVec defines four built-in scalar types that serve as vector
+/* AltiVec defines five built-in scalar types that serve as vector
-elements; we must teach the compiler how to mangle them.  */
+elements; we must teach the compiler how to mangle them.  The 128-bit
+floating point mangling is target-specific as well.  */
 static const char *
 rs6000_mangle_type (const_tree type)
 {
 type = TYPE_MAIN_VARIANT (type);
 if (type == bool_char_type_node) return "U6__boolc";
 if (type == bool_short_type_node) return "U6__bools";
 if (type == pixel_type_node) return "u7__pixel";
 if (type == bool_int_type_node) return "U6__booli";
-if (type == bool_long_type_node) return "U6__booll";
+if (type == bool_long_long_type_node) return "U6__boolx";
-/* Use a unique name for __float128 rather than trying to use "e" or "g". Use
+if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
-"g" for IBM extended double, no matter whether it is long double (using
--mabi=ibmlongdouble) or the distinct __ibm128 type.  */
-if (TARGET_FLOAT128_TYPE)
-{
-if (type == ieee128_float_type_node)
-	return "U10__float128";
-if (TARGET_LONG_DOUBLE_128)
-	{
-	  if (type == long_double_type_node)
-	    return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
-	  if (type == ibm128_float_type_node)
-	    return "g";
-	}
-}
-/* Mangle IBM extended float long double as `g' (__float128) on
-powerpc*-linux where long-double-64 previously was the default.  */
-if (TYPE_MAIN_VARIANT (type) == long_double_type_node
-&& TARGET_ELF
-&& TARGET_LONG_DOUBLE_128
-&& !TARGET_IEEEQUAD)
 return "g";
+if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
-/* For all other types, use normal C++ mangling.  */
+return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
+/* For all other types, use the default mangling.  */
 return NULL;
 }
 /* Handle a "longcall" or "shortcall" attribute; arguments as in
 struct attribute_spec.handler.  */
 	  || strcmp (section, ".PPC.EMB.sbss0") == 0)
 	return true;
 }
 else
 {
+/* If we are told not to put readonly data in sdata, then don't.  */
+if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
+	  && !rs6000_readonly_in_sdata)
+	return false;
 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
 if (size > 0
 	  && size <= g_switch_value
 	  /* If it's not public, and we're not going to reference it there,
 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
 && rs6000_passes_float)
 {
 int fp;
-if (TARGET_DF_FPR)
+if (TARGET_HARD_FLOAT)
 	fp = 1;
-else if (TARGET_SF_FPR)
-	fp = 3;
 else
 	fp = 2;
 if (rs6000_passes_long_double)
 	{
 	  if (!TARGET_LONG_DOUBLE_128)
 static const char * const visibility_types[] = {
 "", ",protected", ",hidden", ",internal"
 };
 enum symbol_visibility vis = DECL_VISIBILITY (decl);
-if (TREE_CODE (decl) == FUNCTION_DECL
-&& cgraph_node::get (decl)
-&& cgraph_node::get (decl)->instrumentation_clone
-&& cgraph_node::get (decl)->instrumented_version)
-vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
 return visibility_types[vis];
 }
 #endif
 	  && (outer_code == NEG || outer_code == PLUS))
 	{
 	  *total = COSTS_N_INSNS (1);
 	  return true;
 	}
+/* FALLTHRU */
+case GT:
+case LT:
+case UNORDERED:
 if (outer_code == SET)
 	{
 	  if (XEXP (x, 1) == const0_rtx)
 	    {
-	      if (TARGET_ISEL && !TARGET_MFCRF)
+	      *total = COSTS_N_INSNS (2);
-		*total = COSTS_N_INSNS (8);
-	      else
-		*total = COSTS_N_INSNS (2);
 	      return true;
 	    }
 	  else
 	    {
 	      *total = COSTS_N_INSNS (3);
 	      return false;
 	    }
-	}
-/* FALLTHRU */
-case GT:
-case LT:
-case UNORDERED:
-if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
-	{
-	  if (TARGET_ISEL && !TARGET_MFCRF)
-	    *total = COSTS_N_INSNS (8);
-	  else
-	    *total = COSTS_N_INSNS (2);
-	  return true;
 	}
 /* CC COMPARE.  */
 if (outer_code == COMPARE)
 	{
 	  *total = 0;
 cost = n * rs6000_cost->ddiv;
 break;
 case TYPE_SYNC:
 case TYPE_LOAD_L:
+case TYPE_MFCR:
+case TYPE_MFCRF:
 cost = COSTS_N_INSNS (n + 2);
 break;
 default:
 cost = COSTS_N_INSNS (n);
 else if (rclass == CR_REGS)
 	ret = 4;
 /* For those processors that have slow LR/CTR moves, make them more
 expensive than memory in order to bias spills to memory .*/
-else if ((rs6000_cpu == PROCESSOR_POWER6
+else if ((rs6000_tune == PROCESSOR_POWER6
-		|| rs6000_cpu == PROCESSOR_POWER7
+		|| rs6000_tune == PROCESSOR_POWER7
-		|| rs6000_cpu == PROCESSOR_POWER8
+		|| rs6000_tune == PROCESSOR_POWER8
-		|| rs6000_cpu == PROCESSOR_POWER9)
+		|| rs6000_tune == PROCESSOR_POWER9)
 	       && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
 ret = 6 * hard_regno_nregs (0, mode);
 else
 	/* A move will cost one instruction per GPR moved.  */
 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
 }
 }
 /* Expand an Altivec constant permutation for little endian mode.
+OP0 and OP1 are the input vectors and TARGET is the output vector.
+SEL specifies the constant permutation vector.
 There are two issues: First, the two input operands must be
 swapped so that together they form a double-wide array in LE
 order.  Second, the vperm instruction has surprising behavior
 in LE mode:  it interprets the elements of the source vectors
 in BE mode ("left to right") and interprets the elements of
 we get the desired
 vr9  = 00000006 00000004 00000002 00000000.  */
-void
+static void
-altivec_expand_vec_perm_const_le (rtx operands[4])
+altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
+				  const vec_perm_indices &sel)
 {
 unsigned int i;
 rtx perm[16];
 rtx constv, unspec;
-rtx target = operands[0];
-rtx op0 = operands[1];
-rtx op1 = operands[2];
-rtx sel = operands[3];
 /* Unpack and adjust the constant selector.  */
 for (i = 0; i < 16; ++i)
 {
-rtx e = XVECEXP (sel, 0, i);
+unsigned int elt = 31 - (sel[i] & 31);
-unsigned int elt = 31 - (INTVAL (e) & 31);
 perm[i] = GEN_INT (elt);
 }
 /* Expand to a permute, swapping the inputs and using the
 adjusted selector.  */
 if (!REG_P (target))
 tmp = gen_reg_rtx (mode);
 if (TARGET_P9_VECTOR)
 {
-unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel),
+unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
 			       UNSPEC_VPERMR);
 }
 else
 {
 /* Invert the selector with a VNAND if available, else a VNOR.
 emit_move_insn (target, unspec);
 }
 /* Expand an Altivec constant permutation.  Return true if we match
-an efficient implementation; false to fall back to VPERM.  */
+an efficient implementation; false to fall back to VPERM.
-bool
+OP0 and OP1 are the input vectors and TARGET is the output vector.
-altivec_expand_vec_perm_const (rtx operands[4])
+SEL specifies the constant permutation vector.  */
+static bool
+altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+			       const vec_perm_indices &sel)
 {
 struct altivec_perm_insn {
 HOST_WIDE_INT mask;
 enum insn_code impl;
 unsigned char perm[16];
 {  4,  5,  6,  7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
 };
 unsigned int i, j, elt, which;
 unsigned char perm[16];
-rtx target, op0, op1, sel, x;
+rtx x;
 bool one_vec;
-target = operands[0];
-op0 = operands[1];
-op1 = operands[2];
-sel = operands[3];
 /* Unpack the constant selector.  */
 for (i = which = 0; i < 16; ++i)
 {
-rtx e = XVECEXP (sel, 0, i);
+elt = sel[i] & 31;
-elt = INTVAL (e) & 31;
 which |= (elt < 16 ? 1 : 2);
 perm[i] = elt;
 }
 /* Simplify the constant selector based on operands.  */
 	}
 }
 if (!BYTES_BIG_ENDIAN)
 {
-altivec_expand_vec_perm_const_le (operands);
+altivec_expand_vec_perm_const_le (target, op0, op1, sel);
 return true;
 }
 return false;
 }
-/* Expand a Paired Single or VSX Permute Doubleword constant permutation.
+/* Expand a VSX Permute Doubleword constant permutation.
 Return true if we match an efficient implementation.  */
 static bool
 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
 				unsigned char perm0, unsigned char perm1)
 emit_insn (gen_rtx_SET (target, x));
 }
 return true;
 }
-bool
+/* Implement TARGET_VECTORIZE_VEC_PERM_CONST.  */
-rs6000_expand_vec_perm_const (rtx operands[4])
-{
-rtx target, op0, op1, sel;
-unsigned char perm0, perm1;
-target = operands[0];
-op0 = operands[1];
-op1 = operands[2];
-sel = operands[3];
-/* Unpack the constant selector.  */
-perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
-perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
-return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
-}
-/* Test whether a constant permutation is supported.  */
 static bool
-rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
+rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
-{
+				 rtx op1, const vec_perm_indices &sel)
+{
+bool testing_p = !target;
 /* AltiVec (and thus VSX) can handle arbitrary permutations.  */
+if (TARGET_ALTIVEC && testing_p)
+return true;
+/* Check for ps_merge* or xxpermdi insns.  */
+if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
+{
+if (testing_p)
+	{
+	  op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
+	  op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
+	}
+if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
+	return true;
+}
 if (TARGET_ALTIVEC)
-return true;
+{
+/* Force the target-independent code to lower to V16QImode.  */
-/* Check for ps_merge* or evmerge* insns.  */
+if (vmode != V16QImode)
-if (TARGET_PAIRED_FLOAT && vmode == V2SFmode)
+	return false;
-{
+if (altivec_expand_vec_perm_const (target, op0, op1, sel))
-rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
+	return true;
-rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
-return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
 }
 return false;
 }
-/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.  */
+/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
+OP0 and OP1 are the input vectors and TARGET is the output vector.
+PERM specifies the constant permutation vector.  */
 static void
 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
-			   machine_mode vmode, unsigned nelt, rtx perm[])
+			   machine_mode vmode, const vec_perm_builder &perm)
 {
-machine_mode imode;
+rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
-rtx x;
-imode = vmode;
-if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
-imode = mode_for_int_vector (vmode).require ();
-x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
-x = expand_vec_perm (vmode, op0, op1, x, target);
 if (x != target)
 emit_move_insn (target, x);
 }
 /* Expand an extract even operation.  */
 void
 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
 {
 machine_mode vmode = GET_MODE (target);
 unsigned i, nelt = GET_MODE_NUNITS (vmode);
-rtx perm[16];
+vec_perm_builder perm (nelt, nelt, 1);
 for (i = 0; i < nelt; i++)
-perm[i] = GEN_INT (i * 2);
+perm.quick_push (i * 2);
-rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
+rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
 }
 /* Expand a vector interleave operation.  */
 void
 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
 {
 machine_mode vmode = GET_MODE (target);
 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
-rtx perm[16];
+vec_perm_builder perm (nelt, nelt, 1);
 high = (highp ? 0 : nelt / 2);
 for (i = 0; i < nelt / 2; i++)
 {
-perm[i * 2] = GEN_INT (i + high);
+perm.quick_push (i + high);
-perm[i * 2 + 1] = GEN_INT (i + nelt + high);
+perm.quick_push (i + nelt + high);
 }
-rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
+rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
 }
 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT.  */
 void
 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
 /* _Decimal128 must use an even/odd register pair.  */
 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
-	   && !FLOAT128_VECTOR_P (mode)
+	   && !FLOAT128_VECTOR_P (mode))
-	   && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
 regno = FP_ARG_RETURN;
 else if (TREE_CODE (valtype) == COMPLEX_TYPE
 	   && targetm.calls.split_complex_arg)
 return rs6000_complex_function_value (mode);
 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode.  Since the same
 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
 /* _Decimal128 must use an even/odd register pair.  */
 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
-else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
+else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
-	   && TARGET_HARD_FLOAT
-&& ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
 regno = FP_ARG_RETURN;
 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode.  Since the same
 return register is used in both cases, and we won't see V2DImode/V2DFmode
 for pure altivec, combine the two cases.  */
 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
 rs6000_eh_return_filter_mode (void)
 {
 return TARGET_32BIT ? SImode : word_mode;
 }
+/* Target hook for translate_mode_attribute.  */
+static machine_mode
+rs6000_translate_mode_attribute (machine_mode mode)
+{
+if ((FLOAT128_IEEE_P (mode)
+&& ieee128_float_type_node == long_double_type_node)
+|| (FLOAT128_IBM_P (mode)
+	  && ibm128_float_type_node == long_double_type_node))
+return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
+return mode;
+}
 /* Target hook for scalar_mode_supported_p.  */
 static bool
 rs6000_scalar_mode_supported_p (scalar_mode mode)
 {
 /* -m32 does not support TImode.  This is the default, from
 /* Target hook for vector_mode_supported_p.  */
 static bool
 rs6000_vector_mode_supported_p (machine_mode mode)
 {
-if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
-return true;
 /* There is no vector form for IEEE 128-bit.  If we return true for IEEE
 128-bit, the compiler might try to widen IEEE 128-bit to IBM
 double-double.  */
-else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
+if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
 return true;
 else
 return false;
 }
 { "powerpc-gpopt",		OPTION_MASK_PPC_GPOPT,		false, true  },
 { "quad-memory",		OPTION_MASK_QUAD_MEMORY,	false, true  },
 { "quad-memory-atomic",	OPTION_MASK_QUAD_MEMORY_ATOMIC,	false, true  },
 { "recip-precision",		OPTION_MASK_RECIP_PRECISION,	false, true  },
 { "save-toc-indirect",	OPTION_MASK_SAVE_TOC_INDIRECT,	false, true  },
-{ "string",			OPTION_MASK_STRING,		false, true  },
+{ "string",			0,				false, true  },
-{ "toc-fusion",		OPTION_MASK_TOC_FUSION,		false, true  },
 { "update",			OPTION_MASK_NO_UPDATE,		true , true  },
 { "vsx",			OPTION_MASK_VSX,		false, true  },
 #ifdef OPTION_MASK_64BIT
 #if TARGET_AIX_OS
 { "aix64",			OPTION_MASK_64BIT,		false, false },
 #endif
 #ifdef OPTION_MASK_STRICT_ALIGN
 { "strict-align",		OPTION_MASK_STRICT_ALIGN,	false, false },
 #endif
 { "soft-float",		OPTION_MASK_SOFT_FLOAT,		false, false },
-{ "string",			OPTION_MASK_STRING,		false, false },
+{ "string",			0,				false, false },
 };
 /* Builtin mask mapping for printing the flags.  */
 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
 {
 { "altivec",		 RS6000_BTM_ALTIVEC,	false, false },
 { "vsx",		 RS6000_BTM_VSX,	false, false },
-{ "paired",		 RS6000_BTM_PAIRED,	false, false },
 { "fre",		 RS6000_BTM_FRE,	false, false },
 { "fres",		 RS6000_BTM_FRES,	false, false },
 { "frsqrte",		 RS6000_BTM_FRSQRTE,	false, false },
 { "frsqrtes",		 RS6000_BTM_FRSQRTES,	false, false },
 { "popcntd",		 RS6000_BTM_POPCNTD,	false, false },
 { "crypto",		 RS6000_BTM_CRYPTO,	false, false },
 { "htm",		 RS6000_BTM_HTM,	false, false },
 { "hard-dfp",		 RS6000_BTM_DFP,	false, false },
 { "hard-float",	 RS6000_BTM_HARD_FLOAT,	false, false },
 { "long-double-128",	 RS6000_BTM_LDBL128,	false, false },
+{ "powerpc64",	 RS6000_BTM_POWERPC64,  false, false },
 { "float128",		 RS6000_BTM_FLOAT128,   false, false },
 { "float128-hw",	 RS6000_BTM_FLOAT128_HW,false, false },
 };
 /* Option variables that we want to support inside attribute((target)) and
 offsetof (struct gcc_options, x_TARGET_FRIZ),
 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
 { "avoid-indexed-addresses",
 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
-{ "paired",
-offsetof (struct gcc_options, x_rs6000_paired_float),
-offsetof (struct cl_target_option, x_rs6000_paired_float), },
 { "longcall",
 offsetof (struct gcc_options, x_rs6000_default_long_calls),
 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
 { "optimize-swaps",
 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
 { "sched-epilog",
 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
+{ "speculate-indirect-jumps",
+offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
+offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
 };
 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
 parsing.  Return true if there were no errors.  */
 {
 rtx addr;
 gcc_assert (MEM_P (x));
 addr = XEXP (x, 0);
-if (! legitimate_indirect_address_p (addr, reload_completed)
+if (can_create_pseudo_p ()
+&& ! legitimate_indirect_address_p (addr, reload_completed)
 && ! legitimate_indexed_address_p (addr, reload_completed))
 {
 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
 	{
 	  rtx reg = XEXP (addr, 0);
 	  emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
 	  addr = reg;
 	}
 x = replace_equiv_address (x, copy_addr_to_reg (addr));
-}
-return x;
-}
-/* Given a memory reference, if it is not in the form for altivec memory
-reference instructions (i.e. reg or reg+reg addressing with AND of -16),
-convert to the altivec format.  */
-rtx
-rs6000_address_for_altivec (rtx x)
-{
-gcc_assert (MEM_P (x));
-if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
-{
-rtx addr = XEXP (x, 0);
-if (!legitimate_indexed_address_p (addr, reload_completed)
-	  && !legitimate_indirect_address_p (addr, reload_completed))
-	addr = copy_to_mode_reg (Pmode, addr);
-addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
-x = change_address (x, GET_MODE (x), addr);
 }
 return x;
 }
 /* Emit the addis instruction that will be part of a fused instruction
 sequence.  */
 void
-emit_fusion_addis (rtx target, rtx addis_value, const char *comment,
+emit_fusion_addis (rtx target, rtx addis_value)
-		   const char *mode_name)
 {
 rtx fuse_ops[10];
-char insn_template[80];
 const char *addis_str = NULL;
-const char *comment_str = ASM_COMMENT_START;
-if (*comment_str == ' ')
-comment_str++;
 /* Emit the addis instruction.  */
 fuse_ops[0] = target;
 if (satisfies_constraint_L (addis_value))
 {
 }
 if (!addis_str)
 fatal_insn ("Could not generate addis value for fusion", addis_value);
-sprintf (insn_template, "%s\t\t%s %s, type %s", addis_str, comment_str,
+output_asm_insn (addis_str, fuse_ops);
-	   comment, mode_name);
-output_asm_insn (insn_template, fuse_ops);
 }
 /* Emit a D-form load or store instruction that is the second instruction
 of a fusion sequence.  */
 fatal_insn ("Unable to generate load/store offset for fusion", offset);
 return;
 }
-/* Wrap a TOC address that can be fused to indicate that special fusion
-processing is needed.  */
-rtx
-fusion_wrap_memory_address (rtx old_mem)
-{
-rtx old_addr = XEXP (old_mem, 0);
-rtvec v = gen_rtvec (1, old_addr);
-rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
-return replace_equiv_address_nv (old_mem, new_addr, false);
-}
 /* Given an address, convert it into the addis and load offset parts.  Addresses
 created during the peephole2 process look like:
 	(lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
-		(unspec [(...)] UNSPEC_TOCREL))
+		(unspec [(...)] UNSPEC_TOCREL))  */
-Addresses created via toc fusion look like:
-	(unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS))  */
 static void
 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
 {
 rtx hi, lo;
-if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
+if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
-{
-lo = XVECEXP (addr, 0, 0);
-hi = gen_rtx_HIGH (Pmode, lo);
-}
-else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
 {
 hi = XEXP (addr, 0);
 lo = XEXP (addr, 1);
 }
 else
 /* Return a string to fuse an addis instruction with a gpr load to the same
 register that we loaded up the addis instruction.  The address that is used
 is the logical address that was formed during peephole2:
 	(lo_sum (high) (low-part))
-Or the address is the TOC address that is wrapped before register allocation:
-	(unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
 The code is complicated, so we call output_asm_insn directly, and just
 return "".  */
 const char *
 emit_fusion_gpr_load (rtx target, rtx mem)
 {
 rtx addis_value;
 rtx addr;
 rtx load_offset;
 const char *load_str = NULL;
-const char *mode_name = NULL;
 machine_mode mode;
 if (GET_CODE (mem) == ZERO_EXTEND)
 mem = XEXP (mem, 0);
 /* Now emit the load instruction to the same register.  */
 mode = GET_MODE (mem);
 switch (mode)
 {
 case E_QImode:
-mode_name = "char";
 load_str = "lbz";
 break;
 case E_HImode:
-mode_name = "short";
 load_str = "lhz";
 break;
 case E_SImode:
 case E_SFmode:
-mode_name = (mode == SFmode) ? "float" : "int";
 load_str = "lwz";
 break;
 case E_DImode:
 case E_DFmode:
 gcc_assert (TARGET_POWERPC64);
-mode_name = (mode == DFmode) ? "double" : "long";
 load_str = "ld";
 break;
 default:
 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
 }
 /* Emit the addis instruction.  */
-emit_fusion_addis (target, addis_value, "gpr load fusion", mode_name);
+emit_fusion_addis (target, addis_value);
 /* Emit the D-form load instruction.  */
 emit_fusion_load_store (target, target, load_offset, load_str);
 return "";
 addr = XEXP (mem, 0);
 fusion_split_address (addr, &hi, &lo);
 /* Emit the addis instruction.  */
-emit_fusion_addis (tmp_reg, hi, "power9 load fusion", GET_MODE_NAME (mode));
+emit_fusion_addis (tmp_reg, hi);
 /* Emit the D-form load instruction.  */
 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
 return "";
 addr = XEXP (mem, 0);
 fusion_split_address (addr, &hi, &lo);
 /* Emit the addis instruction.  */
-emit_fusion_addis (tmp_reg, hi, "power9 store fusion", GET_MODE_NAME (mode));
+emit_fusion_addis (tmp_reg, hi);
 /* Emit the D-form load instruction.  */
 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
 return "";
 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
 }
 void
-rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
+rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
 {
 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
-rtx_tmp0 = gen_reg_rtx (V2DImode);
+rtx_tmp0 = gen_reg_rtx (V2DFmode);
-rtx_tmp1 = gen_reg_rtx (V2DImode);
+rtx_tmp1 = gen_reg_rtx (V2DFmode);
 /* The destination of the vmrgew instruction layout is:
 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
 vmrgew instruction will be correct.  */
-if (VECTOR_ELT_ORDER_BIG)
+if (BYTES_BIG_ENDIAN)
+{
+emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
+					    GEN_INT (0)));
+emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
+					    GEN_INT (3)));
+}
+else
+{
+emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
+emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
+}
+rtx_tmp2 = gen_reg_rtx (V4SFmode);
+rtx_tmp3 = gen_reg_rtx (V4SFmode);
+emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
+emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
+if (BYTES_BIG_ENDIAN)
+emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
+else
+emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
+}
+void
+rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
+{
+rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
+rtx_tmp0 = gen_reg_rtx (V2DImode);
+rtx_tmp1 = gen_reg_rtx (V2DImode);
+/* The destination of the vmrgew instruction layout is:
+rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
+Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
+vmrgew instruction will be correct.  */
+if (BYTES_BIG_ENDIAN)
 {
 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
 }
 else
 {
 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
 }
-if (VECTOR_ELT_ORDER_BIG)
+if (BYTES_BIG_ENDIAN)
 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
 else
 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
 }
 if (FRAME_GROWS_DOWNWARD)
 return 0;
 return RS6000_STARTING_FRAME_OFFSET;
 }
+/* Create an alias for a mangled name where we have changed the mangling (in
+GCC 8.1, we used U10__float128, and now we use u9__ieee128).  This is called
+via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME.  */
+#if TARGET_ELF && RS6000_WEAK
+static void
+rs6000_globalize_decl_name (FILE * stream, tree decl)
+{
+const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+targetm.asm_out.globalize_label (stream, name);
+if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
+{
+tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
+const char *old_name;
+ieee128_mangling_gcc_8_1 = true;
+lang_hooks.set_decl_assembler_name (decl);
+old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
+SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
+ieee128_mangling_gcc_8_1 = false;
+if (strcmp (name, old_name) != 0)
+	{
+	  fprintf (stream, "\t.weak %s\n", old_name);
+	  fprintf (stream, "\t.set %s,%s\n", old_name, name);
+	}
+}
+}
+#endif
+/* On 64-bit Linux and Freebsd systems, possibly switch the long double library
+function names from <foo>l to <foo>f128 if the default long double type is
+IEEE 128-bit.  Typically, with the C and C++ languages, the standard math.h
+include file switches the names on systems that support long double as IEEE
+128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
+In the future, glibc will export names like __ieee128_sinf128 and we can
+switch to using those instead of using sinf128, which pollutes the user's
+namespace.
+This will switch the names for Fortran math functions as well (which doesn't
+use math.h).  However, Fortran needs other changes to the compiler and
+library before you can switch the real*16 type at compile time.
+We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name.  We
+only do this if the default is that long double is IBM extended double, and
+the user asked for IEEE 128-bit.  */
+static tree
+rs6000_mangle_decl_assembler_name (tree decl, tree id)
+{
+if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
+&& TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
+{
+size_t len = IDENTIFIER_LENGTH (id);
+const char *name = IDENTIFIER_POINTER (id);
+if (name[len - 1] == 'l')
+	{
+	  bool uses_ieee128_p = false;
+	  tree type = TREE_TYPE (decl);
+	  machine_mode ret_mode = TYPE_MODE (type);
+	  /* See if the function returns a IEEE 128-bit floating point type or
+	     complex type.  */
+	  if (ret_mode == TFmode || ret_mode == TCmode)
+	    uses_ieee128_p = true;
+	  else
+	    {
+	      function_args_iterator args_iter;
+	      tree arg;
+	      /* See if the function passes a IEEE 128-bit floating point type
+		 or complex type.  */
+	      FOREACH_FUNCTION_ARGS (type, arg, args_iter)
+		{
+		  machine_mode arg_mode = TYPE_MODE (arg);
+		  if (arg_mode == TFmode || arg_mode == TCmode)
+		    {
+		      uses_ieee128_p = true;
+		      break;
+		    }
+		}
+	    }
+	  /* If we passed or returned an IEEE 128-bit floating point type,
+	     change the name.  */
+	  if (uses_ieee128_p)
+	    {
+	      char *name2 = (char *) alloca (len + 4);
+	      memcpy (name2, name, len - 1);
+	      strcpy (name2 + len - 1, "f128");
+	      id = get_identifier (name2);
+	    }
+	}
+}
+return id;
+}
 struct gcc_target targetm = TARGET_INITIALIZER;
 #include "gt-rs6000.h"

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/rs6000/rs6000.c @ 131:84e7813d76e9