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comparison gcc/config/rs6000/rs6000.h @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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111:04ced10e8804 131:84e7813d76e9
1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc. 2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify it 7 GCC is free software; you can redistribute it and/or modify it
26 /* Note that some other tm.h files include this one and then override 26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */ 27 many of the definitions. */
28 28
29 #ifndef RS6000_OPTS_H 29 #ifndef RS6000_OPTS_H
30 #include "config/rs6000/rs6000-opts.h" 30 #include "config/rs6000/rs6000-opts.h"
31 #endif
32
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
31 #endif 36 #endif
32 37
33 /* Definitions for the object file format. These are set at 38 /* Definitions for the object file format. These are set at
34 compile-time. */ 39 compile-time. */
35 40
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
66 #else 71 #else
67 #define PPC405_ERRATUM77 0 72 #define PPC405_ERRATUM77 0
68 #endif 73 #endif
69 74
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
72 #endif
73
74 #ifdef HAVE_AS_POPCNTB
75 #define ASM_CPU_POWER5_SPEC "-mpower5"
76 #else
77 #define ASM_CPU_POWER5_SPEC "-mpower4"
78 #endif
79
80 #ifdef HAVE_AS_DFP
81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
82 #else
83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
84 #endif
85
86 #ifdef HAVE_AS_POPCNTD
87 #define ASM_CPU_POWER7_SPEC "-mpower7"
88 #else
89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
90 #endif
91
92 #ifdef HAVE_AS_POWER8
93 #define ASM_CPU_POWER8_SPEC "-mpower8"
94 #else
95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
96 #endif
97
98 #ifdef HAVE_AS_POWER9
99 #define ASM_CPU_POWER9_SPEC "-mpower9"
100 #else
101 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC
102 #endif
103
104 #ifdef HAVE_AS_DCI
105 #define ASM_CPU_476_SPEC "-m476"
106 #else
107 #define ASM_CPU_476_SPEC "-mpower4"
108 #endif
109
110 /* Common ASM definitions used by ASM_SPEC among the various targets for 75 /* Common ASM definitions used by ASM_SPEC among the various targets for
111 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 76 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
112 provide the default assembler options if the user uses -mcpu=native, so if 77 provide the default assembler options if the user uses -mcpu=native, so if
113 you make changes here, make them also there. */ 78 you make changes here, make them also there. PR63177: Do not pass -mpower8
79 to the assembler if -mpower9-vector was also used. */
114 #define ASM_CPU_SPEC \ 80 #define ASM_CPU_SPEC \
115 "%{!mcpu*: \ 81 "%{!mcpu*: \
116 %{mpowerpc64*: -mppc64} \ 82 %{mpowerpc64*: -mppc64} \
117 %{!mpowerpc64*: %(asm_default)}} \ 83 %{!mpowerpc64*: %(asm_default)}} \
118 %{mcpu=native: %(asm_cpu_native)} \ 84 %{mcpu=native: %(asm_cpu_native)} \
119 %{mcpu=cell: -mcell} \ 85 %{mcpu=cell: -mcell} \
120 %{mcpu=power3: -mppc64} \ 86 %{mcpu=power3: -mppc64} \
121 %{mcpu=power4: -mpower4} \ 87 %{mcpu=power4: -mpower4} \
122 %{mcpu=power5: %(asm_cpu_power5)} \ 88 %{mcpu=power5: -mpower5} \
123 %{mcpu=power5+: %(asm_cpu_power5)} \ 89 %{mcpu=power5+: -mpower5} \
124 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 90 %{mcpu=power6: -mpower6 -maltivec} \
125 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 91 %{mcpu=power6x: -mpower6 -maltivec} \
126 %{mcpu=power7: %(asm_cpu_power7)} \ 92 %{mcpu=power7: -mpower7} \
127 %{mcpu=power8: %(asm_cpu_power8)} \ 93 %{mcpu=power8: %{!mpower9-vector: -mpower8}} \
128 %{mcpu=power9: %(asm_cpu_power9)} \ 94 %{mcpu=power9: -mpower9} \
129 %{mcpu=a2: -ma2} \ 95 %{mcpu=a2: -ma2} \
130 %{mcpu=powerpc: -mppc} \ 96 %{mcpu=powerpc: -mppc} \
131 %{mcpu=powerpc64le: %(asm_cpu_power8)} \ 97 %{mcpu=powerpc64le: -mpower8} \
132 %{mcpu=rs64a: -mppc64} \ 98 %{mcpu=rs64a: -mppc64} \
133 %{mcpu=401: -mppc} \ 99 %{mcpu=401: -mppc} \
134 %{mcpu=403: -m403} \ 100 %{mcpu=403: -m403} \
135 %{mcpu=405: -m405} \ 101 %{mcpu=405: -m405} \
136 %{mcpu=405fp: -m405} \ 102 %{mcpu=405fp: -m405} \
137 %{mcpu=440: -m440} \ 103 %{mcpu=440: -m440} \
138 %{mcpu=440fp: -m440} \ 104 %{mcpu=440fp: -m440} \
139 %{mcpu=464: -m440} \ 105 %{mcpu=464: -m440} \
140 %{mcpu=464fp: -m440} \ 106 %{mcpu=464fp: -m440} \
141 %{mcpu=476: %(asm_cpu_476)} \ 107 %{mcpu=476: -m476} \
142 %{mcpu=476fp: %(asm_cpu_476)} \ 108 %{mcpu=476fp: -m476} \
143 %{mcpu=505: -mppc} \ 109 %{mcpu=505: -mppc} \
144 %{mcpu=601: -m601} \ 110 %{mcpu=601: -m601} \
145 %{mcpu=602: -mppc} \ 111 %{mcpu=602: -mppc} \
146 %{mcpu=603: -mppc} \ 112 %{mcpu=603: -mppc} \
147 %{mcpu=603e: -mppc} \ 113 %{mcpu=603e: -mppc} \
169 %{mcpu=e500mc: -me500mc} \ 135 %{mcpu=e500mc: -me500mc} \
170 %{mcpu=e500mc64: -me500mc64} \ 136 %{mcpu=e500mc64: -me500mc64} \
171 %{mcpu=e5500: -me5500} \ 137 %{mcpu=e5500: -me5500} \
172 %{mcpu=e6500: -me6500} \ 138 %{mcpu=e6500: -me6500} \
173 %{maltivec: -maltivec} \ 139 %{maltivec: -maltivec} \
174 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ 140 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: -mpower7}} \
175 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ 141 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: -mpower8}} \
142 %{mpower9-vector: %{!mcpu*|mcpu=power8: -mpower9}} \
176 -many" 143 -many"
177 144
178 #define CPP_DEFAULT_SPEC "" 145 #define CPP_DEFAULT_SPEC ""
179 146
180 #define ASM_DEFAULT_SPEC "" 147 #define ASM_DEFAULT_SPEC ""
195 { "cpp_default", CPP_DEFAULT_SPEC }, \ 162 { "cpp_default", CPP_DEFAULT_SPEC }, \
196 { "asm_cpu", ASM_CPU_SPEC }, \ 163 { "asm_cpu", ASM_CPU_SPEC }, \
197 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 164 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
198 { "asm_default", ASM_DEFAULT_SPEC }, \ 165 { "asm_default", ASM_DEFAULT_SPEC }, \
199 { "cc1_cpu", CC1_CPU_SPEC }, \ 166 { "cc1_cpu", CC1_CPU_SPEC }, \
200 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
201 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
202 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
203 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
204 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \
205 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
206 SUBTARGET_EXTRA_SPECS 167 SUBTARGET_EXTRA_SPECS
207 168
208 /* -mcpu=native handling only makes sense with compiler running on 169 /* -mcpu=native handling only makes sense with compiler running on
209 an PowerPC chip. If changing this condition, also change 170 an PowerPC chip. If changing this condition, also change
210 the condition in driver-rs6000.c. */ 171 the condition in driver-rs6000.c. */
238 #ifndef HAVE_AS_MFCRF 199 #ifndef HAVE_AS_MFCRF
239 #undef TARGET_MFCRF 200 #undef TARGET_MFCRF
240 #define TARGET_MFCRF 0 201 #define TARGET_MFCRF 0
241 #endif 202 #endif
242 203
243 /* Define TARGET_POPCNTB if the target assembler does not support the
244 popcount byte instruction. */
245
246 #ifndef HAVE_AS_POPCNTB
247 #undef TARGET_POPCNTB
248 #define TARGET_POPCNTB 0
249 #endif
250
251 /* Define TARGET_FPRND if the target assembler does not support the
252 fp rounding instructions. */
253
254 #ifndef HAVE_AS_FPRND
255 #undef TARGET_FPRND
256 #define TARGET_FPRND 0
257 #endif
258
259 /* Define TARGET_CMPB if the target assembler does not support the
260 cmpb instruction. */
261
262 #ifndef HAVE_AS_CMPB
263 #undef TARGET_CMPB
264 #define TARGET_CMPB 0
265 #endif
266
267 /* Define TARGET_MFPGPR if the target assembler does not support the
268 mffpr and mftgpr instructions. */
269
270 #ifndef HAVE_AS_MFPGPR
271 #undef TARGET_MFPGPR
272 #define TARGET_MFPGPR 0
273 #endif
274
275 /* Define TARGET_DFP if the target assembler does not support decimal
276 floating point instructions. */
277 #ifndef HAVE_AS_DFP
278 #undef TARGET_DFP
279 #define TARGET_DFP 0
280 #endif
281
282 /* Define TARGET_POPCNTD if the target assembler does not support the
283 popcount word and double word instructions. */
284
285 #ifndef HAVE_AS_POPCNTD
286 #undef TARGET_POPCNTD
287 #define TARGET_POPCNTD 0
288 #endif
289
290 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
291 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
292 instructions. */
293
294 #ifndef HAVE_AS_POWER8
295 #undef TARGET_DIRECT_MOVE
296 #undef TARGET_CRYPTO
297 #undef TARGET_HTM
298 #undef TARGET_P8_VECTOR
299 #define TARGET_DIRECT_MOVE 0
300 #define TARGET_CRYPTO 0
301 #define TARGET_HTM 0
302 #define TARGET_P8_VECTOR 0
303 #endif
304
305 /* Define the ISA 3.0 flags as 0 if the target assembler does not support
306 Power9 instructions. Allow -mpower9-fusion, since it does not add new
307 instructions. Allow -misel, since it predates ISA 3.0 and does
308 not require any Power9 features. */
309
310 #ifndef HAVE_AS_POWER9
311 #undef TARGET_FLOAT128_HW
312 #undef TARGET_MODULO
313 #undef TARGET_P9_VECTOR
314 #undef TARGET_P9_MINMAX
315 #undef TARGET_P9_MISC
316 #define TARGET_FLOAT128_HW 0
317 #define TARGET_MODULO 0
318 #define TARGET_P9_VECTOR 0
319 #define TARGET_P9_MINMAX 0
320 #define TARGET_P9_MISC 0
321 #endif
322
323 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
324 not, generate the lwsync code as an integer constant. */
325 #ifdef HAVE_AS_LWSYNC
326 #define TARGET_LWSYNC_INSTRUCTION 1
327 #else
328 #define TARGET_LWSYNC_INSTRUCTION 0
329 #endif
330
331 /* Define TARGET_TLS_MARKERS if the target assembler does not support 204 /* Define TARGET_TLS_MARKERS if the target assembler does not support
332 arg markers for __tls_get_addr calls. */ 205 arg markers for __tls_get_addr calls. */
333 #ifndef HAVE_AS_TLS_MARKERS 206 #ifndef HAVE_AS_TLS_MARKERS
334 #undef TARGET_TLS_MARKERS 207 #undef TARGET_TLS_MARKERS
335 #define TARGET_TLS_MARKERS 0 208 #define TARGET_TLS_MARKERS 0
378 #endif 251 #endif
379 #else 252 #else
380 /* The option machinery will define this. */ 253 /* The option machinery will define this. */
381 #endif 254 #endif
382 255
383 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) 256 #define TARGET_DEFAULT (MASK_MULTIPLE)
384
385 /* FPU operations supported.
386 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
387 also test TARGET_HARD_FLOAT. */
388 #define TARGET_SINGLE_FLOAT 1
389 #define TARGET_DOUBLE_FLOAT 1
390 #define TARGET_SINGLE_FPU 0
391 #define TARGET_SIMPLE_FPU 0
392 #define TARGET_XILINX_FPU 0
393
394 /* Recast the processor type to the cpu attribute. */
395 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
396 257
397 /* Define generic processor types based upon current deployment. */ 258 /* Define generic processor types based upon current deployment. */
398 #define PROCESSOR_COMMON PROCESSOR_PPC601 259 #define PROCESSOR_COMMON PROCESSOR_PPC601
399 #define PROCESSOR_POWERPC PROCESSOR_PPC604 260 #define PROCESSOR_POWERPC PROCESSOR_PPC604
400 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 261 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
438 point. KFmode was added as a way to represent IEEE 128-bit floating point, 299 point. KFmode was added as a way to represent IEEE 128-bit floating point,
439 even if the default for long double is the IBM long double format. 300 even if the default for long double is the IBM long double format.
440 Similarly IFmode is the IBM long double format even if the default is IEEE 301 Similarly IFmode is the IBM long double format even if the default is IEEE
441 128-bit. Don't allow IFmode if -msoft-float. */ 302 128-bit. Don't allow IFmode if -msoft-float. */
442 #define FLOAT128_IEEE_P(MODE) \ 303 #define FLOAT128_IEEE_P(MODE) \
443 ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ 304 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
305 && ((MODE) == TFmode || (MODE) == TCmode)) \
444 || ((MODE) == KFmode) || ((MODE) == KCmode)) 306 || ((MODE) == KFmode) || ((MODE) == KCmode))
445 307
446 #define FLOAT128_IBM_P(MODE) \ 308 #define FLOAT128_IBM_P(MODE) \
447 ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ 309 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
310 && ((MODE) == TFmode || (MODE) == TCmode)) \
448 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 311 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
449 312
450 /* Helper macros to say whether a 128-bit floating point type can go in a 313 /* Helper macros to say whether a 128-bit floating point type can go in a
451 single vector register, or whether it needs paired scalar values. */ 314 single vector register, or whether it needs paired scalar values. */
452 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 315 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
524 #define VECTOR_ALIGN(MODE) \ 387 #define VECTOR_ALIGN(MODE) \
525 ((rs6000_vector_align[(MODE)] != 0) \ 388 ((rs6000_vector_align[(MODE)] != 0) \
526 ? rs6000_vector_align[(MODE)] \ 389 ? rs6000_vector_align[(MODE)] \
527 : (int)GET_MODE_BITSIZE ((MODE))) 390 : (int)GET_MODE_BITSIZE ((MODE)))
528 391
529 /* Determine the element order to use for vector instructions. By
530 default we use big-endian element order when targeting big-endian,
531 and little-endian element order when targeting little-endian. For
532 programs being ported from BE Power to LE Power, it can sometimes
533 be useful to use big-endian element order when targeting little-endian.
534 This is set via -maltivec=be, for example. */
535 #define VECTOR_ELT_ORDER_BIG \
536 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
537
538 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 392 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
539 with scalar instructions. */ 393 with scalar instructions. */
540 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 394 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
541 395
542 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 396 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
558 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 412 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
559 #else 413 #else
560 #define TARGET_ALIGN_NATURAL 0 414 #define TARGET_ALIGN_NATURAL 0
561 #endif 415 #endif
562 416
563 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 417 /* We use values 126..128 to pick the appropriate long double type (IFmode,
418 KFmode, TFmode). */
419 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
564 #define TARGET_IEEEQUAD rs6000_ieeequad 420 #define TARGET_IEEEQUAD rs6000_ieeequad
565 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 421 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
566 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 422 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
567 423
568 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 424 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
569 Enable 32-bit fcfid's on any of the switches for newer ISA machines or 425 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
570 XILINX. */
571 #define TARGET_FCFID (TARGET_POWERPC64 \ 426 #define TARGET_FCFID (TARGET_POWERPC64 \
572 || TARGET_PPC_GPOPT /* 970/power4 */ \ 427 || TARGET_PPC_GPOPT /* 970/power4 */ \
573 || TARGET_POPCNTB /* ISA 2.02 */ \ 428 || TARGET_POPCNTB /* ISA 2.02 */ \
574 || TARGET_CMPB /* ISA 2.05 */ \ 429 || TARGET_CMPB /* ISA 2.05 */ \
575 || TARGET_POPCNTD /* ISA 2.06 */ \ 430 || TARGET_POPCNTD) /* ISA 2.06 */
576 || TARGET_XILINX_FPU)
577 431
578 #define TARGET_FCTIDZ TARGET_FCFID 432 #define TARGET_FCTIDZ TARGET_FCFID
579 #define TARGET_STFIWX TARGET_PPC_GFXOPT 433 #define TARGET_STFIWX TARGET_PPC_GFXOPT
580 #define TARGET_LFIWAX TARGET_CMPB 434 #define TARGET_LFIWAX TARGET_CMPB
581 #define TARGET_LFIWZX TARGET_POPCNTD 435 #define TARGET_LFIWZX TARGET_POPCNTD
619 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 473 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
620 474
621 /* ISA 3.0 has new min/max functions that don't need fast math that are being 475 /* ISA 3.0 has new min/max functions that don't need fast math that are being
622 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 476 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
623 answers if the arguments are not in the normal range. */ 477 answers if the arguments are not in the normal range. */
624 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ 478 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
625 && (TARGET_P9_MINMAX || !flag_trapping_math)) 479 && (TARGET_P9_MINMAX || !flag_trapping_math))
626
627 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
628 && (TARGET_P9_MINMAX || !flag_trapping_math))
629 480
630 /* In switching from using target_flags to using rs6000_isa_flags, the options 481 /* In switching from using target_flags to using rs6000_isa_flags, the options
631 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 482 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
632 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 483 OPTION_MASK_<xxx> back into MASK_<xxx>. */
633 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 484 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
657 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 508 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
658 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 509 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
659 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 510 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
660 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 511 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
661 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 512 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
662 #define MASK_STRING OPTION_MASK_STRING
663 #define MASK_UPDATE OPTION_MASK_UPDATE 513 #define MASK_UPDATE OPTION_MASK_UPDATE
664 #define MASK_VSX OPTION_MASK_VSX 514 #define MASK_VSX OPTION_MASK_VSX
665 515
666 #ifndef IN_LIBGCC2 516 #ifndef IN_LIBGCC2
667 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 517 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
689 539
690 540
691 /* For power systems, we want to enable Altivec and VSX builtins even if the 541 /* For power systems, we want to enable Altivec and VSX builtins even if the
692 user did not use -maltivec or -mvsx to allow the builtins to be used inside 542 user did not use -maltivec or -mvsx to allow the builtins to be used inside
693 of #pragma GCC target or the target attribute to change the code level for a 543 of #pragma GCC target or the target attribute to change the code level for a
694 given system. The Paired builtins are only enabled if you configure the 544 given system. */
695 compiler for those builtins, and those machines don't support altivec or 545
696 VSX. */ 546 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
697 547 || TARGET_PPC_GPOPT /* 970/power4 */ \
698 #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ 548 || TARGET_POPCNTB /* ISA 2.02 */ \
699 && ((TARGET_POWERPC64 \ 549 || TARGET_CMPB /* ISA 2.05 */ \
700 || TARGET_PPC_GPOPT /* 970/power4 */ \ 550 || TARGET_POPCNTD /* ISA 2.06 */ \
701 || TARGET_POPCNTB /* ISA 2.02 */ \ 551 || TARGET_ALTIVEC \
702 || TARGET_CMPB /* ISA 2.05 */ \ 552 || TARGET_VSX \
703 || TARGET_POPCNTD /* ISA 2.06 */ \ 553 || TARGET_HARD_FLOAT)
704 || TARGET_ALTIVEC \
705 || TARGET_VSX \
706 || TARGET_HARD_FLOAT)))
707 554
708 /* E500 cores only support plain "sync", not lwsync. */ 555 /* E500 cores only support plain "sync", not lwsync. */
709 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 556 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
710 || rs6000_cpu == PROCESSOR_PPC8548) 557 || rs6000_cpu == PROCESSOR_PPC8548)
711 558
712 559
713 /* Whether SF/DF operations are supported by the normal floating point unit
714 (or the vector/scalar unit). */
715 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
716 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
717
718 /* Whether SF/DF operations are supported by any hardware. */
719 #define TARGET_SF_INSN TARGET_SF_FPR
720 #define TARGET_DF_INSN TARGET_DF_FPR
721
722 /* Which machine supports the various reciprocal estimate instructions. */ 560 /* Which machine supports the various reciprocal estimate instructions. */
723 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 561 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
724 && TARGET_SINGLE_FLOAT) 562
725 563 #define TARGET_FRE (TARGET_HARD_FLOAT \
726 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
727 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 564 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
728 565
729 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 566 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
730 && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) 567 && TARGET_PPC_GFXOPT)
731 568
732 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ 569 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
733 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 570 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
734
735 /* Conditions to allow TOC fusion for loading/storing integers. */
736 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
737 && TARGET_TOC_FUSION \
738 && (TARGET_CMODEL != CMODEL_SMALL) \
739 && TARGET_POWERPC64)
740
741 /* Conditions to allow TOC fusion for loading/storing floating point. */
742 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
743 && TARGET_TOC_FUSION \
744 && (TARGET_CMODEL != CMODEL_SMALL) \
745 && TARGET_POWERPC64 \
746 && TARGET_HARD_FLOAT \
747 && TARGET_SINGLE_FLOAT \
748 && TARGET_DOUBLE_FLOAT)
749 571
750 /* Macro to say whether we can do optimizations where we need to do parts of 572 /* Macro to say whether we can do optimizations where we need to do parts of
751 the calculation in 64-bit GPRs and then is transfered to the vector 573 the calculation in 64-bit GPRs and then is transfered to the vector
752 registers. Do not allow -maltivec=be for these optimizations, because it 574 registers. */
753 adds to the complexity of the code. */
754 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 575 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
755 && TARGET_P8_VECTOR \ 576 && TARGET_P8_VECTOR \
756 && TARGET_POWERPC64 \ 577 && TARGET_POWERPC64)
757 && (rs6000_altivec_element_order != 2))
758 578
759 /* Whether the various reciprocal divide/square root estimate instructions 579 /* Whether the various reciprocal divide/square root estimate instructions
760 exist, and whether we should automatically generate code for the instruction 580 exist, and whether we should automatically generate code for the instruction
761 by default. */ 581 by default. */
762 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 582 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
857 #define MIN_UNITS_PER_WORD 4 677 #define MIN_UNITS_PER_WORD 4
858 #endif 678 #endif
859 #define UNITS_PER_FP_WORD 8 679 #define UNITS_PER_FP_WORD 8
860 #define UNITS_PER_ALTIVEC_WORD 16 680 #define UNITS_PER_ALTIVEC_WORD 16
861 #define UNITS_PER_VSX_WORD 16 681 #define UNITS_PER_VSX_WORD 16
862 #define UNITS_PER_PAIRED_WORD 8
863 682
864 /* Type used for ptrdiff_t, as a string used in a declaration. */ 683 /* Type used for ptrdiff_t, as a string used in a declaration. */
865 #define PTRDIFF_TYPE "int" 684 #define PTRDIFF_TYPE "int"
866 685
867 /* Type used for size_t, as a string used in a declaration. */ 686 /* Type used for size_t, as a string used in a declaration. */
902 /* A C expression for the size in bits of the type `double' on the 721 /* A C expression for the size in bits of the type `double' on the
903 target machine. If you don't define this, the default is two 722 target machine. If you don't define this, the default is two
904 words. */ 723 words. */
905 #define DOUBLE_TYPE_SIZE 64 724 #define DOUBLE_TYPE_SIZE 64
906 725
907 /* A C expression for the size in bits of the type `long double' on 726 /* A C expression for the size in bits of the type `long double' on the target
908 the target machine. If you don't define this, the default is two 727 machine. If you don't define this, the default is two words. */
909 words. */
910 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 728 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
911 729
912 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 730 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
913 #define WIDEST_HARDWARE_FP_SIZE 64 731 #define WIDEST_HARDWARE_FP_SIZE 64
914 732
1132 /* not use fr14 which is a saved register. */ \ 950 /* not use fr14 which is a saved register. */ \
1133 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 951 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1134 33, \ 952 33, \
1135 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 953 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1136 50, 49, 48, 47, 46, \ 954 50, 49, 48, 47, 46, \
1137 75, 73, 74, 69, 68, 72, 71, 70, \ 955 68, 75, 73, 74, 69, 72, 71, 70, \
1138 MAYBE_R2_AVAILABLE \ 956 MAYBE_R2_AVAILABLE \
1139 9, 10, 8, 7, 6, 5, 4, \ 957 9, 10, 8, 7, 6, 5, 4, \
1140 3, EARLY_R12 11, 0, \ 958 3, EARLY_R12 11, 0, \
1141 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 959 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1142 18, 17, 16, 15, 14, 13, LATE_R12 \ 960 18, 17, 16, 15, 14, 13, LATE_R12 \
1163 981
1164 /* True if register is an integer register. */ 982 /* True if register is an integer register. */
1165 #define INT_REGNO_P(N) \ 983 #define INT_REGNO_P(N) \
1166 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 984 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1167 985
1168 /* PAIRED SIMD registers are just the FPRs. */
1169 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1170
1171 /* True if register is the CA register. */ 986 /* True if register is the CA register. */
1172 #define CA_REGNO_P(N) ((N) == CA_REGNO) 987 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1173 988
1174 /* True if register is an AltiVec register. */ 989 /* True if register is an AltiVec register. */
1175 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 990 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1225 || FLOAT128_VECTOR_P (MODE)) 1040 || FLOAT128_VECTOR_P (MODE))
1226 1041
1227 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1042 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1228 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1043 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1229 || (MODE) == V2DImode || (MODE) == V1TImode) 1044 || (MODE) == V2DImode || (MODE) == V1TImode)
1230
1231 #define PAIRED_VECTOR_MODE(MODE) \
1232 ((MODE) == V2SFmode)
1233 1045
1234 /* Post-reload, we can't use any new AltiVec registers, as we already 1046 /* Post-reload, we can't use any new AltiVec registers, as we already
1235 emitted the vrsave mask. */ 1047 emitted the vrsave mask. */
1236 1048
1237 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1049 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1566 machines. See `function.c' for details. 1378 machines. See `function.c' for details.
1567 1379
1568 This value must be a multiple of STACK_BOUNDARY (hard coded in 1380 This value must be a multiple of STACK_BOUNDARY (hard coded in
1569 `emit-rtl.c'). */ 1381 `emit-rtl.c'). */
1570 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1382 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1571 RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \ 1383 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1384 + STACK_POINTER_OFFSET, \
1572 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1385 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1573 1386
1574 /* If we generate an insn to push BYTES bytes, 1387 /* If we generate an insn to push BYTES bytes,
1575 this says how many the stack pointer really advances by. 1388 this says how many the stack pointer really advances by.
1576 On RS/6000, don't define this because there are no push insns. */ 1389 On RS/6000, don't define this because there are no push insns. */
2477 /* Convenience macros to document the instruction type. */ 2290 /* Convenience macros to document the instruction type. */
2478 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2291 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2479 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2292 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2480 2293
2481 /* Builtin targets. For now, we reuse the masks for those options that are in 2294 /* Builtin targets. For now, we reuse the masks for those options that are in
2482 target flags, and pick two random bits for paired and ldbl128, which 2295 target flags, and pick a random bit for ldbl128, which isn't in
2483 aren't in target_flags. */ 2296 target_flags. */
2484 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2297 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2485 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2298 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2486 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2299 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2487 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2300 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2488 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2301 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2489 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2302 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2490 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2303 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2491 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2304 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2492 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2305 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2493 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
2494 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2306 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2495 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2307 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2496 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2308 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2497 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2309 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2498 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2310 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2499 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2311 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2500 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2312 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2501 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2313 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2502 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2314 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2503 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2315 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2316 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2504 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2317 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2505 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2318 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2506 2319
2507 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2320 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2508 | RS6000_BTM_VSX \ 2321 | RS6000_BTM_VSX \
2519 | RS6000_BTM_POPCNTD \ 2332 | RS6000_BTM_POPCNTD \
2520 | RS6000_BTM_CELL \ 2333 | RS6000_BTM_CELL \
2521 | RS6000_BTM_DFP \ 2334 | RS6000_BTM_DFP \
2522 | RS6000_BTM_HARD_FLOAT \ 2335 | RS6000_BTM_HARD_FLOAT \
2523 | RS6000_BTM_LDBL128 \ 2336 | RS6000_BTM_LDBL128 \
2337 | RS6000_BTM_POWERPC64 \
2524 | RS6000_BTM_FLOAT128 \ 2338 | RS6000_BTM_FLOAT128 \
2525 | RS6000_BTM_FLOAT128_HW) 2339 | RS6000_BTM_FLOAT128_HW)
2526 2340
2527 /* Define builtin enum index. */ 2341 /* Define builtin enum index. */
2528 2342
2532 #undef RS6000_BUILTIN_3 2346 #undef RS6000_BUILTIN_3
2533 #undef RS6000_BUILTIN_A 2347 #undef RS6000_BUILTIN_A
2534 #undef RS6000_BUILTIN_D 2348 #undef RS6000_BUILTIN_D
2535 #undef RS6000_BUILTIN_H 2349 #undef RS6000_BUILTIN_H
2536 #undef RS6000_BUILTIN_P 2350 #undef RS6000_BUILTIN_P
2537 #undef RS6000_BUILTIN_Q
2538 #undef RS6000_BUILTIN_X 2351 #undef RS6000_BUILTIN_X
2539 2352
2540 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2353 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2541 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2354 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2542 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2355 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2543 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2356 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2544 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2357 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2545 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2358 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2546 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2359 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2547 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2360 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2548 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2549 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2361 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2550 2362
2551 enum rs6000_builtins 2363 enum rs6000_builtins
2552 { 2364 {
2553 #include "rs6000-builtin.def" 2365 #include "rs6000-builtin.def"
2561 #undef RS6000_BUILTIN_3 2373 #undef RS6000_BUILTIN_3
2562 #undef RS6000_BUILTIN_A 2374 #undef RS6000_BUILTIN_A
2563 #undef RS6000_BUILTIN_D 2375 #undef RS6000_BUILTIN_D
2564 #undef RS6000_BUILTIN_H 2376 #undef RS6000_BUILTIN_H
2565 #undef RS6000_BUILTIN_P 2377 #undef RS6000_BUILTIN_P
2566 #undef RS6000_BUILTIN_Q
2567 #undef RS6000_BUILTIN_X 2378 #undef RS6000_BUILTIN_X
2568 2379
2569 enum rs6000_builtin_type_index 2380 enum rs6000_builtin_type_index
2570 { 2381 {
2571 RS6000_BTI_NOT_OPAQUE, 2382 RS6000_BTI_NOT_OPAQUE,
2572 RS6000_BTI_opaque_V2SI,
2573 RS6000_BTI_opaque_V2SF,
2574 RS6000_BTI_opaque_p_V2SI,
2575 RS6000_BTI_opaque_V4SI, 2383 RS6000_BTI_opaque_V4SI,
2576 RS6000_BTI_V16QI, 2384 RS6000_BTI_V16QI, /* __vector signed char */
2577 RS6000_BTI_V1TI, 2385 RS6000_BTI_V1TI,
2578 RS6000_BTI_V2SI,
2579 RS6000_BTI_V2SF,
2580 RS6000_BTI_V2DI, 2386 RS6000_BTI_V2DI,
2581 RS6000_BTI_V2DF, 2387 RS6000_BTI_V2DF,
2582 RS6000_BTI_V4HI, 2388 RS6000_BTI_V4HI,
2583 RS6000_BTI_V4SI, 2389 RS6000_BTI_V4SI,
2584 RS6000_BTI_V4SF, 2390 RS6000_BTI_V4SF,
2585 RS6000_BTI_V8HI, 2391 RS6000_BTI_V8HI,
2586 RS6000_BTI_unsigned_V16QI, 2392 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2587 RS6000_BTI_unsigned_V1TI, 2393 RS6000_BTI_unsigned_V1TI,
2588 RS6000_BTI_unsigned_V8HI, 2394 RS6000_BTI_unsigned_V8HI,
2589 RS6000_BTI_unsigned_V4SI, 2395 RS6000_BTI_unsigned_V4SI,
2590 RS6000_BTI_unsigned_V2DI, 2396 RS6000_BTI_unsigned_V2DI,
2591 RS6000_BTI_bool_char, /* __bool char */ 2397 RS6000_BTI_bool_char, /* __bool char */
2592 RS6000_BTI_bool_short, /* __bool short */ 2398 RS6000_BTI_bool_short, /* __bool short */
2593 RS6000_BTI_bool_int, /* __bool int */ 2399 RS6000_BTI_bool_int, /* __bool int */
2594 RS6000_BTI_bool_long, /* __bool long */ 2400 RS6000_BTI_bool_long_long, /* __bool long long */
2595 RS6000_BTI_pixel, /* __pixel */ 2401 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2402 channels of 1, 5, 5, and 5 bits
2403 respectively as packed with the
2404 vpkpx insn. __pixel is only
2405 meaningful as a vector type.
2406 There is no corresponding scalar
2407 __pixel data type.) */
2596 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2408 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2597 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2409 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2598 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2410 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2599 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2411 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2600 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2412 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2601 RS6000_BTI_long, /* long_integer_type_node */ 2413 RS6000_BTI_long, /* long_integer_type_node */
2602 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2414 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2603 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2415 RS6000_BTI_long_long, /* long_long_integer_type_node */
2604 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2416 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2605 RS6000_BTI_INTQI, /* intQI_type_node */ 2417 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2606 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2418 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2607 RS6000_BTI_INTHI, /* intHI_type_node */ 2419 RS6000_BTI_INTHI, /* intHI_type_node */
2608 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2420 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2609 RS6000_BTI_INTSI, /* intSI_type_node */ 2421 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2610 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2422 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2611 RS6000_BTI_INTDI, /* intDI_type_node */ 2423 RS6000_BTI_INTDI, /* intDI_type_node */
2612 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2424 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2613 RS6000_BTI_INTTI, /* intTI_type_node */ 2425 RS6000_BTI_INTTI, /* intTI_type_node */
2614 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2426 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2623 RS6000_BTI_const_str, /* pointer to const char * */ 2435 RS6000_BTI_const_str, /* pointer to const char * */
2624 RS6000_BTI_MAX 2436 RS6000_BTI_MAX
2625 }; 2437 };
2626 2438
2627 2439
2628 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2629 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2630 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2631 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2440 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2632 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2441 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2633 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2442 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2634 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2443 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2635 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2444 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2636 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2637 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2638 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2445 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2639 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2446 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2640 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2447 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2641 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2448 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2642 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2449 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2645 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2452 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2646 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2453 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2647 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2454 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2648 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2455 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2649 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2456 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2650 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) 2457 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2651 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2458 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2652 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2459 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2653 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2460 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2654 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2461 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2655 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2462 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])