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comparison gcc/config/s390/vx-builtins.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 ;;- Instruction patterns for the System z vector facility builtins. 1 ;;- Instruction patterns for the System z vector facility builtins.
2 ;; Copyright (C) 2015-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 2015-2018 Free Software Foundation, Inc.
3 ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 3 ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify it under 7 ;; GCC is free software; you can redistribute it and/or modify it under
89 [(match_operand:VI_HW 0 "register_operand" "=v") 89 [(match_operand:VI_HW 0 "register_operand" "=v")
90 (match_operand:QI 1 "const_int_operand" "C") 90 (match_operand:QI 1 "const_int_operand" "C")
91 (match_operand:QI 2 "const_int_operand" "C")] 91 (match_operand:QI 2 "const_int_operand" "C")]
92 "TARGET_VX" 92 "TARGET_VX"
93 { 93 {
94 int nunits = GET_MODE_NUNITS (<VI_HW:MODE>mode);
95 int bitlen = GET_MODE_UNIT_BITSIZE (<VI_HW:MODE>mode); 94 int bitlen = GET_MODE_UNIT_BITSIZE (<VI_HW:MODE>mode);
96 /* To bit little endian style. */ 95 /* To bit little endian style. */
97 int end = bitlen - 1 - INTVAL (operands[1]); 96 int end = bitlen - 1 - INTVAL (operands[1]);
98 int start = bitlen - 1 - INTVAL (operands[2]); 97 int start = bitlen - 1 - INTVAL (operands[2]);
99 rtx const_vec[16];
100 int i; 98 int i;
101 unsigned HOST_WIDE_INT mask; 99 unsigned HOST_WIDE_INT mask;
102 bool swapped_p = false; 100 bool swapped_p = false;
103 101
104 if (start > end) 102 if (start > end)
114 mask &= ~((HOST_WIDE_INT_1U << start) - 1); 112 mask &= ~((HOST_WIDE_INT_1U << start) - 1);
115 113
116 if (swapped_p) 114 if (swapped_p)
117 mask = ~mask; 115 mask = ~mask;
118 116
119 for (i = 0; i < nunits; i++) 117 rtx mask_rtx = gen_int_mode (mask, GET_MODE_INNER (<VI_HW:MODE>mode));
120 const_vec[i] = GEN_INT (trunc_int_for_mode (mask,
121 GET_MODE_INNER (<VI_HW:MODE>mode)));
122 118
123 emit_insn (gen_rtx_SET (operands[0], 119 emit_insn (gen_rtx_SET (operands[0],
124 gen_rtx_CONST_VECTOR (<VI_HW:MODE>mode, 120 gen_const_vec_duplicate (<VI_HW:MODE>mode,
125 gen_rtvec_v (nunits, const_vec)))); 121 mask_rtx)));
126 DONE; 122 DONE;
127 }) 123 })
128 124
129 (define_expand "vec_genbytemaskv16qi" 125 (define_expand "vec_genbytemaskv16qi"
130 [(match_operand:V16QI 0 "register_operand" "") 126 [(match_operand:V16QI 0 "register_operand" "")
1621 rtx c; 1617 rtx c;
1622 1618
1623 real_2expN (&f, -INTVAL (operands[2]), DFmode); 1619 real_2expN (&f, -INTVAL (operands[2]), DFmode);
1624 c = const_double_from_real_value (f, DFmode); 1620 c = const_double_from_real_value (f, DFmode);
1625 1621
1626 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); 1622 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1627 operands[3] = force_reg (V2DFmode, operands[3]); 1623 operands[3] = force_reg (V2DFmode, operands[3]);
1628 }) 1624 })
1629 1625
1630 (define_insn "vcdlgb" 1626 (define_insn "vcdlgb"
1631 [(set (match_operand:V2DF 0 "register_operand" "=v") 1627 [(set (match_operand:V2DF 0 "register_operand" "=v")
1652 rtx c; 1648 rtx c;
1653 1649
1654 real_2expN (&f, -INTVAL (operands[2]), DFmode); 1650 real_2expN (&f, -INTVAL (operands[2]), DFmode);
1655 c = const_double_from_real_value (f, DFmode); 1651 c = const_double_from_real_value (f, DFmode);
1656 1652
1657 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); 1653 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1658 operands[3] = force_reg (V2DFmode, operands[3]); 1654 operands[3] = force_reg (V2DFmode, operands[3]);
1659 }) 1655 })
1660 1656
1661 (define_insn "vcgdb" 1657 (define_insn "vcgdb"
1662 [(set (match_operand:V2DI 0 "register_operand" "=v") 1658 [(set (match_operand:V2DI 0 "register_operand" "=v")
1684 rtx c; 1680 rtx c;
1685 1681
1686 real_2expN (&f, INTVAL (operands[2]), DFmode); 1682 real_2expN (&f, INTVAL (operands[2]), DFmode);
1687 c = const_double_from_real_value (f, DFmode); 1683 c = const_double_from_real_value (f, DFmode);
1688 1684
1689 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); 1685 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1690 operands[3] = force_reg (V2DFmode, operands[3]); 1686 operands[3] = force_reg (V2DFmode, operands[3]);
1691 operands[4] = gen_reg_rtx (V2DFmode); 1687 operands[4] = gen_reg_rtx (V2DFmode);
1692 }) 1688 })
1693 1689
1694 (define_insn "vclgdb" 1690 (define_insn "vclgdb"
1717 rtx c; 1713 rtx c;
1718 1714
1719 real_2expN (&f, INTVAL (operands[2]), DFmode); 1715 real_2expN (&f, INTVAL (operands[2]), DFmode);
1720 c = const_double_from_real_value (f, DFmode); 1716 c = const_double_from_real_value (f, DFmode);
1721 1717
1722 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c)); 1718 operands[3] = gen_const_vec_duplicate (V2DFmode, c);
1723 operands[3] = force_reg (V2DFmode, operands[3]); 1719 operands[3] = force_reg (V2DFmode, operands[3]);
1724 operands[4] = gen_reg_rtx (V2DFmode); 1720 operands[4] = gen_reg_rtx (V2DFmode);
1725 }) 1721 })
1726 1722
1727 ; Vector load fp integer - IEEE inexact exception is suppressed 1723 ; Vector load fp integer - IEEE inexact exception is suppressed