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comparison gcc/lra.c @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
comparison
equal deleted inserted replaced
111:04ced10e8804 131:84e7813d76e9
1 /* LRA (local register allocator) driver and LRA utilities. 1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc. 2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify it under 7 GCC is free software; you can redistribute it and/or modify it under
533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it 533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
534 is reference through subreg (SUBREG_P), flag that is early 534 is reference through subreg (SUBREG_P), flag that is early
535 clobbered in the insn (EARLY_CLOBBER), and reference to the next 535 clobbered in the insn (EARLY_CLOBBER), and reference to the next
536 insn reg info (NEXT). If REGNO can be early clobbered, 536 insn reg info (NEXT). If REGNO can be early clobbered,
537 alternatives in which it can be early clobbered are given by 537 alternatives in which it can be early clobbered are given by
538 EARLY_CLOBBER_ALTS. */ 538 EARLY_CLOBBER_ALTS. CLOBBER_HIGH marks if reference is a clobber
539 high. */
539 static struct lra_insn_reg * 540 static struct lra_insn_reg *
540 new_insn_reg (rtx_insn *insn, int regno, enum op_type type, 541 new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
541 machine_mode mode, 542 machine_mode mode,
542 bool subreg_p, bool early_clobber, 543 bool subreg_p, bool early_clobber,
543 alternative_mask early_clobber_alts, 544 alternative_mask early_clobber_alts,
544 struct lra_insn_reg *next) 545 struct lra_insn_reg *next, bool clobber_high)
545 { 546 {
546 lra_insn_reg *ir = lra_insn_reg_pool.allocate (); 547 lra_insn_reg *ir = lra_insn_reg_pool.allocate ();
547 ir->type = type; 548 ir->type = type;
548 ir->biggest_mode = mode; 549 ir->biggest_mode = mode;
549 if (NONDEBUG_INSN_P (insn) 550 if (NONDEBUG_INSN_P (insn)
550 && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode)) 551 && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
551 lra_reg_info[regno].biggest_mode = mode; 552 lra_reg_info[regno].biggest_mode = mode;
552 ir->subreg_p = subreg_p; 553 ir->subreg_p = subreg_p;
553 ir->early_clobber = early_clobber; 554 ir->early_clobber = early_clobber;
554 ir->early_clobber_alts = early_clobber_alts; 555 ir->early_clobber_alts = early_clobber_alts;
556 ir->clobber_high = clobber_high;
555 ir->regno = regno; 557 ir->regno = regno;
556 ir->next = next; 558 ir->next = next;
557 return ir; 559 return ir;
558 } 560 }
559 561
600 OP_IN, 602 OP_IN,
601 0, 0, 0, 0 603 0, 0, 0, 0
602 }; 604 };
603 605
604 /* The following data are used as static insn data for all debug 606 /* The following data are used as static insn data for all debug
605 insns. If structure lra_static_insn_data is changed, the 607 bind insns. If structure lra_static_insn_data is changed, the
606 initializer should be changed too. */ 608 initializer should be changed too. */
607 static struct lra_static_insn_data debug_insn_static_data = 609 static struct lra_static_insn_data debug_bind_static_data =
608 { 610 {
609 &debug_operand_data, 611 &debug_operand_data,
610 0, /* Duplication operands #. */ 612 0, /* Duplication operands #. */
611 -1, /* Commutative operand #. */ 613 -1, /* Commutative operand #. */
612 1, /* Operands #. There is only one operand which is debug RTL 614 1, /* Operands #. There is only one operand which is debug RTL
613 expression. */ 615 expression. */
616 0, /* Duplications #. */
617 0, /* Alternatives #. We are not interesting in alternatives
618 because we does not proceed debug_insns for reloads. */
619 NULL, /* Hard registers referenced in machine description. */
620 NULL /* Descriptions of operands in alternatives. */
621 };
622
623 /* The following data are used as static insn data for all debug
624 marker insns. If structure lra_static_insn_data is changed, the
625 initializer should be changed too. */
626 static struct lra_static_insn_data debug_marker_static_data =
627 {
628 &debug_operand_data,
629 0, /* Duplication operands #. */
630 -1, /* Commutative operand #. */
631 0, /* Operands #. There isn't any operand. */
614 0, /* Duplications #. */ 632 0, /* Duplications #. */
615 0, /* Alternatives #. We are not interesting in alternatives 633 0, /* Alternatives #. We are not interesting in alternatives
616 because we does not proceed debug_insns for reloads. */ 634 because we does not proceed debug_insns for reloads. */
617 NULL, /* Hard registers referenced in machine description. */ 635 NULL, /* Hard registers referenced in machine description. */
618 NULL /* Descriptions of operands in alternatives. */ 636 NULL /* Descriptions of operands in alternatives. */
803 821
804 /* Recursively process X and collect info about registers, which are 822 /* Recursively process X and collect info about registers, which are
805 not the insn operands, in X with TYPE (in/out/inout) and flag that 823 not the insn operands, in X with TYPE (in/out/inout) and flag that
806 it is early clobbered in the insn (EARLY_CLOBBER) and add the info 824 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
807 to LIST. X is a part of insn given by DATA. Return the result 825 to LIST. X is a part of insn given by DATA. Return the result
808 list. */ 826 list. CLOBBER_HIGH marks if X is a clobber high. */
809 static struct lra_insn_reg * 827 static struct lra_insn_reg *
810 collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, 828 collect_non_operand_hard_regs (rtx_insn *insn, rtx *x,
829 lra_insn_recog_data_t data,
811 struct lra_insn_reg *list, 830 struct lra_insn_reg *list,
812 enum op_type type, bool early_clobber) 831 enum op_type type, bool early_clobber,
832 bool clobber_high)
813 { 833 {
814 int i, j, regno, last; 834 int i, j, regno, last;
815 bool subreg_p; 835 bool subreg_p;
816 machine_mode mode; 836 machine_mode mode;
817 struct lra_insn_reg *curr; 837 struct lra_insn_reg *curr;
871 && ! (FIRST_STACK_REG <= regno 891 && ! (FIRST_STACK_REG <= regno
872 && regno <= LAST_STACK_REG)); 892 && regno <= LAST_STACK_REG));
873 #endif 893 #endif
874 list = new_insn_reg (data->insn, regno, type, mode, subreg_p, 894 list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
875 early_clobber, 895 early_clobber,
876 early_clobber ? ALL_ALTERNATIVES : 0, list); 896 early_clobber ? ALL_ALTERNATIVES : 0, list,
897 clobber_high);
877 } 898 }
878 } 899 }
879 return list; 900 return list;
880 } 901 }
881 switch (code) 902 switch (code)
882 { 903 {
883 case SET: 904 case SET:
884 list = collect_non_operand_hard_regs (&SET_DEST (op), data, 905 list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data,
885 list, OP_OUT, false); 906 list, OP_OUT, false, false);
886 list = collect_non_operand_hard_regs (&SET_SRC (op), data, 907 list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data,
887 list, OP_IN, false); 908 list, OP_IN, false, false);
888 break; 909 break;
889 case CLOBBER: 910 case CLOBBER:
890 /* We treat clobber of non-operand hard registers as early 911 /* We treat clobber of non-operand hard registers as early clobber. */
891 clobber (the behavior is expected from asm). */ 912 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
892 list = collect_non_operand_hard_regs (&XEXP (op, 0), data, 913 list, OP_OUT, true, false);
893 list, OP_OUT, true); 914 break;
915 case CLOBBER_HIGH:
916 /* Clobber high should always span exactly one register. */
917 gcc_assert (REG_NREGS (XEXP (op, 0)) == 1);
918 /* We treat clobber of non-operand hard registers as early clobber. */
919 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
920 list, OP_OUT, true, true);
894 break; 921 break;
895 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: 922 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
896 list = collect_non_operand_hard_regs (&XEXP (op, 0), data, 923 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
897 list, OP_INOUT, false); 924 list, OP_INOUT, false, false);
898 break; 925 break;
899 case PRE_MODIFY: case POST_MODIFY: 926 case PRE_MODIFY: case POST_MODIFY:
900 list = collect_non_operand_hard_regs (&XEXP (op, 0), data, 927 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
901 list, OP_INOUT, false); 928 list, OP_INOUT, false, false);
902 list = collect_non_operand_hard_regs (&XEXP (op, 1), data, 929 list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data,
903 list, OP_IN, false); 930 list, OP_IN, false, false);
904 break; 931 break;
905 default: 932 default:
906 fmt = GET_RTX_FORMAT (code); 933 fmt = GET_RTX_FORMAT (code);
907 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
908 { 935 {
909 if (fmt[i] == 'e') 936 if (fmt[i] == 'e')
910 list = collect_non_operand_hard_regs (&XEXP (op, i), data, 937 list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data,
911 list, OP_IN, false); 938 list, OP_IN, false, false);
912 else if (fmt[i] == 'E') 939 else if (fmt[i] == 'E')
913 for (j = XVECLEN (op, i) - 1; j >= 0; j--) 940 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
914 list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, 941 list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j),
915 list, OP_IN, false); 942 data, list, OP_IN, false,
943 false);
916 } 944 }
917 } 945 }
918 return list; 946 return list;
919 } 947 }
920 948
940 INSN_CODE (insn) = icode = recog_memoized (insn); 968 INSN_CODE (insn) = icode = recog_memoized (insn);
941 } 969 }
942 data = XNEW (struct lra_insn_recog_data); 970 data = XNEW (struct lra_insn_recog_data);
943 lra_insn_recog_data[uid] = data; 971 lra_insn_recog_data[uid] = data;
944 data->insn = insn; 972 data->insn = insn;
945 data->used_insn_alternative = -1; 973 data->used_insn_alternative = LRA_UNKNOWN_ALT;
946 data->icode = icode; 974 data->icode = icode;
947 data->regs = NULL; 975 data->regs = NULL;
948 if (DEBUG_INSN_P (insn)) 976 if (DEBUG_INSN_P (insn))
949 { 977 {
950 data->insn_static_data = &debug_insn_static_data;
951 data->dup_loc = NULL; 978 data->dup_loc = NULL;
952 data->arg_hard_regs = NULL; 979 data->arg_hard_regs = NULL;
953 data->preferred_alternatives = ALL_ALTERNATIVES; 980 data->preferred_alternatives = ALL_ALTERNATIVES;
954 data->operand_loc = XNEWVEC (rtx *, 1); 981 if (DEBUG_BIND_INSN_P (insn))
955 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); 982 {
983 data->insn_static_data = &debug_bind_static_data;
984 data->operand_loc = XNEWVEC (rtx *, 1);
985 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn);
986 }
987 else if (DEBUG_MARKER_INSN_P (insn))
988 {
989 data->insn_static_data = &debug_marker_static_data;
990 data->operand_loc = NULL;
991 }
956 return data; 992 return data;
957 } 993 }
958 if (icode < 0) 994 if (icode < 0)
959 { 995 {
960 int nop, nalt; 996 int nop, nalt;
1013 data->preferred_alternatives = ALL_ALTERNATIVES; 1049 data->preferred_alternatives = ALL_ALTERNATIVES;
1014 if (nop > 0) 1050 if (nop > 0)
1015 { 1051 {
1016 operand_alternative *op_alt = XCNEWVEC (operand_alternative, 1052 operand_alternative *op_alt = XCNEWVEC (operand_alternative,
1017 nalt * nop); 1053 nalt * nop);
1018 preprocess_constraints (nop, nalt, constraints, op_alt); 1054 preprocess_constraints (nop, nalt, constraints, op_alt,
1055 data->operand_loc);
1019 setup_operand_alternative (data, op_alt); 1056 setup_operand_alternative (data, op_alt);
1020 } 1057 }
1021 } 1058 }
1022 else 1059 else
1023 { 1060 {
1053 } 1090 }
1054 if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) 1091 if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE)
1055 insn_static_data->hard_regs = NULL; 1092 insn_static_data->hard_regs = NULL;
1056 else 1093 else
1057 insn_static_data->hard_regs 1094 insn_static_data->hard_regs
1058 = collect_non_operand_hard_regs (&PATTERN (insn), data, 1095 = collect_non_operand_hard_regs (insn, &PATTERN (insn), data,
1059 NULL, OP_IN, false); 1096 NULL, OP_IN, false, false);
1060 data->arg_hard_regs = NULL; 1097 data->arg_hard_regs = NULL;
1061 if (CALL_P (insn)) 1098 if (CALL_P (insn))
1062 { 1099 {
1063 bool use_p; 1100 bool use_p;
1064 rtx link; 1101 rtx link;
1080 /* It is an argument register. */ 1117 /* It is an argument register. */
1081 for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) 1118 for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--)
1082 arg_hard_regs[n_hard_regs++] 1119 arg_hard_regs[n_hard_regs++]
1083 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); 1120 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER);
1084 } 1121 }
1122 else if (GET_CODE (XEXP (link, 0)) == CLOBBER_HIGH)
1123 /* We could support CLOBBER_HIGH and treat it in the same way as
1124 HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */
1125 gcc_unreachable ();
1126
1085 if (n_hard_regs != 0) 1127 if (n_hard_regs != 0)
1086 { 1128 {
1087 arg_hard_regs[n_hard_regs++] = -1; 1129 arg_hard_regs[n_hard_regs++] = -1;
1088 data->arg_hard_regs = XNEWVEC (int, n_hard_regs); 1130 data->arg_hard_regs = XNEWVEC (int, n_hard_regs);
1089 memcpy (data->arg_hard_regs, arg_hard_regs, 1131 memcpy (data->arg_hard_regs, arg_hard_regs,
1162 { 1204 {
1163 lra_insn_recog_data_t data; 1205 lra_insn_recog_data_t data;
1164 int n; 1206 int n;
1165 unsigned int uid = INSN_UID (insn); 1207 unsigned int uid = INSN_UID (insn);
1166 struct lra_static_insn_data *insn_static_data; 1208 struct lra_static_insn_data *insn_static_data;
1167 HOST_WIDE_INT sp_offset = 0; 1209 poly_int64 sp_offset = 0;
1168 1210
1169 check_and_expand_insn_recog_data (uid); 1211 check_and_expand_insn_recog_data (uid);
1170 if ((data = lra_insn_recog_data[uid]) != NULL 1212 if ((data = lra_insn_recog_data[uid]) != NULL
1171 && data->icode != INSN_CODE (insn)) 1213 && data->icode != INSN_CODE (insn))
1172 { 1214 {
1181 /* Initiate or restore SP offset. */ 1223 /* Initiate or restore SP offset. */
1182 data->sp_offset = sp_offset; 1224 data->sp_offset = sp_offset;
1183 return data; 1225 return data;
1184 } 1226 }
1185 insn_static_data = data->insn_static_data; 1227 insn_static_data = data->insn_static_data;
1186 data->used_insn_alternative = -1; 1228 data->used_insn_alternative = LRA_UNKNOWN_ALT;
1187 if (DEBUG_INSN_P (insn)) 1229 if (DEBUG_INSN_P (insn))
1188 return data; 1230 return data;
1189 if (data->icode < 0) 1231 if (data->icode < 0)
1190 { 1232 {
1191 int nop; 1233 int nop;
1262 1304
1263 /* The size of the following array. */ 1305 /* The size of the following array. */
1264 static int reg_info_size; 1306 static int reg_info_size;
1265 /* Common info about each register. */ 1307 /* Common info about each register. */
1266 struct lra_reg *lra_reg_info; 1308 struct lra_reg *lra_reg_info;
1309
1310 HARD_REG_SET hard_regs_spilled_into;
1267 1311
1268 /* Last register value. */ 1312 /* Last register value. */
1269 static int last_reg_value; 1313 static int last_reg_value;
1270 1314
1271 /* Return new register value. */ 1315 /* Return new register value. */
1312 reg_info_size = max_reg_num () * 3 / 2 + 1; 1356 reg_info_size = max_reg_num () * 3 / 2 + 1;
1313 lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); 1357 lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size);
1314 for (i = 0; i < reg_info_size; i++) 1358 for (i = 0; i < reg_info_size; i++)
1315 initialize_lra_reg_info_element (i); 1359 initialize_lra_reg_info_element (i);
1316 copy_vec.truncate (0); 1360 copy_vec.truncate (0);
1361 CLEAR_HARD_REG_SET (hard_regs_spilled_into);
1317 } 1362 }
1318 1363
1319 1364
1320 /* Finish common reg info and copies. */ 1365 /* Finish common reg info and copies. */
1321 static void 1366 static void
1400 1445
1401 1446
1402 /* This page contains code dealing with info about registers in 1447 /* This page contains code dealing with info about registers in
1403 insns. */ 1448 insns. */
1404 1449
1405 /* Process X of insn UID recursively and add info (operand type is 1450 /* Process X of INSN recursively and add info (operand type is
1406 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) 1451 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1407 about registers in X to the insn DATA. If X can be early clobbered, 1452 about registers in X to the insn DATA. If X can be early clobbered,
1408 alternatives in which it can be early clobbered are given by 1453 alternatives in which it can be early clobbered are given by
1409 EARLY_CLOBBER_ALTS. */ 1454 EARLY_CLOBBER_ALTS. */
1410 static void 1455 static void
1411 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, 1456 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
1457 rtx_insn *insn,
1412 enum op_type type, bool early_clobber, 1458 enum op_type type, bool early_clobber,
1413 alternative_mask early_clobber_alts) 1459 alternative_mask early_clobber_alts)
1414 { 1460 {
1415 int i, j, regno; 1461 int i, j, regno;
1416 bool subreg_p; 1462 bool subreg_p;
1434 { 1480 {
1435 regno = REGNO (x); 1481 regno = REGNO (x);
1436 /* Process all regs even unallocatable ones as we need info about 1482 /* Process all regs even unallocatable ones as we need info about
1437 all regs for rematerialization pass. */ 1483 all regs for rematerialization pass. */
1438 expand_reg_info (); 1484 expand_reg_info ();
1439 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) 1485 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn)))
1440 { 1486 {
1441 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, 1487 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
1442 early_clobber, early_clobber_alts, 1488 early_clobber, early_clobber_alts,
1443 data->regs); 1489 data->regs, false);
1444 return; 1490 return;
1445 } 1491 }
1446 else 1492 else
1447 { 1493 {
1448 for (curr = data->regs; curr != NULL; curr = curr->next) 1494 for (curr = data->regs; curr != NULL; curr = curr->next)
1451 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) 1497 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
1452 /* The info can not be integrated into the found 1498 /* The info can not be integrated into the found
1453 structure. */ 1499 structure. */
1454 data->regs = new_insn_reg (data->insn, regno, type, mode, 1500 data->regs = new_insn_reg (data->insn, regno, type, mode,
1455 subreg_p, early_clobber, 1501 subreg_p, early_clobber,
1456 early_clobber_alts, data->regs); 1502 early_clobber_alts, data->regs,
1503 false);
1457 else 1504 else
1458 { 1505 {
1459 if (curr->type != type) 1506 if (curr->type != type)
1460 curr->type = OP_INOUT; 1507 curr->type = OP_INOUT;
1461 if (curr->early_clobber != early_clobber) 1508 if (curr->early_clobber != early_clobber)
1469 } 1516 }
1470 1517
1471 switch (code) 1518 switch (code)
1472 { 1519 {
1473 case SET: 1520 case SET:
1474 add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false, 0); 1521 add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, false, 0);
1475 add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false, 0); 1522 add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, false, 0);
1476 break; 1523 break;
1477 case CLOBBER: 1524 case CLOBBER:
1478 /* We treat clobber of non-operand hard registers as early 1525 /* We treat clobber of non-operand hard registers as early
1479 clobber (the behavior is expected from asm). */ 1526 clobber. */
1480 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true, ALL_ALTERNATIVES); 1527 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT,
1528 true, ALL_ALTERNATIVES);
1481 break; 1529 break;
1530 case CLOBBER_HIGH:
1531 gcc_unreachable ();
1482 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: 1532 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
1483 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false, 0); 1533 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
1484 break; 1534 break;
1485 case PRE_MODIFY: case POST_MODIFY: 1535 case PRE_MODIFY: case POST_MODIFY:
1486 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false, 0); 1536 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
1487 add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false, 0); 1537 add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, false, 0);
1488 break; 1538 break;
1489 default: 1539 default:
1490 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) 1540 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT)
1491 /* Some targets place small structures in registers for return 1541 /* Some targets place small structures in registers for return
1492 values of functions, and those registers are wrapped in 1542 values of functions, and those registers are wrapped in
1503 type = OP_IN; 1553 type = OP_IN;
1504 fmt = GET_RTX_FORMAT (code); 1554 fmt = GET_RTX_FORMAT (code);
1505 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1555 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1506 { 1556 {
1507 if (fmt[i] == 'e') 1557 if (fmt[i] == 'e')
1508 add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false, 0); 1558 add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, false, 0);
1509 else if (fmt[i] == 'E') 1559 else if (fmt[i] == 'E')
1510 { 1560 {
1511 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1561 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1512 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, 1562 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn,
1513 type, false, 0); 1563 type, false, 0);
1514 } 1564 }
1515 } 1565 }
1516 } 1566 }
1517 } 1567 }
1583 /* Set up insn reg info of INSN. Update common reg info from reg info 1633 /* Set up insn reg info of INSN. Update common reg info from reg info
1584 of INSN. */ 1634 of INSN. */
1585 void 1635 void
1586 lra_update_insn_regno_info (rtx_insn *insn) 1636 lra_update_insn_regno_info (rtx_insn *insn)
1587 { 1637 {
1588 int i, uid, freq; 1638 int i, freq;
1589 lra_insn_recog_data_t data; 1639 lra_insn_recog_data_t data;
1590 struct lra_static_insn_data *static_data; 1640 struct lra_static_insn_data *static_data;
1591 enum rtx_code code; 1641 enum rtx_code code;
1592 rtx link; 1642 rtx link;
1593 1643
1594 if (! INSN_P (insn)) 1644 if (! INSN_P (insn))
1595 return; 1645 return;
1596 data = lra_get_insn_recog_data (insn); 1646 data = lra_get_insn_recog_data (insn);
1597 static_data = data->insn_static_data; 1647 static_data = data->insn_static_data;
1598 freq = get_insn_freq (insn); 1648 freq = NONDEBUG_INSN_P (insn) ? get_insn_freq (insn) : 0;
1599 invalidate_insn_data_regno_info (data, insn, freq); 1649 invalidate_insn_data_regno_info (data, insn, freq);
1600 uid = INSN_UID (insn);
1601 for (i = static_data->n_operands - 1; i >= 0; i--) 1650 for (i = static_data->n_operands - 1; i >= 0; i--)
1602 add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, 1651 add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn,
1603 static_data->operand[i].type, 1652 static_data->operand[i].type,
1604 static_data->operand[i].early_clobber, 1653 static_data->operand[i].early_clobber,
1605 static_data->operand[i].early_clobber_alts); 1654 static_data->operand[i].early_clobber_alts);
1606 if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) 1655 if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE)
1607 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, 1656 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn,
1608 code == USE ? OP_IN : OP_OUT, false, 0); 1657 code == USE ? OP_IN : OP_OUT, false, 0);
1609 if (CALL_P (insn)) 1658 if (CALL_P (insn))
1610 /* On some targets call insns can refer to pseudos in memory in 1659 /* On some targets call insns can refer to pseudos in memory in
1611 CALL_INSN_FUNCTION_USAGE list. Process them in order to 1660 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1612 consider their occurrences in calls for different 1661 consider their occurrences in calls for different
1613 transformations (e.g. inheritance) with given pseudos. */ 1662 transformations (e.g. inheritance) with given pseudos. */
1614 for (link = CALL_INSN_FUNCTION_USAGE (insn); 1663 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1615 link != NULL_RTX; 1664 link != NULL_RTX;
1616 link = XEXP (link, 1)) 1665 link = XEXP (link, 1))
1617 if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) 1666 {
1618 && MEM_P (XEXP (XEXP (link, 0), 0))) 1667 code = GET_CODE (XEXP (link, 0));
1619 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, 1668 /* We could support CLOBBER_HIGH and treat it in the same way as
1620 code == USE ? OP_IN : OP_OUT, false, 0); 1669 HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */
1670 gcc_assert (code != CLOBBER_HIGH);
1671 if ((code == USE || code == CLOBBER)
1672 && MEM_P (XEXP (XEXP (link, 0), 0)))
1673 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn,
1674 code == USE ? OP_IN : OP_OUT, false, 0);
1675 }
1621 if (NONDEBUG_INSN_P (insn)) 1676 if (NONDEBUG_INSN_P (insn))
1622 setup_insn_reg_info (data, freq); 1677 setup_insn_reg_info (data, freq);
1623 } 1678 }
1624 1679
1625 /* Return reg info of insn given by it UID. */ 1680 /* Return reg info of insn given by it UID. */
1803 taken from the next BB insn after LAST or zero if there in such 1858 taken from the next BB insn after LAST or zero if there in such
1804 insn. */ 1859 insn. */
1805 static void 1860 static void
1806 setup_sp_offset (rtx_insn *from, rtx_insn *last) 1861 setup_sp_offset (rtx_insn *from, rtx_insn *last)
1807 { 1862 {
1808 rtx_insn *before = next_nonnote_insn_bb (last); 1863 rtx_insn *before = next_nonnote_nondebug_insn_bb (last);
1809 HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before) 1864 poly_int64 offset = (before == NULL_RTX || ! INSN_P (before)
1810 ? 0 : lra_get_insn_recog_data (before)->sp_offset); 1865 ? 0 : lra_get_insn_recog_data (before)->sp_offset);
1811 1866
1812 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) 1867 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
1813 lra_get_insn_recog_data (insn)->sp_offset = offset; 1868 lra_get_insn_recog_data (insn)->sp_offset = offset;
1814 } 1869 }
1815 1870
1866 } 1921 }
1867 1922
1868 1923
1869 /* Replace all references to register OLD_REGNO in *LOC with pseudo 1924 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1870 register NEW_REG. Try to simplify subreg of constant if SUBREG_P. 1925 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1871 Return true if any change was made. */ 1926 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
1927 change was made. */
1872 bool 1928 bool
1873 lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p) 1929 lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p,
1930 bool debug_p)
1874 { 1931 {
1875 rtx x = *loc; 1932 rtx x = *loc;
1876 bool result = false; 1933 bool result = false;
1877 enum rtx_code code; 1934 enum rtx_code code;
1878 const char *fmt; 1935 const char *fmt;
1904 machine_mode inner_mode = GET_MODE (new_reg); 1961 machine_mode inner_mode = GET_MODE (new_reg);
1905 1962
1906 if (mode != inner_mode 1963 if (mode != inner_mode
1907 && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) 1964 && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode)))
1908 { 1965 {
1909 if (!partial_subreg_p (mode, inner_mode) 1966 poly_uint64 offset = 0;
1910 || ! SCALAR_INT_MODE_P (inner_mode)) 1967 if (partial_subreg_p (mode, inner_mode)
1911 new_reg = gen_rtx_SUBREG (mode, new_reg, 0); 1968 && SCALAR_INT_MODE_P (inner_mode))
1969 offset = subreg_lowpart_offset (mode, inner_mode);
1970 if (debug_p)
1971 new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset);
1912 else 1972 else
1913 new_reg = gen_lowpart_SUBREG (mode, new_reg); 1973 new_reg = gen_rtx_SUBREG (mode, new_reg, offset);
1914 } 1974 }
1915 *loc = new_reg; 1975 *loc = new_reg;
1916 return true; 1976 return true;
1917 } 1977 }
1918 1978
1921 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1981 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1922 { 1982 {
1923 if (fmt[i] == 'e') 1983 if (fmt[i] == 'e')
1924 { 1984 {
1925 if (lra_substitute_pseudo (&XEXP (x, i), old_regno, 1985 if (lra_substitute_pseudo (&XEXP (x, i), old_regno,
1926 new_reg, subreg_p)) 1986 new_reg, subreg_p, debug_p))
1927 result = true; 1987 result = true;
1928 } 1988 }
1929 else if (fmt[i] == 'E') 1989 else if (fmt[i] == 'E')
1930 { 1990 {
1931 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1991 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1932 if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, 1992 if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno,
1933 new_reg, subreg_p)) 1993 new_reg, subreg_p, debug_p))
1934 result = true; 1994 result = true;
1935 } 1995 }
1936 } 1996 }
1937 return result; 1997 return result;
1938 } 1998 }
1943 bool 2003 bool
1944 lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, 2004 lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno,
1945 rtx new_reg, bool subreg_p) 2005 rtx new_reg, bool subreg_p)
1946 { 2006 {
1947 rtx loc = insn; 2007 rtx loc = insn;
1948 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p); 2008 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p,
2009 DEBUG_INSN_P (insn));
1949 } 2010 }
1950 2011
1951 2012
1952 2013
1953 /* This page contains code dealing with scratches (changing them onto 2014 /* This page contains code dealing with scratches (changing them onto
2370 bitmap_initialize (&lra_inheritance_pseudos, &reg_obstack); 2431 bitmap_initialize (&lra_inheritance_pseudos, &reg_obstack);
2371 bitmap_initialize (&lra_split_regs, &reg_obstack); 2432 bitmap_initialize (&lra_split_regs, &reg_obstack);
2372 bitmap_initialize (&lra_optional_reload_pseudos, &reg_obstack); 2433 bitmap_initialize (&lra_optional_reload_pseudos, &reg_obstack);
2373 bitmap_initialize (&lra_subreg_reload_pseudos, &reg_obstack); 2434 bitmap_initialize (&lra_subreg_reload_pseudos, &reg_obstack);
2374 live_p = false; 2435 live_p = false;
2375 if (get_frame_size () != 0 && crtl->stack_alignment_needed) 2436 if (maybe_ne (get_frame_size (), 0) && crtl->stack_alignment_needed)
2376 /* If we have a stack frame, we must align it now. The stack size 2437 /* If we have a stack frame, we must align it now. The stack size
2377 may be a part of the offset computation for register 2438 may be a part of the offset computation for register
2378 elimination. */ 2439 elimination. */
2379 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); 2440 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
2380 lra_init_equiv (); 2441 lra_init_equiv ();
2424 } 2485 }
2425 lra_inheritance (); 2486 lra_inheritance ();
2426 } 2487 }
2427 if (live_p) 2488 if (live_p)
2428 lra_clear_live_ranges (); 2489 lra_clear_live_ranges ();
2429 /* We need live ranges for lra_assign -- so build them. But 2490 bool fails_p;
2430 don't remove dead insns or change global live info as we 2491 do
2431 can undo inheritance transformations after inheritance
2432 pseudo assigning. */
2433 lra_create_live_ranges (true, false);
2434 live_p = true;
2435 /* If we don't spill non-reload and non-inheritance pseudos,
2436 there is no sense to run memory-memory move coalescing.
2437 If inheritance pseudos were spilled, the memory-memory
2438 moves involving them will be removed by pass undoing
2439 inheritance. */
2440 if (lra_simple_p)
2441 lra_assign ();
2442 else
2443 { 2492 {
2444 bool spill_p = !lra_assign (); 2493 /* We need live ranges for lra_assign -- so build them.
2445 2494 But don't remove dead insns or change global live
2446 if (lra_undo_inheritance ()) 2495 info as we can undo inheritance transformations after
2447 live_p = false; 2496 inheritance pseudo assigning. */
2448 if (spill_p) 2497 lra_create_live_ranges (true, false);
2498 live_p = true;
2499 /* If we don't spill non-reload and non-inheritance
2500 pseudos, there is no sense to run memory-memory move
2501 coalescing. If inheritance pseudos were spilled, the
2502 memory-memory moves involving them will be removed by
2503 pass undoing inheritance. */
2504 if (lra_simple_p)
2505 lra_assign (fails_p);
2506 else
2449 { 2507 {
2508 bool spill_p = !lra_assign (fails_p);
2509
2510 if (lra_undo_inheritance ())
2511 live_p = false;
2512 if (spill_p && ! fails_p)
2513 {
2514 if (! live_p)
2515 {
2516 lra_create_live_ranges (true, true);
2517 live_p = true;
2518 }
2519 if (lra_coalesce ())
2520 live_p = false;
2521 }
2450 if (! live_p) 2522 if (! live_p)
2451 { 2523 lra_clear_live_ranges ();
2452 lra_create_live_ranges (true, true);
2453 live_p = true;
2454 }
2455 if (lra_coalesce ())
2456 live_p = false;
2457 } 2524 }
2458 if (! live_p) 2525 if (fails_p)
2459 lra_clear_live_ranges (); 2526 {
2527 /* It is a very rare case. It is the last hope to
2528 split a hard regno live range for a reload
2529 pseudo. */
2530 if (live_p)
2531 lra_clear_live_ranges ();
2532 live_p = false;
2533 if (! lra_split_hard_reg_for ())
2534 break;
2535 }
2460 } 2536 }
2537 while (fails_p);
2461 } 2538 }
2462 /* Don't clear optional reloads bitmap until all constraints are 2539 /* Don't clear optional reloads bitmap until all constraints are
2463 satisfied as we need to differ them from regular reloads. */ 2540 satisfied as we need to differ them from regular reloads. */
2464 bitmap_clear (&lra_optional_reload_pseudos); 2541 bitmap_clear (&lra_optional_reload_pseudos);
2465 bitmap_clear (&lra_subreg_reload_pseudos); 2542 bitmap_clear (&lra_subreg_reload_pseudos);