CbC/CbC_gcc: gcc/reload1.c comparison

comparison gcc/reload1.c @ 131:84e7813d76e9

gcc-8.2

author	mir3636
date	Thu, 25 Oct 2018 07:37:49 +0900
parents	04ced10e8804
children	1830386684a0

comparison

equal deleted inserted replaced

-:04ced10e8804
+:84e7813d76e9
 /* Reload pseudo regs into hard regs for insns that require hard regs.
-Copyright (C) 1987-2017 Free Software Foundation, Inc.
+Copyright (C) 1987-2018 Free Software Foundation, Inc.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free
 /* Record the stack slot for each spilled hard register.  */
 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 /* Width allocated so far for that stack slot.  */
-static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
+static poly_uint64_pod spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 /* Record which pseudos needed to be spilled.  */
 static regset_head spilled_pseudos;
 /* Record which pseudos changed their allocation in finish_spills.  */
 struct elim_table
 {
 int from;			/* Register number to be eliminated.  */
 int to;			/* Register number used as replacement.  */
-HOST_WIDE_INT initial_offset;	/* Initial difference between values.  */
+poly_int64_pod initial_offset; /* Initial difference between values.  */
 int can_eliminate;		/* Nonzero if this elimination can be done.  */
 int can_eliminate_previous;	/* Value returned by TARGET_CAN_ELIMINATE
 				   target hook in previous scan over insns
 				   made by reload.  */
-HOST_WIDE_INT offset;		/* Current offset between the two regs.  */
+poly_int64_pod offset;	/* Current offset between the two regs.  */
-HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
+poly_int64_pod previous_offset; /* Offset at end of previous insn.  */
 int ref_outside_mem;		/* "to" has been referenced outside a MEM.  */
 rtx from_rtx;			/* REG rtx for the register to be eliminated.
 				   We cannot simply compare the number since
 				   we might then spuriously replace a hard
 				   register corresponding to a pseudo
 have yet encountered a label and the second table is an array of arrays,
 one entry in the latter array for each elimination.  */
 static int first_label_num;
 static char *offsets_known_at;
-static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
+static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS];
 vec<reg_equivs_t, va_gc> *reg_equivs;
 /* Stack of addresses where an rtx has been changed.  We can undo the
 changes by popping items off the stack and restoring the original
 static void do_output_reload (struct insn_chain *, struct reload *, int);
 static void emit_reload_insns (struct insn_chain *);
 static void delete_output_reload (rtx_insn *, int, int, rtx);
 static void delete_address_reloads (rtx_insn *, rtx_insn *);
 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
-static void inc_for_reload (rtx, rtx, rtx, int);
+static void inc_for_reload (rtx, rtx, rtx, poly_int64);
 static void add_auto_inc_notes (rtx_insn *, rtx);
 static void substitute (rtx *, const_rtx, rtx);
 static bool gen_reload_chain_without_interm_reg_p (int, int);
 static int reloads_conflict (int, int);
 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
 /* This loop scans the entire function each go-round
 and repeats until one repetition spills no additional hard regs.  */
 for (;;)
 {
 int something_changed;
-HOST_WIDE_INT starting_frame_size;
+poly_int64 starting_frame_size;
 starting_frame_size = get_frame_size ();
 something_was_spilled = false;
 set_initial_elim_offsets ();
 	  }
 if (caller_save_needed)
 	setup_save_areas ();
-if (starting_frame_size && crtl->stack_alignment_needed)
+if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
 	{
 	  /* If we have a stack frame, we must align it now.  The
 	     stack size may be a part of the offset computation for
 	     register elimination.  So if this changes the stack size,
 	     then repeat the elimination bookkeeping.  We don't
 	     TARGET_STARTING_FRAME_OFFSET not be already aligned to
 	     STACK_BOUNDARY.  */
 	  assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
 	}
 /* If we allocated another stack slot, redo elimination bookkeeping.  */
-if (something_was_spilled || starting_frame_size != get_frame_size ())
+if (something_was_spilled
+	  || maybe_ne (starting_frame_size, get_frame_size ()))
 	{
 	  if (update_eliminables_and_spill ())
 	    finish_spills (0);
 	  continue;
 	}
 something_changed = 0;
 /* If we allocated any new memory locations, make another pass
 	 since it might have changed elimination offsets.  */
-if (something_was_spilled || starting_frame_size != get_frame_size ())
+if (something_was_spilled
+	  || maybe_ne (starting_frame_size, get_frame_size ()))
 	something_changed = 1;
 /* Even if the frame size remained the same, we might still have
 	 changed elimination offsets, e.g. if find_reloads called
 	 force_const_mem requiring the back end to allocate a constant
 values into or out of the reload registers.  */
 if (insns_need_reload != 0 || something_needs_elimination
 || something_needs_operands_changed)
 {
-HOST_WIDE_INT old_frame_size = get_frame_size ();
+poly_int64 old_frame_size = get_frame_size ();
 reload_as_needed (global);
-gcc_assert (old_frame_size == get_frame_size ());
+gcc_assert (known_eq (old_frame_size, get_frame_size ()));
 gcc_assert (verify_initial_elim_offsets ());
 }
 /* If we were able to eliminate the frame pointer, show that it is no
 	}
 /* We don't want complex addressing modes in debug insns
 	 if simpler ones will do, so delegitimize equivalences
 	 in debug insns.  */
-if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
+if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
 	{
 	  rtx reg = regno_reg_rtx[i];
 	  rtx equiv = 0;
 	  df_ref use, next;
 		 so that we're not affected by the rescan.  */
 	      next = DF_REF_NEXT_REG (use);
 	      while (next && DF_REF_INSN (next) == insn)
 		next = DF_REF_NEXT_REG (next);
-	      if (DEBUG_INSN_P (insn))
+	      if (DEBUG_BIND_INSN_P (insn))
 		{
 		  if (!equiv)
 		    {
 		      INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
 		      df_insn_rescan_debug_internal (insn);
 for (i = 0; i < XVECLEN (pat, 0); i++)
 	{
 	  rtx t = XVECEXP (pat, 0, i);
 	  if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
 	    SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
+	  /* CLOBBER_HIGH is only supported for LRA.  */
+	  gcc_assert (GET_CODE (t) != CLOBBER_HIGH);
 	}
 /* Get the operand values and constraints out of the insn.  */
 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
 			   constraints, operand_mode, NULL);
 	  || reg_equiv_init (i) == 0)
 && reg_equiv_memory_loc (i) == 0)
 {
 rtx x = NULL_RTX;
 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
-unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
+poly_uint64 inherent_size = GET_MODE_SIZE (mode);
 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
-unsigned int total_size = GET_MODE_SIZE (wider_mode);
+poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
-unsigned int min_align = GET_MODE_BITSIZE (reg_max_ref_mode[i]);
+/* ??? Seems strange to derive the minimum alignment from the size,
-int adjust = 0;
+	 but that's the traditional behavior.  For polynomial-size modes,
+	 the natural extension is to use the minimum possible size.  */
+unsigned int min_align
+	= constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
+poly_int64 adjust = 0;
 something_was_spilled = true;
 if (ira_conflicts_p)
 	{
 	 inherent space, and no less total space, then the previous slot.  */
 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
 	{
 	  rtx stack_slot;
+	  /* The sizes are taken from a subreg operation, which guarantees
+	     that they're ordered.  */
+	  gcc_checking_assert (ordered_p (total_size, inherent_size));
 	  /* No known place to spill from => no slot to reuse.  */
 	  x = assign_stack_local (mode, total_size,
 				  min_align > inherent_align
-				  || total_size > inherent_size ? -1 : 0);
+				  || maybe_gt (total_size, inherent_size)
+				  ? -1 : 0);
 	  stack_slot = x;
 	  /* Cancel the big-endian correction done in assign_stack_local.
 	     Get the address of the beginning of the slot.  This is so we
 	     can do a big-endian correction unconditionally below.  */
 	  if (BYTES_BIG_ENDIAN)
 	    {
 	      adjust = inherent_size - total_size;
-	      if (adjust)
+	      if (maybe_ne (adjust, 0))
 		{
-		  unsigned int total_bits = total_size * BITS_PER_UNIT;
+		  poly_uint64 total_bits = total_size * BITS_PER_UNIT;
 		  machine_mode mem_mode
 		    = int_mode_for_size (total_bits, 1).else_blk ();
 		  stack_slot = adjust_address_nv (x, mem_mode, adjust);
 		}
 	    }
 	    ira_mark_new_stack_slot (stack_slot, i, total_size);
 	}
 /* Reuse a stack slot if possible.  */
 else if (spill_stack_slot[from_reg] != 0
-	       && spill_stack_slot_width[from_reg] >= total_size
+	       && known_ge (spill_stack_slot_width[from_reg], total_size)
-	       && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
+	       && known_ge (GET_MODE_SIZE
-		   >= inherent_size)
+			    (GET_MODE (spill_stack_slot[from_reg])),
+			    inherent_size)
 	       && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
 	x = spill_stack_slot[from_reg];
 /* Allocate a bigger slot.  */
 else
 	  if (spill_stack_slot[from_reg])
 	    {
 	      if (partial_subreg_p (mode,
 				    GET_MODE (spill_stack_slot[from_reg])))
 		mode = GET_MODE (spill_stack_slot[from_reg]);
-	      if (spill_stack_slot_width[from_reg] > total_size)
+	      total_size = ordered_max (total_size,
-		total_size = spill_stack_slot_width[from_reg];
+					spill_stack_slot_width[from_reg]);
 	      if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
 		min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
 	    }
+	  /* The sizes are taken from a subreg operation, which guarantees
+	     that they're ordered.  */
+	  gcc_checking_assert (ordered_p (total_size, inherent_size));
 	  /* Make a slot with that size.  */
 	  x = assign_stack_local (mode, total_size,
 				  min_align > inherent_align
-				  || total_size > inherent_size ? -1 : 0);
+				  || maybe_gt (total_size, inherent_size)
+				  ? -1 : 0);
 	  stack_slot = x;
 	  /* Cancel the  big-endian correction done in assign_stack_local.
 	     Get the address of the beginning of the slot.  This is so we
 	     can do a big-endian correction unconditionally below.  */
 	  if (BYTES_BIG_ENDIAN)
 	    {
 	      adjust = GET_MODE_SIZE (mode) - total_size;
-	      if (adjust)
+	      if (maybe_ne (adjust, 0))
 		{
-		  unsigned int total_bits = total_size * BITS_PER_UNIT;
+		  poly_uint64 total_bits = total_size * BITS_PER_UNIT;
 		  machine_mode mem_mode
 		    = int_mode_for_size (total_bits, 1).else_blk ();
 		  stack_slot = adjust_address_nv (x, mem_mode, adjust);
 		}
 	    }
 	/* If neither of the above cases is true, compare each offset
 	   with those previously recorded and suppress any eliminations
 	   where the offsets disagree.  */
 	for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
-	  if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
+	  if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
-	      != (initial_p ? reg_eliminate[i].initial_offset
+			(initial_p ? reg_eliminate[i].initial_offset
-		  : reg_eliminate[i].offset))
+			 : reg_eliminate[i].offset)))
 	    reg_eliminate[i].can_eliminate = 0;
 return;
 case JUMP_TABLE_DATA:
 	}
 /* If we reach here, all eliminations must be at their initial
 	 offset because we are doing a jump to a variable address.  */
 for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
-	if (p->offset != p->initial_offset)
+	if (maybe_ne (p->offset, p->initial_offset))
 	  p->can_eliminate = 0;
 break;
 default:
 break;
 		   to do so at other times because that would change the
 		   structure of the insn in a way that reload can't handle.
 		   We special-case the commonest situation in
 		   eliminate_regs_in_insn, so just replace a PLUS with a
 		   PLUS here, unless inside a MEM.  */
-		if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
+		if (mem_mode != 0
-		    && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
+		    && CONST_INT_P (XEXP (x, 1))
+		    && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
 		  return ep->to_rtx;
 		else
 		  return gen_rtx_PLUS (Pmode, ep->to_rtx,
 				       plus_constant (Pmode, XEXP (x, 1),
 						      ep->previous_offset));
 else
 	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
 if (new_rtx != SUBREG_REG (x))
 	{
-	  int x_size = GET_MODE_SIZE (GET_MODE (x));
+	  poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x));
-	  int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
+	  poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
 	  if (MEM_P (new_rtx)
 	      && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
 		   /* On RISC machines, combine can create rtl of the form
 		      (set (subreg:m1 (reg:m2 R) 0) ...)
 		      happen to the entire word.  Moreover, it will use the
 		      (reg:m2 R) later, expecting all bits to be preserved.
 		      So if the number of words is the same, preserve the
 		      subreg so that push_reload can see it.  */
 		   && !(WORD_REGISTER_OPERATIONS
-			&& (x_size - 1) / UNITS_PER_WORD
+			&& known_equal_after_align_down (x_size - 1,
-			   == (new_size -1 ) / UNITS_PER_WORD))
+							 new_size - 1,
-		  || x_size == new_size)
+							 UNITS_PER_WORD)))
+		  || known_eq (x_size, new_size))
 	      )
 	    return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
 	  else if (insn && GET_CODE (insn) == DEBUG_INSN)
 	    return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
 	  else
 if (new_rtx != XEXP (x, 0))
 	return gen_rtx_USE (GET_MODE (x), new_rtx);
 return x;
 case CLOBBER:
+case CLOBBER_HIGH:
 case ASM_OPERANDS:
 gcc_assert (insn && DEBUG_INSN_P (insn));
 break;
 case SET:
 	 update its offset.  If we modify the target in any other way, we'll
 	 have to disable the rule as well.  */
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 	if (ep->to_rtx == XEXP (x, 0))
 	  {
-	    int size = GET_MODE_SIZE (mem_mode);
+	    poly_int64 size = GET_MODE_SIZE (mem_mode);
 	    /* If more bytes than MEM_MODE are pushed, account for them.  */
 #ifdef PUSH_ROUNDING
 	    if (ep->to_rtx == stack_pointer_rtx)
 	      size = PUSH_ROUNDING (size);
 	  ep->can_eliminate = 0;
 elimination_effects (XEXP (x, 0), mem_mode);
 return;
+case CLOBBER_HIGH:
+/* CLOBBER_HIGH is only supported for LRA.  */
+return;
 case SET:
 /* Check for setting a register that we know about.  */
 if (REG_P (SET_DEST (x)))
 	{
 	  /* See if this is setting the replacement register for an
 {
 gcc_assert (DEBUG_INSN_P (insn)
 		  || GET_CODE (PATTERN (insn)) == USE
 		  || GET_CODE (PATTERN (insn)) == CLOBBER
 		  || GET_CODE (PATTERN (insn)) == ASM_INPUT);
-if (DEBUG_INSN_P (insn))
+if (DEBUG_BIND_INSN_P (insn))
 	INSN_VAR_LOCATION_LOC (insn)
 	  = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
 return 0;
 }
 	}
 }
 if (plus_cst_src)
 {
 rtx reg = XEXP (plus_cst_src, 0);
-HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
+poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
 if (GET_CODE (reg) == SUBREG)
 	reg = SUBREG_REG (reg);
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 	    /* If we have a nonzero offset, and the source is already
 	       a simple REG, the following transformation would
 	       increase the cost of the insn by replacing a simple REG
 	       with (plus (reg sp) CST).  So try only when we already
 	       had a PLUS before.  */
-	    if (offset == 0 || plus_src)
+	    if (known_eq (offset, 0) || plus_src)
 	      {
 		rtx new_src = plus_constant (GET_MODE (to_rtx),
 					     to_rtx, offset);
 		new_body = old_body;
 If anything changes, return nonzero.  */
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 {
-if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
+if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
 	ep->can_eliminate = 0;
 ep->ref_outside_mem = 0;
-if (ep->previous_offset != ep->offset)
+if (maybe_ne (ep->previous_offset, ep->offset))
 	val = 1;
 }
 done:
 /* If we changed something, perform elimination in REG_NOTES.  This is
 insn.  The changes we make were determined by the earlier call to
 elimination_effects.  */
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 {
-if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
+if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
 	ep->can_eliminate = 0;
 ep->ref_outside_mem = 0;
 }
 num_not_at_initial_offset = 0;
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 {
 ep->previous_offset = ep->offset;
-if (ep->can_eliminate && ep->offset != ep->initial_offset)
+if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
 	num_not_at_initial_offset++;
 }
 }
 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
 if (GET_CODE (dest) == SUBREG)
 dest = SUBREG_REG (dest);
 if (dest == hard_frame_pointer_rtx)
 return;
+/* CLOBBER_HIGH is only supported for LRA.  */
+gcc_assert (GET_CODE (x) != CLOBBER_HIGH);
 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
 	&& (GET_CODE (x) != SET
 	    || GET_CODE (SET_SRC (x)) != PLUS
 cause incorrect code to be generated if we did not check for it.  */
 static bool
 verify_initial_elim_offsets (void)
 {
-HOST_WIDE_INT t;
+poly_int64 t;
 struct elim_table *ep;
 if (!num_eliminable)
 return true;
 targetm.compute_frame_layout ();
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
 {
 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
-if (t != ep->initial_offset)
+if (maybe_ne (t, ep->initial_offset))
 	return false;
 }
 return true;
 }
 num_not_at_initial_offset = 0;
 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
 {
 ep->offset = ep->previous_offset
 		 = offsets_at[label_nr - first_label_num][i];
-if (ep->can_eliminate && ep->offset != ep->initial_offset)
+if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
 	num_not_at_initial_offset++;
 }
 }
 /* See if anything that happened changes which eliminations are valid.
 first_label_num = get_first_label_num ();
 num_labels = max_label_num () - first_label_num;
 /* Allocate the tables used to store offset information at labels.  */
 offsets_known_at = XNEWVEC (char, num_labels);
-offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
+offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS])
+xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
 to.  If DO_SUBREGS is true, also find all paradoxical subregs and
 find largest such for each pseudo.  FIRST is the head of the insn
 list.  */
 CASE_CONST_ANY:
 case CC0:
 case PC:
 case USE:
 case CLOBBER:
+case CLOBBER_HIGH:
 return;
 case SUBREG:
 if (REG_P (SUBREG_REG (x)))
 	{
 	      rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
 	      if (p)
 		{
 		  remove_note (insn, p);
 		  fixup_args_size_notes (prev, PREV_INSN (next),
-					 INTVAL (XEXP (p, 0)));
+					 get_args_size (p));
 		}
 	      /* If this was an ASM, make sure that all the reload insns
 		 we have generated are valid.  If not, give an error
 		 and delete them.  */
 When DATA is non-NULL just mark the registers in regset
 to be forgotten later.  */
 static void
-forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
+forget_old_reloads_1 (rtx x, const_rtx setter,
 		      void *data)
 {
 unsigned int regno;
 unsigned int nr;
 regset regs = (regset) data;
 x = SUBREG_REG (x);
 }
 if (!REG_P (x))
 return;
+/* CLOBBER_HIGH is only supported for LRA.  */
+gcc_assert (setter == NULL_RTX || GET_CODE (setter) != CLOBBER_HIGH);
 regno = REGNO (x);
 if (regno >= FIRST_PSEUDO_REGISTER)
 nr = 1;
 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
 otherwise it is NULL.  */
-static int
+static poly_int64
 compute_reload_subreg_offset (machine_mode outermode,
 			      rtx subreg,
 			      machine_mode innermode)
 {
-int outer_offset;
+poly_int64 outer_offset;
 machine_mode middlemode;
 if (!subreg)
 return subreg_lowpart_offset (outermode, innermode);
 	     register be allocated here.  In `emit_reload_insns' we suppress
 	     one of the loads in the case described above.  */
 	  if (inheritance)
 	    {
-	      int byte = 0;
+	      poly_int64 byte = 0;
 	      int regno = -1;
 	      machine_mode mode = VOIDmode;
 	      rtx subreg = NULL_RTX;
 	      if (rld[r].in == 0)
 		regno = subreg_regno (rld[r].in);
 #endif
 	      if (regno >= 0
 		  && reg_last_reload_reg[regno] != 0
-		  && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
+		  && (known_ge
-		      >= GET_MODE_SIZE (mode) + byte)
+		      (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
+		       GET_MODE_SIZE (mode) + byte))
 		  /* Verify that the register it's in can be used in
 		     mode MODE.  */
 		  && (REG_CAN_CHANGE_MODE_P
 		      (REGNO (reg_last_reload_reg[regno]),
 		       GET_MODE (reg_last_reload_reg[regno]),
 		}
 	      special = 1;
 	      /* Adjust any debug insns between temp and insn.  */
 	      while ((temp = NEXT_INSN (temp)) != insn)
-		if (DEBUG_INSN_P (temp))
+		if (DEBUG_BIND_INSN_P (temp))
 		  INSN_VAR_LOCATION_LOC (temp)
 		    = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
 					    old, reloadreg);
 		else
-		  gcc_assert (NOTE_P (temp));
+		  gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
 	    }
 	  else
 	    {
 	      SET_DEST (PATTERN (temp)) = old;
 	    }
 return;
 }
 /* Likewise for a SUBREG of an operand that dies.  */
 else if (GET_CODE (old) == SUBREG
 	   && REG_P (SUBREG_REG (old))
-	   && 0 != (note = find_reg_note (insn, REG_UNUSED,
+	   && (note = find_reg_note (insn, REG_UNUSED,
-					  SUBREG_REG (old))))
+				     SUBREG_REG (old))) != 0)
 {
 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
 return;
 }
 else if (GET_CODE (old) == SCRATCH)
 INC_AMOUNT is the number to increment or decrement by (always positive).
 This cannot be deduced from VALUE.  */
 static void
-inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
+inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
 {
 /* REG or MEM to be copied and incremented.  */
 rtx incloc = find_replacement (&XEXP (value, 0));
 /* Nonzero if increment after copying.  */
 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
 else
 {
 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
 	inc_amount = -inc_amount;
-inc = GEN_INT (inc_amount);
+inc = gen_int_mode (inc_amount, Pmode);
 }
 /* If this is post-increment, first copy the location to the reload reg.  */
 if (post && real_in != reloadreg)
 emit_insn (gen_move_insn (reloadreg, real_in));

Mercurial > hg > CbC > CbC_gcc

comparison gcc/reload1.c @ 131:84e7813d76e9